WO2021051446A1 - 一种印刷电路板及电子产品 - Google Patents

一种印刷电路板及电子产品 Download PDF

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Publication number
WO2021051446A1
WO2021051446A1 PCT/CN2019/108549 CN2019108549W WO2021051446A1 WO 2021051446 A1 WO2021051446 A1 WO 2021051446A1 CN 2019108549 W CN2019108549 W CN 2019108549W WO 2021051446 A1 WO2021051446 A1 WO 2021051446A1
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Prior art keywords
hole
filling
printed circuit
circuit board
ended signal
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PCT/CN2019/108549
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English (en)
French (fr)
Inventor
吕信宏
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苏州浪潮智能科技有限公司
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Publication of WO2021051446A1 publication Critical patent/WO2021051446A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections

Definitions

  • the invention relates to the technical field of single-ended signal vias, in particular to a printed circuit board and an electronic product.
  • the method of adjusting the aperture of the via hole or the size of the soldering tab is usually adopted.
  • the size of the via or the soldering tab is large enough, there may be a problem of wasting the area of the printed circuit board.
  • the purpose of the present invention is to provide a printed circuit board for effectively reducing the area of the printed circuit board used during impedance adjustment.
  • the object of the present invention is to provide an electronic product including the above-mentioned printed circuit board.
  • the present invention provides a printed circuit board that includes a single-ended signal via provided on a multilayer PCB, and further includes a single-ended signal via provided on the multilayer PCB and spaced from the single-ended signal via A filling hole with a preset distance, the filling hole being used for filling a filling medium that adjusts the impedance characteristic of the single-ended signal via.
  • the filling hole is a round hole.
  • the dielectric constant of the filling medium is 12
  • the center distance between the filling hole and the single-ended signal via is 25 mils
  • the diameter of the filling hole is 10 mils.
  • the dielectric constant of the filling medium is 8
  • the center distance between the filling hole and the single-ended signal via hole is 25 mils
  • the diameter of the filling hole is 16 mils.
  • a pad is further included, and the filling hole is symmetrical with respect to the long handle of the pad.
  • the filling medium is resin
  • the filling hole is a through hole.
  • the present invention provides an electronic product, which includes an electronic product body and the printed circuit board described above.
  • the printed circuit board provided by the present invention includes a single-ended signal via hole arranged on a multilayer PCB and a filling hole arranged on the multilayer PCB and spaced a predetermined distance from the single-ended signal via hole.
  • the filling hole is used for filling
  • the filling medium for adjusting the impedance characteristics of single-ended signal vias. It can be seen that in this application, the impedance of the single-ended signal via can be adjusted by adjusting the size of the filling hole, adjusting the filling medium in the filling hole, adjusting the number of filling holes, and adjusting the position of the filling hole, compared with the existing In the technology, the adjustment parameters can only be adjusted by adjusting the via hole diameter and the size of the solder lug. When the impedance does not meet the requirements, it can be adjusted by adjusting the via hole diameter and the size of the solder lug, which effectively reduces waste. Risk of printed circuit board area.
  • FIG. 1 is a structural diagram of a printed circuit board provided by an embodiment of the present invention
  • FIG. 2 is a structural diagram of another printed circuit board provided by an embodiment of the present invention.
  • FIG. 3 is a comparison diagram of the loss value corresponding to a single filling hole provided by this embodiment
  • FIG. 5 is a comparison diagram of loss values corresponding to two filling holes provided by this embodiment.
  • FIG. 6 is a comparison diagram of impedance corresponding to two filling holes provided by an embodiment of the present invention.
  • the core of the present invention is to provide a printed circuit board for effectively reducing the area used for the printed circuit board during impedance adjustment.
  • the core of the present invention also provides an electronic product including the above-mentioned printed circuit board.
  • FIG. 1 is a structural diagram of a printed circuit board provided by an embodiment of the present invention. As shown in Figure 1, it includes a single-ended signal via 2 arranged on the multilayer PCB1, and also includes a filling hole 3 arranged on the multilayer PCB1 and separated from the single-ended signal via 2 by a predetermined distance, and the filling hole 3 It is used to fill the filling medium for adjusting the impedance characteristic of the single-ended signal via 2.
  • the single-ended signal via 2 is a hole penetrating through the multilayer PCB 1 for passing signal lines.
  • the number of layers of the PCB 1 is not limited, and it can be selected according to actual needs.
  • the number of single-ended signal vias 2 is not limited, and can be set according to different application scenarios and user requirements, and does not affect the implementation of this solution.
  • the filling hole 3 is also provided on the multilayer PCB1, and is on the same plane as the single-ended signal via 2. As shown in Figure 1, the shape, number and position of the filling hole 3 need to be determined according to the actual situation. This embodiment is not limited.
  • the filling hole 3 is filled with a filling medium, and the resistance of the via is changed by filling the medium.
  • the specific principle is that different filling mediums correspond to different dielectric constants, and different dielectric constants determine the size of the via impedance.
  • the filling medium is usually a solid filling medium, which may be resin, for example. Resin usually means that it has a softening or melting range after being heated.
  • the filling hole 3 mentioned in this embodiment may be a through hole or a groove. It is understandable that in addition to resin, other high dielectric constant materials can also be used as the filling medium, which does not affect the implementation of this solution.
  • the filling hole 3 provided in this embodiment can be selected to be provided on the PCB 1.
  • the filling hole 3 is filled with the filling medium, the signal line passes through the single-ended signal via 2.
  • the filling medium filled in the filling hole 3 will affect the external capacitance and inductance of the entire circuit board, that is, the single-ended signal can be adjusted.
  • the impedance characteristic of the hole 2 and the good impedance characteristic can reduce the reflection when the signal passes through the single-ended signal via 2 and realize a lower loss value.
  • the via impedance can be adjusted by only setting the filling hole 3 and the filling medium, and it can also be combined with the method of adjusting the via hole diameter and the solder tab size of the single-ended signal via 2.
  • the examples are not limited.
  • the printed circuit board provided in this embodiment includes a single-ended signal via hole arranged on a multilayer PCB and a filling hole arranged on the multilayer PCB and spaced a predetermined distance from the single-ended signal via hole.
  • the filling hole is used for filling
  • the filling medium for adjusting the impedance characteristics of single-ended signal vias. It can be seen that in this application, the impedance of the single-ended signal via can be adjusted by adjusting the size of the filling hole, adjusting the filling medium in the filling hole, adjusting the number of filling holes, and adjusting the position of the filling hole, compared with the existing In the technology, the adjustment parameters can only be adjusted by adjusting the via hole diameter and the size of the solder lug. When the impedance does not meet the requirements, it can be adjusted by adjusting the via hole diameter and the size of the solder lug, which effectively reduces waste. Risk of printed circuit board area.
  • the filling hole 3 is a round hole.
  • the shape of the filling hole 3 does not affect the via impedance, and the specific shape needs to be determined according to the actual use of the current PCB 1. Considering that the single-ended signal via 2 on the PCB1 is usually circular, the filling hole 3 is also a circular hole, which can effectively use the area of the PCB1.
  • the number of filling holes 3 is not limited. As shown in FIG. 1, the number of filling holes 3 is one.
  • the invention also provides another structure diagram of the printed circuit board. As shown in FIG. 2, there are two filling holes 3. Further, it also includes a pad 4, and the filling hole 3 is symmetrical with respect to the long handle 5 of the pad 4, as shown in FIG.
  • the dielectric constant of the filling medium is 12
  • the center distance between the filling hole 3 and the single-ended signal via 2 is 25 mils
  • the diameter of the filling hole 3 is 10 mils.
  • the center distance between the filled hole 3 of the PCB 1 and the single-ended signal via 2 refers to the distance between the center of the filled hole 3 and the center of the single short signal via 2.
  • FIG. 3 is a comparison diagram of the loss value corresponding to a single filled hole provided by this embodiment.
  • FIG. 4 is a comparison diagram of impedance corresponding to a single filling hole provided by an embodiment of the present invention. Wherein, in FIG. 3, the dotted line is the loss value before the filling hole is not provided, and the solid line is the loss value corresponding to the parameters provided in this embodiment. In FIG. 4, the dashed line is the impedance before the filling hole is provided, and the solid line is the impedance corresponding to the parameters provided in this embodiment.
  • the ordinate IL in Fig. 3 is the loss value, which reflects the improvement of the signal and can be clearly determined. Compared with no filling hole, one filling hole 3 is used, and the dielectric constant of the filling medium If it is 12, the center distance between the filled hole 3 and the single-ended signal via 2 is 25 mil, and the diameter of the filled hole 3 is 10 mil, the loss value is significantly reduced.
  • FIG. 2 there are two filling holes 3, and they are symmetrical with respect to the single-ended signal via 2, the dielectric constant of the filling medium is 8, and the filling hole 3 and the single-ended signal via The center distance of 2 is 25 mils, and the diameter of the filling hole 3 is 16 mils.
  • the center distance between the filled hole 3 of the PCB 1 and the single-ended signal via 2 refers to the distance between the center of the filled hole 3 and the center of the single short signal via 1.
  • FIG. 5 is a comparison diagram of loss values corresponding to two filled holes provided by this embodiment.
  • FIG. 6 is a comparison diagram of impedance corresponding to two filling holes provided by an embodiment of the present invention. Wherein, in FIG. 5, the dotted line is the loss value before the filling hole is not provided, and the solid line is the loss value corresponding to the parameters provided in this embodiment. In FIG. 6, the dashed line is the impedance before the filling hole is provided, and the solid line is the impedance corresponding to the parameters provided in this embodiment.
  • the ordinate IL in Figure 5 is the loss value, reflecting the improvement of the signal, which can be clearly determined.
  • the dielectric constant of the filling medium If it is 8, the center distance between the filled hole 3 and the single-ended signal via 2 is 25 mil, and the diameter of the filled hole 3 is 16 mil, the loss value is significantly reduced.
  • an embodiment of the present invention also provides an electronic product, which includes an electronic product body, and also includes the printed circuit board provided in any of the foregoing embodiments.
  • the main body of the electronic product in this embodiment may be an electronic device such as a server, and the printed circuit board realizes different functions by being connected to the corresponding hardware in the main body of the electronic product, which is not repeated in the present invention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种印刷电路板及电子产品，其中，印刷电路板包括设置于多层PCB上的单端讯号过孔，还包括设置于所述多层PCB上，并与所述单端讯号过孔间隔预设距离的填充孔，所述填充孔用于填充调整所述单端讯号过孔的阻抗特性的填充介质。通过调整填充孔的尺寸、调整填充孔中的填充介质、调整填充孔的数量以及调整填充孔的位置来调整单端讯号过孔的阻抗，相比于现有技术中只能通过调节过孔孔径和焊片尺寸的方式而言，调整的参数多样化，当阻抗不满足要求时，可以通过除调整过孔孔径和焊片尺寸的方式调整，有效降低了浪费印制电路板的面积的风险。

Description

一种印刷电路板及电子产品
本申请要求于2019年9月20日提交中国专利局、申请号为201910894956.3、发明名称为“一种印刷电路板及电子产品”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及单端讯号过孔技术领域，特别是涉及一种印刷电路板及电子产品。
背景技术
电子产品的设计离不开印刷电路板，现今电子产品设计趋势讲究高效能，讯号的传输速度逐年增快，使得印刷电路板的上的电路设计也越趋复杂。在印刷电路板迭层中，需要将传输线从单端讯号过孔中穿过，此时，讯号的传输质量除了受传输线的影响外，还受到其它因素的影响，例如讯号穿层过孔(负责讯号穿层)。良好的过孔阻抗，可大幅减少讯号的反射，因此单端讯号过孔阻抗设计，亦是一项相当重要的工作。
现有技术中，为了提高讯号的传输质量，通常采用调整过孔孔径或者调整焊片尺寸的方式，当过孔或者焊片的尺寸足够大时，可能存在浪费印制电路板的面积的问题。
由此可见，在进行阻抗调整时，如何避免上述问题是本领域技术人员亟待解决的问题。
发明内容
本发明的目的是提供一种印刷电路板用于在进行阻抗调整时，有效降低使用印制电路板的面积。此外，本发明的目的还提供一种包含上述印刷电路板的电子产品。
为解决上述技术问题，本发明提供一种印刷电路板，包括设置于多层PCB上的单端讯号过孔，还包括设置于所述多层PCB上，并与所述单端讯号过孔间隔预设距离的填充孔，所述填充孔用于填充调整所述单端讯号过 孔的阻抗特性的填充介质。
优选地，所述填充孔为圆孔。
优选地，所述填充孔为1个。
优选地，所述填充介质的介电常数为12，所述填充孔与所述单端讯号过孔的中心距为25mil，所述填充孔的直径为10mil。
优选地，所述填充孔为2个并关于所述单端讯号过孔对称。
优选地，所述填充介质的介电常数为8，所述填充孔与所述单端讯号过孔的中心距为25mil，所述填充孔的直径为16mil。
优选地，还包括焊盘，所述填充孔关于所述焊盘的长柄对称。
优选地，所述填充介质为树脂。
优选地，所述填充孔为通孔。
为解决上述技术问题，本发明提供一种电子产品，包括电子产品本体，还包括所述的印刷电路板。
本发明所提供的印刷电路板，包括设置于多层PCB上的单端讯号过孔和设置于多层PCB上，并与单端讯号过孔间隔预设距离的填充孔，填充孔用于填充调整单端讯号过孔的阻抗特性的填充介质。由此可见，本申请中，可以通过调整填充孔的尺寸、调整填充孔中的填充介质、调整填充孔的数量以及调整填充孔的位置来调整单端讯号过孔的阻抗，相比于现有技术中只能通过调节过孔孔径和焊片尺寸的方式而言，调整的参数多样化，当阻抗不满足要求时，可以通过除调整过孔孔径和焊片尺寸的方式调整，有效降低了浪费印制电路板的面积的风险。
附图说明
为了更清楚地说明本发明实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种印刷电路板的结构图；
图2为本发明实施例提供的另一种印刷电路板的结构图；
图3为本实施例提供的一种单个填充孔对应的损耗值的对比图；
图4为本发明实施例提供的一种单个填充孔对应的阻抗的对比图；
图5为本实施例提供的一种两个填充孔对应的损耗值的对比图；
图6为本发明实施例提供的一种两个填充孔对应的阻抗的对比图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下，所获得的所有其他实施例，都属于本发明保护范围。
本发明的核心是提供一种印刷电路板用于在进行阻抗调整时，有效降低使用印制电路板的面积。此外，本发明的核心还提供一种包含上述印刷电路板的电子产品。
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。
图1为本发明实施例提供的一种印刷电路板的结构图。如图1所示，包括设置于多层PCB1上的单端讯号过孔2，还包括设置于多层PCB1上，并与单端讯号过孔2间隔预设距离的填充孔3，填充孔3用于填充调整单端讯号过孔2的阻抗特性的填充介质。
在具体实施中，单端讯号过孔2是贯穿在多层PCB1上的孔，用于将信号线穿过，本实施例中，对于PCB1的层数不作限定，根据实际需求选取即可。另外，对于单端讯号过孔2的数量不作限定，可以根据不同的应用场景和用户需求自行设置，不影响本方案的实施。
需要说明的是，填充孔3也是设置在多层PCB1上，与单端讯号过孔2在同一个平面上，如图1所示，填充孔3的形状、数量和位置需要根据实际情况确定，本实施例不作限定。填充孔3中填充有填充介质，通过填充介质来改变过孔阻抗，具体原理是，不同的填充介质对应的介电常数不 同，而不同的介电常数决定了过孔阻抗的大小。在具体实施例中，填充介质通常选取固体填充介质，例如可以为树脂。树脂通常是指受热后有软化或熔融范围，软化时在外力作用下有流动倾向，常温下是固态。另外，本实施例中提到的填充孔3可以为通孔，也可以是凹槽。可以理解的是，除了树脂之外，其它高介电系数材料也可作为填充介质，不影响本方案的实施。
当单端讯号过孔2的阻抗不满足要求，且PCB1的面积较紧张时，可以选择在PCB1上设置本实施例提供的填充孔3。当填充孔3填充好填充介质后，讯号线穿过单端讯号过孔2，填充在填充孔3的填充介质就会影响整个电路板对外所呈现的电容和电感，即能够调整单端讯号过孔2的阻抗特性，良好的阻抗特性，可使得讯号在穿过单端讯号过孔2时，减少反射，实现较低的损耗值。需要说明的是，在具体实施中，可以通过只设置填充孔3和填充介质的方式调整过孔阻抗，还可以结合调整单端讯号过孔2的过孔孔径和焊片尺寸的方式，本实施例不作限定。
本实施例提供的印刷电路板，包括设置于多层PCB上的单端讯号过孔和设置于多层PCB上，并与单端讯号过孔间隔预设距离的填充孔，填充孔用于填充调整单端讯号过孔的阻抗特性的填充介质。由此可见，本申请中，可以通过调整填充孔的尺寸、调整填充孔中的填充介质、调整填充孔的数量以及调整填充孔的位置来调整单端讯号过孔的阻抗，相比于现有技术中只能通过调节过孔孔径和焊片尺寸的方式而言，调整的参数多样化，当阻抗不满足要求时，可以通过除调整过孔孔径和焊片尺寸的方式调整，有效降低了浪费印制电路板的面积的风险。
在上述实施例的基础上，作为优选地实施方式，填充孔3为圆孔。
可以理解的是，填充孔3的形状不影响过孔阻抗，具体的形状需要依据当前PCB1的实际使用情况确定。考虑到PCB1上的单端讯号过孔2通常是圆形的，所以填充孔3也为圆形孔，可以有效利用PCB1的面积。
上述实施例中，对于填充孔3的数量不作限定，如图1所示，填充孔 3为1个。本发明还提供另一种印刷电路板的结构图。如图2所示，填充孔3为2个。进一步的，还包括焊盘4，填充孔3关于焊盘4的长柄5对称，如图2所示。
在一种具体实施例中，填充孔3为1个，填充介质的介电常数为12，填充孔3与单端讯号过孔2的中心距为25mil，填充孔3的直径为10mil。
本实施例中，PCB1的填充孔3与单端讯号过孔2的中心距是指填充孔3的圆心与单短讯号过孔2的圆心的距离。图3为本实施例提供的一种单个填充孔对应的损耗值的对比图。图4为本发明实施例提供的一种单个填充孔对应的阻抗的对比图。其中，在图3中，虚线为未设置填充孔之前的损耗值，实线为采用本实施例提供的参数对应的损耗值。在图4中，虚线为未设置填充孔之前的阻抗，实线为采用本实施例提供的参数对应的阻抗。可以理解的是，图3中纵坐标IL为损耗值，反映讯号的改善程度，可以很明显的确定，相对于未设置填充孔而言，采用填充孔3为1个，填充介质的介电常数为12，填充孔3与单端讯号过孔2的中心距为25mil，填充孔3的直径为10mil的方案，损耗值明显降低。
在另一种具体实施例中，如图2所示，填充孔3为2个，且关于单端讯号过孔2对称，填充介质的介电常数为8，填充孔3与单端讯号过孔2的中心距为25mil，填充孔3的直径为16mil。
本实施例中，PCB1的填充孔3与单端讯号过孔2的中心距是指填充孔3的圆心与单短讯号过孔1的圆心的距离。图5为本实施例提供的一种两个填充孔对应的损耗值的对比图。图6为本发明实施例提供的一种两个填充孔对应的阻抗的对比图。其中，在图5中，虚线为未设置填充孔之前的损耗值，实线为采用本实施例提供的参数对应的损耗值。在图6中，虚线为未设置填充孔之前的阻抗，实线为采用本实施例提供的参数对应的阻抗。可以理解的是，图5中纵坐标IL为损耗值，反映讯号的改善程度，可以很明显的确定，相对于未设置填充孔而言，采用填充孔3为2个，填充介质的介电常数为8，填充孔3与单端讯号过孔2的中心距为25mil，填充孔3的直径为16mil的方案，损耗值明显降低。
最后，本发明实施例还提供一种电子产品，包括电子产品本体，还包括上述任意一实施例提供的印刷电路板。
需要说明的是，本实施例中的电子产品本体可以是服务器等电子设备，，印刷电路板通过与电子产品本体中的相应硬件连接实现不同的功能，本发明不再赘述。
以上对本发明所提供的印刷电路板及电子产品进行了详细介绍。说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。

Claims (10)

  1. 一种印刷电路板，包括设置于多层PCB上的单端讯号过孔，其特征在于，还包括设置于所述多层PCB上，并与所述单端讯号过孔间隔预设距离的填充孔，所述填充孔用于填充调整所述单端讯号过孔的阻抗特性的填充介质。
  2. 根据权利要求1所述的印刷电路板，其特征在于，所述填充孔为圆孔。
  3. 根据权利要求2所述的印刷电路板，其特征在于，所述填充孔为1个。
  4. 根据权利要求3所述的印刷电路板，其特征在于，所述填充介质的介电常数为12，所述填充孔与所述单端讯号过孔的中心距为25mil，所述填充孔的直径为10mil。
  5. 根据权利要求2所述的印刷电路板，其特征在于，所述填充孔为2个并关于所述单端讯号过孔对称。
  6. 根据权利要求5所述的印刷电路板，其特征在于，所述填充介质的介电常数为8，所述填充孔与所述单端讯号过孔的中心距为25mil，所述填充孔的直径为16mil。
  7. 根据权利要求6所述的印刷电路板，其特征在于，还包括焊盘，所述填充孔关于所述焊盘的长柄对称。
  8. 根据权利要求1所述的印刷电路板，其特征在于，所述填充介质为树脂。
  9. 根据权利要求1-8任意一项所述的印刷电路板，其特征在于，所述填充孔为通孔。
  10. 一种电子产品，包括电子产品本体，其特征在于，还包括权利要求1-9任意一项所述的印刷电路板。
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