1310668 …九、發明說明： 【發明所屬之技術領域】 本發明涉及一種差分過孔阻抗與差分導線阻抗匹配的方法。 【先前技術】 隨著資料通信速度的提高，錢完整㈣於資料傳輸的糊進行至關 重要。因此’彳5號元整性已經成爲印刷電路板（pantedcircuit B〇ard，PCBJ 設計必須考量的因素之-。元器件和PCB的參數、元件在pCB上的佈局等 因素，都會影響到信號的完整性，導致系統工作不穩定，甚至完全不工作。 如何在PCB的設計過程中充分考慮到信號完整性的因素，並採取有效的控 ΦΦ 制措施，已經成爲當今PCB設計業界中的一個熱門課題。對於PCB來講， 保持彳5號元整性最重要係阻抗的匹配和一致連續性。阻抗不連續會導致差 分導線信號的反射，過孔（via)係導致差分導線信號不連續的重要因素。 過孔（via)係多層PCB的重要組成部分之一，pCB上的每一個孔都可 以稱之爲過孔。從侧上看，過孔可时成_ >制作各層間的電氣 — 連接，二制作时的111定或定位。過録差分導線上纽爲阻抗不連續 的中斷點，會造成訊號的反射。一般過孔的等效阻抗比差分導線的阻抗低 12%左右，例如50歐姆的差分導線在經過過孔時阻抗會減小6歐姆（具體 和過孔的尺寸、板厚也有關，不是絕對減小）^在印刷電路板上，位於不同 佈線層間的兩條差分導線’將以過孔連接。此兩個過孔可稱爲差分過孔。 差分過孔結構亦造成訊號在通過時明顯的阻抗不匹配效應而影響訊號質 量。當訊號切換速度日益增快的時候，這種效應將更加嚴重。例如當25〇 毫伏的布階減透過差分過孔，即產生23毫伏的反射（約戰> 可見通 過差分過孔對訊號的影響係很重大的。此不連續反射可視爲一種阻抗不匹 配的結果。 若能將過孔的阻抗控制得和差分導線阻抗匹配，訊號反射就會降低， 訊號傳輸的質量就會提高，系統就會穩定工作。 【發明内容】 本發明提供一種差分過孔阻抗與差分導線阻抗匹配的方法，其中，該 6 ③ 1310668 方法包括以下步驟.咖差分過孔的互感公式和互容公式得出差分阻抗公 式；由差分導線阻抗和差分過孔阻抗相等得到兩過孔中心的距離和過孔半 徑的關係；仿真差分過孔阻抗與差分轉阻抗進行比較，不_整兩過孔 中心的距離和過孔半徑的值，得出雜抗㈣時的兩過孔中心的距離和過 孔半徑的值。 所述利用差分過孔阻抗與差分導線阻抗匹配的方法能將差分過孔的阻 抗控制得和差分導線的阻抗桃g&，反雜會大大降低，纖傳輸的質量 就會提面，系統就會穩定工作。 【實施方式】 如第-圖所示，係本發雜佳實施方式的差分過孔的示意圖，該示意圖 包括過孔焊盤30，反焊盤4G，差分導線5G，過孔導通柱⑹。由於差分過 孔的結構_雙金屬導線，其域和互容公式可依電磁理論推得如下： vC〇Sh (p) ’其中·"爲磁導率’ d爲兩過孔中心距離，r爲過孔半徑大 cosh-1 (d/2r)其中’ f爲介電常數，d.爲兩過孔中心距離，Γ爲過孔 半徑大小。差分過孔的特徵阻抗值可推導得： = 1⑷20，其中7=芒、7爲本徵阻抗、爲相對介電 ㊉數由於差分導線50的阻抗值已知，只要使差分導線5()的阻抗值與差 伤過孔的特徵阻抗值相等，就可以推出兩過孔中心距離d及過孔半徑大小r 的關係，改變兩過孔中心距離d及過孔半徑大小r的值，使差分過孔的特徵 阻抗值與差分導線5G的阻抗值树，就達到了祕配的效果。例如，以pCB 四層板的架構爲例，依據兩過孔中心距離d及過孔半徑大小【，已知差分導 線5〇的阻抗值爲腦歐姆，調整d、r的參數代入公式使過孔的特徵阻抗值 與差分導線50的阻抗麵等，再彻這_參數所確定的雜人到仿真軟 Q10668 體改變參數的值，當輪出的仿真軟體的輪出值與差分導線％的阻抗值最 爲接近時.差分舰阻抗，劇差分導線％ _抗和差分過孔的 阻抗基本随’這樣就可以減少減反射，達雖抗匹配的目的。其調節 前後的參數對比如下（表工）： 衣丄1310668 ... 9. Description of the Invention: [Technical Field] The present invention relates to a method of impedance matching between differential via impedance and differential wiring. [Prior Art] As the speed of data communication increases, the integrity of money (4) is crucial in the transmission of data. Therefore, '彳5 yuan integrity has become a printed circuit board (pantedcircuit B〇ard, PCBJ design must consider the factors - components and PCB parameters, components on the pCB layout and other factors, will affect the integrity of the signal Sexuality leads to unstable system operation or even no work at all. How to fully consider the signal integrity factor in the PCB design process and adopt effective ΦΦ control measures has become a hot topic in the PCB design industry today. For the PCB, the matching and consistent continuity of the most important impedance of the 彳5 element is maintained. The discontinuity of the impedance causes the reflection of the differential wire signal, and the via is an important factor that causes the differential wire signal to be discontinuous. Via is one of the important components of a multi-layer PCB. Each hole on the pCB can be called a via. From the side, the via can be made into a _ > electrical-connection between the layers. II. Fixed or positioned at the time of production. Over-recording the differential wire is a discontinuous point of impedance discontinuity, which will cause signal reflection. Generally, the equivalent impedance of the via is lower than that of the differential wire. The resistance is about 12% lower. For example, the 50 ohm differential wire will reduce the impedance by 6 ohms when passing through the via (specifically, the size of the via and the thickness of the via are not related to the absolute reduction). The two differential wires between the wiring layers will be connected by vias. These two vias can be called differential vias. The differential via structure also causes significant impedance mismatch effects when the signal passes, which affects the signal quality. This effect will be more severe when the speed is increasing. For example, when the 25 〇 millivolt step is reduced through the differential via, it produces a reflection of 23 millivolts (about war > visible through the differential vias on the signal) This system is very important. This discontinuous reflection can be regarded as a result of impedance mismatch. If the impedance of the via can be controlled to match the impedance of the differential conductor, the signal reflection will be reduced, the quality of the signal transmission will be improved, and the system will Stable operation. SUMMARY OF THE INVENTION The present invention provides a method for matching differential via impedance to differential wire impedance, wherein the 6 3 1310668 method includes the following steps. The mutual inductance formula and the mutual capacitance formula of the hole are used to obtain the differential impedance formula; the relationship between the distance between the center of the two via holes and the radius of the via hole is obtained by the difference between the differential wire impedance and the differential via impedance; the simulated differential via impedance is compared with the differential transimpedance. The distance between the center of the two via holes and the value of the via radius are not obtained, and the distance between the center of the two via holes and the value of the via radius at the time of the hybrid resistance (4) is obtained. The method of matching the differential via impedance with the differential line impedance The impedance of the differential via can be controlled to be the impedance of the differential conductor, and the anti-noise will be greatly reduced, the quality of the fiber transmission will be raised, and the system will work stably. [Embodiment] As shown in the figure - A schematic diagram of a differential via of the present embodiment, including a via pad 30, an anti-pad 4G, a differential lead 5G, and a via via (6). Due to the structure of the differential via _ bimetallic wire, its domain and mutual capacitance formula can be derived from the electromagnetic theory as follows: vC〇Sh (p) 'where ·" is the magnetic permeability 'd is the distance between two via centers, r The via radius is large cosh-1 (d/2r) where 'f is the dielectric constant, d. is the distance between the two via centers, and Γ is the size of the via radius. The characteristic impedance value of the differential via can be derived as: = 1(4)20, where 7= awn, 7 is the intrinsic impedance, and is the relative dielectric tens. Since the impedance value of the differential wire 50 is known, as long as the impedance of the differential wire 5() is made The value is equal to the characteristic impedance value of the differential wound via, and the relationship between the center distance d of the two via holes and the radius r of the via hole can be derived, and the values of the distance d between the center of the two via holes and the size of the via radius r are changed to make the differential vias The characteristic impedance value and the impedance value tree of the differential wire 5G achieve the effect of the secret match. For example, taking the architecture of the pCB four-layer board as an example, according to the distance between the center of the two via holes and the radius of the via hole, it is known that the impedance value of the differential wire 5〇 is brain ohm, and the parameters of adjusting d and r are substituted into the formula to make the via hole. The characteristic impedance value and the impedance surface of the differential conductor 50, etc., and then the value of the parametric parameter determined by the _ parameter to the simulated soft Q10668 body change value, when the rounded out simulation software has a round-off value and the differential wire % impedance value When it is closest, the differential ship impedance, the differential differential wire % _ and the resistance of the differential via are basically the same as 'this can reduce the anti-reflection, although the anti-matching purpose. The parameters before and after adjustment are as follows (table worker):
參數 ------ 過孔焊盤30 原本 ~ "-- 25 密爾（mil) 匹配後 20 密爾（mil) 過孔導通柱60 14 密爾（mii) 1〇 密爾（mil) 反焊盤40 36 密爾（mil) 40 密爾（mil) 兩過孔中心的距離d 介電 係數 30 密爾（mil) 38 密爾（mii) 4 /、t ’6G和反雜4G狀寸係俩舰雜3G和兩孔中 、二距離d決定’ t過孔焊盤30和兩過孔中心的距離d爲定值時，過孔導 通柱60和反焊盤40的尺寸與過孔焊盤％和兩過孔中心的距離d有關。 如第二圖所示’縣發縣分過餘抗與差分導雜抗她配方法的 較佳實施方式的流程圖。於步驟S21中，利用差分過孔减和互容公式得 出差分過孔阻抗公式Z峨> =念⑽A-1(,/2r)，其中”爲本徵阻抗、 〜爲相對介電常數、d兩過孔中心的距離、Γ過孔的半徑；Parameters ------ Via pad 30 Original ~ "-- 25 mil (mil) matched 20 mil (via) vias 60 14 mil (mii) 1 mil (mil) Anti-pad 40 36 mil 40 mil distance of the center of the two vias d dielectric coefficient 30 mil 38 mil (mii) 4 /, t '6G and anti-hybrid 4G The size and over-hole welding of the via-conducting post 60 and the anti-pad 40 are determined when the distance d between the via pad 30 and the center of the two vias is constant. The disk % is related to the distance d between the centers of the two via holes. As shown in the second figure, a flow chart of a preferred embodiment of the method of dividing the excess and the differential heterogeneous anti-matching method is performed. In step S21, the differential via resistance formula is obtained by using the differential via reduction and mutual capacitance formula. Z峨> =[10)A-1(,/2r), where "the intrinsic impedance, ~ is the relative dielectric constant, d the distance between the centers of the two vias and the radius of the through holes;
於步驟S22中’由差分導線和差分過孔阻抗相等得到的關係； >於步驟S2；3中，仿真出差分過孔阻抗值，並將其與差分導線阻抗值進 行比較’得出兩阻抗匹配時的d和r的值； 於步驟S24中，透過d和Γ的值確定出差分過孔的結構。 【圖式簡單說明】 第一圖係本發明較佳實施方式的差分過孔的示意圖。 第二圖係本發明差分過孔阻抗與差分導線阻抗相匹配方法的較佳實施 方式的流程圖。 【主要元件符號說明】 過孔焊盤 1310668 反焊盤 40 差分導線 50 過孔導通柱 60In step S22, 'the relationship obtained by equalizing the differential wire and the differential via hole impedance; > in step S2; 3, simulating the differential via hole impedance value and comparing it with the differential wire impedance value' to obtain two impedances The values of d and r at the time of matching; in step S24, the structure of the differential via is determined by the values of d and Γ. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic view of a differential via of a preferred embodiment of the present invention. The second figure is a flow chart of a preferred embodiment of the method for matching the differential via impedance to the differential lead impedance of the present invention. [Main component symbol description] Via pad 1310668 Anti-pad 40 Differential wire 50 Via via 60
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