WO2021035716A1 - 显示基板及显示面板 - Google Patents

显示基板及显示面板 Download PDF

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Publication number
WO2021035716A1
WO2021035716A1 PCT/CN2019/103799 CN2019103799W WO2021035716A1 WO 2021035716 A1 WO2021035716 A1 WO 2021035716A1 CN 2019103799 W CN2019103799 W CN 2019103799W WO 2021035716 A1 WO2021035716 A1 WO 2021035716A1
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Prior art keywords
light
circuit
display
transistor
emitting element
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Application number
PCT/CN2019/103799
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English (en)
French (fr)
Inventor
杨盛际
陈小川
王辉
黄冠达
卢鹏程
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/959,858 priority Critical patent/US11322092B2/en
Priority to PCT/CN2019/103799 priority patent/WO2021035716A1/zh
Priority to CN201980001568.6A priority patent/CN112823386B/zh
Priority to EP19933236.2A priority patent/EP4024380A4/en
Publication of WO2021035716A1 publication Critical patent/WO2021035716A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
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    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
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Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display panel.
  • Silicon-based organic light emitting diode (Organic Light Emitting Diode, OLED) micro display is an emerging branch of the display industry.
  • Silicon-based OLED micro display is a new type of OLED technology combined with CMOS (Complementary Metal Oxide Semiconductor) technology.
  • Display technology Silicon-based OLED micro-display devices are based on monocrystalline silicon chips, with small pixel size and much higher precision than traditional display devices.
  • Silicon-based OLED micro-displays have a broad market application space and are particularly suitable for use in helmet-mounted displays and stereoscopic display mirrors. And eye-type displays, etc.
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, the base substrate is a silicon substrate, and includes a display area, a sensing area, and a dummy area; at least part of the dummy area is located in the display area and the Between the sensing regions; a plurality of sensing pixel units are provided in the sensing region, at least one of the plurality of sensing pixel units includes a first light-emitting element and a first pixel circuit, the first The pixel circuit is connected to the first terminal of the first light-emitting element and the voltage sensor, and is configured to drive the first light-emitting element to emit light and control the voltage sensor to sense the voltage sensor of the first light-emitting element.
  • the first pixel circuit includes a first data writing circuit, a first driving circuit, and a first storage circuit, and the first data writing circuit is connected to the The control terminal of the first driving circuit is configured to write the first data signal into the control terminal of the first driving circuit under the control of the first scan signal; the second terminal of the first driving circuit is connected to the A first terminal of a first light-emitting element, the first driving circuit is configured to drive the first light-emitting element to emit light under the control of a voltage applied to the control terminal of the first driving circuit; the first storage circuit is connected The control terminal to the first drive circuit is configured to store the first data signal and hold it at the control terminal of the first drive circuit; the second pixel circuit includes a second data writing circuit, A second drive circuit and a second storage circuit, the second data writing circuit is connected to the control terminal of the second drive circuit, and is configured to write the second data signal into the The second end of the second drive circuit; the second end of the second drive circuit is connected
  • the first pixel circuit further includes a first reset circuit, and the first reset circuit is connected to the first end of the first light-emitting element and is configured to A first reset voltage is applied to the first terminal of the first light-emitting element under the control of the first reset control signal to reset the first terminal of the first light-emitting element;
  • the second pixel circuit further includes a second pixel circuit.
  • a reset circuit where the second reset circuit is configured to reset the first end of the second light-emitting element by using a second reset voltage under the control of a second reset control signal.
  • the second reset circuit is connected to the first end of the second light-emitting element, and is configured to reduce the second reset voltage under the control of the second reset control signal. Applied to the first end of the second light-emitting element to reset the first end of the second light-emitting element.
  • the second reset circuit is connected to the first end of the second drive circuit, and is configured to reduce the second reset voltage under the control of the second reset control signal. Applied to the first terminal of the second driving circuit to reset the first terminal of the second light-emitting element through the second driving circuit.
  • the second pixel circuit further includes a voltage control circuit, the voltage control circuit is connected to the first end of the second drive circuit, and is configured to control the voltage The first voltage is applied to the first end of the second driving circuit under the control of the signal.
  • the first data writing circuit includes a first data writing transistor
  • the first driving circuit includes a first driving transistor
  • the first storage circuit includes a first data writing transistor.
  • a storage capacitor the first reset circuit includes a first reset transistor
  • the control terminal of the first drive circuit includes the gate of the first drive transistor
  • the first terminal of the first drive circuit includes the first The first electrode of a driving transistor
  • the second end of the first driving circuit includes the second electrode of the first driving transistor
  • the gate of the first data writing transistor receives the first scan signal, so The first electrode of the first data writing transistor receives the first data signal, and the second electrode of the first data writing transistor is connected to the gate of the first driving transistor;
  • the first terminal is connected to the gate of the first driving transistor, the second terminal of the first storage capacitor is connected to the second terminal of the first driving transistor;
  • the gate of the first reset transistor receives the A first reset control signal, the first electrode of the first reset transistor receives the first reset voltage, and the second electrode of the first reset transistor is connected to the
  • the second data writing circuit includes a second data writing transistor
  • the second driving circuit includes a second driving transistor
  • the second storage circuit includes a second data writing transistor.
  • Two storage capacitors the second reset circuit includes a second reset transistor
  • the control terminal of the second drive circuit includes the gate of the second drive transistor
  • the first terminal of the second drive circuit includes the first The first pole of the two driving transistors
  • the second terminal of the second driving circuit includes the second pole of the second driving transistor
  • the gate of the second data writing transistor receives the second scan signal, so The first electrode of the second data writing transistor receives the second data signal, and the second electrode of the second data writing transistor is connected to the gate of the second driving transistor;
  • the first end is connected to the gate of the second driving transistor, the second end of the second storage capacitor is connected to the second electrode of the second driving transistor;
  • the gate of the second reset transistor receives the A second reset control signal, the first pole of the second reset transistor receives the second reset voltage, and the second pole of the second reset transistor is connected
  • the second data writing circuit includes a second data writing transistor
  • the second driving circuit includes a second driving transistor
  • the second storage circuit includes a second data writing transistor.
  • the second reset circuit includes a second reset transistor
  • the voltage control circuit includes a voltage control transistor
  • the control terminal of the second drive circuit includes the gate of the second drive transistor
  • the second The first terminal of the driving circuit includes the first pole of the second driving transistor
  • the second terminal of the second driving circuit includes the second pole of the second driving transistor
  • the gate of the second data writing transistor The first electrode of the second data writing transistor receives the second data signal
  • the second electrode of the second data writing transistor is connected to the second drive transistor.
  • the gate; the first end of the second storage capacitor is connected to the gate of the second drive transistor, and the second end of the second storage capacitor is connected to the ground; the gate of the second reset transistor receives For the second reset control signal, the first pole of the second reset transistor receives the second reset voltage, and the second pole of the second reset transistor is connected to the first pole of the second drive transistor;
  • the gate of the voltage control transistor receives the voltage control signal, the first electrode of the voltage control transistor receives the first voltage, and the second electrode of the voltage control transistor is connected to the first electrode of the second driving transistor. pole.
  • the sensing area, at least a part of the dummy area, and the display area are sequentially arranged along a first direction, and in the first direction, the sensing area
  • the size of the measurement area is between the size of the display area and the size of at least part of the virtual area.
  • the first pixel circuit further includes a sensing circuit connected to the first end of the first light-emitting element and configured to sense The voltage sensor is controlled to sense the voltage of the first terminal of the first light-emitting element under the control of the control signal.
  • the sensing circuit includes a sensing transistor, the gate of the sensing transistor receives the sensing control signal, and the first electrode of the sensing transistor is connected to To the voltage sensor, the second electrode of the sensing transistor is connected to the first end of the first light-emitting element.
  • the display substrate provided by the embodiment of the present disclosure further includes an adjustment circuit, wherein the adjustment circuit is configured to be based on the sensed voltage of the first terminal of the first light-emitting element and the temperature and the temperature of the display substrate.
  • the light-emitting brightness is preset, and the voltage provided by the common voltage terminal is adjusted.
  • the display substrate provided by the embodiment of the present disclosure further includes a light-shielding layer, wherein the light-shielding layer is at least disposed in the sensing area, and the light-shielding layer is located far from the plurality of sensing pixel units.
  • the light shielding layer is configured to shield light emitted from the sensing pixel unit of the sensing area.
  • the light-shielding layer includes a first light-shielding color film layer, a second light-shielding color film layer, and a third light-shielding color film layer.
  • the first light-shielding color film layer, the second light-shielding color film layer, and the third light-shielding color film layer are sequentially arranged on a side away from the base substrate, and the first light-shielding color film layer,
  • the orthographic projection of the overlapping area of the second light-shielding color film layer and the third light-shielding color film layer on the base substrate covers the sensing area;
  • the plurality of display pixel units includes a first display pixel unit , A second display pixel unit and a third display pixel unit, the first display pixel unit includes a first display color filter layer, the second display pixel unit includes a second display color filter layer, and the third display pixel unit It includes a third display color film layer, the first light-shielding color film layer and the first display color film layer have the same color filter characteristics, and the second light-shielding color film layer and the second display color film layer They have the same color filter characteristics, and the third light-shielding color film
  • the light-shielding layer includes a black light-shielding layer, and in a direction perpendicular to the base substrate, the orthographic projection of the black light-shielding layer on the base substrate Cover the sensing area.
  • the light-shielding layer is further disposed in the virtual area, and the light-shielding layer is located on a side of the plurality of virtual pixel units away from the base substrate
  • the light shielding layer is configured to shield light emitted from the virtual pixel unit of the virtual area.
  • the first light-emitting element and the second light-emitting element are the same or different; the first pixel circuit and the second pixel circuit are the same or different.
  • At least one embodiment of the present disclosure provides a display panel including the display substrate according to any one of the above-mentioned embodiments.
  • FIG. 1 is a schematic block diagram of a display substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic block diagram of the sensing pixel unit in FIG. 1;
  • FIG. 3 is a circuit structure diagram of the sensing pixel unit in FIG. 2;
  • FIG. 4 is a timing diagram of signals input to the first pixel circuit in FIG. 3;
  • 5A is an equivalent circuit diagram of the first pixel circuit in FIG. 3 in the reset stage
  • 5B is an equivalent circuit diagram of the first pixel circuit in FIG. 3 in the data writing stage
  • 5C is an equivalent circuit diagram of the first pixel circuit in FIG. 3 in the light-emitting stage
  • FIG. 5D is an equivalent circuit diagram of the first pixel circuit in FIG. 3 in the sensing phase
  • FIG. 6 is a schematic block diagram of the display pixel unit in FIG. 1;
  • FIG. 7 is a circuit structure diagram of the display pixel unit shown in FIG. 6;
  • FIG. 8 is another schematic block diagram of the display pixel unit in FIG. 1;
  • FIG. 9 is a circuit structure diagram of the display pixel unit shown in FIG. 8;
  • FIG. 10 is a schematic block diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a planar structure of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 12A is a schematic diagram of a cross-sectional structure of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 12B is a schematic diagram of another cross-sectional structure of another display substrate provided by an embodiment of the present disclosure.
  • 12C is a schematic diagram of another cross-sectional structure of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of another cross-sectional structure of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a flowchart of a method for adjusting voltage of a display substrate according to an embodiment of the disclosure.
  • An embodiment of the present disclosure provides a display substrate including a base substrate, a plurality of display pixel units, and a plurality of sensing pixel units.
  • the base substrate is a silicon substrate and includes a display area, a sensing area and a dummy area, and at least a part of the dummy area is located between the display area and the sensing area.
  • a plurality of sensing pixel units are provided in the sensing area, at least one of the plurality of sensing pixel units includes a first light-emitting element and a first pixel circuit, the first pixel circuit is connected to the first end of the first light-emitting element and The voltage sensor is configured to drive the first light-emitting element to emit light and control the voltage sensor to sense the voltage of the first terminal of the first light-emitting element.
  • a plurality of display pixel units are provided in the display area, at least one of the plurality of display pixel units includes a second pixel circuit and a second light-emitting element, and the second pixel circuit is connected to the first end of the second light-emitting element and is configured To drive the second light-emitting element to emit light to display an image.
  • a plurality of virtual pixel units are provided in the virtual area, and at least one of the plurality of virtual pixel units includes a third pixel circuit and a third light-emitting element.
  • the third pixel circuit is the same as the second pixel circuit, and the third light-emitting element is the same as the second pixel circuit.
  • the light-emitting elements are the same, and the third pixel circuit is not connected to the third light-emitting element.
  • the second end of the first light-emitting element, the second end of the second light-emitting element, and the second end of the third light-emitting element form an integrated structure; the integrated structure is connected to the common voltage terminal and covers at least the display area, the sensing area, and At least part of the virtual area located between the display area and the sensing area.
  • the display substrate provided by the embodiment of the present disclosure can adjust the second light-emitting element of the second light-emitting element in the display pixel unit based on the temperature of the display substrate, the preset light-emitting brightness, and the sensed voltage at the first end of the first light-emitting element.
  • the voltage provided by the common voltage terminal connected to the terminal enables the second light-emitting element in the display pixel unit to achieve a preset light-emitting brightness under a certain temperature condition, so that the display substrate can display image information with a gamma value of 2.2 in real time.
  • FIG. 1 is a schematic block diagram of a display substrate provided by an embodiment of the disclosure.
  • the display substrate includes a base substrate 10, a plurality of sensing pixel units 20, and a plurality of display pixel units 30.
  • the base substrate 10 is a silicon substrate and includes a sensing area 11, a display area 12, and a dummy area. 13.
  • a plurality of sensing pixel units 20 are arranged in the sensing area 11, and a plurality of display pixel units 30 are arranged in the display area 12.
  • the area on the base substrate 10 excluding the sensing area 11 and the display area 12 is a dummy area 13, and the sensing area and the display area 12 are separated by at least a part of the dummy area 13.
  • the provision of the dummy area 13 can avoid short-circuiting of components in the sensing area 11 and the display area 12 that need to be insulated from each other, and facilitate the packaging of the display substrate and improve the packaging effect.
  • At least one of the plurality of sensing pixel units 20 may include a first pixel circuit 21 and a first light-emitting element 22.
  • each sensing pixel unit 20 may also include The first pixel circuit 21 and the first light-emitting element 22.
  • the first pixel circuit 21 is connected to the first terminal of the first light-emitting element 22 and a voltage sensor (not shown in the figure), and is configured to drive the first light-emitting element 22 to emit light, and control the voltage sensor to sense the first The voltage of the first terminal of the light-emitting element 22.
  • At least one of the plurality of display pixel units 30 may include a second pixel circuit 31 and a second light-emitting element 32.
  • each display pixel unit 30 may also include a second pixel circuit.
  • the second pixel circuit 31 is connected to the first end of the second light-emitting element 32 and is configured to drive the second light-emitting element 32 to emit light to display an image.
  • the first light-emitting element 22 included in the sensing pixel unit 20 and the second light-emitting element 32 included in the display pixel unit 30 may be the same light-emitting element and different light-emitting elements, and the first pixel included in the sensing pixel unit 20
  • the circuit 21 and the second pixel circuit 31 included in the display pixel unit 30 may be the same pixel circuit or different pixel circuits, which is not limited in the embodiment of the present disclosure.
  • sensing pixel unit 20 and one display pixel unit 30 are shown in FIG. 1, but the number of sensing pixel units 20 and display pixel units 30 is obviously not limited to this, and can be based on It is necessary to provide an appropriate number of sensing pixel units 20 and display pixel units 30.
  • a plurality of dummy pixel units may be provided in at least part of the dummy area 13, and at least one of the plurality of dummy pixel units may include a third light-emitting element and a third pixel circuit.
  • each virtual pixel unit may also include a third light-emitting element and a third pixel circuit, so as to ensure the same uniformity as the display area 12.
  • the third light-emitting element in the first part of the dummy area 13 has the same structure as the second light-emitting element 32 in the display area 12, and
  • the third pixel circuit in the first part of the area 13 and the second pixel circuit 31 in the display area 12 have the same structure.
  • the difference from the sensing area and the display area 12 is that in the first part of the dummy area 13, the third light-emitting element is not electrically connected to the third pixel circuit.
  • the cathode pattern can be set.
  • the second end of the first light-emitting element 22 included in the sensing pixel unit 20, the second end of the second light-emitting element 32 included in the display pixel unit, and the second end of the third light-emitting element included in the dummy pixel unit Both are connected to the common voltage terminal (not shown in the figure).
  • the second end of the first light-emitting element 22, the second end of the second light-emitting element 32, and the second end of the third light-emitting element may be integrated into a structure that is connected to the common voltage terminal and covers at least the sensing area 11.
  • the silicon substrate may be a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate.
  • the silicon substrate includes a first pixel circuit 21 and a second pixel circuit 31, that is, the first pixel circuit 21 and the second pixel circuit 31 are prepared in the silicon substrate.
  • any applicable circuit components such as gate drive circuits and data drive circuits can also be integrated on the silicon substrate.
  • These circuit components ie, the first pixel circuit 21, the second pixel circuit 31, the gate drive circuit, the data drive circuit, etc.
  • Etc. silicon semiconductor process
  • it is prepared by a silicon semiconductor process (for example, a CMOS process), which is not limited in the embodiments of the present disclosure.
  • the first light-emitting element 22 and the second light-emitting element 32 may be the same light-emitting element, and the first pixel circuit 21 except for the first pixel circuit 21 that can sense the first light-emitting element 22 Except for the voltage sensing structure at the terminal, the rest of the structure can be basically the same or similar to the second pixel circuit 31, that is, when writing the same data signal to the first pixel circuit 21 and the second pixel circuit 31 In this case, the voltage at the first end of the first light-emitting element 22 sensed by the first pixel circuit 21 controlled by the voltage sensor is actually equivalent to the voltage at the first end of the second light-emitting element 32.
  • a display substrate provided by an embodiment of the present disclosure may further include an adjustment circuit (not shown in the figure), and the adjustment circuit is configured to be based on the temperature of the display substrate, preset light-emitting brightness, and the sensed first light-emitting element 22 to adjust the voltage provided by the common voltage terminal connected to the second terminal of the second light-emitting element 32 in the display pixel unit 30, so that the second light-emitting element 32 in the display pixel unit 30 can be at a certain
  • the preset luminous brightness is reached under the temperature condition.
  • the preset light-emitting brightness is determined by the data signal applied to the second pixel circuit 31, and the preset light-emitting brightness represents the desired brightness that the second light-emitting element 32 can achieve.
  • the relationship between the preset light-emitting brightness, the temperature of the display substrate and the data signal can be preset.
  • the temperature of the display substrate represents the temperature inside the device when the display substrate is in the working state, which can be detected by a temperature sensor arranged in the virtual area 13 of the driving chip or the base substrate 10.
  • the voltage sensor and the regulating circuit can be separately provided, or can be integrated into the same IC (Integrated Circuit, integrated circuit) chip.
  • the light-emitting characteristics of the light-emitting element ie, the first light-emitting element 22 or the second light-emitting element 32
  • the light-emitting characteristics will be affected by the temperature of the display substrate, and have different characteristics under different temperature conditions.
  • Light-emitting characteristics specifically, when the voltage difference between the voltage at the first terminal and the voltage at the second terminal of the light-emitting element is constant, as the temperature of the display substrate changes, the light-emitting brightness of the light-emitting element is different.
  • the light-emitting brightness of the light-emitting element, the temperature of the display substrate, and the voltage difference between the voltage at the first end of the light-emitting element and the voltage at the second end of the light-emitting element are in a corresponding relationship with each other.
  • the voltage difference between the voltage at the first terminal and the voltage at the second terminal of the light-emitting element can be increased to increase the light-emitting brightness of the light-emitting element; when the temperature of the display substrate is relatively high At this time, the light-emitting brightness of the light-emitting element can be reduced by reducing the voltage difference between the voltage of the first terminal and the voltage of the second terminal of the light-emitting element.
  • the voltage of the first terminal of the first light-emitting element 22 (that is, the first terminal of the second light-emitting element 32) sensed by the first pixel circuit 21 is controlled by the voltage sensor. Voltage) and the common voltage provided by the common voltage terminal to which the second terminal of the second light-emitting element 32 is connected, the actual voltage between the current voltage of the first terminal of the second light-emitting element 32 and the voltage of the second terminal can be obtained According to the current temperature of the display substrate and the preset light-emitting brightness sensed by the temperature sensor, the first end of the second light-emitting element 32 corresponding to the preset light-emitting brightness can be determined at the current display substrate temperature.
  • the preset voltage difference between the voltage at the second terminal and the voltage at the second terminal If the actual voltage difference is not the same as the preset voltage difference, the magnitude of the common voltage provided by the common voltage terminal can be adjusted to change the second light-emitting element 32
  • the actual voltage difference between the voltage at the first terminal and the voltage at the second terminal makes the actual voltage difference the same as the preset voltage difference, so that the luminous brightness of the second light-emitting element 32 is the same as the current temperature of the display substrate. correspond.
  • the first pixel circuit 21 controls the voltage sensor to sense the voltage of the first terminal of the first light-emitting element 22, and since the first pixel circuit 21 can sense the first end of the light-emitting element 22 Except for the voltage sensing structure of the first terminal of a light-emitting element 22, the rest of the structure is basically the same or similar to that of the second pixel circuit 31. Therefore, the same is written to the first pixel circuit 21 and the second pixel circuit 31.
  • the voltage at the first end of the first light-emitting element 22 sensed by the voltage sensor is equivalent to the voltage at the first end of the second light-emitting element 32, so that there is no need to add additional information to the second pixel circuit 31.
  • the sensing structure is provided to directly sense the voltage of the first terminal of the second light-emitting element 32 to prevent the additional sensing structure from affecting the display performance of the display pixel unit 30.
  • FIG. 2 is a schematic block diagram of the sensing pixel unit 20 in FIG. 1.
  • the first pixel circuit 21 includes a first reset circuit 210, a first data writing circuit 220, a first driving circuit 230, a first storage circuit 240, and a sensing circuit 250. .
  • the first reset circuit 210 is connected to the first reset control signal line RST1, the first reset voltage terminal VINT1, the second terminal of the first driving circuit 230, and the first terminal of the first light-emitting element 22, and is configured To apply the first reset voltage to the second terminal of the first driving circuit 230 and the first terminal of the first light-emitting element 22 under the control of the first reset control signal to reset the second terminal of the first driving circuit 230, That is, the first end of the first light-emitting element 22 is reset.
  • the first data writing circuit 220 is connected to the first scan signal line SCAN1, the first data signal line DATA1, and the control terminal of the first driving circuit 230, and is configured to be controlled by the first scan signal The first data signal is written into the control terminal of the first driving circuit 230.
  • the first terminal of the first driving circuit 230 is connected to the first voltage terminal VDD
  • the second terminal of the first driving circuit 230 is connected to the first terminal of the first light-emitting element 22
  • the first driving circuit 230 is It is configured to drive the first light emitting element 22 to emit light under the control of the voltage applied to the control terminal of the first driving circuit 230.
  • the first storage circuit 240 is connected to the control terminal and the second terminal of the first driving circuit 230 and is configured to store the first data signal and hold it at the control terminal of the first driving circuit 230.
  • the sensing circuit 250 is connected to the voltage sensor VSEN, the sensing control signal line SENS, the second end of the first driving circuit 230, and the first end of the first light emitting element 22, and is configured to sense Under the control of the sensing control signal, the voltage sensor VSEN is used to sense the voltage of the second terminal of the first driving circuit 230, that is, the voltage of the first terminal of the first light-emitting element 22 is sensed.
  • the first terminal of the first light-emitting element 22 is connected to the second terminal of the first driving circuit 230, and the second terminal of the first light-emitting element 22 is connected to the common voltage terminal VCOM.
  • FIG. 3 is a circuit structure diagram of the sensing pixel unit 20 in FIG. 2.
  • the first reset circuit 210 includes a first reset transistor Tr1
  • the first data writing circuit 220 includes a first data writing transistor Tw1.
  • the driving circuit 230 includes a first driving transistor Td1
  • the first storage circuit 240 includes a first storage capacitor C1
  • the sensing circuit 250 includes a sensing transistor Ts.
  • the first light-emitting element 22 includes a first OLED D1.
  • control terminal of the first driving circuit 230 includes the gate of the first driving transistor Td1
  • first terminal of the first driving circuit 230 includes the first terminal of the first driving transistor Td1
  • second terminal of the first driving circuit 230 includes The second electrode of the first driving transistor Td1
  • first end of the first light-emitting element 22 includes the anode of the first OLED D1
  • the second end of the first light-emitting element 22 includes the cathode of the first OLED D1.
  • the gate of the first reset transistor Tr1 is connected to the first reset control signal line RST1 to receive the first reset control signal, and the first pole of the first reset transistor Tr1 is connected to the first reset voltage terminal VINT1 to receive To reset the voltage, the second electrode of the first reset transistor Tr1 is connected to the second electrode of the first driving transistor Td1 and the anode of the first OLED D1.
  • the gate of the first data writing transistor Tw1 is connected to the first scan signal line SCAN1 to receive the first scan signal, and the first electrode of the first data writing transistor Tw1 is connected to the first data signal line DATA1 To receive the first data signal, the second electrode of the first data writing transistor Tw1 is connected to the gate of the first driving transistor Td1.
  • the gate of the first driving transistor Td1 is connected to the second electrode of the first data writing transistor Tw1
  • the first electrode of the first driving transistor Td1 is connected to the first voltage terminal VDD
  • the first driving transistor Td1 The second pole of is connected to the anode of the first OLED D1.
  • the first end of the first storage capacitor C1 is connected to the second electrode of the first data writing transistor Tw1 and the gate of the first driving transistor Td1, and the second end of the first storage capacitor C1 is connected to the second electrode of the first drive transistor Td1.
  • the gate of the sensing transistor Ts is connected to the sensing control signal line SENS to receive the sensing control signal
  • the first pole of the sensing transistor Ts is connected to the voltage sensor VSEN
  • the first pole of the sensing transistor Ts is connected to the voltage sensor VSEN.
  • the two poles are connected to the second pole of the first driving transistor Td1 and the anode of the first OLED D1.
  • the anode of the first OLED D1 is connected to the second electrode of the first driving transistor Td1, and the cathode of the first OLED D1 is connected to the common voltage terminal VCOM.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors used in the embodiments of the present disclosure can all be P-type transistors or N-type transistors, and it is only necessary to refer to the respective poles of the transistors of the selected type with reference to the respective transistors in the embodiments of the present disclosure. Connect the poles accordingly, and make the corresponding voltage terminals provide the corresponding high voltage or low voltage.
  • N-type transistor its (current) input terminal is the drain and its output terminal is the source, and its control terminal is the gate
  • a P-type transistor its (current) input terminal is the source and the output terminal is the drain.
  • And its control terminal is the gate.
  • the level of the control signal at the control terminal is also different.
  • N-type transistor when the control signal is at a high level, the N-type transistor is in an on state; and when the control signal is at a low level, the N-type transistor is in an off state.
  • P-type transistor when the control signal is at a low level, the P-type transistor is in an on state; and when the control signal is at a high level, the P-type transistor is in an off state.
  • oxide semiconductors such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), can be used as the active layer of thin film transistors.
  • Low-temperature polysilicon generally refers to a situation where the crystallization temperature of polysilicon obtained from the crystallization of amorphous silicon is lower than 600 degrees Celsius.
  • FIG. 4 is a timing chart of signals input to the first pixel circuit shown in FIG. 3.
  • the working process of the first pixel circuit 21 includes three stages, namely the reset stage P1, the data writing stage P2, the light-emitting stage P3, and the sensing stage P4. The timing waveform of each signal.
  • FIG. 5A is an equivalent circuit diagram of the first pixel circuit shown in FIG. 3 in the reset stage
  • FIG. 5B is an equivalent circuit diagram of the first pixel circuit shown in FIG. 3 in the data writing stage
  • FIG. 5C is the equivalent circuit diagram shown in FIG. 3 An equivalent circuit diagram of the first pixel circuit in the light-emitting stage
  • FIG. 5D is an equivalent circuit diagram of the first pixel circuit shown in FIG. 3 in the sensing stage.
  • FIG. 4 and FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D RST1, SCAN1, SENS, and DATA1 are used to indicate corresponding signal lines and signals.
  • FIG. 5A, FIG. 5B/ FIG. 5C, and FIG. 5D VINT1, VDD, and VCOM are used to represent the corresponding voltage terminals as well as the corresponding voltages.
  • the transistors marked with "x" in FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D all indicate that the transistor is in the off state in the corresponding stage.
  • N-type transistors are used as an example, in conjunction with FIG. 4 and FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D.
  • the working principle of the first pixel circuit 21 shown in FIG. 3 will be described.
  • a high-level first reset control signal RST1 is input to the gate of the first reset transistor Tr1 (ie, the first reset circuit 210), and a high-level first reset control signal RST1 is input to the sensing transistor Ts (ie, the sensing circuit 210).
  • the gate of 250) inputs a low-level sensing control signal SENS, and a low-level first scan signal SCAN1 is input to the gate of the first data writing transistor Tw1 (ie, the first data writing circuit 220).
  • the first reset transistor Tr1 is turned on by the high level of the first reset control signal RST1, and the sensing transistor Ts is turned off by the low level of the sensing control signal SENS.
  • a data writing transistor Tw1 is turned off by the low level of the first scan signal SCAN1, and at the same time, the first driving transistor Td1 is also turned off.
  • the first reset voltage VINT1 can be applied to the second electrode of the first drive transistor Td1 through the first reset transistor Tr1 (ie, the first drive transistor).
  • the second terminal of the circuit 230) and the anode of the first OLED D1 are used to reset the second electrode of the first driving transistor Td1 and the anode of the first OLED D1.
  • the first scan signal SCAN1 of high level is input to the gate of the first data writing transistor Tw1
  • the first scan signal SCAN1 of low level is input to the gate of the first reset transistor Tr1.
  • a reset control signal RST1 inputs a low-level sensing control signal SENS to the gate of the sensing transistor Ts.
  • the first data writing transistor Tw1 is turned on by the high level of the first scan signal SCAN1, and the first reset transistor Tr1 is turned on by the low level of the first reset control signal RST1.
  • the sensing transistor Ts is turned off by the low level of the sensing control signal SENS.
  • the first data signal DATA1 is written into the gate of the first driving transistor Td1 through the first data writing transistor Tw1, and at the same time A data signal DATA1 charges the first storage capacitor C1 (that is, the first storage circuit 240) through the first data writing transistor Tw1 until the voltage at the first end of the first storage capacitor C1 is Vdata1, thereby converting the first data signal DATA1 is stored in the first storage capacitor C1, and the first storage capacitor C1 holds the stored first data signal DATA1 at the gate of the first driving transistor Td1.
  • Vdata1 represents the voltage of the first data signal DATA1.
  • a low-level first scan signal SCAN1 is input to the gate of the first data writing transistor Tw1, and a low-level first reset is input to the gate of the first reset transistor Tr1.
  • the control signal RST1 inputs a low-level sensing control signal SENS to the gate of the sensing transistor Ts.
  • the first data writing transistor Tw1 is turned off by the low level of the first scan signal SCAN1
  • the first reset transistor Tr1 is turned off by the low level of the first reset control signal RST1
  • the sensing transistor Ts is turned off by the low level of the sensing control signal SENS.
  • the voltage of the gate of the first driving transistor Td1 is Vdata1.
  • a driving transistor Td1 is turned on, and the first voltage VDD drives the first light-emitting element 22 to emit light through the first driving transistor Td1.
  • a high-level sensing control signal SENS is input to the gate of the sensing transistor Ts (ie, the sensing circuit 250) to turn on the sensing transistor Ts, and writing to the first data
  • a low-level first scan signal SCAN1 is input to the gate of the input transistor Tw1
  • a low-level first reset control signal RST1 is input to the gate of the first reset transistor Tr1.
  • the sensing transistor Ts is turned on by the high level of the sensing control signal SENS, and the first data writing transistor Tw1 is turned off by the low level of the first scan signal SCAN1 , The first reset transistor Tr1 is turned off by the low level of the first reset control signal RST1.
  • the voltage sensor VSEN senses the voltage of the second electrode of the first driving transistor Td1 or the anode of the first OLED D1 through the sensing transistor Ts .
  • the sensing phase P4 may be a part of the light-emitting phase P3, that is, in the light-emitting phase P3, when the sensing transistor Ts is turned on by the high level of the sensing control signal SENS, the first pixel circuit 21 also enters the sensing phase P4 at the same time.
  • the voltage sensor VSEN can sense the voltage of the anode of the first OLED D1 in the light-emitting state through the sensing transistor Ts in real time.
  • the first driving transistor Td1 operates in the sub-threshold region, and the driving current generated by the first driving transistor Td1 can be obtained according to the following formula:
  • I L represents the drive current
  • Vth represents the threshold voltage of the first drive transistor Td1
  • Vgs represents the voltage difference between the gate and the second electrode (such as the source) of the first drive transistor Td1
  • Vs represents the voltage of the second electrode of the first drive transistor Td1
  • q is the amount of electrons (a constant value)
  • n is the channel doping concentration of the first drive transistor Td1
  • k is one
  • T is the operating temperature of the first driving transistor Td1 (that is, the temperature of the display substrate).
  • the current flowing through the first OLED D1 can be obtained according to the following formula:
  • I oled represents the current flowing through the first OLED D1
  • Voled represents the voltage difference between the anode and the cathode of the first OLED D1
  • Io2 represents the current flowing through the first OLED D1 at the moment when the first OLED D1 is turned on.
  • Vcom represents the voltage provided by the common voltage terminal VCOM
  • T is the operating temperature of the first OLED D1 (that is, the temperature of the display substrate).
  • the voltage Vs of the second electrode of the first driving transistor Td1 is equal to the voltage Vdata1 of the gate of the first driving transistor Td1.
  • V s a ⁇ Vdata1+b
  • a and b are both constants. That is, the voltage of the second electrode of the first driving transistor Td1 linearly changes following the change of the voltage of the gate of the first driving transistor Td1. Therefore, the voltage written to the gate of the first driving transistor Td1 (that is, the voltage of the first data signal DATA1) is different, and the voltage Vs of the second electrode of the first driving transistor Td1 is also different.
  • the pass voltage The sensor VSEN senses the voltage Vs of the second electrode of the first driving transistor Td1, that is, senses the voltage of the anode of the first OLED D1, and adjusts the common voltage provided by the common voltage terminal VCOM on this basis.
  • the voltage difference between the two poles of an OLED D1 adjusts the light-emitting brightness of the first OLED D1.
  • FIG. 6 is a schematic block diagram of the display pixel unit 30 in FIG. 1.
  • the second pixel circuit 31 includes a second reset circuit 310, a second data writing circuit 320, a second driving circuit 330, and a second storage circuit 340. Except that the display pixel unit 30 shown in FIG. 6 does not include a sensing circuit, the remaining components are basically the same as or similar to the sensing pixel unit 20 shown in FIG. 2.
  • the second reset circuit 310 is connected to the second reset control signal line RST2, the second reset voltage terminal VINT2, the second terminal of the second driving circuit 330, and the first terminal of the second light-emitting element 32, and is configured To apply a second reset voltage to the second terminal of the second driving circuit 330 and the first terminal of the second light-emitting element 32 under the control of the second reset control signal to reset the second terminal of the second driving circuit 330, That is, the first end of the second light-emitting element 32 is reset.
  • the second data writing circuit 320 is connected to the second scan signal line SCAN2, the second data signal line DATA2, and the control terminal of the second driving circuit 330, and is configured to be controlled by the second scan signal The second data signal is written into the control terminal of the second driving circuit 330.
  • the first terminal of the second driving circuit 330 is connected to the first voltage terminal VDD
  • the second terminal of the second driving circuit 330 is connected to the first terminal of the second light-emitting element 32
  • the second driving circuit 330 is connected to the first terminal of the second light emitting element 32. It is configured to drive the second light emitting element 32 to emit light under the control of the voltage applied to the control terminal of the second driving circuit 330.
  • the second storage circuit 340 is connected to the control terminal and the second terminal of the second driving circuit 330 and is configured to store the second data signal and hold it at the control terminal of the second driving circuit 330.
  • the first end of the second light emitting element 32 is connected to the second end of the second driving circuit 330, and the second end of the second light emitting element 32 is connected to the common voltage terminal VCOM.
  • FIG. 7 is a circuit structure diagram of the display pixel unit 30 shown in FIG. 6.
  • the second reset circuit 310 includes a second reset transistor Tr2
  • the second data writing circuit 320 includes a second data writing transistor Tw2
  • the second driving circuit 330 includes a second driving transistor.
  • the transistor Td2 and the second storage circuit 340 include a second storage capacitor C2.
  • the second light-emitting element 32 includes a second OLED D2. Except that the circuit of the display pixel unit 30 shown in FIG. 7 does not include a sensing transistor, the rest of the circuit structure is basically the same as or similar to that of the sensing pixel unit 20 shown in FIG. 3.
  • control terminal of the second driving circuit 330 includes the gate of the second driving transistor Td2, the first terminal of the second driving circuit 330 includes the first terminal of the second driving transistor Td2, and the second terminal of the second driving circuit 330 includes The second electrode of the second driving transistor Td2; the first end of the second light-emitting element 32 includes the anode of the second OLED D2, and the second end of the second light-emitting element 32 includes the cathode of the second OLED D2.
  • the gate of the second reset transistor Tr2 is connected to the second reset control signal line RST2 to receive the second reset control signal, and the first pole of the second reset transistor Tr2 is connected to the second reset voltage terminal VINT2 to receive For the second reset voltage, the second electrode of the second reset transistor Tr2 is connected to the second electrode of the second driving transistor Td2 and the anode of the second OLED D2.
  • the gate of the second data writing transistor Tw2 is connected to the second scanning signal line SCAN2 to receive the second scanning signal, and the first electrode of the second data writing transistor Tw2 is connected to the second data signal line DATA2 To receive the second data signal, the second electrode of the second data writing transistor Tw2 is connected to the gate of the second driving transistor Td2.
  • the gate of the second driving transistor Td2 is connected to the second electrode of the second data writing transistor Tw2, the first electrode of the second driving transistor Td2 is connected to the first voltage terminal VDD, and the second driving transistor Td2 The second pole of is connected to the anode of the second OLED D2.
  • the first end of the second storage capacitor C2 is connected to the second electrode of the second data writing transistor Tw2 and the gate of the second driving transistor Td2, and the second end of the second storage capacitor C2 is connected to the second electrode of the second drive transistor Td2.
  • the anode of the second OLED D2 is connected to the second electrode of the second driving transistor Td2, and the cathode of the second OLED D2 is connected to the common voltage terminal VCOM.
  • the working process of the second pixel circuit 31 in FIG. 7 includes a reset phase, a data writing phase, and a light-emitting phase.
  • the working process of the second pixel circuit 31 in FIG. 7 does not include a sensing phase, and other phases are the same as those in FIG. 3
  • the working process of the first pixel circuit 21 shown is basically the same or similar, so you can refer to the working process of the first pixel circuit 21 described in conjunction with FIG. 4 and FIGS. 5A, 5B, and 5C, which will not be repeated here. .
  • FIG. 8 is another schematic block diagram of the display pixel unit 30 in FIG. 1.
  • the second pixel circuit 31 includes a second reset circuit 350, a second data writing circuit 360, a second driving circuit 370, a second storage circuit 380, and a voltage control circuit 390. Except that the display pixel unit 30 shown in FIG. 8 does not include a sensing circuit and includes a voltage control circuit, the remaining components are basically the same as or similar to the sensing pixel unit 20 shown in FIG. 2.
  • the second reset circuit 350 is connected to the second reset control signal line RST2, the second reset voltage terminal VINT2, and the first terminal of the second drive circuit 370, and is configured to be under the control of the second reset control signal
  • the second reset voltage is applied to the first terminal of the second driving circuit 370 to reset the first terminal of the second light-emitting element 32 through the second driving circuit 370.
  • the second data writing circuit 360 is connected to the second scan signal line SCAN2, the second data signal line DATA2, and the control terminal of the second driving circuit 370, and is configured to be controlled by the second scan signal The second data signal is written into the control terminal of the second driving circuit 370.
  • the second terminal of the second driving circuit 370 is connected to the first terminal of the second light-emitting element 32, and the second driving circuit 370 is configured to be controlled by the voltage applied to the control terminal of the second driving circuit 370.
  • the second light emitting element 32 is driven to emit light.
  • the second storage circuit 380 is connected to the control terminal of the second driving circuit 370 and the ground terminal GND, and is configured to store the second data signal and hold it at the control terminal of the second driving circuit 330.
  • the voltage control circuit 390 is connected to the first voltage terminal VDD, the voltage control signal terminal EM, and the first terminal of the second driving circuit 370, and is configured to apply the first voltage to the first terminal under the control of the voltage control signal.
  • the first end of the second driving circuit 370 is connected to the first voltage terminal VDD, the voltage control signal terminal EM, and the first terminal of the second driving circuit 370, and is configured to apply the first voltage to the first terminal under the control of the voltage control signal.
  • the first end of the second light emitting element 32 is connected to the second end of the second driving circuit 370, and the second end of the second light emitting element 32 is connected to the common voltage terminal VCOM.
  • FIG. 9 is a circuit structure diagram of the display pixel unit 30 shown in FIG. 8.
  • the second reset circuit 350 includes a second reset transistor Tr3
  • the second data writing circuit 360 includes a second data writing transistor Tw3
  • the second driving circuit 370 includes a second driving transistor.
  • the transistor Td3, the second storage circuit 380 includes a second storage capacitor C3, and the voltage control circuit 390 includes a voltage control transistor Tc.
  • the second light-emitting element 32 includes a second OLED D2. Except that the circuit of the display pixel unit 30 shown in FIG. 9 does not include a sensing transistor and includes a voltage control transistor, the remaining circuit structure is basically the same as or similar to that of the sensing pixel unit 20 shown in FIG. 3.
  • the control terminal of the second driving circuit 370 includes the gate of the second driving transistor Td3, the first terminal of the second driving circuit 370 includes the first electrode of the second driving transistor Td3, and the second driving circuit 370
  • the second end includes the second electrode of the second driving transistor Td3; the first end of the second light-emitting element 32 includes the anode of the second OLED D2, and the second end of the second light-emitting element 32 includes the cathode of the second OLED D2.
  • the gate of the second reset transistor Tr3 is connected to the second reset control signal line RST2 to receive the second reset control signal, and the first pole of the second reset transistor Tr3 is connected to the second reset voltage terminal VINT2 to receive For the second reset voltage, the second electrode of the second reset transistor Tr3 is connected to the first electrode of the second drive transistor Td3.
  • the gate of the second data writing transistor Tw3 is connected to the second scan signal line SCAN2 to receive the second scan signal, and the first electrode of the second data writing transistor Tw3 is connected to the second data signal line DATA2 To receive the second data signal, the second electrode of the second data writing transistor Tw3 is connected to the gate of the second driving transistor Td3.
  • the gate of the second driving transistor Td3 is connected to the second electrode of the second data writing transistor Tw3, and the first electrode of the second driving transistor Td3 is connected to the second electrode of the second reset transistor Tr3 and the voltage
  • the second pole of the control transistor Tc, and the second pole of the second driving transistor Td3 is connected to the anode of the second OLED D2.
  • the first end of the second storage capacitor C3 is connected to the second electrode of the second data writing transistor Tw3 and the gate of the second driving transistor Td3, and the second end of the second storage capacitor C3 is connected to the ground. Terminal GND.
  • the gate of the voltage control transistor Tc is connected to the voltage control signal terminal EM, the first electrode of the voltage control transistor Tc is connected to the first voltage terminal VDD, and the second electrode of the voltage control transistor Tc is connected to the second driver.
  • the anode of the second OLED D2 is connected to the second electrode of the second driving transistor Td2, and the cathode of the second OLED D2 is connected to the common voltage terminal VCOM.
  • the working process of the second pixel circuit 31 in FIG. 9 includes a reset phase, a data writing phase, and a light emitting phase.
  • a reset phase a data writing phase
  • a light emitting phase a light emitting phase.
  • the second reset transistor Tr3 is turned on by the high level of the second reset control signal, and the second reset voltage is applied to the first pole of the second drive transistor Td3 through the second reset transistor Tr3 to affect the second OLED D2
  • the anode is reset.
  • the second data writing transistor Tw3 is turned on by the high level of the second scan signal, and the second data signal charges the second storage capacitor C2 through the second data writing transistor Tw3, thereby charging the second storage capacitor C2.
  • the data signal is stored in the second storage capacitor C3, and the second storage capacitor C3 holds the stored second data signal on the gate of the second driving transistor Td3.
  • the second storage capacitor C3 keeps the stored second data signal on the gate of the second driving transistor Td3
  • the second driving transistor Td3 remains on; at the same time, the voltage control transistor Tc is controlled by the high voltage of the voltage control signal.
  • the first voltage is applied to the first electrode of the second driving transistor Td3 through the voltage control transistor Tc to drive the second OLED D2 to emit light.
  • the first voltage is directly applied to the first electrode of the second driving transistor Td2 to drive the second OLED D2 to emit light;
  • FIG. 9 In the illustrated second pixel circuit 31, in the light-emitting stage, the first voltage is applied to the first electrode of the second driving transistor Td3 through the voltage control transistor Tc to drive the second OLED D2 to emit light.
  • the plurality of second pixel circuits 31 included in the plurality of display pixel units 30 may all adopt the second pixel circuit 31 shown in FIGS. 6 and 7
  • the structure of the second pixel circuit 31 shown in FIG. 9 and FIG. 10 can also be completely adopted, and the structure of the second pixel circuit 31 shown in FIG. 6 and FIG. 7 can also be partially adopted, and the structure of the second pixel circuit 31 shown in FIG. 9 and FIG. 10 may be partially adopted.
  • the structure of the second pixel circuit 31 shown is not limited in the embodiment of the present disclosure.
  • the plurality of third pixel circuits included in the plurality of dummy pixel units may all adopt the structure of the second pixel circuit 31 shown in FIGS. 6 and 7. It is also possible to adopt all the structures of the second pixel circuit 31 shown in FIGS. 9 and 10, and it is also possible to partially adopt the structure of the second pixel circuit 31 shown in FIGS. 6 and 7 and partially adopt the structure shown in FIGS. 9 and 10
  • the structure of the second pixel circuit 31 is not limited in the embodiment of the present disclosure.
  • the first voltage terminal VDD may be a high voltage source to output a constant high voltage.
  • the first reset voltage terminal VINT1, the second reset voltage terminal VINT2, and the common voltage terminal VCOM can be low voltage sources to output a constant low voltage, and the high and low here only indicate the relative magnitude relationship between the input voltages.
  • the value of the first scan signal and the value of the second scan signal may be the same, or the first scan signal and the second scan signal may be the same scan signal;
  • the value and the value of the second data signal may be the same, or the first data signal and the second data signal may be the same data signal;
  • the value of the first reset control signal and the value of the second reset control signal may be the same, or the first The reset control signal and the second reset control signal may be the same reset control signal;
  • the value of the first reset voltage and the value of the second reset voltage may be the same, or the first reset voltage and the second reset voltage may be the same reset voltage.
  • the disclosed embodiment does not limit this.
  • a plurality of display pixel units may be arranged in a Q1 column, and a plurality of sensing pixel units may be arranged in a Q2 column, where Q1 and Q2 are both positive integers.
  • Q1 is greater than Q2.
  • the Q2 second data signals corresponding to the display pixel units of the Q2 column in the display area may be extracted fixedly or randomly, and the Q2 second data signals may be used as the sensor with the Q2 column of the sensing area.
  • the Q2 first data signals corresponding to the sensing pixel unit, for example, the Q2 second data signals have a one-to-one correspondence with the Q2 column sensing pixel unit.
  • the first data signal corresponding to each column of sensing pixel units may be a plurality of second data signals corresponding to multiple columns of display pixel units (for example, 10 columns or 100 columns of display pixel units) in the display area.
  • the average value of the data signal (for example, arithmetic average).
  • the “second data signal” means a data signal applied to a display pixel unit, and the value of the second data signal applied to different display pixel units may be different; similarly,
  • the “first data signal” means a data signal applied to a sensing pixel unit, and the value of the first data signal applied to different sensing pixel units may be different.
  • the rest of the structure is basically the same or similar to that of the first pixel circuit 21, that is to say, the second pixel circuit 31 is substantially the same as or similar to the first pixel circuit 21.
  • the circuit 21 and the second pixel circuit 31 write the same data signal, the voltage at the first end of the first light-emitting element 22 sensed by the voltage sensor VSENS through the first pixel circuit 21 can be equivalent to the second light-emitting element.
  • the voltage of the first terminal of the element 32 can be obtained according to the sensed voltage of the first terminal of the first light-emitting element 22 and the common voltage provided by the common voltage terminal to which the second terminal of the second light-emitting element 32 is connected.
  • the actual voltage difference between the voltage at the first terminal and the voltage at the second terminal of the current second light-emitting element 32, and according to the current temperature of the display substrate sensed by the temperature sensor and the preset light-emitting brightness it can be determined that the current Under the temperature of the display substrate, the preset voltage difference between the voltage at the first terminal and the voltage at the second terminal of the second light-emitting element 32 corresponding to the preset luminous brightness, if the actual voltage difference and the preset voltage difference If they are not the same, the magnitude of the common voltage provided by the common voltage terminal can be adjusted to change the actual voltage difference between the voltage at the first terminal and the voltage at the second terminal of the second light-emitting element 32, so that the actual voltage difference is equal to the preset value.
  • the embodiments of the present disclosure also provide another display substrate, the display substrate further includes a light-shielding layer, the light-shielding layer may be disposed at least in the sensing area on the base substrate, and may be located far from the substrate of the plurality of sensing pixel units On one side of the substrate, the light shielding layer is configured to shield the light emitted from the sensing pixel unit in the sensing area.
  • a light-shielding layer is provided in the sensing area of the display substrate, thereby increasing the optical density (OD) value of the sensing area, thereby achieving the effect of shielding the sensing area.
  • FIG. 10 is a schematic block diagram of another display substrate provided by an embodiment of the disclosure.
  • the display substrate further includes a light-shielding layer 40.
  • the light-shielding layer 40 and the plurality of sensing pixel units 20 are arranged together in the sensing area 11, and the light-shielding layer 40 is arranged on the remote liner of the plurality of sensing pixel units 20.
  • the light shielding layer 40 is configured to shield the light emitted from the sensing pixel unit 20 of the sensing area 11.
  • light emitted from the sensing pixel unit 20 of the sensing region 11 means light emitted from the sensing region 11 toward the user's viewing side.
  • the light emitted by the sensing pixel unit 20 of the sensing area 11 includes the light emitted by the first light emitting element 22 of the plurality of sensing pixel units 20 and the metal layer in the first pixel circuit 21 of the plurality of sensing pixel units 20. Reflected light.
  • the display substrate provided by the embodiment of the present disclosure may also be provided with a light-shielding layer in parts other than the display area 12, that is, a light-shielding layer is provided in both the sensing area 11 and the dummy area 13. .
  • the light shielding layer provided in the sensing area 11 is configured to shield the light emitted from the sensing pixel unit 20 of the sensing area 11, that is, shield the light emitted by the first light emitting element 22 included in the sensing pixel unit 20 and The light reflected by the metal layer in the first pixel circuit 21;
  • the light shielding layer provided in the virtual area 13 is configured to shield the light emitted from the virtual pixel unit of the virtual area 13, that is, shield the third pixel circuit included in the virtual pixel unit Light reflected by the metal layer.
  • FIG. 11 is a schematic diagram of a planar structure of another display substrate provided by some embodiments of the present disclosure.
  • all areas on the base substrate 10 except for the sensing area and the display area 12 are dummy areas 13.
  • the virtual area 13 surrounds the sensing area and the display area 12, and the sensing area and the display area 12 are not in direct contact.
  • the sensing area and the display area 12 are separated by a part of the virtual area 13.
  • the sensing area and the display area 12 are arranged along the first direction X.
  • the second direction Y and the first direction X are perpendicular to each other.
  • the shape of the display area 12 may be a rectangle, and the shape of the sensing area 11 may also be a rectangle. Two adjacent sides of the display area 12 are parallel to the first direction X and the second direction Y, respectively, and two adjacent sides of the sensing area 11 are also parallel to the first direction X and the second direction Y, respectively.
  • the resolution (ie size) of the display area 12 may be 2916*1104, that is, in the first direction X, the length of the display area 12 is 2916, and in the second direction Y, the length of the display area 12 is 1104.
  • the resolution of the sensing area 11 may be 24*1104, that is, in the first direction X, the length of the sensing area 11 is 24, and in the second direction Y, the length of the sensing area 11 is 1104. That is, in the second direction Y, the length of the display area 12 and the length of the sensing area 11 are the same.
  • the length d1 of the portion of the virtual area 13 between the sensing area and the display area 12 may be 6, and the length d1 of the virtual area 13 in the sensing area
  • the length d2 of the portion between the area 11 and the edge of the base substrate 10 can be 3, and the dummy area 13 is at the edge of the display area 12 and the base substrate 10 (the right edge in FIG. 2).
  • the length d3 of the part between the side edges) can be 3; in the second direction Y, the part of the dummy region 13 between the sensing region 11 and the edge of the base substrate 10 (upper edge in FIG.
  • the length d4 of the virtual area 13 can be 2, and the length d5 of the part between the sensing area 11 and the edge of the base substrate 10 (the lower edge in FIG. 2) of the virtual area 13 can also be 2.
  • the length d6 of the portion between the area 12 and the edge of the base substrate 10 (the upper edge in FIG. 2) can be 2, and the dummy area 13 is at the edge of the display area 12 and the base substrate 10 (the lower edge in FIG. 2).
  • the length d7 of the part between the side edges) may also be 2.
  • the units of resolution, size, length, etc. are all pixels.
  • the resolution of the display area 12 may be 2916 pixels*1104 pixels.
  • FIG. 12A is a schematic diagram of a cross-sectional structure of another display substrate provided by an embodiment of the present disclosure
  • FIG. 12B is a schematic diagram of another cross-sectional structure of another display substrate provided by an embodiment of the present disclosure
  • FIG. 12C is a schematic diagram of another cross-sectional structure of another display substrate provided by an embodiment of the disclosure.
  • the light-shielding layer 40 includes a first light-shielding color film layer 401, and the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10 covers the sensing area 11.
  • the shape of the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10 is the same or substantially the same as the shape of the sensing region 11.
  • the sensing area 11 is located within the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10, that is, the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10
  • the size is greater than or equal to the size of the sensing area 11.
  • the sensing area 11 and the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10 completely overlap each other, so that the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10 is
  • the shape may also be a rectangle, and the size of the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10 may be 24*1104.
  • the shape of the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10 may also be a suitable shape such as a trapezoid.
  • the shape is the same or substantially the same means that both are the same type of shape, but it does not mean that the proportions of the sides corresponding to the two are the same.
  • the respective aspect ratios may be the same or different, which is not limited in the embodiment of the present disclosure.
  • orthogonal projection refers to the projection of the element in a plane parallel to the base substrate 10 along a direction perpendicular to the base substrate 10, for example, “the first light-shielding color film layer 401 "Orthographic projection” refers to the projection of the first light-shielding color film layer 401 in a plane parallel to the base substrate 10 along a direction perpendicular to the base substrate 10.
  • the plurality of display pixel units 30 may include a first display pixel unit 301, and the first display pixel unit 301 includes a first display color film layer 3010.
  • the first light-shielding color film layer 401 and the first display color film layer 3010 have the same color filter characteristics.
  • the first light-shielding color film layer 401 and the first display color film layer 3010 use the same filter material through the same patterning process It is prepared so that the first light-shielding color film layer 401 and the first display color film layer 3010 have the same color filter characteristics, so that the first light-shielding color film layer 401 can be prepared without increasing the process, so as to achieve the The sensing area 11 performs a light shielding function.
  • the light-shielding layer 40 since the light-shielding layer 40 includes a first light-shielding color film layer 401, the problem of displaying Mura caused by the color film (CF) process can be avoided or reduced.
  • the first light-shielding color film layer 401 and the first display color film layer 3010 may have the same thickness.
  • the side of the first light-shielding color film layer 401 away from the base substrate 10 is the user's viewing side.
  • the light-shielding layer 40 further includes a second light-shielding color film layer 402.
  • the first light-shielding color film layer 401 is located at the second light-shielding color film layer.
  • the side of the film layer 402 away from the base substrate 10, that is, the second light-shielding color film layer 402 is located between the first light-shielding color film layer 401 and the base substrate 10.
  • the orthographic projection of the second light-shielding color film layer 402 on the base substrate 10 covers the sensing area 11.
  • the shape of the orthographic projection of the second light-shielding color film layer 402 on the base substrate 10 is the same or substantially the same as the shape of the sensing area 11.
  • the sensing area 11 is located within the orthographic projection of the second light-shielding color film layer 402 on the base substrate 10.
  • the sensing area 11 and the second light-shielding color film layer 402 are on the base substrate 10.
  • the orthographic projections completely overlap each other, that is, the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10 and the orthographic projection of the second light-shielding color film layer 402 on the base substrate 10 also completely overlap each other, so that the second light-shielding color
  • the shape of the orthographic projection of the film layer 402 on the base substrate 10 may also be a rectangle, and the size of the orthographic projection of the second light-shielding color film layer 402 on the base substrate 10 may also be 24*1104.
  • the plurality of display pixel units 30 may further include a second display pixel unit 302, and the second display pixel unit 302 includes a second display color film layer 3020.
  • the second light-shielding color film layer 402 and the second display color film layer 3020 have the same color filter characteristics.
  • the second light-shielding color film layer 402 and the second display color film layer 3020 use the same filter material through the same patterning process Prepared so that the second light-shielding color film layer 402 and the second display color film layer 3020 have the same color filter characteristics, so that the first light-shielding color film layer 401 and the second light-shielding color film layer 401 and the second light-shielding color film layer 401 can be prepared without increasing the process
  • the color film layer 402 realizes the function of shielding the sensing area 11 from light.
  • providing the first light-shielding color film layer 401 and the second light-shielding color film layer 402 in the sensing area 11 can better perform the Shading to prevent light leakage in the sensing area 11.
  • the second light-shielding color film layer 402 and the second display color film layer 3020 may have the same thickness.
  • the light-shielding layer 40 may further include a third light-shielding color film layer 403.
  • the second light-shielding color film layer 402 is located on the third light-shielding layer.
  • the side of the color film layer 403 away from the base substrate 10, that is, the third light-shielding color film layer 403 is located between the second light-shielding color film layer 402 and the base substrate 10, and the second light-shielding color film layer 402 is located on the first Between a light-shielding color film layer 401 and a third light-shielding color film layer 403.
  • the orthographic projection of the third light-shielding color film layer 403 on the base substrate 10 covers the sensing area 11.
  • the shape of the orthographic projection of the third light-shielding color film layer 403 on the base substrate 10 is the same or substantially the same as the shape of the sensing area 11.
  • the sensing area 11 is located within the orthographic projection of the third light-shielding color film layer 403 on the base substrate 10.
  • the sensing area 11 and the third light-shielding color film layer 403 are on the base substrate 10.
  • the orthographic projections completely overlap each other, that is, the orthographic projection of the first light-shielding color film layer 401 on the base substrate 10, the orthographic projection of the second light-shielding color film layer 402 on the base substrate 10, and the third light-shielding color film layer 403 on the base substrate 10.
  • the orthographic projections on the base substrate 10 completely overlap each other, so that the shape of the orthographic projection of the third light-shielding color film layer 403 on the base substrate 10 can also be a rectangle, and the third light-shielding color film layer 403 is on the base substrate 10.
  • the size of the orthographic projection can also be 24*1104.
  • the plurality of display pixel units 30 further include a third display pixel unit 303, and the third display pixel unit 303 includes a third display color film layer 3030.
  • the third light-shielding color film layer 403 and the third display color film layer 3030 have the same color filter characteristics.
  • the third light-shielding color film layer 403 and the third display color film layer 3030 use the same filter material through the same patterning process Prepared so that the third light-shielding color film layer 403 and the third display color film layer 3030 have the same color filter characteristics, so that the first light-shielding color film layer 401 and the second light-shielding color film layer 401 and the second light-shielding color film layer 401 can be prepared without increasing the manufacturing process.
  • the color film layer 402 and the third light-shielding color film layer 403 realize the function of shielding the sensing area 11 from light.
  • the first light-shielding color film layer is provided in the sensing area 11 401.
  • the second light-shielding color film layer 402 and the third light-shielding color film layer 13 can better shield the sensing area 11 to prevent light leakage in the sensing area 11.
  • the third light-shielding color film layer 403 and the third display color film layer 3030 may have the same thickness.
  • the thickness of the first light-shielding color film layer 401, the thickness of the second light-shielding color film layer 402, and the thickness of the third light-shielding color film layer 13 may all be equal.
  • the first light-shielding color film layer 401, the second light-shielding color film layer 402, and the third light-shielding color film layer 403 are different color film layers.
  • the first display color film layer 3010, the second display color film layer 3020, and the third display color film layer 3030 are also different color film layers.
  • the first light-shielding color film layer 401 and the first display color film layer 3010 are color film layers of the same color
  • the second light-shielding color film layer 402 and the second display color film layer 3020 are color film layers of the same color
  • the third The light-shielding color film layer 233 and the third display color film layer 3030 are color film layers of the same color.
  • the first light-shielding color film layer 401 and the first display color film layer 3010 are both blue color film layers, that is, the first light-shielding color film layer 401 and the first display color film layer 3010 can both block the red color film layer.
  • the second light-shielding color film layer 402 and the second display color film layer 3020 are both red color film layers, that is, the second light-shielding color film layer 402 and the second display color film layer
  • the layer 3020 can block blue light, green light, etc., and transmit red light
  • the third light-shielding color film layer 233 and the third display color film layer 3030 are both green color film layers, that is, the third light-shielding color film layer 233
  • Both the third display color film layer 3030 and the third display color film layer 3030 can block blue light, red light, etc., and transmit green light.
  • the first light-shielding color film layer 401 and the first display color film layer 3010 are both blue color film layers
  • the second light-shielding color film layer 402 and the second display color film layer 3020 are green color films.
  • the third light-shielding color film layer 233 and the third display color film layer 3030 are both red color film layers.
  • the first light-shielding color film layer 401 and the first display color film layer 3010 may both be red color film layers
  • the second light-shielding color film layer 402 and the second display color film layer 3020 may Both are green color film layers
  • the third light-shielding color film layer 233 and the third display color film layer 3030 may both be blue color film layers
  • the first light-shielding color film layer 401 and the first display color film layer 3010 may be both It is a green color film layer
  • the second light-shielding color film layer 402 and the second display color film layer 3020 may also be blue color film layers
  • the third light-shielding color film layer 233 and the third display color film layer 3030 may both be red color film layers. Color film layer and so on. This disclosure does not specifically limit this.
  • the first light-shielding color film layer 401, the first display color film layer 3010, the second light-shielding color film layer 402, the second display color film layer 3020, the third light-shielding color film layer 233, and the third display color film layer 3030 are all Located on the packaging layer, that is, on the side of the packaging layer away from the base substrate.
  • the following will briefly describe the process and process conditions for preparing the red color film layer, blue color film layer and green color film layer: first carry out the pre-clean operation (Pre-clean), and then manually apply glue, such as red glue,
  • the speed of the red glue is 450rpm/45 seconds (s); the red glue is pre-bake at a temperature of 85°C, and the pre-bake time is 120s; the red glue after the baking is exposed (The exposure dose is 120 megajoules (mj)); the exposed red glue is developed, and the development time is 180s; the developed red glue is post-baked at a temperature of 90°C.
  • the time is 1800s to obtain the red color film layer; then, the glue is applied again, such as blue glue, the speed of applying the blue glue is 1100rpm/25s; the blue glue is pre-baked at a temperature of 85°C (pre- bake), the pre-baking time is 120s; the baked blue glue is exposed (exposure dose is 115mj); the exposed blue glue is developed, and the developing time is 61s; at a temperature of 90°C Next, post bake the developed blue glue again, and the bake time is 1800s to obtain the blue color film layer; finally, apply glue again, such as green glue, and the speed of applying green glue is 1050rpm/20s; Pre-bake the green glue at a temperature of 85°C, the pre-bake time is 120s; the green glue after the baking is exposed (exposure dose is 110mj); the green glue after the exposure The developing process is performed, and the developing time is 58s; the developed green glue is post-baked again at a temperature of 90° C., and the baking time is 1800
  • FIG. 13 is a schematic diagram of another cross-sectional structure of another display substrate provided by an embodiment of the present disclosure.
  • the light shielding layer 40 may include a black light shielding layer 404, and the black light shielding layer 404 may completely shield the light emitted from the sensing pixel unit 20 of the sensing area 11.
  • the orthographic projection of the black light shielding layer 404 on the base substrate 10 covers the sensing area 11.
  • the sensing area 11 is located within the orthographic projection of the black light shielding layer 404 on the base substrate 10, for example, the orthographic projections of the sensing area 11 and the black light shielding layer 404 on the base substrate 10 completely overlap each other, Therefore, the shape of the orthographic projection of the black light shielding layer 404 on the base substrate 10 can also be a rectangle, and the size of the orthographic projection of the black light shielding layer 404 on the base substrate 10 can also be 24*1104.
  • a black light-shielding layer is provided in the sensing area 11 404 can avoid the Mura problem caused by the color film manufacturing process.
  • the black light shielding layer 404 may be a black matrix.
  • the black light-shielding layer 404 may be formed on the base substrate 10 before preparing the first display color filter layer 3010, the second display color filter layer 3020, and the third display color filter layer 3030.
  • the thickness of the black light-shielding layer 404 may be the same as the thickness of any one of the first display color film layer 3010, the second display color film layer 3020, and the third display color film layer 3030. equal.
  • each display pixel unit 30 may include a first pixel circuit 31 and a second light-emitting element 32.
  • the first pixel circuit 31 is connected to the first end of the second light-emitting element 32 and is configured to drive the second light-emitting element.
  • the element 32 emits light, and the second light-emitting element 32 is configured to emit white light.
  • the second light-emitting element 32 in each display pixel unit 30 cooperates with the display color film layer to emit light of different colors, and the display color film layer may be disposed on the side of the second light-emitting element 32 away from the base substrate 10.
  • the first display color film layer 3010 in the first display pixel unit 301 is a blue color film layer
  • the white light emitted by the second light-emitting element in the first display pixel unit 301 passes through the first display color film layer 3010. Blue light is obtained, that is, the first display pixel unit 301 is configured to display blue light.
  • the second display color film layer 3020 in the second display pixel unit 302 is a red color film layer
  • the white light emitted by the second light-emitting element in the second display pixel unit 302 passes through the second display color film layer 3020 to obtain a red color film layer.
  • Light that is, the second display pixel unit 302 is configured to display red light.
  • the third display color film layer 3030 in the third display pixel unit 303 is a green color film layer
  • the white light emitted by the second light-emitting element in the third display pixel unit 303 passes through the third display color film layer 3030 to obtain green Light, that is, the third display pixel unit 303 is configured to display green light.
  • a plurality of display pixel units 30 are arranged in an array along a first direction X and a second direction Y.
  • the first direction X may be the row direction of the plurality of display pixel units 30, and the second direction Y may be The column direction of the plurality of display pixel units 30.
  • a plurality of display pixel units 30 are arranged in the display area 12 in a BV3 array arrangement.
  • the BV3 array arrangement can indicate that in the first direction X, the arrangement of the display pixel units in the odd-numbered pixel unit rows is different from the arrangement of the display pixel units in the even-numbered pixel unit rows.
  • the arrangement of display pixel units is BRGBRG (that is, according to the first display pixel unit B, the second display pixel unit R, the third display pixel unit G, the first Display pixel unit B, second display pixel unit R, and third display pixel unit G); in even-numbered pixel unit rows, the display pixel units are arranged in GBRGBR (that is, according to the third display pixel unit, first The display pixel unit, the second display pixel unit, the third display pixel unit, the first display pixel unit, and the second display pixel unit are arranged).
  • the first display pixel unit B of the first pixel unit row and the first display pixel unit B of the third pixel unit row are both located in the same pixel unit column.
  • the first display pixel unit B of the two pixel unit rows and the first display pixel unit B of the fourth pixel unit row are both located in the same pixel unit column, that is, the first display pixel units B in two adjacent pixel unit rows are arranged staggered.
  • the second display pixel units R in two adjacent pixel unit rows are also staggered
  • the third display pixel units G in two adjacent pixel unit rows are also staggered. .
  • the arrangement of the display pixel units is BRGBRG; in the second pixel unit row, the arrangement of the display pixel units is GBRGBR; and in the third pixel unit row, the arrangement of the display pixel units
  • the mode is BRGBRG, and in the fourth pixel unit row, the arrangement mode of the display pixel units is GBRGBR.
  • arrangement mode refers to an arrangement mode of display pixel units of different colors.
  • the embodiments of the present disclosure also provide a display panel, including the display substrate provided in any of the foregoing embodiments of the present disclosure.
  • the display panel may be a rectangular panel, a circular panel, an oval panel, or a polygonal panel.
  • the display panel can be not only a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel may also have a touch function, that is, the display panel may be a touch display panel.
  • the display panel can be applied to a silicon-based OLED display device, for example, it can be applied to a virtual reality device or an enhanced display device, and of course, it can also be applied to other types of display devices, which is not limited in the embodiments of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure has the same or similar beneficial effects as the display substrate provided by the foregoing embodiment of the present disclosure. Since the display substrate has been described in detail in the foregoing embodiment, it will not be repeated here.
  • the embodiment of the present disclosure also provides a voltage regulation method for the display substrate of the foregoing embodiment.
  • FIG. 14 is a flowchart of a method for adjusting voltage of a display substrate according to an embodiment of the disclosure. As shown in FIG. 14, the voltage adjustment method of the display substrate may include:
  • the voltage sensor is controlled by the first pixel circuit to sense the voltage of the first terminal of the first light-emitting element.
  • S20 Adjust the voltage of the second end of the second light-emitting element based on the temperature of the display substrate, the preset light-emitting brightness, and the sensed voltage of the first end of the first light-emitting element.
  • sensing the voltage of the first terminal of the first light-emitting element through the first pixel circuit may include:
  • S140 In the sensing phase, the voltage of the first terminal of the first light-emitting element is sensed through the sensing circuit.

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Abstract

一种显示基板及显示面板。该显示基板包括衬底基板，衬底基板为硅基板，包括显示区、感测区和至少部分位于显示区和感测区之间的虚拟区；感测区内设有多个包括第一发光元件和第一像素电路的感测像素单元，第一像素电路驱动第一发光元件发光、以及控制电压感测器感测第一发光元件的第一端的电压；显示区内设有多个包括第二像素电路和第二发光元件的显示像素单元，第二像素电路驱动第二发光元件发光；虚拟区内设有多个包括第三像素电路和第三发光元件的虚拟像素单元，第三像素电路与第二像素电路相同，第三发光元件与第二发光元件相同，第三像素电路不与第三发光元件连接；第一发光元件、第二发光元件和第三发光元件的第二端均连接至公共电压端。

Description

显示基板及显示面板 技术领域
本公开的实施例涉及一种显示基板及显示面板。
背景技术
硅基有机发光二极管(Organic Light Emitting Diode，OLED)微型显示是显示行业的一个新兴分支，硅基OLED微显示器是OLED技术和CMOS(Complementary Metal Oxide Semiconductor(互补金属氧化物半导体))技术结合的新型显示技术。硅基OLED微型显示器件以单晶硅芯片为基底，像素尺寸小，精细度远远高于传统显示器件，硅基OLED微型显示器具有广阔的市场应用空间，特别适合应用于头盔显示器、立体显示镜以及眼睛式显示器等。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板，所述衬底基板为硅基板，包括显示区、感测区和虚拟区；至少部分所述虚拟区位于所述显示区和所述感测区之间；在所述感测区内设有多个感测像素单元，所述多个感测像素单元中的至少一个包括第一发光元件和第一像素电路，所述第一像素电路连接至所述第一发光元件的第一端以及电压感测器，且被配置为驱动所述第一发光元件发光、以及控制所述电压感测器感测所述第一发光元件的第一端的电压；在所述显示区内设有多个显示像素单元，所述多个显示像素单元中的至少一个包括第二像素电路和第二发光元件，所述第二像素电路连接至所述第二发光元件的第一端，且被配置为驱动所述第二发光元件发光以显示图像；在所述虚拟区内设有多个虚拟像素单元，所述多个虚拟像素单元中的至少一个包括第三像素电路和第三发光元件，所述第三像素电路与所述第二像素电路相同，所述第三发光元件与所述第二发光元件相同，所述第三像素电路不与所述第三发光元件连接；所述第一发光元件的第二端、所述第二发光元件的第二端和所述第三发光元件的第二端成一体结构；所述一体结构连接 至公共电压端，且至少覆盖所述显示区、所述感测区、以及位于所述显示区和所述感测区之间的至少部分所述虚拟区。
例如，在本公开的实施例提供的显示基板中，所述第一像素电路包括第一数据写入电路、第一驱动电路和第一存储电路，所述第一数据写入电路连接至所述第一驱动电路的控制端，被配置为在第一扫描信号的控制下将第一数据信号写入所述第一驱动电路的控制端；所述第一驱动电路的第二端连接至所述第一发光元件的第一端，所述第一驱动电路被配置为在施加至所述第一驱动电路的控制端的电压的控制下驱动所述第一发光元件发光；所述第一存储电路连接至所述第一驱动电路的控制端，被配置为存储所述第一数据信号并将其保持在所述第一驱动电路的控制端；所述第二像素电路包括第二数据写入电路、第二驱动电路和第二存储电路，所述第二数据写入电路连接至所述第二驱动电路的控制端，被配置为在第二扫描信号的控制下将第二数据信号写入所述第二驱动电路的控制端；所述第二驱动电路的第二端连接至所述第二发光元件的第一端，所述第二驱动电路被配置为在施加至所述第二驱动电路的控制端的电压的控制下驱动所述第二发光元件发光；所述第二存储电路连接至所述第二驱动电路的控制端，被配置为存储所述第二数据信号并将其保持在所述第二驱动电路的控制端。
例如，在本公开的实施例提供的显示基板中，所述第一像素电路还包括第一复位电路，所述第一复位电路连接至所述第一发光元件的第一端，被配置为在第一复位控制信号的控制下将第一复位电压施加至所述第一发光元件的第一端以对所述第一发光元件的第一端进行复位；所述第二像素电路还包括第二复位电路，所述第二复位电路被配置为在第二复位控制信号的控制下利用第二复位电压对所述第二发光元件的第一端进行复位。
例如，在本公开的实施例提供的显示基板中，所述第二复位电路连接至所述第二发光元件的第一端，被配置为在第二复位控制信号的控制下将第二复位电压施加至所述第二发光元件的第一端以对所述第二发光元件的第一端进行复位。
例如，在本公开的实施例提供的显示基板中，所述第二复位电路连 接至所述第二驱动电路的第一端，被配置为在第二复位控制信号的控制下将第二复位电压施加至所述第二驱动电路的第一端以通过所述第二驱动电路对所述第二发光元件的第一端进行复位。
例如，在本公开的实施例提供的显示基板中，所述第二像素电路还包括电压控制电路，所述电压控制电路连接至所述第二驱动电路的第一端，被配置为在电压控制信号的控制下将第一电压施加至所述第二驱动电路的第一端。
例如，在本公开的实施例提供的显示基板中，所述第一数据写入电路包括第一数据写入晶体管，所述第一驱动电路包括第一驱动晶体管，所述第一存储电路包括第一存储电容，所述第一复位电路包括第一复位晶体管，所述第一驱动电路的控制端包括所述第一驱动晶体管的栅极，所述第一驱动电路的第一端包括所述第一驱动晶体管的第一极，所述第一驱动电路的第二端包括所述第一驱动晶体管的第二极；所述第一数据写入晶体管的栅极接收所述第一扫描信号，所述第一数据写入晶体管的第一极接收所述第一数据信号，所述第一数据写入晶体管的第二极连接至所述第一驱动晶体管的栅极；所述第一存储电容的第一端连接至所述第一驱动晶体管的栅极，所述第一存储电容的第二端连接至所述第一驱动晶体管的第二极；所述第一复位晶体管的栅极接收所述第一复位控制信号，所述第一复位晶体管的第一极接收所述第一复位电压，所述第一复位晶体管的第二极连接至所述第一驱动晶体管的第二极。
例如，在本公开的实施例提供的显示基板中，所述第二数据写入电路包括第二数据写入晶体管，所述第二驱动电路包括第二驱动晶体管，所述第二存储电路包括第二存储电容，所述第二复位电路包括第二复位晶体管，所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，所述第二驱动电路的第一端包括所述第二驱动晶体管的第一极，所述第二驱动电路的第二端包括所述第二驱动晶体管的第二极；所述第二数据写入晶体管的栅极接收所述第二扫描信号，所述第二数据写入晶体管的第一极接收所述第二数据信号，所述第二数据写入晶体管的第二极连接至所述第二驱动晶体管的栅极；所述第二存储电容的第一端连接至所述第二驱动晶体管的栅极，所述第二存储电容的第二端连接至所述第二驱 动晶体管的第二极；所述第二复位晶体管的栅极接收所述第二复位控制信号，所述第二复位晶体管的第一极接收所述第二复位电压，所述第二复位晶体管的第二极连接至所述第二驱动晶体管的第二极。
例如，在本公开的实施例提供的显示基板中，所述第二数据写入电路包括第二数据写入晶体管，所述第二驱动电路包括第二驱动晶体管，所述第二存储电路包括第二存储电容，所述第二复位电路包括第二复位晶体管，所述电压控制电路包括电压控制晶体管，所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，所述第二驱动电路的第一端包括所述第二驱动晶体管的第一极，所述第二驱动电路的第二端包括所述第二驱动晶体管的第二极；所述第二数据写入晶体管的栅极接收所述第二扫描信号，所述第二数据写入晶体管的第一极接收所述第二数据信号，所述第二数据写入晶体管的第二极连接至所述第二驱动晶体管的栅极；所述第二存储电容的第一端连接至所述第二驱动晶体管的栅极，所述第二存储电容的第二端连接至接地端；所述第二复位晶体管的栅极接收所述第二复位控制信号，所述第二复位晶体管的第一极接收所述第二复位电压，所述第二复位晶体管的第二极连接至所述第二驱动晶体管的第一极；所述电压控制晶体管的栅极接收所述电压控制信号，所述电压控制晶体管的第一极接收所述第一电压，所述电压控制晶体管的第二极连接至所述第二驱动晶体管的第一极。
例如，在本公开的实施例提供的显示基板中，所述感测区、至少部分所述虚拟区和所述显示区沿第一方向依次排布，在所述第一方向上，所述感测区的尺寸介于所述显示区的尺寸和至少部分所述虚拟区的尺寸之间。
例如，在本公开的实施例提供的显示基板中，所述第一像素电路还包括感测电路，所述感测电路连接至所述第一发光元件的第一端，被配置为在感测控制信号的控制下控制所述电压感测器感测所述第一发光元件的第一端的电压。
例如，在本公开的实施例提供的显示基板中，所述感测电路包括感测晶体管，所述感测晶体管的栅极接收所述感测控制信号，所述感测晶体管的第一极连接至所述电压感测器，所述感测晶体管的第二极连接至 所述第一发光元件的第一端。
例如，本公开的实施例提供的显示基板还包括调节电路，其中，所述调节电路被配置为基于感测到的所述第一发光元件的第一端的电压以及所述显示基板的温度和预设发光亮度，调节所述公共电压端提供的电压。
例如，本公开的实施例提供的显示基板还包括遮光层，其中，所述遮光层至少设置于所述感测区内，且所述遮光层位于所述多个感测像素单元的远离所述衬底基板的一侧，所述遮光层被配置为遮挡从所述感测区的感测像素单元出射的光。
例如，在本公开的实施例提供的显示基板中，所述遮光层包括第一遮光彩膜层、第二遮光彩膜层和第三遮光彩膜层，在垂直于所述衬底基板的方向上，所述第一遮光彩膜层、所述第二遮光彩膜层、所述第三遮光彩膜层依次设置在远离所述衬底基板的一侧，所述第一遮光彩膜层、所述第二遮光彩膜层和所述第三遮光彩膜层的重叠区域在所述衬底基板上的正投影覆盖所述感测区；所述多个显示像素单元包括第一显示像素单元、第二显示像素单元和第三显示像素单元，所述第一显示像素单元包括第一显示彩膜层，所述第二显示像素单元包括第二显示彩膜层，所述第三显示像素单元包括第三显示彩膜层，所述第一遮光彩膜层和所述第一显示彩膜层具有相同的彩色滤光特性，所述第二遮光彩膜层和所述第二显示彩膜层具有相同的彩色滤光特性，所述第三遮光彩膜层和所述第三显示彩膜层具有相同的彩色滤光特性。
例如，在本公开的实施例提供的显示基板中，所述遮光层包括黑色遮光层，在垂直于所述衬底基板的方向上，所述黑色遮光层在所述衬底基板上的正投影覆盖所述感测区。
例如，在本公开的实施例提供的显示基板中，所述遮光层还设置于所述虚拟区内，且所述遮光层位于所述多个虚拟像素单元的远离所述衬底基板的一侧，所述遮光层被配置为遮挡从所述虚拟区的虚拟像素单元出射的光。
例如，在本公开的实施例提供的显示基板中，所述第一发光元件与所述第二发光元件相同或者不同；所述第一像素电路与所述第二像素电 路相同或者不同。
本公开至少一实施例提供一种显示面板，包括根据上述任一实施例所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开的实施例提供的一种显示基板的示意性框图；
图2为图1中的感测像素单元的一种示意性框图；
图3为图2中的感测像素单元的电路结构图；
图4为输入图3中的第一像素电路的信号的时序图；
图5A为图3中的第一像素电路在复位阶段的等效电路图；
图5B为图3中的第一像素电路在数据写入阶段的等效电路图；
图5C为图3中的第一像素电路在发光阶段的等效电路图；
图5D为图3中的第一像素电路在感测阶段的等效电路图；
图6为图1中的显示像素单元的一种示意性框图；
图7为图6所示的显示像素单元的电路结构图；
图8为图1中的显示像素单元的另一种示意性框图；
图9为图8所示的显示像素单元的电路结构图；
图10为本公开的实施例提供的另一种显示基板的示意性框图；
图11为本公开的实施例提供的另一种显示基板的平面结构示意图；
图12A为本公开的实施例提供的另一种显示基板的一种截面结构示意图；
图12B为本公开的实施例提供的另一种显示基板的另一种截面结构示意图；
图12C为本公开的实施例提供的另一种显示基板的又一种截面结构示意图；
图13为本公开的实施例提供的另一种显示基板的又一种截面结构 示意图；
图14为本公开的实施例提供的一种显示基板的调压方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
本公开的实施例提供一种显示基板，该显示基板包括衬底基板、多个显示像素单元和多个感测像素单元。衬底基板为硅基板且包括显示区、感测区和虚拟(dummy)区，至少部分虚拟区位于显示区和感测区之间。
在感测区内设有多个感测像素单元，多个感测像素单元中的至少一个包括第一发光元件和第一像素电路，第一像素电路连接至第一发光元件的第一端以及电压感测器，且被配置为驱动第一发光元件发光、以及 控制电压感测器感测第一发光元件的第一端的电压。
在显示区内设有多个显示像素单元，多个显示像素单元中的至少一个包括第二像素电路和第二发光元件，第二像素电路连接至第二发光元件的第一端，且被配置为驱动第二发光元件发光以显示图像。
在虚拟区内设有多个虚拟像素单元，多个虚拟像素单元中的至少一个包括第三像素电路和第三发光元件，第三像素电路与第二像素电路相同，第三发光元件与第二发光元件相同，第三像素电路不与第三发光元件连接。
第一发光元件的第二端、第二发光元件的第二端和第三发光元件的第二端成一体结构；该一体结构连接至公共电压端，且至少覆盖显示区、感测区、以及位于显示区和感测区之间的至少部分虚拟区。
本公开的实施例提供的显示基板可以基于显示基板的温度、预设发光亮度以及感测到的第一发光元件的第一端的电压，来调节显示像素单元中的第二发光元件的第二端所连接的公共电压端提供的电压，使得显示像素单元中的第二发光元件可以在一定的温度条件下达到预设发光亮度，使显示基板实时显示gamma值为2.2时的图像信息。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开的实施例提供的一种显示基板的示意性框图。如图1所示，该显示基板包括衬底基板10、多个感测像素单元20和多个显示像素单元30，衬底基板10为硅基板且包括感测区11、显示区12和虚拟区13，多个感测像素单元20设置在感测区11内，多个显示像素单元30设置在显示区12内。
如图1所示，衬底基板10上除了感测区11和显示区12之外的区域为虚拟区13，感测区和显示区12由虚拟区13的至少一部分间隔开。设置虚拟区13可以避免感测区11和显示区12的需彼此绝缘的元件短路，并且便于显示基板的封装，利于提高封装效果。
如图1所示，多个感测像素单元20中的至少一个可以包括第一像素电路21和第一发光元件22，在本公开的实施例中也可以是每个感测像素单元20都包括第一像素电路21和第一发光元件22。第一像素电 路21连接至第一发光元件22的第一端和电压感测器(图中未示出)，被配置为驱动第一发光元件22发光，以及控制电压感测器感测第一发光元件22的第一端的电压。
如图1所示，多个显示像素单元30中的至少一个可以包括第二像素电路31和第二发光元件32，在本公开的实施例中也可以是每个显示像素单元30都包括第二像素电路31和第二发光元件32。第二像素电路31连接至第二发光元件32的第一端，被配置为驱动第二发光元件32发光以显示图像。
例如，感测像素单元20中包括的第一发光元件22和显示像素单元30包括的第二发光元件32可以是相同的发光元件和不同的发光元件，感测像素单元20中包括的第一像素电路21和显示像素单元30包括的第二像素电路31可以是相同的像素电路或不同的像素电路，本公开的实施例对此不做限制。
需要说明的是，为了简便，图1中仅示出了一个感测像素单元20和一个显示像素单元30，但是感测像素单元20和显示像素单元30的个数显然不限于此，并且可以根据需要设置适当数量的感测像素单元20和显示像素单元30。
此外，在至少部分虚拟区13中可以设置有多个虚拟像素单元(图中未示出)，多个虚拟像素单元中的至少一个可以包括第三发光元件和第三像素电路，在本公开的实施例中也可以是每个虚拟像素单元都包括第三发光元件和第三像素电路，从而保证与显示区12一样的均一性。例如，对于虚拟区13的位于感测区和显示区12之间的第一部分，虚拟区13的第一部分中的第三发光元件与显示区12中的第二发光元件32的结构相同，在虚拟区13的第一部分中的第三像素电路与显示区12中的第二像素电路31的结构也相同。与感测区和显示区12不同之处在于：在虚拟区13的第一部分中，第三发光元件与第三像素电路没有电连接。例如，对于虚拟区13的位于感测区11和衬底基板10的例如左侧边缘之间的第二部分和位于显示区12和衬底基板10的例如右侧边缘之间的第三部分，在虚拟区13的第二部分和第三部分中仅设置有第三发光元件的阳极图案和像素限定层，需要说明的是，在虚拟区13的第 二部分和第三部分的至少部分区域还可以设置阴极图案。
此外，感测像素单元20中包括的第一发光元件22的第二端、显示像素单元中包括的第二发光元件32的第二端以及虚拟像素单元中包括的第三发光元件的第二端均连接至公共电压端(图中未示出)。例如，第一发光元件22的第二端、第二发光元件32的第二端和第三发光元件的第二端可以成一体结构，该一体结构连接至公共电压端，且至少覆盖感测区11、显示区12以及位于感测区11和显示区12之间的至少部分虚拟区13。
需要说明的是，在本公开的实施例中，硅基板可以为单晶硅基板或者绝缘体上硅(SOI)基板。硅基板包括第一像素电路21和第二像素电路31，也就是说，第一像素电路21和第二像素电路31制备在硅基板中。例如，在硅基板上还可以集成有栅极驱动电路、数据驱动电路等任意适用的电路部件，这些电路部件(即第一像素电路21、第二像素电路31、栅极驱动电路、数据驱动电路等)例如通过硅半导体工艺(例如CMOS工艺)制备，本公开的实施例对此不作限制。
需要说明的是，在本公开的实施例中，第一发光元件22和第二发光元件32可以是相同的发光元件，并且第一像素电路21除了包括可以感测第一发光元件22的第一端的电压的感测结构之外，其余结构与第二像素电路31可以是基本相同或相似的，也就是说，在向第一像素电路21和第二像素电路31写入相同的数据信号的情况下，第一像素电路21控制电压感测器感测到的第一发光元件22的第一端的电压实际上相当于第二发光元件32的第一端的电压。
此外，本公开的实施例提供的一种显示基板还可以包括调节电路(图中未示出)，调节电路被配置为基于显示基板的温度、预设发光亮度以及感测到的第一发光元件22的第一端的电压，来调节显示像素单元30中的第二发光元件32的第二端所连接的公共电压端提供的电压，使得显示像素单元30中的第二发光元件32可以在一定的温度条件下达到预设发光亮度。预设发光亮度由施加到第二像素电路31中的数据信号决定，预设发光亮度表示期望的第二发光元件32能够达到的亮度。预设发光亮度、显示基板的温度和数据信号的关系可以预先设定。显示 基板的温度表示显示基板处于工作状态时器件内部的温度，其可以经由设置在驱动芯片或衬底基板10的虚拟区13中的温度传感器检测得到。
在本公开的实施例中，电压感测器和调节电路可以分别单独设置，也可以集成到同一个IC(Integrated Circuit，集成电路)芯片中。
在本公开的实施例提供的显示基板中，发光元件(即，第一发光元件22或第二发光元件32)的发光特性会受到显示基板的温度的影响，在不同的温度条件下具有不同的发光特性；具体地，在发光元件的第一端的电压与第二端的电压之间的电压差值一定时，随着显示基板的温度变化，发光元件的发光亮度是不同的。在显示基板的温度不变的情况下，发光元件的第一端的电压与第二端的电压之间的电压差值越大，则发光元件的发光亮度越大。发光元件的发光亮度、显示基板的温度以及发光元件的第一端的电压与第二端的电压之间的电压差值三者是彼此对应的关系。例如，当显示基板的温度比较低时，可以通过增大发光元件的第一端的电压与第二端的电压之间的电压差值，来提升发光元件的发光亮度；当显示基板的温度比较高时，可以通过减小发光元件的第一端的电压与第二端的电压之间的电压差值，来降低发光元件的发光亮度。
在本公开的实施例提供的显示基板中，根据第一像素电路21控制电压感测器感测到的第一发光元件22的第一端的电压(即，第二发光元件32的第一端的电压)以及第二发光元件32的第二端连接到的公共电压端所提供的公共电压，可以得到当前的第二发光元件32的第一端的电压与第二端的电压之间的实际电压差值，而根据温度传感器感测到的当前的显示基板的温度以及预设发光亮度，可以确定在当前的显示基板的温度下，与预设发光亮度对应的第二发光元件32的第一端的电压与第二端的电压之间的预设电压差值，若实际电压差值和预设电压差值不相同，则可以调节公共电压端所提供的公共电压的大小以改变第二发光元件32的第一端的电压与第二端的电压之间的实际电压差值，使得实际电压差值和预设电压差值相同，从而使得第二发光元件32的发光亮度与当前的显示基板的温度相对应。
在本公开的实施例提供的显示基板中，通过第一像素电路21控制电压感测器感测第一发光元件22的第一端的电压，并且由于第一像素 电路21除了包括可以感测第一发光元件22的第一端的电压的感测结构之外，其余结构与第二像素电路31是基本相同或相似的，因此，在向第一像素电路21和第二像素电路31写入相同的数据信号的情况下，电压感测器感测到的第一发光元件22的第一端的电压相当于第二发光元件32的第一端的电压，从而无需在第二像素电路31中额外设置感测结构来直接感测第二发光元件32的第一端的电压，避免额外设置的感测结构影响显示像素单元30的显示性能。
图2为图1中的感测像素单元20的一种示意性框图。如图2所示，在感测像素单元20中，第一像素电路21包括第一复位电路210、第一数据写入电路220、第一驱动电路230、第一存储电路240和感测电路250。
如图2所示，第一复位电路210连接至第一复位控制信号线RST1、第一复位电压端VINT1、第一驱动电路230的第二端和第一发光元件22的第一端，被配置为在第一复位控制信号的控制下将第一复位电压施加至第一驱动电路230的第二端和第一发光元件22的第一端以对第一驱动电路230的第二端进行复位，也即对第一发光元件22的第一端进行复位。
如图2所示，第一数据写入电路220连接至第一扫描信号线SCAN1、第一数据信号线DATA1和第一驱动电路230的控制端，被配置为在第一扫描信号的控制下将第一数据信号写入第一驱动电路230的控制端。
如图2所示，第一驱动电路230的第一端连接至第一电压端VDD，第一驱动电路230的第二端连接至第一发光元件22的第一端，第一驱动电路230被配置为在施加至第一驱动电路230的控制端的电压的控制下驱动第一发光元件22发光。
如图2所示，第一存储电路240连接至第一驱动电路230的控制端和第二端，被配置为存储第一数据信号并将其保持在第一驱动电路230的控制端。
如图2所示，感测电路250连接至电压感测器VSEN、感测控制信号线SENS、第一驱动电路230的第二端和第一发光元件22的第一端， 被配置为在感测控制信号的控制下利用电压感测器VSEN感测第一驱动电路230的第二端的电压，也即感测第一发光元件22的第一端的电压。
如图2所示，第一发光元件22的第一端连接至第一驱动电路230的第二端，第一发光元件22的第二端连接至公共电压端VCOM。
图3为图2中的感测像素单元20的电路结构图。如图3所示，在感测像素单元20的第一像素电路21中，第一复位电路210包括第一复位晶体管Tr1，第一数据写入电路220包括第一数据写入晶体管Tw1，第一驱动电路230包括第一驱动晶体管Td1，第一存储电路240包括第一存储电容C1，感测电路250包括感测晶体管Ts。如图3所示，在感测像素单元20中，第一发光元件22包括第一OLED D1。
例如，第一驱动电路230的控制端包括第一驱动晶体管Td1的栅极，第一驱动电路230的第一端包括第一驱动晶体管Td1的第一极，第一驱动电路230的第二端包括第一驱动晶体管Td1的第二极；第一发光元件22的第一端包括第一OLED D1的阳极，第一发光元件22的第二端包括第一OLED D1的阴极。
如图3所示，第一复位晶体管Tr1的栅极连接至第一复位控制信号线RST1以接收第一复位控制信号，第一复位晶体管Tr1的第一极连接至第一复位电压端VINT1以接收复位电压，第一复位晶体管Tr1的第二极连接至第一驱动晶体管Td1的第二极和第一OLED D1的阳极。
如图3所示，第一数据写入晶体管Tw1的栅极连接至第一扫描信号线SCAN1以接收第一扫描信号，第一数据写入晶体管Tw1的第一极连接至第一数据信号线DATA1以接收第一数据信号，第一数据写入晶体管Tw1的第二极连接至第一驱动晶体管Td1的栅极。
如图3所示，第一驱动晶体管Td1的栅极连接至第一数据写入晶体管Tw1的第二极，第一驱动晶体管Td1的第一极连接至第一电压端VDD，第一驱动晶体管Td1的第二极连接至第一OLED D1的阳极。
如图3所示，第一存储电容C1的第一端连接至第一数据写入晶体管Tw1的第二极和第一驱动晶体管Td1的栅极，第一存储电容C1的第二端连接至第一驱动晶体管Td1的第二极。
如图3所示，感测晶体管Ts的栅极连接至感测控制信号线SENS以接收感测控制信号，感测晶体管Ts的第一极连接至电压感测器VSEN，感测晶体管Ts的第二极连接至第一驱动晶体管Td1的第二极和第一OLED D1的阳极。
如图3所示，第一OLED D1的阳极连接至第一驱动晶体管Td1的第二极，第一OLED D1的阴极连接至公共电压端VCOM。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，需要说明的是，本公开的实施例中采用的晶体管均可以为P型晶体管或N型晶体管，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。例如，对于N型晶体管，其(电流)输入端为漏极而输出端为源极，其控制端为栅极；对于P型晶体管，其(电流)输入端为源极而输出端为漏极，其控制端为栅极。对于不同类型的晶体管，其控制端的控制信号的电平也不相同。例如，对于N型晶体管，在控制信号为高电平时，该N型晶体管处于导通状态；而在控制信号为低电平时，N型晶体管处于截止状态。对于P型晶体管时，在控制信号为低电平时，该P型晶体管处于导通状态；而在控制信号为高电平时，P型晶体管处于截止状态。当采用N型晶体管时，可以采用氧化物半导体，例如氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)，作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。低温多晶硅通常指由非晶硅结晶得到多晶硅的结晶温度低于600摄氏度的情形。
图4为输入图3所示的第一像素电路的信号的时序图。如图4所示，第一像素电路21的工作过程包括三个阶段，分别为复位阶段P1、数据 写入阶段P2、发光阶段P3以及感测阶段P4，图4中示出了每个阶段中各个信号的时序波形。
图5A为图3所示的第一像素电路在复位阶段的等效电路图；图5B为图3所示的第一像素电路在数据写入阶段的等效电路图；图5C为图3所示的第一像素电路在发光阶段的等效电路图；图5D为图3所示的第一像素电路在感测阶段的等效电路图。
在图4以及图5A、图5B、图5C和图5D中，RST1、SCAN1、SENS和DATA1既用于表示相应的信号线，也用于表示相应的信号。在图5A、图5B/图5C和图5D中，VINT1、VDD和VCOM既用于表示相应的电压端，也用于表示相应的电压。此外，图5A、图5B、图5C和图5D中用“×”标识的晶体管均表示该晶体管在对应阶段内处于截止状态。
下面以第一复位晶体管Tr1、第一数据写入晶体管Tw1、第一驱动晶体管Td1和感测晶体管Ts均采用N型晶体管为例，结合图4以及图5A、图5B、图5C和图5D对图3所示的第一像素电路21的工作原理进行说明。
如图4所示，在复位阶段P1，向第一复位晶体管Tr1(即第一复位电路210)的栅极输入高电平的第一复位控制信号RST1，向感测晶体管Ts(即感测电路250)的栅极输入低电平的感测控制信号SENS，向第一数据写入晶体管Tw1(即第一数据写入电路220)的栅极输入低电平的第一扫描信号SCAN1。
如图4和图5A所示，在复位阶段P1，第一复位晶体管Tr1被第一复位控制信号RST1的高电平导通，感测晶体管Ts被感测控制信号SENS的低电平截止，第一数据写入晶体管Tw1被第一扫描信号SCAN1的低电平截止，同时，第一驱动晶体管Td1也处于截止状态。
如图5A所示，在复位阶段P1，由于第一复位晶体管Tr1导通，从而可以将第一复位电压VINT1通过第一复位晶体管Tr1施加至第一驱动晶体管Td1的第二极(即第一驱动电路230的第二端)和第一OLED D1的阳极(即第一发光元件22的第一端)以对第一驱动晶体管Td1的第二极和第一OLED D1的阳极进行复位。
如图4所示，在数据写入阶段P2，向第一数据写入晶体管Tw1的 栅极输入高电平的第一扫描信号SCAN1，向第一复位晶体管Tr1的栅极输入低电平的第一复位控制信号RST1，向感测晶体管Ts的栅极输入低电平的感测控制信号SENS。
如图4和图5B所示，在数据写入阶段P2，第一数据写入晶体管Tw1被第一扫描信号SCAN1的高电平导通，第一复位晶体管Tr1被第一复位控制信号RST1的低电平截止，感测晶体管Ts被感测控制信号SENS的低电平截止。
如图5B所示，在数据写入阶段P2，由于第一数据写入晶体管Tw1导通，第一数据信号DATA1通过第一数据写入晶体管Tw1写入第一驱动晶体管Td1的栅极，同时第一数据信号DATA1通过第一数据写入晶体管Tw1对第一存储电容C1(即第一存储电路240)进行充电，直至第一存储电容C1的第一端的电压为Vdata1，从而将第一数据信号DATA1存储在第一存储电容C1中，第一存储电容C1将存储的第一数据信号DATA1保持在第一驱动晶体管Td1的栅极。这里，Vdata1表示第一数据信号DATA1的电压。
如图4所示，在发光阶段P3，向第一数据写入晶体管Tw1的栅极输入低电平的第一扫描信号SCAN1，向第一复位晶体管Tr1的栅极输入低电平的第一复位控制信号RST1，向感测晶体管Ts的栅极输入低电平的感测控制信号SENS。
如图4和图5C所示，在发光阶段P3，第一数据写入晶体管Tw1被第一扫描信号SCAN1的低电平截止，第一复位晶体管Tr1被第一复位控制信号RST1的低电平截止，感测晶体管Ts被感测控制信号SENS的低电平截止。
如图5C所示，在发光阶段P3，由于第一存储电容C1将存储的第一数据信号DATA1保持在第一驱动晶体管Td1的栅极，第一驱动晶体管Td1的栅极的电压为Vdata1，第一驱动晶体管Td1导通，第一电压VDD通过第一驱动晶体管Td1驱动第一发光元件22发光。
如图4所示，在感测阶段P4，向感测晶体管Ts(即感测电路250)的栅极输入高电平的感测控制信号SENS以导通感测晶体管Ts，向第一数据写入晶体管Tw1的栅极输入低电平的第一扫描信号SCAN1，向 第一复位晶体管Tr1的栅极输入低电平的第一复位控制信号RST1。
如图4和图5D所示，在感测阶段P4，感测晶体管Ts被感测控制信号SENS的高电平导通，第一数据写入晶体管Tw1被第一扫描信号SCAN1的低电平截止，第一复位晶体管Tr1被第一复位控制信号RST1的低电平截止。
如图5D所示，在感测阶段P4，由于感测晶体管Ts导通，电压感测器VSEN通过感测晶体管Ts感测第一驱动晶体管Td1的第二极或第一OLED D1的阳极的电压。
如图4所示，感测阶段P4可以是发光阶段P3的一部分，也就是说，在发光阶段P3，当感测晶体管Ts被感测控制信号SENS的高电平导通时，第一像素电路21也同时进入了感测阶段P4。这样，在感测阶段P4，电压感测器VSEN可以通过感测晶体管Ts实时感测第一OLED D1在发光状态时其阳极的电压。
需要说明的是，在本公开的实施例中，第一驱动晶体管Td1工作在亚阈值区，此时第一驱动晶体管Td1产生的驱动电流可以根据下述公式得出：
Figure PCTCN2019103799-appb-000001
在上述公式中，I L表示驱动电流，Vth表示第一驱动晶体管Td1的阈值电压，Vgs表示第一驱动晶体管Td1的栅极和第二极(例如源极)之间的电压差，Io1表示Vgs＝Vth时的驱动电流，Vs表示第一驱动晶体管Td1的第二极的电压，q为电子的电量(为一常数值)，n为第一驱动晶体管Td1的沟道掺杂浓度，k为一常数值，T为第一驱动晶体管Td1的工作温度(即显示基板的温度)。
此外，流过第一OLED D1的电流可以根据下述公式得出：
Figure PCTCN2019103799-appb-000002
在上述公式中，I oled表示流过第一OLED D1的电流，Voled表示第一OLED D1的阳极和阴极之间的电压差，Io2表示第一OLED D1导通瞬间流过第一OLED D1的电流，Vcom表示公共电压端VCOM提供的电压，T为第一OLED D1的工作温度(即显示基板的温度)。
在本公开的实施例中，当第一驱动晶体管Td1工作在亚阈值区时，在理 想情况下，第一驱动晶体管Td1的第二极的电压Vs与第一驱动晶体管Td1的栅极的电压Vdata1之间存在线性关系，V s＝a·Vdata1+b，其中，a、b均为常数。也就是说，第一驱动晶体管Td1第二极的电压跟随第一驱动晶体管Td1栅极的电压的变化而线性变化。因此，写入到第一驱动晶体管Td1的栅极的电压(即第一数据信号DATA1的电压)不同，第一驱动晶体管Td1的第二极的电压Vs也不同，在感测阶段P4，通过电压感测器VSEN感测第一驱动晶体管Td1的第二极的电压Vs，也即感测第一OLED D1的阳极的电压，并在此基础上调节公共电压端VCOM提供的公共电压，可以调节第一OLED D1的两极之间的电压差，进而调整第一OLED D1的发光亮度。
图6为图1中的显示像素单元30的一种示意性框图。如图6所示，在显示像素单元30中，第二像素电路31包括第二复位电路310、第二数据写入电路320、第二驱动电路330和第二存储电路340。图6所示的显示像素单元30除了不包括感测电路之外，其余组成部分与图2所示的感测像素单元20是基本相同或相似的。
如图6所示，第二复位电路310连接至第二复位控制信号线RST2、第二复位电压端VINT2、第二驱动电路330的第二端和第二发光元件32的第一端，被配置为在第二复位控制信号的控制下将第二复位电压施加至第二驱动电路330的第二端和第二发光元件32的第一端以对第二驱动电路330的第二端进行复位，也即对第二发光元件32的第一端进行复位。
如图6所示，第二数据写入电路320连接至第二扫描信号线SCAN2、第二数据信号线DATA2和第二驱动电路330的控制端，被配置为在第二扫描信号的控制下将第二数据信号写入第二驱动电路330的控制端。
如图6所示，第二驱动电路330的第一端连接至第一电压端VDD，第二驱动电路330的第二端连接至第二发光元件32的第一端，第二驱动电路330被配置为在施加至第二驱动电路330的控制端的电压的控制下驱动第二发光元件32发光。
如图6所示，第二存储电路340连接至第二驱动电路330的控制端和第二端，被配置为存储第二数据信号并将其保持在第二驱动电路330 的控制端。
如图6所示，第二发光元件32的第一端连接至第二驱动电路330的第二端，第二发光元件32的第二端连接至公共电压端VCOM。
图7为图6所示的显示像素单元30的电路结构图。如图7所示，在显示像素单元30中，第二复位电路310包括第二复位晶体管Tr2，第二数据写入电路320包括第二数据写入晶体管Tw2，第二驱动电路330包括第二驱动晶体管Td2，第二存储电路340包括第二存储电容C2。如图7所示，在显示像素单元30中，第二发光元件32包括第二OLED D2。图7所示的显示像素单元30的电路除了不包括感测晶体管之外，其余电路结构与图3所示的感测像素单元20是基本相同或相似的。
例如，第二驱动电路330的控制端包括第二驱动晶体管Td2的栅极，第二驱动电路330的第一端包括第二驱动晶体管Td2的第一极，第二驱动电路330的第二端包括第二驱动晶体管Td2的第二极；第二发光元件32的第一端包括第二OLED D2的阳极，第二发光元件32的第二端包括第二OLED D2的阴极。
如图7所示，第二复位晶体管Tr2的栅极连接至第二复位控制信号线RST2以接收第二复位控制信号，第二复位晶体管Tr2的第一极连接至第二复位电压端VINT2以接收第二复位电压，第二复位晶体管Tr2的第二极连接至第二驱动晶体管Td2的第二极和第二OLED D2的阳极。
如图7所示，第二数据写入晶体管Tw2的栅极连接至第二扫描信号线SCAN2以接收第二扫描信号，第二数据写入晶体管Tw2的第一极连接至第二数据信号线DATA2以接收第二数据信号，第二数据写入晶体管Tw2的第二极连接至第二驱动晶体管Td2的栅极。
如图7所示，第二驱动晶体管Td2的栅极连接至第二数据写入晶体管Tw2的第二极，第二驱动晶体管Td2的第一极连接至第一电压端VDD，第二驱动晶体管Td2的第二极连接至第二OLED D2的阳极。
如图7所示，第二存储电容C2的第一端连接至第二数据写入晶体管Tw2的第二极和第二驱动晶体管Td2的栅极，第二存储电容C2的第二端连接至第二驱动晶体管Td2的第二极。
如图7所示，第二OLED D2的阳极连接至第二驱动晶体管Td2的第二极，第二OLED D2的阴极连接至公共电压端VCOM。
图7中的第二像素电路31的工作过程包括复位阶段、数据写入阶段和发光阶段，图7中的第二像素电路31的工作过程除了不包括感测阶段之外，其他阶段与图3所示的第一像素电路21的工作过程是基本相同或相似的，因此可以参看结合图4以及图5A、图5B和图5C所描述的第一像素电路21的工作过程，此处不再赘述。
图8为图1中的显示像素单元30的另一种示意性框图。如图8所示，在显示像素单元30中，第二像素电路31包括第二复位电路350、第二数据写入电路360、第二驱动电路370、第二存储电路380和电压控制电路390。图8所示的显示像素单元30除了不包括感测电路以及包括电压控制电路之外，其余组成部分与图2所示的感测像素单元20是基本相同或相似的。
如图8所示，第二复位电路350连接至第二复位控制信号线RST2、第二复位电压端VINT2和第二驱动电路370的第一端，被配置为在第二复位控制信号的控制下将第二复位电压施加至第二驱动电路370的第一端以通过第二驱动电路370对第二发光元件32的第一端进行复位。
如图8所示，第二数据写入电路360连接至第二扫描信号线SCAN2、第二数据信号线DATA2和第二驱动电路370的控制端，被配置为在第二扫描信号的控制下将第二数据信号写入第二驱动电路370的控制端。
如图8所示，第二驱动电路370的第二端连接至第二发光元件32的第一端，第二驱动电路370被配置为在施加至第二驱动电路370的控制端的电压的控制下驱动第二发光元件32发光。
如图8所示，第二存储电路380连接至第二驱动电路370的控制端和接地端GND，被配置为存储第二数据信号并将其保持在第二驱动电路330的控制端。
如图8所示，电压控制电路390连接至第一电压端VDD、电压控制信号端EM和第二驱动电路370的第一端，被配置为在电压控制信号的控制下将第一电压施加至第二驱动电路370的第一端。
如图8所示，第二发光元件32的第一端连接至第二驱动电路370的第二端，第二发光元件32的第二端连接至公共电压端VCOM。
图9为图8所示的显示像素单元30的电路结构图。如图9所示，在显示像素单元30中，第二复位电路350包括第二复位晶体管Tr3，第二数据写入电路360包括第二数据写入晶体管Tw3，第二驱动电路370包括第二驱动晶体管Td3，第二存储电路380包括第二存储电容C3，电压控制电路390包括电压控制晶体管Tc。如图9所示，在显示像素单元30中，第二发光元件32包括第二OLED D2。图9所示的显示像素单元30的电路除了不包括感测晶体管以及包括电压控制晶体管之外，其余电路结构与图3所示的感测像素单元20是基本相同或相似的。
如图9所示，第二驱动电路370的控制端包括第二驱动晶体管Td3的栅极，第二驱动电路370的第一端包括第二驱动晶体管Td3的第一极，第二驱动电路370的第二端包括第二驱动晶体管Td3的第二极；第二发光元件32的第一端包括第二OLED D2的阳极，第二发光元件32的第二端包括第二OLED D2的阴极。
如图9所示，第二复位晶体管Tr3的栅极连接至第二复位控制信号线RST2以接收第二复位控制信号，第二复位晶体管Tr3的第一极连接至第二复位电压端VINT2以接收第二复位电压，第二复位晶体管Tr3的第二极连接至第二驱动晶体管Td3的第一极。
如图9所示，第二数据写入晶体管Tw3的栅极连接至第二扫描信号线SCAN2以接收第二扫描信号，第二数据写入晶体管Tw3的第一极连接至第二数据信号线DATA2以接收第二数据信号，第二数据写入晶体管Tw3的第二极连接至第二驱动晶体管Td3的栅极。
如图9所示，第二驱动晶体管Td3的栅极连接至第二数据写入晶体管Tw3的第二极，第二驱动晶体管Td3的第一极连接至第二复位晶体管Tr3的第二极和电压控制晶体管Tc的第二极，第二驱动晶体管Td3的第二极连接至第二OLED D2的阳极。
如图9所示，第二存储电容C3的第一端连接至第二数据写入晶体管Tw3的第二极和第二驱动晶体管Td3的栅极，第二存储电容C3的第二端连接至接地端GND。
如图9所示，电压控制晶体管Tc的栅极连接至电压控制信号端EM，电压控制晶体管Tc的第一极连接至第一电压端VDD，电压控制晶体管Tc的第二极连接至第二驱动晶体管Td2的第一极。
如图9所示，第二OLED D2的阳极连接至第二驱动晶体管Td2的第二极，第二OLED D2的阴极连接至公共电压端VCOM。
图9中的第二像素电路31的工作过程包括复位阶段、数据写入阶段和发光阶段。下面以第二复位晶体管Tr3、第二数据写入晶体管Tw3、第二驱动晶体管Td3和电压控制晶体管Tc均采用N型晶体管为例，对图9所示的第二像素电路31的工作原理进行简单说明。
在复位阶段，第二复位晶体管Tr3被第二复位控制信号的高电平导通，第二复位电压通过第二复位晶体管Tr3施加至第二驱动晶体管Td3的第一极，以对第二OLED D2的阳极进行复位。
在数据写入阶段，第二数据写入晶体管Tw3被第二扫描信号的高电平导通，第二数据信号通过第二数据写入晶体管Tw3对第二存储电容C2进行充电，从而将第二数据信号存储在第二存储电容C3中，第二存储电容C3将存储的第二数据信号保持在第二驱动晶体管Td3的栅极。
在发光阶段，由于第二存储电容C3将存储的第二数据信号保持在第二驱动晶体管Td3的栅极，第二驱动晶体管Td3保持导通；同时，电压控制晶体管Tc被电压控制信号的高电平导通，第一电压通过电压控制晶体管Tc施加至第二驱动晶体管Td3的第一极，以驱动第二OLED D2发光。
对比参考图7和图9，图7所示的第二像素电路31，在复位阶段，第二复位电压直接通过第二复位晶体管Tr2施加至第二OLED D2的阳极以对第二OLED D2的阳极进行复位；图9所示的第二像素电路31，在复位阶段，第二复位电压是通过第二复位晶体管Tr3和第二驱动晶体管Td3施加至第二OLED D2的阳极以对第二OLED D2的阳极进行复位。此外，对比参考图7和图9，图7所示的第二像素电路31，在发光阶段，第一电压直接施加至第二驱动晶体管Td2的第一极以驱动第二OLED D2发光；图9所示的第二像素电路31，在发光阶段，第一电压 是通过电压控制晶体管Tc施加在第二驱动晶体管Td3的第一极以驱动第二OLED D2发光。
需要说明的是，在本公开的实施例提供的显示基板中，多个显示像素单元30包括的多个第二像素电路31既可以全部采用图6和图7所示的第二像素电路31的结构，也可以全部采用图9和图10所示的第二像素电路31的结构，还可以部分采用图6和图7所示的第二像素电路31的结构并且部分采用图9和图10所示的第二像素电路31的结构，本公开的实施例对此不作限制。
需要说明的是，在本公开的实施例提供的显示基板中，多个虚拟像素单元包括的多个第三像素电路既可以全部采用图6和图7所示的第二像素电路31的结构，也可以全部采用图9和图10所示的第二像素电路31的结构，还可以部分采用图6和图7所示的第二像素电路31的结构并且部分采用图9和图10所示的第二像素电路31的结构，本公开的实施例对此不作限制。
需要说明的是，在本公开实施例中，第一电压端VDD可以为高电压源以输出恒定的高电压。第一复位电压端VINT1、第二复位电压端VINT2和公共电压端VCOM可以为低电压源以输出恒定的低电压，并且这里的高、低仅表示输入的电压之间的相对大小关系。
需要说明的是，在本公开实施例中，第一扫描信号的值和第二扫描信号的值可以相同，或者，第一扫描信号和第二扫描信号可以是同一扫描信号；第一数据信号的值和第二数据信号的值可以相同，或者，第一数据信号和第二数据信号可以是同一数据信号；第一复位控制信号的值和第二复位控制信号的值可以相同，或者，第一复位控制信号和第二复位控制信号可以是同一复位控制信号；第一复位电压的值和第二复位电压的值可以相同，或者，第一复位电压和第二复位电压可以是同一复位电压，本公开的实施例对此不作限制。
此外，需要说明的是，在本公开实施例中，例如，多个显示像素单元可以排布为Q1列，多个感测像素单元可以排布为Q2列，其中，Q1和Q2均为正整数，且例如Q1大于Q2。在一些示例中，可以固定抽取或者随机抽取在显示区内的Q2列显示像素单元所对应的Q2个第二数 据信号，且将该Q2个第二数据信号分别作为与感测区的Q2列感测像素单元对应的Q2个第一数据信号，例如，Q2个第二数据信号与Q2列感测像素单元一一对应。在另一些示例中，每一列感测像素单元所对应的第一数据信号可以为在显示区内的多列显示像素单元(例如，10列或者100列显示像素单元)所对应的多个第二数据信号的平均值(例如，算术平均值)。需要说明的是，在本公开的实施例中，“第二数据信号”表示施加至显示像素单元的数据信号，而施加至不同显示像素单元的第二数据信号的值可以不相同；类似地，“第一数据信号”表示施加至感测像素单元的数据信号，而施加至不同感测像素单元的第一数据信号的值可以不相同。
在本公开的实施例提供的显示基板中，第二像素电路31除了不包括感测晶体管之外，其余结构与第一像素电路21是基本相同或相似的，也就是说，在向第一像素电路21和第二像素电路31写入相同的数据信号的情况下，电压感测器VSENS通过第一像素电路21感测到的第一发光元件22的第一端的电压可以相当于第二发光元件32的第一端的电压，因此根据感测到的第一发光元件22的第一端的电压以及第二发光元件32的第二端连接到的公共电压端所提供的公共电压，可以得到当前的第二发光元件32的第一端的电压与第二端的电压之间的实际电压差值，而根据温度传感器感测到的当前的显示基板的温度以及预设发光亮度，可以确定在当前的显示基板的温度下，与预设发光亮度对应的第二发光元件32的第一端的电压与第二端的电压之间的预设电压差值，若实际电压差值和预设电压差值不相同，则可以调节公共电压端所提供的公共电压的大小以改变第二发光元件32的第一端的电压与第二端的电压之间的实际电压差值，使得实际电压差值和预设电压差值相同，从而使得第二发光元件32的发光亮度与当前的显示基板的温度相对应。
本公开的实施例还提供另一种显示基板，该显示基板还包括遮光层，遮光层可以至少设置于衬底基板上的感测区内，且可以位于多个感测像素单元的远离衬底基板的一侧，遮光层被配置为遮挡从感测区的感测像素单元出射的光。
本公开的实施例提供的显示基板，通过在显示基板的感测区设置遮 光层，从而提高感测区的光密度(optical density，OD)值，进而起到对感测区进行遮光的效果。
图10为本公开的实施例提供的另一种显示基板的示意性框图。
如图10所示，该显示基板还包括遮光层40，遮光层40和多个感测像素单元20一起设置在感测区11内，遮光层40设置在多个感测像素单元20的远离衬底基板10的一侧，遮光层40被配置为遮挡从感测区11的感测像素单元20出射的光。
需要说明的是，“从感测区11的感测像素单元20出射的光”表示从感测区11朝向用户观看侧出射的光。例如，感测区11的感测像素单元20出射的光包括多个感测像素单元20的第一发光元件22发射的光和多个感测像素单元20的第一像素电路21中的金属层反射的光。
此外，需要说明的是，本公开的实施例提供的显示基板还可以在显示区12以外的部分均设置有遮光层，也就是说，在感测区11和虚拟区13中均设置有遮光层。此时，在感测区11中设置的遮光层被配置为遮挡从感测区11的感测像素单元20出射的光，即遮挡感测像素单元20包括的第一发光元件22发射的光和第一像素电路21中的金属层反射的光；在虚拟区13中设置的遮光层被配置为遮挡从虚拟区13的虚拟像素单元出射的光，即遮挡虚拟像素单元包括的第三像素电路的金属层反射的光。
图11为本公开一些实施例提供的另一种显示基板的平面结构示意图。
如图11所示，衬底基板10上除了感测区和显示区12之外的所有区域均为虚拟区13。如图11所示，虚拟区13包围感测区和显示区12，感测区和显示区12不直接接触，例如，感测区和显示区12由虚拟区13的一部分间隔开。
例如，如图11所示，感测区和显示区12沿第一方向X排布。第二方向Y与第一方向X相互垂直。
例如，显示区12的形状可以为矩形，感测区11的形状也可以为矩形。显示区12的相邻两条边分别与第一方向X和第二方向Y平行，感测区11的相邻两条边也分别与第一方向X和第二方向Y平行。
例如，显示区12的分辨率(即尺寸)可以为2916*1104，也就是说，在第一方向X上，显示区12的长度是2916，在第二方向Y上，显示区12的长度是1104。
例如，感测区11的分辨率可以为24*1104，也就是说，在第一方向X上，感测区11的长度是24，在第二方向Y上，感测区11的长度是1104，即在第二方向Y上，显示区12的长度和感测区11的长度相同。
例如，如图11所示，对于虚拟区13，在第一方向X上，虚拟区13的在感测区和显示区12之间的部分的长度d1可以为6，虚拟区13的在感测区11和衬底基板10的边缘(图2中的左侧边缘)之间的部分的长度d2可以为3，虚拟区13的在显示区12和衬底基板10的边缘(图2中的右侧边缘)之间的部分的长度d3可以为3；在第二方向Y上，虚拟区13的在感测区11和衬底基板10的边缘(图2中的上侧边缘)之间的部分的长度d4可以为2，虚拟区13的在感测区11和衬底基板10的边缘(图2中的下侧边缘)之间的部分的长度d5也可以为2，虚拟区13的在显示区12和衬底基板10的边缘(图2中的上侧边缘)之间的部分的长度d6可以为2，虚拟区13的在显示区12和衬底基板10的边缘(图2中的下侧边缘)之间的部分的长度d7也可以为2。
需要说明的是，在本公开的实施例中，分辨率、尺寸、长度等的单位均是像素，例如，显示区12的分辨率可以为2916像素*1104像素。
图12A为本公开的实施例提供的另一种显示基板的一种截面结构示意图，图12B为本公开的实施例提供的另一种显示基板的另一种截面结构示意图，图12C为本公开的实施例提供的另一种显示基板的又一种截面结构示意图。
如图12A所示，在一些实施例中，遮光层40包括第一遮光彩膜层401，第一遮光彩膜层401在衬底基板10上的正投影覆盖感测区11。第一遮光彩膜层401在衬底基板10上的正投影的形状与感测区11的形状相同或基本相同。在一些示例中，感测区11位于第一遮光彩膜层401在衬底基板10上的正投影之内，也就是说，第一遮光彩膜层401在衬底基板10上的正投影的尺寸大于或等于感测区11的尺寸。例如，在一 些示例中，感测区11与第一遮光彩膜层401在衬底基板10上的正投影彼此完全重叠，从而第一遮光彩膜层401在衬底基板10上的正投影的形状也可以为矩形，且第一遮光彩膜层401在衬底基板10上的正投影的尺寸可以为24*1104。
需要说明的是，第一遮光彩膜层401在衬底基板10上的正投影的形状还可以为梯形等合适的形状。这里，“形状相同或基本相同”是指两者都为同一类形状，但是并非指两者对应的边的比例相同。例如，当两者均为矩形时，各自的长宽比可以相同也可以不同，本公开的实施例对此不作限制。
这里，在本公开的实施例中，“正投影”是指元件沿垂直于衬底基板10的方向在平行于衬底基板10的平面内的投影，例如，“第一遮光彩膜层401的正投影”是指第一遮光彩膜层401沿垂直于衬底基板10的方向在平行于衬底基板10的平面内的投影。
例如，如图11和图12A所示，多个显示像素单元30可以包括第一显示像素单元301，第一显示像素单元301包括第一显示彩膜层3010。第一遮光彩膜层401和第一显示彩膜层3010具有相同的彩色滤光特性，例如，第一遮光彩膜层401和第一显示彩膜层3010通过同一构图工艺采用相同的滤光材料制备以使第一遮光彩膜层401和第一显示彩膜层3010具有相同的彩色滤光特性，从而在不增加工艺制程的基础上，即可制备第一遮光彩膜层401，从而实现对感测区11进行遮光的功能。此外，对于图12A所示的示例，由于遮光层40包括一层第一遮光彩膜层401，从而可以避免或减低彩膜(CF)制程造成的显示Mura的问题。
例如，在垂直于衬底基板10的方向上，第一遮光彩膜层401和第一显示彩膜层3010可以具有相同的厚度。
例如，第一遮光彩膜层401的远离衬底基板10的一侧为用户观看侧。
例如，在另一些示例中，如图12B所示，遮光层40还包括第二遮光彩膜层402，在垂直于衬底基板10的方向上，第一遮光彩膜层401位于第二遮光彩膜层402的远离衬底基板10的一侧，也就是说，第二遮光彩膜层402位于第一遮光彩膜层401和衬底基板10之间。
例如，第二遮光彩膜层402在衬底基板10上的正投影覆盖感测区11。第二遮光彩膜层402在衬底基板10上的正投影的形状与感测区11的形状相同或基本相同。在一些示例中，感测区11位于第二遮光彩膜层402在衬底基板10上的正投影之内，例如，感测区11与第二遮光彩膜层402在衬底基板10上的正投影彼此完全重叠，即第一遮光彩膜层401在衬底基板10上的正投影与第二遮光彩膜层402在衬底基板10上的正投影也彼此完全重叠，从而第二遮光彩膜层402在衬底基板10上的正投影的形状也可以为矩形，且第二遮光彩膜层402在衬底基板10上的正投影的尺寸也可以为24*1104。
例如，如图11和图12B所示，多个显示像素单元30还可以包括第二显示像素单元302，第二显示像素单元302包括第二显示彩膜层3020。第二遮光彩膜层402和第二显示彩膜层3020具有相同的彩色滤光特性，例如，第二遮光彩膜层402和第二显示彩膜层3020通过同一构图工艺采用相同的滤光材料制备以使第二遮光彩膜层402和第二显示彩膜层3020具有相同的彩色滤光特性，从而在不增加工艺制程的基础上，即可制备第一遮光彩膜层401和第二遮光彩膜层402，从而实现对感测区11进行遮光的功能。相对于仅在感测区11设置一层第一遮光彩膜层401，在感测区11设置第一遮光彩膜层401和第二遮光彩膜层402可以较好地对感测区11进行遮光，防止感测区11漏光。
例如，在垂直于衬底基板10的方向上，第二遮光彩膜层402和第二显示彩膜层3020可以具有相同的厚度。
例如，在又一些示例中，如图12C所示，遮光层40还可以包括第三遮光彩膜层403，在垂直于衬底基板10的方向上，第二遮光彩膜层402位于第三遮光彩膜层403的远离衬底基板10的一侧，也就是说，第三遮光彩膜层403位于第二遮光彩膜层402和衬底基板10之间，第二遮光彩膜层402位于第一遮光彩膜层401和第三遮光彩膜层403之间。
例如，第三遮光彩膜层403在衬底基板10上的正投影覆盖感测区11。第三遮光彩膜层403在衬底基板10上的正投影的形状与感测区11的形状相同或基本相同。在一些示例中，感测区11位于第三遮光彩膜 层403在衬底基板10上的正投影之内，例如，感测区11与第三遮光彩膜层403在衬底基板10上的正投影彼此完全重叠，即第一遮光彩膜层401在衬底基板10上的正投影、第二遮光彩膜层402在衬底基板10上的正投影、第三遮光彩膜层403在衬底基板10上的正投影均彼此完全重叠，从而第三遮光彩膜层403在衬底基板10上的正投影的形状也可以为矩形，且第三遮光彩膜层403在衬底基板10上的正投影的尺寸也可以为24*1104。
例如，如图11和图12C所示，多个显示像素单元30还包括第三显示像素单元303，第三显示像素单元303包括第三显示彩膜层3030。第三遮光彩膜层403和第三显示彩膜层3030具有相同的彩色滤光特性，例如，第三遮光彩膜层403和第三显示彩膜层3030通过同一构图工艺采用相同的滤光材料制备以使第三遮光彩膜层403和第三显示彩膜层3030具有相同的彩色滤光特性，从而在不增加工艺制程的基础上，即可制备第一遮光彩膜层401、第二遮光彩膜层402和第三遮光彩膜层403，从而实现对感测区11进行遮光的功能。相对于仅在感测区11设置一层第一遮光彩膜层401或设置第一遮光彩膜层401和第二遮光彩膜层402的情况，在感测区11设置第一遮光彩膜层401、第二遮光彩膜层402和第三遮光彩膜层13可以更好地对感测区11进行遮光，防止感测区11漏光。
例如，在垂直于衬底基板10的方向上，第三遮光彩膜层403和第三显示彩膜层3030可以具有相同的厚度。
例如，在垂直于衬底基板10的方向上，第一遮光彩膜层401的厚度、第二遮光彩膜层402的厚度和第三遮光彩膜层13的厚度可以均相等。
例如，第一遮光彩膜层401、第二遮光彩膜层402和第三遮光彩膜层403为不同的彩膜层。第一显示彩膜层3010、第二显示彩膜层3020和第三显示彩膜层3030也为不同的彩膜层。
例如，第一遮光彩膜层401和第一显示彩膜层3010为相同颜色的彩膜层，第二遮光彩膜层402和第二显示彩膜层3020为相同颜色的彩膜层，第三遮光彩膜层233和第三显示彩膜层3030为相同颜色的彩膜 层。在一些示例中，第一遮光彩膜层401和第一显示彩膜层3010均为蓝色彩膜层，也就是说，第一遮光彩膜层401和第一显示彩膜层3010均能遮挡红光、绿光等，而透过蓝光；第二遮光彩膜层402和第二显示彩膜层3020均为红色彩膜层，也就是说，第二遮光彩膜层402和第二显示彩膜层3020均能遮挡蓝光、绿光等，而透过红光；第三遮光彩膜层233和第三显示彩膜层3030均为绿色彩膜层，也就是说，第三遮光彩膜层233和第三显示彩膜层3030均能遮挡蓝光、红光等，而透过绿光。
又例如，在另一些示例中，第一遮光彩膜层401和第一显示彩膜层3010均为蓝色彩膜层，第二遮光彩膜层402和第二显示彩膜层3020为绿色彩膜层，第三遮光彩膜层233和第三显示彩膜层3030均为红色彩膜层。
需要说明的是，在又一些示例中，第一遮光彩膜层401和第一显示彩膜层3010可以均为红色彩膜层，第二遮光彩膜层402和第二显示彩膜层3020可以均为绿色彩膜层，第三遮光彩膜层233和第三显示彩膜层3030可以均为蓝色彩膜层；或者，第一遮光彩膜层401和第一显示彩膜层3010也可以均为绿色彩膜层，第二遮光彩膜层402和第二显示彩膜层3020也可以均为蓝色彩膜层，第三遮光彩膜层233和第三显示彩膜层3030也可以均为红色彩膜层等。本公开对此不作具体限制。
例如，第一遮光彩膜层401、第一显示彩膜层3010、第二遮光彩膜层402、第二显示彩膜层3020、第三遮光彩膜层233和第三显示彩膜层3030均位于封装层上，即位于封装层的远离衬底基板的一侧。
例如，下面将简单描述制备红色彩膜层、蓝色彩膜层和绿色彩膜层的工艺流程和工艺条件：首先进行预清洗的操作(Pre-clean)，然后手动涂胶，例如红色胶，涂红色胶的速度为450rpm/45秒(s)；在85℃的温度下对红色胶进行预烘烤(pre-bake)，预烘烤的时间为120s；对烘烤后的红色胶进行曝光处理(曝光剂量为120兆焦耳(mj))；对曝光后的红色胶进行显影处理，显影时间为180s；在90℃的温度下对显影后的红色胶再次进行烘烤(post bake)，烘烤时间为1800s，从而得到红色彩膜层；然后，再次涂胶，例如蓝色胶，涂蓝色胶的速度为 1100rpm/25s；在85℃的温度下对蓝色胶进行预烘烤(pre-bake)，预烘烤的时间为120s；对烘烤后的蓝色胶进行曝光处理(曝光剂量为115mj)；对曝光后的蓝色胶进行显影处理，显影时间为61s；在90℃的温度下对显影后的蓝色胶再次进行烘烤(post bake)，烘烤时间为1800s，从而得到蓝色彩膜层；最后，再次涂胶，例如绿色胶，涂绿色胶的速度为1050rpm/20s；在85℃的温度下对绿色胶进行预烘烤(pre-bake)，预烘烤的时间为120s；对烘烤后的绿色胶进行曝光处理(曝光剂量为110mj)；对曝光后的绿色胶进行显影处理，显影时间为58s；在90℃的温度下对显影后的绿色胶再次进行烘烤(post bake)，烘烤时间为1800s，从而得到绿色彩膜层。
图13为本公开的实施例提供的另一种显示基板的又一种截面结构示意图。
例如，如图13所示，遮光层40可以包括黑色遮光层404，黑色遮光层404可以完全遮挡从感测区11的感测像素单元20出射的光。黑色遮光层404在衬底基板10上的正投影覆盖感测区11。在一些示例中，感测区11位于黑色遮光层404在衬底基板10上的正投影之内，例如，感测区11与黑色遮光层404在衬底基板10上的正投影彼此完全重叠，从而黑色遮光层404在衬底基板10上的正投影的形状也可以为矩形，且黑色遮光层404在衬底基板10上的正投影的尺寸也可以为24*1104。相对于在感测区11设置彩膜层(例如，第一遮光彩膜层401、第二遮光彩膜层402、第三遮光彩膜层403)的方式，在感测区11设置黑色遮光层404可以避免彩膜制程工艺造成的Mura问题。
例如，黑色遮光层404可以为黑矩阵。
例如，黑色遮光层404可以在制备第一显示彩膜层3010、第二显示彩膜层3020和第三显示彩膜层3030之前形成在衬底基板10上。
例如，在垂直于衬底基板10的方向上，黑色遮光层404的厚度可以与第一显示彩膜层3010、第二显示彩膜层3020和第三显示彩膜层3030中的任意一个的厚度相等。
再次参考图1，每个显示像素单元30可以包括第一像素电路31和第二发光元件32，第一像素电路31连接至第二发光元件32的第一端， 且被配置为驱动第二发光元件32发光，该第二发光元件32被配置为发出白光。
例如，每个显示像素单元30中的第二发光元件32与显示彩膜层配合以发出不同颜色的光，显示彩膜层可以设置在第二发光元件32的远离衬底基板10的一侧。例如，若第一显示像素单元301中的第一显示彩膜层3010为蓝色彩膜层，则第一显示像素单元301中的第二发光元件发出的白光经过该第一显示彩膜层3010后得到蓝光，也就是说，第一显示像素单元301被配置为显示蓝光。若第二显示像素单元302中的第二显示彩膜层3020为红色彩膜层，则第二显示像素单元302中的第二发光元件发出的白光经过该第二显示彩膜层3020后得到红光，也就是说，第二显示像素单元302被配置为显示红光。若第三显示像素单元303中的第三显示彩膜层3030为绿色彩膜层，则第三显示像素单元303中的第二发光元件发出的白光经过该第三显示彩膜层3030后得到绿光，也就是说，第三显示像素单元303被配置为显示绿光。
例如，如图11所示，多个显示像素单元30沿第一方向X和第二方向Y阵列排布，第一方向X可以为多个显示像素单元30的行方向，第二方向Y可以为多个显示像素单元30的列方向。
例如，如图11所示，多个显示像素单元30采用BV3阵列排布方式排布在显示区12内。BV3阵列排布方式可以表示：在第一方向X上，奇数像素单元行中的各显示像素单元的排列方式与偶数像素单元行的各显示像素单元的排列方式不相同。如图11所示，例如，在奇数像素单元行中，显示像素单元的排列方式均为BRGBRG(即按照第一显示像素单元B、第二显示像素单元R、第三显示像素单元G、第一显示像素单元B、第二显示像素单元R、第三显示像素单元G的方式排列)；在偶数像素单元行中，显示像素单元的排列方式均为GBRGBR(即按照第三显示像素单元、第一显示像素单元、第二显示像素单元、第三显示像素单元、第一显示像素单元、第二显示像素单元的方式排列)。
例如，如图11所示，对于第一显示像素单元B，第一像素单元行的第一显示像素单元B和第三像素单元行的第一显示像素单元B均位于同一像素单元列中，第二像素单元行的第一显示像素单元B和第四 像素单元行的第一显示像素单元B均位于同一像素单元列中，即相邻两像素单元行中的第一显示像素单元B错开排列。如图11所示，与第一显示像素单元B类似，相邻两像素单元行中的第二显示像素单元R也错开排列，相邻两像素单元行中的第三显示像素单元G也错开排列。例如，在第一像素单元行中，显示像素单元的排列方式为BRGBRG；在第二像素单元行中，显示像素单元的排列方式为GBRGBR；而在第三像素单元行中，显示像素单元的排列方式为BRGBRG，而在第四像素单元行中，显示像素单元的排列方式为GBRGBR。
需要说明的是，“排列方式”表示不同颜色的显示像素单元的排列方式。
本公开的实施例还提供一种显示面板，包括本公开的前述任一实施例提供的显示基板。
例如，显示面板可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板不仅可以为平面面板，也可以为曲面面板，甚至球面面板。例如，显示面板还可以具备触控功能，即显示面板可以为触控显示面板。
例如，显示面板可以应用于硅基OLED显示装置，例如，可以应用在虚拟现实设备或增强显示设备中，当然，也可以应用于其他类型的显示装置，本公开的实施例对此不作限制。
本公开实施例提供的显示面板具有与本公开前述实施例提供的显示基板相同或相似的有益效果，由于显示基板在前述实施例中已经进行了详细说明，此处不再赘述。
本公开实施例还提供一种用于前述实施例的显示基板的调压方法。
图14为本公开的实施例提供的一种显示基板的调压方法的流程图。如图14所示，该显示基板的调压方法可以包括：
S10：通过第一像素电路控制电压感测器感测第一发光元件的第一端的电压。
S20：基于显示基板的温度、预设发光亮度以及感测到的第一发光元件的第一端的电压，调节第二发光元件的第二端的电压。
例如，在步骤S10中，通过第一像素电路感测第一发光元件的第一 端的电压可以包括：
S110：复位阶段，通过第一复位电路将第一复位电压施加至第一发光元件的第一端以对第一发光元件的第一端进行复位。
S120：数据写入阶段，通过第一数据写入电路将第一数据信号写入第一驱动电路的控制端。
S130：发光阶段，通过第一驱动电路驱动第一发光元件发光。
S140：感测阶段，通过感测电路感测第一发光元件的第一端的电压。
关于本公开的实施例提供的显示基板的调压方法的详细描述以及技术效果可以参考显示基板的实施例中的相应描述，这里不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示基板，包括衬底基板，所述衬底基板为硅基板，包括显示区、感测区和虚拟区；至少部分所述虚拟区位于所述显示区和所述感测区之间；
    在所述感测区内设有多个感测像素单元，所述多个感测像素单元中的至少一个包括第一发光元件和第一像素电路，所述第一像素电路连接至所述第一发光元件的第一端以及电压感测器，且被配置为驱动所述第一发光元件发光、以及控制所述电压感测器感测所述第一发光元件的第一端的电压；
    在所述显示区内设有多个显示像素单元，所述多个显示像素单元中的至少一个包括第二像素电路和第二发光元件，所述第二像素电路连接至所述第二发光元件的第一端，且被配置为驱动所述第二发光元件发光以显示图像；
    在所述虚拟区内设有多个虚拟像素单元，所述多个虚拟像素单元中的至少一个包括第三像素电路和第三发光元件，所述第三像素电路与所述第二像素电路相同，所述第三发光元件与所述第二发光元件相同，所述第三像素电路不与所述第三发光元件连接；
    所述第一发光元件的第二端、所述第二发光元件的第二端和所述第三发光元件的第二端成一体结构；所述一体结构连接至公共电压端，且至少覆盖所述显示区、所述感测区、以及位于所述显示区和所述感测区之间的至少部分所述虚拟区。
  2. 如权利要求1所述的显示基板，其中，所述第一像素电路包括第一数据写入电路、第一驱动电路和第一存储电路；其中，
    所述第一数据写入电路连接至所述第一驱动电路的控制端，被配置为在第一扫描信号的控制下将第一数据信号写入所述第一驱动电路的控制端；
    所述第一驱动电路的第二端连接至所述第一发光元件的第一端，所述第一驱动电路被配置为在施加至所述第一驱动电路的控制端的电压的控制下驱动所述第一发光元件发光；
    所述第一存储电路连接至所述第一驱动电路的控制端，被配置为存储所述第一数据信号并将其保持在所述第一驱动电路的控制端；
    所述第二像素电路包括第二数据写入电路、第二驱动电路和第二存储电路；其中，
    所述第二数据写入电路连接至所述第二驱动电路的控制端，被配置为在第二扫描信号的控制下将第二数据信号写入所述第二驱动电路的控制端；
    所述第二驱动电路的第二端连接至所述第二发光元件的第一端，所述第二驱动电路被配置为在施加至所述第二驱动电路的控制端的电压的控制下驱动所述第二发光元件发光；
    所述第二存储电路连接至所述第二驱动电路的控制端，被配置为存储所述第二数据信号并将其保持在所述第二驱动电路的控制端。
  3. 如权利要求2所述的显示基板，其中，所述第一像素电路还包括第一复位电路；所述第一复位电路连接至所述第一发光元件的第一端，被配置为在第一复位控制信号的控制下将第一复位电压施加至所述第一发光元件的第一端以对所述第一发光元件的第一端进行复位；
    所述第二像素电路还包括第二复位电路；所述第二复位电路被配置为在第二复位控制信号的控制下利用第二复位电压对所述第二发光元件的第一端进行复位。
  4. 如权利要3所述的显示基板，其中，所述第二复位电路连接至所述第二发光元件的第一端，被配置为在第二复位控制信号的控制下将第二复位电压施加至所述第二发光元件的第一端以对所述第二发光元件的第一端进行复位。
  5. 如权利要3所述的显示基板，其中，所述第二复位电路连接至所述第二驱动电路的第一端，被配置为在第二复位控制信号的控制下将第二复位电压施加至所述第二驱动电路的第一端以通过所述第二驱动电路对所述第二发光元件的第一端进行复位。
  6. 如权利要5所述的显示基板，其中，所述第二像素电路还包括电压控制电路，
    所述电压控制电路连接至所述第二驱动电路的第一端，被配置为在电压控制信号的控制下将第一电压施加至所述第二驱动电路的第一端。
  7. 如权利要求3所述的显示基板，其中，所述第一数据写入电路包括第一数据写入晶体管，所述第一驱动电路包括第一驱动晶体管，所述第一存储电路包括第一存储电容，所述第一复位电路包括第一复位晶 体管；
    所述第一驱动电路的控制端包括所述第一驱动晶体管的栅极，所述第一驱动电路的第一端包括所述第一驱动晶体管的第一极，所述第一驱动电路的第二端包括所述第一驱动晶体管的第二极；
    所述第一数据写入晶体管的栅极接收所述第一扫描信号，所述第一数据写入晶体管的第一极接收所述第一数据信号，所述第一数据写入晶体管的第二极连接至所述第一驱动晶体管的栅极；
    所述第一存储电容的第一端连接至所述第一驱动晶体管的栅极，所述第一存储电容的第二端连接至所述第一驱动晶体管的第二极；
    所述第一复位晶体管的栅极接收所述第一复位控制信号，所述第一复位晶体管的第一极接收所述第一复位电压，所述第一复位晶体管的第二极连接至所述第一驱动晶体管的第二极。
  8. 如权利要求4所述的显示基板，其中，所述第二数据写入电路包括第二数据写入晶体管，所述第二驱动电路包括第二驱动晶体管，所述第二存储电路包括第二存储电容，所述第二复位电路包括第二复位晶体管；
    所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，所述第二驱动电路的第一端包括所述第二驱动晶体管的第一极，所述第二驱动电路的第二端包括所述第二驱动晶体管的第二极；
    所述第二数据写入晶体管的栅极接收所述第二扫描信号，所述第二数据写入晶体管的第一极接收所述第二数据信号，所述第二数据写入晶体管的第二极连接至所述第二驱动晶体管的栅极；
    所述第二存储电容的第一端连接至所述第二驱动晶体管的栅极，所述第二存储电容的第二端连接至所述第二驱动晶体管的第二极；
    所述第二复位晶体管的栅极接收所述第二复位控制信号，所述第二复位晶体管的第一极接收所述第二复位电压，所述第二复位晶体管的第二极连接至所述第二驱动晶体管的第二极。
  9. 如权利要求6所述的显示基板，其中，所述第二数据写入电路包括第二数据写入晶体管，所述第二驱动电路包括第二驱动晶体管，所述第二存储电路包括第二存储电容，所述第二复位电路包括第二复位晶体管，所述电压控制电路包括电压控制晶体管；
    所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，所述 第二驱动电路的第一端包括所述第二驱动晶体管的第一极，所述第二驱动电路的第二端包括所述第二驱动晶体管的第二极；
    所述第二数据写入晶体管的栅极接收所述第二扫描信号，所述第二数据写入晶体管的第一极接收所述第二数据信号，所述第二数据写入晶体管的第二极连接至所述第二驱动晶体管的栅极；
    所述第二存储电容的第一端连接至所述第二驱动晶体管的栅极，所述第二存储电容的第二端连接至接地端；
    所述第二复位晶体管的栅极接收所述第二复位控制信号，所述第二复位晶体管的第一极接收所述第二复位电压，所述第二复位晶体管的第二极连接至所述第二驱动晶体管的第一极；
    所述电压控制晶体管的栅极接收所述电压控制信号，所述电压控制晶体管的第一极接收所述第一电压，所述电压控制晶体管的第二极连接至所述第二驱动晶体管的第一极。
  10. 如权利要求1-3中任一项所述的显示基板，其中，所述第一像素电路还包括感测电路；
    所述感测电路连接至所述第一发光元件的第一端，被配置为在感测控制信号的控制下控制所述电压感测器感测所述第一发光元件的第一端的电压。
  11. 如权利要求10所述的显示基板，其中，所述感测电路包括感测晶体管，
    所述感测晶体管的栅极接收所述感测控制信号，所述感测晶体管的第一极连接至所述电压感测器，所述感测晶体管的第二极连接至所述第一发光元件的第一端。
  12. 如权利要求1所述的显示基板，其中，所述感测区、至少部分所述虚拟区和所述显示区沿第一方向依次排布；
    在所述第一方向上，所述感测区的尺寸介于所述显示区的尺寸和至少部分所述虚拟区的尺寸之间。
  13. 如权利要求1-12中任一项所述的显示基板，还包括调节电路，其中，所述调节电路被配置为基于感测到的所述第一发光元件的第一端的电压以及所述显示基板的温度和预设发光亮度，调节所述公共电压端提供的电压。
  14. 如权利要求1-13中任一项所述的显示基板，还包括遮光层， 其中，所述遮光层至少设置于所述感测区内，且所述遮光层位于所述多个感测像素单元的远离所述衬底基板的一侧，所述遮光层被配置为遮挡从所述感测区的感测像素单元出射的光。
  15. 如权利要求14所述的显示基板，其中，所述遮光层包括第一遮光彩膜层、第二遮光彩膜层和第三遮光彩膜层，
    在垂直于所述衬底基板的方向上，所述第一遮光彩膜层、所述第二遮光彩膜层、所述第三遮光彩膜层依次设置在远离所述衬底基板的一侧，所述第一遮光彩膜层、所述第二遮光彩膜层和所述第三遮光彩膜层的重叠区域在所述衬底基板上的正投影覆盖所述感测区；
    所述多个显示像素单元包括第一显示像素单元、第二显示像素单元和第三显示像素单元，所述第一显示像素单元包括第一显示彩膜层，所述第二显示像素单元包括第二显示彩膜层，所述第三显示像素单元包括第三显示彩膜层，
    所述第一遮光彩膜层和所述第一显示彩膜层具有相同的彩色滤光特性，所述第二遮光彩膜层和所述第二显示彩膜层具有相同的彩色滤光特性，所述第三遮光彩膜层和所述第三显示彩膜层具有相同的彩色滤光特性。
  16. 如权利要求14所述的显示基板，其中，所述遮光层包括黑色遮光层，在垂直于所述衬底基板的方向上，所述黑色遮光层在所述衬底基板上的正投影覆盖所述感测区。
  17. 如权利要求14-16任一项所述的显示基板，其中，所述遮光层还设置于所述虚拟区内，且所述遮光层位于所述多个虚拟像素单元的远离所述衬底基板的一侧，所述遮光层被配置为遮挡从所述虚拟区的虚拟像素单元出射的光。
  18. 如权利要求1所述的显示基板，其中，所述第一发光元件与所述第二发光元件相同或者不同；
    所述第一像素电路与所述第二像素电路相同或者不同。
  19. 一种显示面板，包括权利要求1-18中任一项所述的显示基板。
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