WO2021032166A1 - 一种移位寄存器及其驱动方法、栅极驱动电路 - Google Patents

一种移位寄存器及其驱动方法、栅极驱动电路 Download PDF

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Publication number
WO2021032166A1
WO2021032166A1 PCT/CN2020/110277 CN2020110277W WO2021032166A1 WO 2021032166 A1 WO2021032166 A1 WO 2021032166A1 CN 2020110277 W CN2020110277 W CN 2020110277W WO 2021032166 A1 WO2021032166 A1 WO 2021032166A1
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Prior art keywords
transistor
terminal
electrode
node
pull
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PCT/CN2020/110277
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/294,690 priority Critical patent/US11455936B2/en
Publication of WO2021032166A1 publication Critical patent/WO2021032166A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a shift register, a driving method thereof, and a gate driving circuit.
  • the display panel includes a gate driving circuit and a pixel circuit arranged in an array.
  • the gate drive circuit includes a plurality of shift registers. Different shift registers are connected to different rows of pixel circuits, and are arranged to provide scanning signals to the connected pixel circuits during the display phase.
  • the pixel circuit includes a driving transistor. Due to the limitation of the manufacturing process of the driving transistor, the parameters of different driving transistors are different, so that different pixel circuits output different driving currents. In order to ensure the display effect of the display panel, the pixel circuit is detected in the non-display stage, and the parameters of the driving transistor can be obtained to externally compensate the pixel circuit.
  • the present disclosure provides a shift register including: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit;
  • the input sub-circuit is respectively connected with the signal input terminal, the first power terminal and the pull-up node, and is configured to provide the signal of the first power terminal with the pull-up node under the control of the signal input terminal;
  • the detection control sub-circuit is connected to the random detection signal terminal, the signal input terminal, the first clock signal terminal, the first reset terminal, and the pull-up node, respectively, and is set at the signal input terminal, the random detection signal terminal, and the first clock signal terminal. Under the control of the terminal and the first reset terminal, the pull-up node provides the signal of the first clock signal terminal;
  • the first reset sub-circuit is respectively connected to the first reset terminal, the pull-up node and the second power terminal, and is configured to provide a signal of the second power terminal to the pull-up node under the control of the first reset terminal;
  • the output sub-circuit is respectively connected to the second clock signal terminal, the third clock signal terminal, the pull-up node, the first output terminal and the second output terminal, and is set to output to the first output terminal under the control of the pull-up node Provide the signal of the third clock signal terminal, and provide the signal of the second clock signal terminal to the second output terminal;
  • the pull-down sub-circuit is connected to the first power supply terminal, the second power supply terminal, the third power supply terminal, the pull-up node, the first output terminal and the second output terminal, respectively, and is arranged at the first power supply terminal and the pull-up node Under control, the pull-up node and the second output terminal provide the signal of the second power terminal, and the signal of the third power terminal is provided to the first output terminal.
  • the detection control sub-circuit includes: a detection node control sub-circuit and a detection output sub-circuit;
  • the detection node control sub-circuit is respectively connected with the signal input terminal, the detection node, the random detection signal, the pull-up node and the first reset terminal, and is set to be under the control of the signal input terminal, the random detection signal terminal and the first reset terminal, Provide the signal input terminal or pull-up node signal to the detection node;
  • the detection output sub-circuit is respectively connected to the detection node, the first clock signal terminal and the pull-up node, and is configured to provide the signal of the first clock signal terminal to the pull-up node under the control of the first clock signal terminal and the detection node.
  • it further includes: a second reset sub-circuit
  • the second reset sub-circuit is respectively connected to the second reset terminal, the pull-up node, the detection node and the second power terminal, and is configured to provide a signal of the second power terminal to the pull-up node and the detection node under the control of the second reset terminal .
  • the detection node control sub-circuit includes: a first transistor, a second transistor, and a third transistor;
  • control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode of the first transistor is connected to the detection node;
  • the control electrode of the second transistor is connected to the random detection signal terminal, the first electrode of the second transistor is connected to the detection node, and the second electrode of the second transistor is connected to the first electrode of the third transistor;
  • the control electrode of the third transistor is connected to the first reset terminal, and the second electrode of the third transistor is connected to the pull-up node.
  • the detection output sub-circuit includes: a fourth transistor, a fifth transistor, and a first capacitor;
  • the control electrode of the fourth transistor is connected to the detection node, the first electrode of the fourth transistor is connected to the first clock signal terminal, and the second electrode of the fourth transistor is connected to the first electrode of the fifth transistor;
  • the control electrode of the fifth transistor is connected to the first clock signal terminal, and the second electrode of the fifth transistor is connected to the pull-up node;
  • the first end of the first capacitor is connected to the detection node, and the second end of the first capacitor is connected to the second electrode of the fourth transistor.
  • the input sub-circuit includes: a sixth transistor
  • the control electrode of the sixth transistor is connected to the signal input terminal, the first electrode of the sixth transistor is connected to the first power terminal, and the second electrode of the sixth transistor is connected to the pull-up node.
  • the output sub-circuit includes: a seventh transistor, an eighth transistor, and a second capacitor;
  • the control electrode of the seventh transistor is connected to the pull-up node, the first electrode of the seventh transistor is connected to the second clock signal terminal, and the second electrode of the seventh transistor is connected to the second output terminal;
  • the control electrode of the eighth transistor is connected to the pull-up node, the first electrode of the eighth transistor is connected to the third clock signal terminal, and the second electrode of the eighth transistor is connected to the first output terminal;
  • the first end of the second capacitor is connected to the pull-up node, and the second end of the second capacitor is connected to the first output end.
  • the pull-down sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • control electrode and the first electrode of the ninth transistor are connected to the first power terminal, and the second electrode of the ninth transistor is connected to the pull-down node;
  • the control electrode of the tenth transistor is connected to the pull-up node, the first electrode of the tenth transistor is connected to the pull-down node, and the second electrode of the tenth transistor is connected to the second power terminal;
  • the control electrode of the eleventh transistor is connected to the pull-down node, the first electrode of the eleventh transistor is connected to the pull-up node, and the second electrode of the eleventh transistor is connected to the second power terminal;
  • the control electrode of the twelfth transistor is connected to the pull-down node, the first electrode of the twelfth transistor is connected to the second output terminal, and the second electrode of the twelfth transistor is connected to the second power terminal;
  • the control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode of the thirteenth transistor is connected to the first output terminal, and the second electrode of the thirteenth transistor is connected to the third power terminal.
  • the first reset sub-circuit includes: a fourteenth transistor
  • the control electrode of the fourteenth transistor is connected to the first reset terminal, the first electrode of the fourteenth transistor is connected to the pull-up node, and the second electrode of the fourteenth transistor is connected to the second power terminal.
  • the second reset sub-circuit includes: a fifteenth transistor and a sixteenth transistor;
  • the control electrode of the fifteenth transistor is connected to the second reset terminal, the first electrode of the fifteenth transistor is connected to the detection node, and the second electrode of the fifteenth transistor is connected to the pull-up node;
  • the control electrode of the sixteenth transistor is connected to the second reset terminal, the first electrode of the sixteenth transistor is connected to the pull-up node, and the second electrode of the sixteenth transistor is connected to the second power terminal.
  • it further includes: a second reset sub-circuit
  • the detection control sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor;
  • the input sub-circuit includes: a sixth transistor;
  • the output sub-circuit Including: a seventh transistor, an eighth transistor and a second capacitor;
  • the pull-down sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the first reset sub-circuit The circuit includes: a fourteenth transistor;
  • the second reset sub-circuit includes: a fifteenth transistor and a sixteenth transistor;
  • control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode of the first transistor is connected to the detection node;
  • the control electrode of the second transistor is connected to the random detection signal terminal, the first electrode of the second transistor is connected to the detection node, and the second electrode of the second transistor is connected to the first electrode of the third transistor;
  • the control electrode of the third transistor is connected to the first reset terminal, and the second electrode of the third transistor is connected to the pull-up node;
  • the control electrode of the fourth transistor is connected to the detection node, the first electrode of the fourth transistor is connected to the first clock signal terminal, and the second electrode of the fourth transistor is connected to the first electrode of the fifth transistor;
  • the control electrode of the fifth transistor is connected to the first clock signal terminal, and the second electrode of the fifth transistor is connected to the pull-up node;
  • the first terminal of the first capacitor is connected to the detection node, and the second terminal of the first capacitor is connected to the second electrode of the fourth transistor;
  • the control electrode of the sixth transistor is connected to the signal input terminal, the first electrode of the sixth transistor is connected to the first power supply terminal, and the second electrode of the sixth transistor is connected to the pull-up node;
  • the control electrode of the seventh transistor is connected to the pull-up node, the first electrode of the seventh transistor is connected to the second clock signal terminal, and the second electrode of the seventh transistor is connected to the second output terminal;
  • the control electrode of the eighth transistor is connected to the pull-up node, the first electrode of the eighth transistor is connected to the third clock signal terminal, and the second electrode of the eighth transistor is connected to the first output terminal;
  • the first end of the second capacitor is connected to the pull-up node, and the second end of the second capacitor is connected to the first output end;
  • control electrode and the first electrode of the ninth transistor are connected to the first power terminal, and the second electrode of the ninth transistor is connected to the pull-down node;
  • the control electrode of the tenth transistor is connected to the pull-up node, the first electrode of the tenth transistor is connected to the pull-down node, and the second electrode of the tenth transistor is connected to the second power terminal;
  • the control electrode of the eleventh transistor is connected to the pull-down node, the first electrode of the eleventh transistor is connected to the pull-up node, and the second electrode of the eleventh transistor is connected to the second power terminal;
  • the control electrode of the twelfth transistor is connected to the pull-down node, the first electrode of the twelfth transistor is connected to the second output terminal, and the second electrode of the twelfth transistor is connected to the second power terminal;
  • the control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode of the thirteenth transistor is connected to the first output terminal, and the second electrode of the thirteenth transistor is connected to the third power terminal;
  • the control electrode of the fourteenth transistor is connected to the first reset terminal, the first electrode of the fourteenth transistor is connected to the pull-up node, and the second electrode of the fourteenth transistor is connected to the second power terminal;
  • the control electrode of the fifteenth transistor is connected to the second reset terminal, the first electrode of the fifteenth transistor is connected to the detection node, and the second electrode of the fifteenth transistor is connected to the pull-up node;
  • the control electrode of the sixteenth transistor is connected to the second reset terminal, the first electrode of the sixteenth transistor is connected to the pull-up node, and the second electrode of the sixteenth transistor is connected to the second power terminal.
  • the present disclosure also provides a gate driving circuit, including: a plurality of shift registers described above;
  • the signal input terminal of the first stage shift register is connected with the initial signal terminal
  • the signal input terminal of the second stage shift register is connected with the initial signal terminal
  • the signal input terminal of the N+2 stage shift register is connected with the Nth stage shift
  • the second output terminal of the register is connected
  • the first reset terminal of the Nth stage shift register is connected with the second output terminal of the N+3 stage shift register, and N ⁇ 1.
  • the gate drive circuit includes: a first clock terminal, a second clock terminal, a third clock terminal, a fourth clock terminal, a fifth clock terminal, a sixth clock terminal, and a seventh clock terminal And the eighth clock terminal;
  • the second clock signal terminal of the 4i+1 stage shift register is connected to the first clock terminal, the third clock signal terminal of the 4i+1 stage shift register is connected to the fifth clock terminal, and the 4i+2 stage shift register
  • the second clock signal terminal is connected to the second clock terminal, the third clock signal terminal of the 4i+2 stage shift register is connected to the sixth clock terminal, and the second clock signal terminal of the 4i+3 stage shift register is connected to the first
  • the three clock terminals are connected, the third clock signal terminal of the 4i+3 stage shift register is connected to the seventh clock terminal, the second clock signal terminal of the 4i+4 stage shift register is connected to the fourth clock terminal, and the 4i+ The third clock signal terminal of the 4-stage shift register is connected to the eighth clock terminal.
  • the present disclosure also provides a method for driving a shift register, which is applied to the above shift register, the shift register is arranged in a display panel, and the display panel includes: a display phase and a detection phase, so
  • the methods include:
  • the input sub-circuit under the control of the signal input terminal, the input sub-circuit provides the signal of the first power terminal to the pull-up node; under the control of the pull-up node, the output sub-circuit provides the signal of the third clock signal terminal to the first output terminal, The second output terminal provides the signal of the second clock signal terminal; under the control of the first power terminal and the pull-up node, and under the control of the first reset terminal, the first reset sub-circuit provides the signal of the second power terminal to the pull-up node; Under the control of the power terminal and the pull-up node, the pull-down sub-circuit provides the signal of the second power terminal to the pull-up node and the second output terminal, and provides the signal of the third power terminal to the first output terminal;
  • the detection control sub-circuit In the detection phase, under the control of the signal input terminal, the random detection signal terminal, the first clock signal terminal and the first reset terminal, the detection control sub-circuit provides the signal of the first clock signal terminal to the pull-up node, and under the control of the pull-up node, The output sub-circuit provides the signal of the third clock signal terminal to the first output terminal.
  • the method further includes: under the control of the second reset terminal, the second reset sub-circuit provides a signal of the second power terminal to the pull-up node and the detection node.
  • FIG. 1 is a schematic structural diagram of a shift register provided by an embodiment of the disclosure
  • Fig. 2 is a schematic structural diagram of a shift register provided by an exemplary embodiment
  • Fig. 3 is a schematic structural diagram of a shift register provided by another exemplary embodiment
  • FIG. 4 is an equivalent circuit diagram of a detection node control sub-circuit provided by an exemplary embodiment
  • Fig. 5 is an equivalent circuit diagram of a detection output sub-circuit provided by an exemplary embodiment
  • Fig. 6 is an equivalent circuit diagram of an input sub-circuit provided by an exemplary embodiment
  • Fig. 7 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment
  • Fig. 8 is an equivalent circuit diagram of a pull-down sub-circuit provided by an exemplary embodiment
  • Fig. 9 is an equivalent circuit diagram of a first reset sub-circuit provided by an exemplary embodiment
  • Fig. 10 is an equivalent circuit diagram of a second reset sub-circuit provided by an exemplary embodiment
  • Fig. 11 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment
  • FIG. 12A is a first working sequence diagram of a shift register provided by an exemplary embodiment
  • FIG. 12B is a second working sequence diagram of the shift register provided by an exemplary embodiment
  • FIG. 12C is a third working timing diagram of the shift register provided by an exemplary embodiment
  • FIG. 13 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the disclosure.
  • FIG. 14 is a working timing diagram of a gate driving circuit provided by an exemplary embodiment.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the thin film transistor may be an oxide semiconductor transistor. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged.
  • the gate of the transistor becomes the control electrode. In order to distinguish the two poles of the transistor except the gate, one of the poles is called the first pole and the other is called the second pole.
  • the first pole can be the source or drain, and the second can be the drain or source. pole.
  • the output of the shift register is relatively single, and multiple pulse outputs cannot be realized, so that the shift register cannot output the scanning signal in the non-display stage, resulting in the inability to detect the pixel circuit, which affects the display effect.
  • FIG. 1 is a schematic structural diagram of a shift register provided by an embodiment of the disclosure.
  • the shift register provided by the embodiment of the present disclosure includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit.
  • the input sub-circuits are respectively connected to the signal input terminal INPUT, the first power supply terminal VDD and the pull-up node PU, and are set to provide the first power terminal VDD signal to the pull-up node PU under the control of the signal input terminal INPUT;
  • the circuit is connected to the random detection signal terminal OE, the signal input terminal INPUT, the first clock signal terminal CLKA, the first reset terminal RST1, and the pull-up node PU, respectively, and is set at the signal input terminal INPUT, the random detection signal terminal OE, and the first Under the control of the clock signal terminal CLKA and the first reset terminal RST1, the pull-up node PU provides the signal of the first clock signal terminal CLKA;
  • the first reset sub-circuit is respectively connected with the first reset terminal RST1, the pull-up node PU and the second power supply
  • the terminal VGL1 is connected, and is set to pull up the node PU to provide the signal of the second power terminal VGL1 under the control of the first reset terminal
  • the first power supply terminal VDD continuously provides a high-level signal.
  • the second power terminal VGL1 and the third power terminal VGL2 continuously provide low-level signals.
  • the signal potentials of the second power terminal VGL1 and the third power terminal VGL2 may be the same or may be different.
  • the potential of the signal of the third power terminal VGL2 is higher than the signal potential of the second power terminal VGL1.
  • the first output terminal may be set to output a driving signal of the current level
  • the second output terminal may be set to output a cascade signal
  • the shift register is provided in the display panel.
  • the display panel includes a display phase and a detection phase, where the detection phase is a period of time in the non-display phase.
  • the detection control sub-circuit provided in this embodiment may not affect the potential of the pull-up node during the display phase.
  • the signal input terminal INPUT in the input sub-circuit provides a signal to the pull-up node PU, and the pull-up node PU provides the first clock during the detection phase.
  • the signal of the signal terminal CLKA can make the shift register output a scanning signal in the detection phase.
  • the clock signals of the second clock signal terminal CLKB and the third clock signal terminal CLKC are the same.
  • the pulse width relationship of the signals of the first clock signal terminal CLKA, the second clock signal terminal CLKB, and the third clock signal terminal CLKC can be adjusted.
  • the signal of the random detection signal terminal OE is a random signal, which is generated by an external circuit such as a field programmable gate array.
  • the signal of the random detection signal terminal OE is different, and the pixel circuit to be detected is also different, that is, the shift register that can realize multiple pulse output is also different.
  • the shift register provided by the embodiment of the present disclosure includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit and a pull-down sub-circuit;
  • the input sub-circuit is connected to the signal input terminal, the first power terminal and the upper
  • the pull node connection is set to provide the signal of the first power terminal to the pull node under the control of the signal input terminal;
  • the detection control sub-circuit is connected to the random detection signal terminal, the signal input terminal, the first clock signal terminal, the first reset terminal and
  • the pull-up node is connected, and is set to provide the signal of the first clock signal terminal to the pull-up node under the control of the signal input terminal, the random detection signal terminal, the first clock signal terminal and the first reset terminal;
  • the first reset sub-circuit is connected with the A reset terminal, a pull-up node and a second power terminal are connected, and are set to provide a signal of the second power terminal to the pull-up node
  • Fig. 2 is a schematic structural diagram of a shift register provided by an exemplary embodiment.
  • the detection control sub-circuit in the shift register provided by an exemplary embodiment includes: a detection node control sub-circuit and a detection output sub-circuit.
  • the detection node control sub-circuit is connected to the signal input terminal INPUT, the detection node PS, the random detection signal terminal OE, the pull-up node PU, and the first reset terminal RST1, respectively, and is set at the signal input terminal INPUT, the random detection signal terminal OE and the first reset terminal. Under the control of a reset terminal RST1, the signal input terminal INPUT or the signal of the pull-up node PU is provided to the detection node PS.
  • the detection output sub-circuit is respectively connected with the detection node PS, the first clock signal terminal CLKA and the pull-up node PU, and is set to provide the first clock signal to the pull-up node PU under the control of the first clock signal terminal CLKA and the detection node PS The signal of terminal CLKA.
  • Fig. 3 is a schematic structural diagram of a shift register provided by another exemplary embodiment. As shown in FIG. 3, the shift register provided by an exemplary embodiment further includes: a second reset sub-circuit.
  • the second reset sub-circuit is respectively connected to the second reset terminal RST2, the pull-up node PU, the detection node PS and the second power supply terminal VGL1, and is set to pull up the node PU and the detection node PS under the control of the second reset terminal RST2 Provide the signal of the second power terminal VGL1.
  • Fig. 4 is an equivalent circuit diagram of a detection node control sub-circuit provided by an exemplary embodiment.
  • the detection node control sub-circuit provided by an exemplary embodiment includes: a first transistor M1, a second transistor M2, and a third transistor M3.
  • the control electrode and the first electrode of the first transistor M1 are connected to the signal input terminal INPUT, and the second electrode of the first transistor M1 is connected to the detection node PS.
  • the control electrode of the second transistor M2 is connected to the random detection signal terminal OE, the first electrode of the second transistor M2 is connected to the detection node PS, and the second electrode of the second transistor M2 is connected to the first electrode of the third transistor M3.
  • the control electrode of the third transistor M3 is connected to the first reset terminal RST1, and the second electrode of the third transistor M3 is connected to the pull-up node PU.
  • FIG. 4 An exemplary structure of the detection node control sub-circuit is shown in FIG. 4.
  • the implementation of the detection node control sub-circuit is not limited to this.
  • Fig. 5 is an equivalent circuit diagram of a detection output sub-circuit provided by an exemplary embodiment.
  • the detection output sub-circuit provided by an exemplary embodiment includes: a fourth transistor M4, a fifth transistor M5, and a first capacitor C1.
  • the control electrode of the fourth transistor M4 is connected to the detection node PS, the first electrode of the fourth transistor M4 is connected to the first clock signal terminal CLKA, and the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5.
  • the control electrode of the fifth transistor M5 is connected to the first clock signal terminal CLKA, and the second electrode of the fifth transistor M5 is connected to the pull-up node PU.
  • the first terminal of the first capacitor C1 is connected to the detection node PS, and the second terminal of the first capacitor C1 is connected to the second electrode of the fourth transistor M4.
  • FIG. 5 An exemplary structure of the detection output sub-circuit is shown in FIG. 5. The implementation of the detection output sub-circuit is not limited to this.
  • Fig. 6 is an equivalent circuit diagram of an input sub-circuit provided by an exemplary embodiment. As shown in FIG. 6, the input sub-circuit provided by an exemplary embodiment includes: a sixth transistor M6.
  • the control electrode of the sixth transistor M6 is connected to the signal input terminal INPUT, the first electrode of the sixth transistor M6 is connected to the first power terminal VDD, and the second electrode of the sixth transistor M6 is connected to the pull-up node PU.
  • FIG. 6 An exemplary structure of the input sub-circuit is shown in FIG. 6. The implementation of the input sub-circuit is not limited to this.
  • Fig. 7 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment.
  • the output sub-circuit provided by an exemplary embodiment includes: a seventh transistor M7, an eighth transistor M8, and a second capacitor C2.
  • the control electrode of the seventh transistor M7 is connected to the pull-up node PU, the first electrode of the seventh transistor M7 is connected to the second clock signal terminal CLKB, and the second electrode of the seventh transistor M7 is connected to the second output terminal OUT2.
  • the control electrode of the eighth transistor M8 is connected to the pull-up node PU, the first electrode of the eighth transistor M8 is connected to the third clock signal terminal CLKC, and the second electrode of the eighth transistor M8 is connected to the first output terminal OUT1.
  • the first end of the second capacitor C2 is connected to the pull-up node PU, and the second end of the second capacitor C2 is connected to the first output terminal OUT1.
  • FIG. 7 An exemplary structure of the output sub-circuit is shown in FIG. 7.
  • the implementation of the output sub-circuit is not limited to this.
  • Fig. 8 is an equivalent circuit diagram of a pull-down sub-circuit provided by an exemplary embodiment.
  • the pull-down sub-circuit provided by an exemplary embodiment includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13.
  • the control electrode and the first electrode of the ninth transistor M9 are connected to the first power supply terminal VDD, and the second electrode of the ninth transistor M9 is connected to the pull-down node PD.
  • the control electrode of the tenth transistor M10 is connected to the pull-up node PU, the first electrode of the tenth transistor M10 is connected to the pull-down node PD, and the second electrode of the tenth transistor M10 is connected to the second power terminal VGL1.
  • the control electrode of the eleventh transistor M11 is connected to the pull-down node PD, the first electrode of the eleventh transistor M11 is connected to the pull-up node PU, and the second electrode of the eleventh transistor M11 is connected to the second power terminal VGL1.
  • the control electrode of the twelfth transistor M12 is connected to the pull-down node PD, the first electrode of the twelfth transistor M12 is connected to the second output terminal OUT2, and the second electrode of the twelfth transistor M12 is connected to the second power terminal VGL1.
  • the control electrode of the thirteenth transistor M13 is connected to the pull-down node PD, the first electrode of the thirteenth transistor M13 is connected to the first output terminal OUT1, and the second electrode of the thirteenth transistor M13 is connected to the third power terminal VGL2.
  • FIG. 8 An exemplary structure of the pull-down sub-circuit is shown in FIG. 8. The implementation of the pull-down sub-circuit is not limited to this.
  • Fig. 9 is an equivalent circuit diagram of a first reset sub-circuit provided by an exemplary embodiment. As shown in FIG. 9, the first reset sub-circuit provided by an exemplary embodiment includes: a fourteenth transistor M14.
  • the control electrode of the fourteenth transistor M14 is connected to the first reset terminal RST1, the first electrode of the fourteenth transistor M14 is connected to the pull-up node PU, and the second electrode of the fourteenth transistor M14 is connected to the second power terminal VGL1.
  • FIG. 9 An exemplary structure of the first reset sub-circuit is shown in FIG. 9. The implementation of the first reset sub-circuit is not limited to this.
  • Fig. 10 is an equivalent circuit diagram of a second reset sub-circuit provided by an exemplary embodiment.
  • the second reset sub-circuit provided by an exemplary embodiment includes: a fifteenth transistor M15 and a sixteenth transistor M16.
  • the control electrode of the fifteenth transistor M15 is connected to the second reset terminal RST2, the first electrode of the fifteenth transistor M15 is connected to the detection node PS, and the second electrode of the fifteenth transistor M15 is connected to the pull-up node PU.
  • the control electrode of the sixteenth transistor M16 is connected to the second reset terminal RST2, the first electrode of the sixteenth transistor M16 is connected to the pull-up node PU, and the second electrode of the sixteenth transistor M16 is connected to the second power supply terminal VGL1.
  • FIG. 10 An exemplary structure of the second reset sub-circuit is shown in FIG. 10. The implementation of the second reset sub-circuit is not limited to this.
  • Fig. 11 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment.
  • the shift register provided by an exemplary embodiment may further include: a second reset sub-circuit.
  • the detection control sub-circuit includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a first capacitor C1;
  • the input sub-circuit includes: a sixth transistor M6;
  • the circuit includes: a seventh transistor M7, an eighth transistor M8, and a second capacitor C2;
  • the pull-down sub-circuit includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13 ;
  • the first reset sub-circuit includes: a fourteenth transistor M14;
  • the second reset sub-circuit includes: a fifteenth transistor M15 and a sixteenth transistor M16.
  • the control electrode and the first electrode of the first transistor M1 are connected to the signal input terminal INPUT, and the second electrode of the first transistor M1 is connected to the detection node PS.
  • the control electrode of the second transistor M2 is connected to the random detection signal terminal OE, the first electrode of the second transistor M2 is connected to the detection node PS, and the second electrode of the second transistor M2 is connected to the first electrode of the third transistor M3.
  • the control electrode of the third transistor M3 is connected to the first reset terminal RST1, and the second electrode of the third transistor M3 is connected to the pull-up node PU.
  • the control electrode of the fourth transistor M4 is connected to the detection node PS, the first electrode of the fourth transistor M4 is connected to the first clock signal terminal CLKA, and the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5.
  • the control electrode of the fifth transistor M5 is connected to the first clock signal terminal CLKA, and the second electrode of the fifth transistor M5 is connected to the pull-up node PU.
  • the first terminal of the first capacitor C1 is connected to the detection node PS, and the second terminal of the first capacitor C1 is connected to the second electrode of the fourth transistor M4.
  • the control electrode of the sixth transistor M6 is connected to the signal input terminal INPUT, the first electrode of the sixth transistor M6 is connected to the first power terminal VDD, and the second electrode of the sixth transistor M6 is connected to the pull-up node PU.
  • the control electrode of the seventh transistor M7 is connected to the pull-up node PU, the first electrode of the seventh transistor M7 is connected to the second clock signal terminal CLKB, and the second electrode of the seventh transistor M7 is connected to the second output terminal OUT2.
  • the control electrode of the eighth transistor M8 is connected to the pull-up node PU, the first electrode of the eighth transistor M8 is connected to the third clock signal terminal CLKC, and the second electrode of the eighth transistor M8 is connected to the first output terminal OUT1.
  • the first terminal of the second capacitor C2 is connected to the pull-up node PU, and the second terminal of the second capacitor C2 is connected to the first output terminal OUT1.
  • the control electrode and the first electrode of the ninth transistor M9 are connected to the first power supply terminal VDD, and the second electrode of the ninth transistor M9 is connected to the pull-down node PD.
  • the control electrode of the tenth transistor M10 is connected to the pull-up node PU, the first electrode of the tenth transistor M10 is connected to the pull-down node PD, and the second electrode of the tenth transistor M10 is connected to the second power terminal VGL1.
  • the control electrode of the eleventh transistor M11 is connected to the pull-down node PD, the first electrode of the eleventh transistor M11 is connected to the pull-up node PU, and the second electrode of the eleventh transistor M11 is connected to the second power terminal VGL1.
  • the control electrode of the twelfth transistor M12 is connected to the pull-down node PD, the first electrode of the twelfth transistor M12 is connected to the second output terminal OUT2, and the second electrode of the twelfth transistor M12 is connected to the second power terminal VGL1.
  • the control electrode of the thirteenth transistor M13 is connected to the pull-down node PD, the first electrode of the thirteenth transistor M13 is connected to the first output terminal OUT1, and the second electrode of the thirteenth transistor M13 is connected to the third power terminal VGL2.
  • the control electrode of the fourteenth transistor M14 is connected to the first reset terminal RST1, the first electrode of the fourteenth transistor M14 is connected to the pull-up node PU, and the second electrode of the fourteenth transistor M14 is connected to the second power terminal VGL1.
  • the control electrode of the fifteenth transistor M15 is connected to the second reset terminal RST2, the first electrode of the fifteenth transistor M15 is connected to the detection node PS, and the second electrode of the fifteenth transistor M15 is connected to the pull-up node PU.
  • the control electrode of the sixteenth transistor M16 is connected to the second reset terminal RST2, the first electrode of the sixteenth transistor M16 is connected to the pull-up node PU, and the second electrode of the sixteenth transistor M16 is connected to the second power terminal
  • the transistors M1 to M16 may be N-type thin film transistors, or may be P-type thin film transistors.
  • the process flow can be unified, the process process can be reduced, and the product yield can be improved.
  • all transistors may be low temperature polysilicon thin film transistors. All transistors are low-temperature polysilicon thin film transistors, which can reduce leakage current in the shift register.
  • the thin film transistor may be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure.
  • the first capacitor C1 and the second capacitor C2 may be parasitic capacitors of transistors, or may be external capacitors.
  • FIG. 12A is a working sequence diagram 1 of the shift register provided by an exemplary embodiment
  • FIG. 12B is The second working sequence diagram of the shift register provided by an exemplary embodiment
  • FIG. 12C is the third working sequence diagram of the shift register provided by an exemplary embodiment. As shown in FIGS.
  • the shift register provided by an exemplary embodiment includes 16 transistor units (M1 to M16), 2 capacitors (C1 and C2), and 7 signal input terminals (INPUT, RST1, RST2, OE, CLKA, CLKB and CLKC), 2 signal output terminals (OUT1 and OUT2) and 3 power terminals (VDD, VGL1 and VGL2).
  • the first power terminal VDD continuously provides a high level signal.
  • the second power terminal VGL1 and the second power terminal VGL2 continuously provide low-level signals.
  • the display panel includes: display stage Display and detection stage Sense.
  • the input signals of the second reset terminal RST2 and the first clock signal terminal CLKA are always low level.
  • the detection phase Sense the input signals of the first reset terminal RST1, the signal input terminal INPUT, the random detection signal terminal OE, and the second clock signal terminal CLKB are always low level.
  • the input signal of the second reset terminal RST2 is at a high level, which can make the fifteenth transistor M15 and the sixteenth transistor M16 in the shift register turn on to connect the pull-up node PU and the detection node PS The potential is initialized.
  • the working process of the shift register includes:
  • the first stage D1 that is, the input stage, the input signals of the signal input terminal INPUT and the random detection signal terminal OE are high, the first transistor M1 and the second transistor M2 are turned on, and the potential of the detection node PS is pulled high.
  • a capacitor C1 is charged and the fourth transistor M4 is turned on, but since the clock signal of the first clock signal terminal CLKA is low, the potential of the pull-up node PU will not be affected by the clock signal of the first clock signal terminal CLKA.
  • the sixth transistor M6 is turned on to pull up the potential of the pull-up node PU to charge the second capacitor C2.
  • the seventh transistor M7 and the eighth transistor M8 are turned on, but due to the second clock signal terminal CLKB and the third clock signal The clock signal of the terminal CLKC is low, therefore, the first output terminal OUT1 and the second output terminal OUT2 are not output.
  • the ninth transistor M9 is turned on under the control of the first power supply terminal VDD, since the tenth transistor M10 is turned on under the control of the pull-up node PU, the potential of the pull-down node PD is pulled low, so that the eleventh transistors M11, The twelfth transistor M12 and the thirteenth transistor M13 are turned off, the input signal of the first reset terminal RST1 is low, and the third transistor M3 and the fourteenth transistor M14 are turned off. Therefore, the pull-up node PU remains high.
  • the output stage, the input signal of the random detection signal terminal OE continues to be high, the second transistor M2 is turned on, and the input signal of the signal input terminal INPUT is low, the first transistor M1 and the sixth transistor M6 is turned off.
  • the potential of the detection node PS is pulled up, and the fourth transistor M4 is turned on.
  • the clock signal of the first clock signal terminal CLKA is low, the potential of the pull-up node PU will not be affected by the clock signal of the first clock signal terminal CLKA.
  • the pull-up node PU The potential of PU is pulled high, and the seventh transistor M7 and the eighth transistor M8 are turned on.
  • the clock signals of the second clock signal terminal CLKB and the third clock signal terminal CLKC are high level, and the first output terminal OUT1 and the second output terminal OUT2 output high level signals.
  • the ninth transistor M9 is turned on under the control of the first power supply terminal VDD, since the tenth transistor M10 is turned on under the control of the pull-up node PU, the potential of the pull-down node PD is pulled low, so that the eleventh transistors M11, The twelfth transistor M12 and the thirteenth transistor M13 are turned off, the input signal of the first reset terminal RST1 is low, and the third transistor M3 and the fourteenth transistor M14 are turned off. Therefore, the pull-up node PU remains high.
  • the input signal of the random detection signal terminal OE is still high, the second transistor M2 is turned on, the input signal of the signal input terminal INPUT is still low, the first transistor M1 and the sixth transistor M6 are turned off, The potential of the detection node PS starts to drop, but the fourth transistor M4 can still be turned on. Since the clock signal of the first clock signal terminal CLKA is low, the potential of the pull-up node PU will not be affected by the clock signal of the first clock signal terminal CLKA. The potential of the pull-up node PU begins to drop, but the seventh transistor M7 and the eighth transistor M8 can still be turned on.
  • the first output terminal OUT1 and the second output terminal OUT2 are not output.
  • the ninth transistor M9 is turned on under the control of the first power supply terminal VDD, since the tenth transistor M10 can still be turned on under the control of the pull-up node PU, the potential of the pull-down node PD is pulled down, so that the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are still off, the input signal of the first reset terminal RST1 is low, and the third transistor M3 and the fourteenth transistor M14 are still off.
  • the reset stage the input signal of the random detection signal terminal OE is still high, the second transistor M2 is turned on, the input signal of the first reset terminal RST1 is high, the third transistor M3 and the tenth
  • the four transistor M14 is turned on to pull down the potential of the pull-up node PU and the detection node PS.
  • the ninth transistor M9 is turned on under the control of the first power supply terminal VDD to pull the potential of the pull-down node PD high.
  • the tenth transistor M10 is at The pull-up node PU is turned off under the control, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are turned on, pulling down the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 To reduce noise.
  • the input signal of the signal input terminal INPUT is a pulse signal, which is high level only in the input stage.
  • the output signals of the first output terminal OUT1 and the second output terminal OUT2 are pulse signals, which are high level only in the output stage.
  • the signal of the first reset terminal RST1 is a pulse signal, which is high level only in the reset phase.
  • the random signal output by the random detection signal terminal OE and the output signal of a certain stage of shift register in the display stage are inverted signals. Take the random signal and the output signal of the Nth shift register as an inverted signal as an example, from the first shift register to the Nth shift register except for the N-3th shift register In the reset phase of the shift register, the random signal of the random detection signal terminal OE is always high, that is, during the reset phase, the second transistor M2 and the third transistor M3 are turned on, the potential of the detection node PS is pulled down, and other working processes The working process is the same as before.
  • the working process of the N-3th stage shift register is different from the above working process in that the input signal of the random detection signal terminal OE in the reset phase is low, the second transistor M2 is turned off, and the third transistor M3 is turned on, so that the detection The potential of the node PS is not pulled low, therefore, the potential of the detection node PS in the N-3th stage shift register is always high.
  • the working process of the N-stage shift register is described as an example, and FIG. 12C is described with the N-3th stage shift register as an example.
  • the pixel circuit to be detected depends on the input signal of the random detection signal terminal OE. If the input signal of the random detection signal terminal OE and the output signal of the Nth stage shift register are inverted signals, the pixel circuit to be detected is the pixel circuit connected to the N-3th stage shift register.
  • the working process of the shift register connected to the pixel circuit to be detected includes:
  • the signal of the detection node PS is high, the fourth transistor M4 is turned on, the clock signal of the first clock signal terminal CLKA is high, the fifth transistor M5 is turned on, and the potential of the pull-up node PU is The clock signal of the first clock signal terminal CLKA is pulled high, the seventh transistor M7 and the eighth transistor M8 are turned on, but because the clock signal of the third clock signal terminal CLKC is low, the first output terminal OUT1 is not output.
  • the ninth transistor M9 is turned on under the control of the first power supply terminal VDD, since the tenth transistor M10 is turned on under the control of the pull-up node PU, the potential of the pull-down node PD is pulled low, so that the eleventh transistors M11, The twelfth transistor M12 and the thirteenth transistor M13 are turned off, and the potential of the pull-up node PU remains high.
  • the clock signal of the first clock signal terminal CLKA is low, and the fifth transistor M5 is turned off.
  • the potential of the pull-up node PU is pulled high, and the seventh transistor M7 And the eighth transistor M8 is turned on, the clock signal of the third clock signal terminal CLKC is high level, and the first output terminal OUT1 outputs a high level signal.
  • the ninth transistor M9 is turned on under the control of the first power supply terminal VDD, since the tenth transistor M10 is turned on under the control of the pull-up node PU, the potential of the pull-down node PD is pulled low, so that the eleventh transistors M11, The twelfth transistor M12 and the thirteenth transistor M13 are turned off, and therefore, the potential of the pull-up node PU remains high.
  • the potential of the pull-up node PU begins to drop, but the seventh transistor M7 and the eighth transistor M8 can still be turned on. Since the clock signal of the third clock signal terminal CLKC is at a low level, there is no output from the first output terminal OUT1. Although the ninth transistor M9 is turned on under the control of the first power supply terminal VDD, since the tenth transistor M10 can still be turned on under the control of the pull-up node PU, the potential of the pull-down node PD is pulled down, so that the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 are still off.
  • the input signal of the second reset terminal RST2 is high, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, and the potentials of the pull-up node PU and the detection node PS are pulled low.
  • the ninth transistor M9 is turned on under the control of the first power supply terminal VDD to pull the potential of the pull-down node PD high, the tenth transistor M10 is turned off under the control of the pull-up node PU, and the eleventh transistor M11 and the twelfth transistor M12 and the thirteenth transistor M13 are turned on, and the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 can be pulled down to reduce noise.
  • the shift registers of the other stages except the N-3th stage shift register have no output in the detection stage.
  • the shift register realizes multiple pulse output, which can not only output the drive signal in the display stage, but also output the drive signal in the detection stage.
  • FIG. 13 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the disclosure.
  • the gate driving circuit provided by the embodiment of the present disclosure includes a plurality of shift registers.
  • the signal input terminal INPUT of the first stage shift register GOA(1) is connected to the initial signal terminal STV
  • the signal input terminal INPUT of the second stage shift register GOA(2) is connected to the initial signal terminal STV
  • the N+2 stage shift register The signal input terminal of the bit register GOA(N+2) is connected to the second output terminal OUT2 of the Nth stage shift register.
  • the first reset terminal RST1 of the Nth stage shift register is connected to the first reset terminal RST1 of the N+3 stage shift register.
  • the two output terminals OUT2 are connected, N ⁇ 1, and N is an integer.
  • the signal input terminal INPUT of the third stage shift register GOA(3) is connected to the second output terminal OUT2 of the first stage shift register GOA(1), and the signal input terminal INPUT of the fourth stage shift register GOA(4) is connected to The second output terminal OUT2 of the second stage shift register GOA(2) is connected, and so on, the first reset terminal RST1 of the first stage shift register GOA(1) and the fourth stage shift register GOA(4)
  • the second output terminal OUT2 is connected, the first reset terminal RST1 of the second stage shift register GOA(2) is connected to the second output terminal OUT2 of the fifth stage shift register GOA(5), and so on.
  • the second reset terminals RST2 of all shift registers may be connected to the same signal line.
  • the first clock signal terminal CLKA of all shift registers can be connected to the same signal line CKA.
  • the random detection signal terminals OE of all shift registers can be connected to the same signal line.
  • the gate driving circuit provided by the embodiment of the present disclosure may further include: a first clock terminal CK1, a second clock terminal CK2, a third clock terminal CK3, a fourth clock terminal CK4, a fifth clock terminal CK5, The sixth clock terminal CK6, the seventh clock terminal CK7 and the eighth clock terminal CK8.
  • the second clock signal terminal CLKB of the 4i+1 stage shift register GOA (4i+1) is connected to the first clock terminal CK1, and the third clock signal terminal CLKC of the 4i+1 stage shift register GOA (4i+1) Connected to the fifth clock terminal CK5, the second clock signal terminal CLKB of the 4i+2 stage shift register GOA(4i+2) is connected to the second clock terminal CK2, the 4i+2 stage shift register GOA(4i+2) )
  • the third clock signal terminal CLKC is connected to the sixth clock terminal CK6, the second clock signal terminal CLKB of the 4i+3 stage shift register GOA (4i+3) is connected to the third clock terminal CK3, the 4i+3 stage
  • the third clock signal terminal CLKC of the shift register GOA (4i+3) is connected to the seventh clock terminal CK7, and the second clock signal terminal CLKB and the fourth clock terminal of the 4i+4th stage shift register GOA (4i+4) CK4 is connected, and the third clock signal terminal CLKC of the 4i+4th stage shift register
  • the shift register is the shift register provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and will not be repeated here.
  • FIG. 14 is a working timing diagram of a gate driving circuit provided by an exemplary embodiment.
  • FIG. 14 is an example of detecting the pixel circuit of the fourth row, and OUT1(i) represents the first output terminal of the i-th stage shift register.
  • the clock signals of the first clock terminal CK1 and the fifth clock terminal CK5 are the same, the clock signals of the second clock terminal CK2 and the sixth clock terminal CK6 are the same, and the third clock terminal CK3 and the seventh clock terminal CK3
  • the clock signals of the clock terminal CK7 are the same, the clock signals of the fourth clock terminal CK4 and the eighth clock terminal CK8 are the same, the clock signals of the first clock terminal CK1 and the third clock terminal CK3 are mutually opposite signals, and the second clock terminal CK2 and The clock signals of the fourth clock terminal CK4 are mutually opposite signals.
  • the clock signal of the clock terminal connected to the shift register connected to the pixel circuit to be detected is high, and the clock signal of the clock terminal connected to the remaining shift registers is low. Only the first output terminal of the shift register connected to the pixel circuit to be detected outputs multiple pulses, and the remaining shift registers only output a single pulse.
  • the embodiment of the present disclosure also provides a driving method of the shift register, which is applied to the shift register, the shift register is arranged in the display panel, and the display panel includes: a display stage and a detection stage.
  • the driving method of the shift register provided by the embodiment of the present disclosure includes the following steps:
  • Step 100 In the display phase, under the control of the signal input terminal, the input sub-circuit provides the signal of the first power terminal to the pull-up node; under the control of the pull-up node, the output sub-circuit provides the signal of the third clock signal terminal to the first output terminal , Provide the signal of the second clock signal terminal to the second output terminal; under the control of the first power terminal and the pull-up node, and under the control of the first reset terminal, the first reset sub-circuit provides the signal of the second power terminal to the pull-up node; Under the control of the first power terminal and the pull-up node, the pull-down sub-circuit provides the signal of the second power terminal to the pull-up node and the second output terminal, and provides the signal of the third power terminal to the first output terminal.
  • Step 200 In the detection phase, under the control of the signal input terminal, the random detection signal terminal, the first clock signal terminal and the first reset terminal, the detection control sub-circuit provides the signal of the first clock signal terminal to the pull-up node, and the pull-up node Under control, the output sub-circuit provides the signal of the third clock signal terminal to the first output terminal.
  • the shift register is the shift register provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and will not be repeated here.
  • the driving method of the shift register provided by the exemplary embodiment may further include: under the control of the second reset terminal, the second reset sub-circuit pulls up the node and detects the node. Provide the signal of the second power terminal.

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  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器及其驱动方法、栅极驱动电路，该移位寄存器包括：输入子电路、检测控制子电路、输出子电路、第一复位子电路和下拉子电路；其中，检测控制子电路，分别与随机检测信号端（OE）、信号输入端（INPUT）、第一时钟信号端（CLKA）、第一复位端（RST1）和上拉节点（PU）连接，设置为在信号输入端（INPUT）、随机检测信号端（OE）、第一时钟信号端（CLKA）和第一复位端（RST1）的控制下，向上拉节点（PU）提供第一时钟信号端（CLKA）的信号。

Description

一种移位寄存器及其驱动方法、栅极驱动电路
本申请要求于2019年8月21日提交中国专利局、申请号为201910774312.0、发明名称为“一种移位寄存器及其驱动方法、栅极驱动电路”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，特别涉及一种移位寄存器及其驱动方法、栅极驱动电路。
背景技术
显示面板包括：栅极驱动电路和阵列设置的像素电路。栅极驱动电路包括：多个移位寄存器。不同移位寄存器与不同行像素电路连接，且设置为在显示阶段向所连接的像素电路提供扫描信号。像素电路中包括驱动晶体管，由于驱动晶体管的制造工艺的局限性，不同的驱动晶体管的参数存在差异，使得不同的像素电路输出的驱动电流不同。为了保证显示面板的显示效果，在非显示阶段对像素电路进行检测，可以获得驱动晶体管的参数以对像素电路进行外部补偿。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种移位寄存器，包括：输入子电路、检测控制子电路、输出子电路、第一复位子电路和下拉子电路；
所述输入子电路，分别与信号输入端、第一电源端和上拉节点连接，设置为在信号输入端的控制下，向上拉节点提供第一电源端的信号；
所述检测控制子电路，分别与随机检测信号端、信号输入端、第一时钟信号端、第一复位端和上拉节点连接，设置为在信号输入端、随机检测信号端、第一时钟信号端和第一复位端的控制下，向上拉节点提供第一时钟信号 端的信号；
所述第一复位子电路，分别与第一复位端、上拉节点和第二电源端连接，设置为在第一复位端的控制下，向上拉节点提供第二电源端的信号；
所述输出子电路，分别与第二时钟信号端、第三时钟信号端、上拉节点、第一输出端和第二输出端连接，设置为在上拉节点的控制下，向第一输出端提供第三时钟信号端的信号，向第二输出端提供第二时钟信号端的信号；
所述下拉子电路，分别与第一电源端、第二电源端、第三电源端、上拉节点、第一输出端和第二输出端连接，设置为在第一电源端和上拉节点的控制下，向上拉节点和第二输出端提供第二电源端的信号，向第一输出端提供第三电源端的信号。
在一些可能的实现方式中，所述检测控制子电路包括：检测节点控制子电路和检测输出子电路；
所述检测节点控制子电路，分别与信号输入端、检测节点、随机检测信号、上拉节点和第一复位端连接，设置为在信号输入端、随机检测信号端和第一复位端的控制下，向检测节点提供信号输入端或上拉节点的信号；
所述检测输出子电路，分别与检测节点、第一时钟信号端和上拉节点连接，设置为在第一时钟信号端和检测节点的控制下，向上拉节点提供第一时钟信号端的信号。
在一些可能的实现方式中，还包括：第二复位子电路；
所述第二复位子电路，分别与第二复位端、上拉节点、检测节点和第二电源端连接，设置为在第二复位端的控制下，向上拉节点和检测节点提供第二电源端的信号。
在一些可能的实现方式中，所述检测节点控制子电路包括：第一晶体管、第二晶体管和第三晶体管；
第一晶体管的控制极和第一极与信号输入端连接，第一晶体管的第二极与检测节点连接；
第二晶体管的控制极与随机检测信号端连接，第二晶体管的第一极与检测节点连接，第二晶体管的第二极与第三晶体管的第一极连接；
第三晶体管的控制极与第一复位端连接，第三晶体管的第二极与上拉节点连接。
在一些可能的实现方式中，所述检测输出子电路包括：第四晶体管、第五晶体管和第一电容；
第四晶体管的控制极与检测节点连接，第四晶体管的第一极与第一时钟信号端连接，第四晶体管的第二极与第五晶体管的第一极连接；
第五晶体管的控制极与第一时钟信号端连接，第五晶体管的第二极与上拉节点连接；
第一电容的第一端与检测节点连接，第一电容的第二端与第四晶体管的第二极连接。
在一些可能的实现方式中，所述输入子电路包括：第六晶体管；
第六晶体管的控制极与信号输入端连接，第六晶体管的第一极与第一电源端连接，第六晶体管的第二极与上拉节点连接。
在一些可能的实现方式中，所述输出子电路包括：第七晶体管、第八晶体管和第二电容；
第七晶体管的控制极与上拉节点连接，第七晶体管的第一极与第二时钟信号端连接，第七晶体管的第二极与第二输出端连接；
第八晶体管的控制极与上拉节点连接，第八晶体管的第一极与第三时钟信号端连接，第八晶体管的第二极与第一输出端连接；
第二电容的第一端与上拉节点连接，第二电容的第二端与第一输出端连接。
在一些可能的实现方式中，所述下拉子电路包括：第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
第九晶体管的控制极和第一极与第一电源端连接，第九晶体管的第二极与下拉节点连接；
第十晶体管的控制极与上拉节点连接，第十晶体管的第一极与下拉节点连接，第十晶体管的第二极与第二电源端连接；
第十一晶体管的控制极与下拉节点连接，第十一晶体管的第一极与上拉节点连接，第十一晶体管的第二极与第二电源端连接；
第十二晶体管的控制极与下拉节点连接，第十二晶体管的第一极与第二输出端连接，第十二晶体管的第二极与第二电源端连接；
第十三晶体管的控制极与下拉节点连接，第十三晶体管的第一极与第一输出端连接，第十三晶体管的第二极与第三电源端连接。
在一些可能的实现方式中，所述第一复位子电路包括：第十四晶体管；
第十四晶体管的控制极与第一复位端连接，第十四晶体管的第一极与上拉节点连接，第十四晶体管的第二极与第二电源端连接。
在一些可能的实现方式中，所述第二复位子电路包括：第十五晶体管和第十六晶体管；
第十五晶体管的控制极与第二复位端连接，第十五晶体管的第一极与检测节点连接，第十五晶体管的第二极与上拉节点连接；
第十六晶体管的控制极与第二复位端连接，第十六晶体管的第一极与上拉节点连接，第十六晶体管的第二极与第二电源端连接。
在一些可能的实现方式中，还包括：第二复位子电路；
其中，所述检测控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第一电容；所述输入子电路包括：第六晶体管；所述输出子电路包括：第七晶体管、第八晶体管和第二电容；所述下拉子电路包括：第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；所述第一复位子电路包括：第十四晶体管；所述第二复位子电路包括：第十五晶体管和第十六晶体管；
第一晶体管的控制极和第一极与信号输入端连接，第一晶体管的第二极与检测节点连接；
第二晶体管的控制极与随机检测信号端连接，第二晶体管的第一极与检测节点连接，第二晶体管的第二极与第三晶体管的第一极连接；
第三晶体管的控制极与第一复位端连接，第三晶体管的第二极与上拉节点连接；
第四晶体管的控制极与检测节点连接，第四晶体管的第一极与第一时钟信号端连接，第四晶体管的第二极与第五晶体管的第一极连接；
第五晶体管的控制极与第一时钟信号端连接，第五晶体管的第二极与上拉节点连接；
第一电容的第一端与检测节点连接，第一电容的第二端与第四晶体管的第二极连接；
第六晶体管的控制极与信号输入端连接，第六晶体管的第一极与第一电源端连接，第六晶体管的第二极与上拉节点连接；
第七晶体管的控制极与上拉节点连接，第七晶体管的第一极与第二时钟信号端连接，第七晶体管的第二极与第二输出端连接；
第八晶体管的控制极与上拉节点连接，第八晶体管的第一极与第三时钟信号端连接，第八晶体管的第二极与第一输出端连接；
第二电容的第一端与上拉节点连接，第二电容的第二端与第一输出端连接；
第九晶体管的控制极和第一极与第一电源端连接，第九晶体管的第二极与下拉节点连接；
第十晶体管的控制极与上拉节点连接，第十晶体管的第一极与下拉节点连接，第十晶体管的第二极与第二电源端连接；
第十一晶体管的控制极与下拉节点连接，第十一晶体管的第一极与上拉节点连接，第十一晶体管的第二极与第二电源端连接；
第十二晶体管的控制极与下拉节点连接，第十二晶体管的第一极与第二输出端连接，第十二晶体管的第二极与第二电源端连接；
第十三晶体管的控制极与下拉节点连接，第十三晶体管的第一极与第一输出端连接，第十三晶体管的第二极与第三电源端连接；
第十四晶体管的控制极与第一复位端连接，第十四晶体管的第一极与上拉节点连接，第十四晶体管的第二极与第二电源端连接；
第十五晶体管的控制极与第二复位端连接，第十五晶体管的第一极与检 测节点连接，第十五晶体管的第二极与上拉节点连接；
第十六晶体管的控制极与第二复位端连接，第十六晶体管的第一极与上拉节点连接，第十六晶体管的第二极与第二电源端连接。
第二方面，本公开还提供了一种栅极驱动电路，包括：多个上述移位寄存器；
第一级移位寄存器的信号输入端与初始信号端连接，第二级移位寄存器的信号输入端与初始信号端连接，第N+2级移位寄存器的信号输入端与第N级移位寄存器的第二输出端连接，第N级移位寄存器的第一复位端与第N+3级移位寄存器的第二输出端连接，N≥1。
在一些可能的实现方式中，所述栅极驱动电路包括：第一时钟端、第二时钟端、第三时钟端、第四时钟端、第五时钟端、第六时钟端、第七时钟端和第八时钟端；
第4i+1级移位寄存器的第二时钟信号端与第一时钟端连接，第4i+1级移位寄存器的第三时钟信号端与第五时钟端连接，第4i+2级移位寄存器的第二时钟信号端与第二时钟端连接，第4i+2级移位寄存器的第三时钟信号端与第六时钟端连接，第4i+3级移位寄存器的第二时钟信号端与第三时钟端连接，第4i+3级移位寄存器的第三时钟信号端与第七时钟端连接，第4i+4级移位寄存器的第二时钟信号端与第四时钟端连接，第4i+4级移位寄存器的第三时钟信号端与第八时钟端连接。
第三方面，本公开还提供了一种移位寄存器的驱动方法，应用于上述移位寄存器中，所述移位寄存器设置在显示面板中，所述显示面板包括：显示阶段和检测阶段，所述方法包括：
在显示阶段，在信号输入端的控制下，输入子电路向上拉节点提供第一电源端的信号；在上拉节点的控制下，输出子电路向第一输出端提供第三时钟信号端的信号，向第二输出端提供第二时钟信号端的信号；在第一电源端和上拉节点的控制下，在第一复位端的控制下，第一复位子电路向上拉节点提供第二电源端的信号；在第一电源端和上拉节点的控制下，下拉子电路向上拉节点和第二输出端提供第二电源端的信号，向第一输出端提供第三电源端的信号；
在检测阶段，在信号输入端、随机检测信号端、第一时钟信号端和第一复位端的控制下，检测控制子电路向上拉节点提供第一时钟信号端的信号，在上拉节点的控制下，输出子电路向第一输出端提供第三时钟信号端的信号。
在一些可能的实现方式中，在检测阶段，所述方法还包括：在第二复位端的控制下，第二复位子电路向上拉节点和检测节点提供第二电源端的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的移位寄存器的结构示意图；
图2为一种示例性实施例提供的移位寄存器的结构示意图；
图3为另一示例性实施例提供的移位寄存器的结构示意图；
图4为一种示例性实施例提供的检测节点控制子电路的等效电路图；
图5为一种示例性实施例提供的检测输出子电路的等效电路图；
图6为一种示例性实施例提供的输入子电路的等效电路图；
图7为一种示例性实施例提供的输出子电路的等效电路图；
图8为一种示例性实施例提供的下拉子电路的等效电路图；
图9为一种示例性实施例提供的第一复位子电路的等效电路图；
图10为一种示例性实施例提供的第二复位子电路的等效电路图；
图11为一种示例性实施例提供的移位寄存器的等效电路图；
图12A为一种示例性实施例提供的移位寄存器的工作时序图一；
图12B为一种示例性实施例提供的移位寄存器的工作时序图二；
图12C为一种示例性实施例提供的移位寄存器的工作时序图三；
图13为本公开实施例提供的栅极驱动电路的结构示意图；
图14为一种示例性实施例提供的栅极驱动电路的工作时序图。
详述
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详述中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。薄膜晶体管可以是氧化物半导体晶体管。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将晶体管的栅极成为控制极。为区分晶体管除栅极之外的两极，将 其中一极称为第一极，另一极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。
通常，移位寄存器的输出比较单一，无法实现多次脉冲输出，使得移位寄存器无法在非显示阶段输出扫描信号，导致无法对像素电路进行检测，影响了显示效果。
图1为本公开实施例提供的移位寄存器的结构示意图。如图1所示，本公开实施例提供的移位寄存器包括：输入子电路、检测控制子电路、输出子电路、第一复位子电路和下拉子电路。
输入子电路，分别与信号输入端INPUT、第一电源端VDD和上拉节点PU连接，设置为在信号输入端INPUT的控制下，向上拉节点PU提供第一电源端VDD的信号；检测控制子电路，分别与随机检测信号端OE、信号输入端INPUT、第一时钟信号端CLKA、第一复位端RST1和上拉节点PU连接，设置为在信号输入端INPUT、随机检测信号端OE、第一时钟信号端CLKA和第一复位端RST1的控制下，向上拉节点PU提供第一时钟信号端CLKA的信号；第一复位子电路，分别与第一复位端RST1、上拉节点PU和第二电源端VGL1连接，设置为在第一复位端RST1的控制下，向上拉节点PU提供第二电源端VGL1的信号；输出子电路，分别与第二时钟信号端CLKB、第三时钟信号端CLKC、上拉节点PU、第一输出端OUT1和第二输出端OUT2连接，设置为在上拉节点PU的控制下，向第一输出端OUT1提供第三时钟信号端CLKC的信号，向第二输出端OUT2提供第二时钟信号端CLKB的信号；下拉子电路，分别与第一电源端VDD、第二电源端VGL1、第三电源端VGL2、上拉节点PU、第一输出端OUT1和第二输出端OUT2连接，设置为在第一电源端VDD和上拉节点PU的控制下，向上拉节点PU和第二输出端OUT2提供第二电源端VGL1的信号，向第一输出端OUT1提供第三电源端VGL2的信号。
在一种示例性实施例中，第一电源端VDD持续提供高电平信号。
在一种示例性实施例中，第二电源端VGL1和第三电源端VGL2持续提供低电平信号。第二电源端VGL1和第三电源端VGL2的信号电位可以相同，或者可以不同。当第二电源端VGL1和第三电源端VGL2的电位不同时，第 三电源端VGL2的信号的电位高于第二电源端VGL1的信号电位。
在一种示例性实施例中，第一输出端可以设置为输出本级驱动信号，第二输出端可以设置为输出级联信号。
在一种示例性实施例中，移位寄存器设置于显示面板中。显示面板包括：显示阶段和检测阶段，其中，检测阶段为非显示阶段的一段时间。本实施例提供的检测控制子电路可以在显示阶段并不影响上拉节点的电位，由输入子电路中的信号输入端INPUT向上拉节点PU提供信号，在检测阶段向上拉节点PU提供第一时钟信号端CLKA的信号，可以使得移位寄存器在检测阶段输出扫描信号。
在一种示例性实施例中，在显示阶段，第二时钟信号端CLKB和第三时钟信号端CLKC的时钟信号相同。
在一种示例性实施例中，第一时钟信号端CLKA，第二时钟信号端CLKB，第三时钟信号端CLKC的信号的脉宽关系可以调节。
在一种示例性实施例中，随机检测信号端OE的信号是随机信号，由外部电路例如现场可编程门阵产生。随机检测信号端OE的信号不同，待检测的像素电路也不相同，即可以实现多次脉冲输出的移位寄存器也不相同。
本公开实施例提供的移位寄存器包括：输入子电路、检测控制子电路、输出子电路、第一复位子电路和下拉子电路；输入子电路，分别与信号输入端、第一电源端和上拉节点连接，设置为在信号输入端的控制下，向上拉节点提供第一电源端的信号；检测控制子电路，分别与随机检测信号端、信号输入端、第一时钟信号端、第一复位端和上拉节点连接，设置为在信号输入端、随机检测信号端、第一时钟信号端和第一复位端的控制下，向上拉节点提供第一时钟信号端的信号；第一复位子电路，分别与第一复位端、上拉节点和第二电源端连接，设置为在第一复位端的控制下，向上拉节点提供第二电源端的信号；输出子电路，分别与第二时钟信号端、第三时钟信号端、上拉节点、第一输出端和第二输出端连接，设置为在上拉节点的控制下，向第一输出端提供第三时钟信号端的信号，向第二输出端提供第二时钟信号端的信号；下拉子电路，分别与第一电源端、第二电源端、第三电源端、上拉节点、第一输出端和第二输出端连接，设置为在第一电源端和上拉节点的控制 下，向上拉节点和第二输出端提供第二电源端的信号，向第一输出端提供第三电源端的信号。本公开实施例提供的技术方案通过设置检测控制子电路使移位寄存器实现可多次脉冲输出，可以对像素电路进行检测，提升了显示效果。
图2为一种示例性实施例提供的移位寄存器的结构示意图。如图2所示，一种示例性实施例提供的移位寄存器中检测控制子电路包括：检测节点控制子电路和检测输出子电路。
检测节点控制子电路，分别与信号输入端INPUT、检测节点PS、随机检测信号端OE、上拉节点PU和第一复位端RST1连接，设置为在信号输入端INPUT、随机检测信号端OE和第一复位端RST1的控制下，向检测节点PS提供信号输入端INPUT或上拉节点PU的信号。检测输出子电路，分别与检测节点PS、第一时钟信号端CLKA和上拉节点PU连接，设置为在第一时钟信号端CLKA和检测节点PS的控制下，向上拉节点PU提供第一时钟信号端CLKA的信号。
图3为另一示例性实施例提供的移位寄存器的结构示意图。如图3所示，一种示例性实施例提供的移位寄存器还包括：第二复位子电路。
第二复位子电路，分别与第二复位端RST2、上拉节点PU、检测节点PS和第二电源端VGL1连接，设置为在第二复位端RST2的控制下，向上拉节点PU和检测节点PS提供第二电源端VGL1的信号。
图4为一种示例性实施例提供的检测节点控制子电路的等效电路图。如图4所示，一种示例性实施例提供的检测节点控制子电路包括：第一晶体管M1、第二晶体管M2和第三晶体管M3。
第一晶体管M1的控制极和第一极与信号输入端INPUT连接，第一晶体管M1的第二极与检测节点PS连接。第二晶体管M2的控制极与随机检测信号端OE连接，第二晶体管M2的第一极与检测节点PS连接，第二晶体管M2的第二极与第三晶体管M3的第一极连接。第三晶体管M3的控制极与第一复位端RST1连接，第三晶体管M3的第二极与上拉节点PU连接。
图4中示出了检测节点控制子电路的示例性结构。检测节点控制子电路的实现方式不限于此。
图5为一种示例性实施例提供的检测输出子电路的等效电路图。如图5所示，一种示例性实施例提供的检测输出子电路包括：第四晶体管M4、第五晶体管M5和第一电容C1。
第四晶体管M4的控制极与检测节点PS连接，第四晶体管M4的第一极与第一时钟信号端CLKA连接，第四晶体管M4的第二极与第五晶体管M5的第一极连接。第五晶体管M5的控制极与第一时钟信号端CLKA连接，第五晶体管M5的第二极与上拉节点PU连接。第一电容C1的第一端与检测节点PS连接，第一电容C1的第二端与第四晶体管M4的第二极连接。
图5中示出了检测输出子电路的示例性结构。检测输出子电路的实现方式不限于此。
图6为一种示例性实施例提供的输入子电路的等效电路图。如图6所示，一种示例性实施例提供的输入子电路包括：第六晶体管M6。
第六晶体管M6的控制极与信号输入端INPUT连接，第六晶体管M6的第一极与第一电源端VDD连接，第六晶体管M6的第二极与上拉节点PU连接。
图6中示出了输入子电路的示例性结构。输入子电路的实现方式不限于此。
图7为一种示例性实施例提供的输出子电路的等效电路图。如图7所示，一种示例性实施例提供的输出子电路包括：第七晶体管M7、第八晶体管M8和第二电容C2。
第七晶体管M7的控制极与上拉节点PU连接，第七晶体管M7的第一极与第二时钟信号端CLKB连接，第七晶体管M7的第二极与第二输出端OUT2连接。第八晶体管M8的控制极与上拉节点PU连接，第八晶体管M8的第一极与第三时钟信号端CLKC连接，第八晶体管M8的第二极与第一输出端OUT1连接。第二电容C2的第一端与上拉节点PU连接，第二电容C2的第二端与第一输出端OUT1连接。
图7中示出了输出子电路的示例性结构。输出子电路的实现方式不限于此。
图8为一种示例性实施例提供的下拉子电路的等效电路图。如图8所示，一种示例性实施例提供的下拉子电路包括：第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13。
第九晶体管M9的控制极和第一极与第一电源端VDD连接，第九晶体管M9的第二极与下拉节点PD连接。第十晶体管M10的控制极与上拉节点PU连接，第十晶体管M10的第一极与下拉节点PD连接，第十晶体管M10的第二极与第二电源端VGL1连接。第十一晶体管M11的控制极与下拉节点PD连接，第十一晶体管M11的第一极与上拉节点PU连接，第十一晶体管M11的第二极与第二电源端VGL1连接。第十二晶体管M12的控制极与下拉节点PD连接，第十二晶体管M12的第一极与第二输出端OUT2连接，第十二晶体管M12的第二极与第二电源端VGL1连接。第十三晶体管M13的控制极与下拉节点PD连接，第十三晶体管M13的第一极与第一输出端OUT1连接，第十三晶体管M13的第二极与第三电源端VGL2连接。
图8中示出了下拉子电路的示例性结构。下拉子电路的实现方式不限于此。
图9为一种示例性实施例提供的第一复位子电路的等效电路图。如图9所示，一种示例性实施例提供的第一复位子电路包括：第十四晶体管M14。
第十四晶体管M14的控制极与第一复位端RST1连接，第十四晶体管M14的第一极与上拉节点PU连接，第十四晶体管M14的第二极与第二电源端VGL1连接。
图9中示出了第一复位子电路的示例性结构。第一复位子电路的实现方式不限于此。
图10为一种示例性实施例提供的第二复位子电路的等效电路图。如图10所示，一种示例性实施例提供的第二复位子电路包括：第十五晶体管M15和第十六晶体管M16。
第十五晶体管M15的控制极与第二复位端RST2连接，第十五晶体管M15的第一极与检测节点PS连接，第十五晶体管M15的第二极与上拉节点PU连接。第十六晶体管M16的控制极与第二复位端RST2连接，第十六晶体管M16的第一极与上拉节点PU连接，第十六晶体管M16的第二极与第 二电源端VGL1连接。
图10中示出了第二复位子电路的示例性结构。第二复位子电路的实现方式不限于此。
图11为一种示例性实施例提供的移位寄存器的等效电路图。如图11所示，一种示例性实施例提供的移位寄存器还可以包括：第二复位子电路。其中，检测控制子电路包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5和第一电容C1；输入子电路包括：第六晶体管M6；输出子电路包括：第七晶体管M7、第八晶体管M8和第二电容C2；下拉子电路包括：第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13；第一复位子电路包括：第十四晶体管M14；第二复位子电路包括：第十五晶体管M15和第十六晶体管M16。
第一晶体管M1的控制极和第一极与信号输入端INPUT连接，第一晶体管M1的第二极与检测节点PS连接。第二晶体管M2的控制极与随机检测信号端OE连接，第二晶体管M2的第一极与检测节点PS连接，第二晶体管M2的第二极与第三晶体管M3的第一极连接。第三晶体管M3的控制极与第一复位端RST1连接，第三晶体管M3的第二极与上拉节点PU连接。第四晶体管M4的控制极与检测节点PS连接，第四晶体管M4的第一极与第一时钟信号端CLKA连接，第四晶体管M4的第二极与第五晶体管M5的第一极连接。第五晶体管M5的控制极与第一时钟信号端CLKA连接，第五晶体管M5的第二极与上拉节点PU连接。第一电容C1的第一端与检测节点PS连接，第一电容C1的第二端与第四晶体管M4的第二极连接。第六晶体管M6的控制极与信号输入端INPUT连接，第六晶体管M6的第一极与第一电源端VDD连接，第六晶体管M6的第二极与上拉节点PU连接。第七晶体管M7的控制极与上拉节点PU连接，第七晶体管M7的第一极与第二时钟信号端CLKB连接，第七晶体管M7的第二极与第二输出端OUT2连接。第八晶体管M8的控制极与上拉节点PU连接，第八晶体管M8的第一极与第三时钟信号端CLKC连接，第八晶体管M8的第二极与第一输出端OUT1连接。第二电容C2的第一端与上拉节点PU连接，第二电容C2的第二端与第一输出 端OUT1连接。第九晶体管M9的控制极和第一极与第一电源端VDD连接，第九晶体管M9的第二极与下拉节点PD连接。第十晶体管M10的控制极与上拉节点PU连接，第十晶体管M10的第一极与下拉节点PD连接，第十晶体管M10的第二极与第二电源端VGL1连接。第十一晶体管M11的控制极与下拉节点PD连接，第十一晶体管M11的第一极与上拉节点PU连接，第十一晶体管M11的第二极与第二电源端VGL1连接。第十二晶体管M12的控制极与下拉节点PD连接，第十二晶体管M12的第一极与第二输出端OUT2连接，第十二晶体管M12的第二极与第二电源端VGL1连接。第十三晶体管M13的控制极与下拉节点PD连接，第十三晶体管M13的第一极与第一输出端OUT1连接，第十三晶体管M13的第二极与第三电源端VGL2连接。第十四晶体管M14的控制极与第一复位端RST1连接，第十四晶体管M14的第一极与上拉节点PU连接，第十四晶体管M14的第二极与第二电源端VGL1连接。第十五晶体管M15的控制极与第二复位端RST2连接，第十五晶体管M15的第一极与检测节点PS连接，第十五晶体管M15的第二极与上拉节点PU连接。第十六晶体管M16的控制极与第二复位端RST2连接，第十六晶体管M16的第一极与上拉节点PU连接，第十六晶体管M16的第二极与第二电源端VGL1连接。
一种示例性实施例中，晶体管M1至M16可以为N型薄膜晶体管，或者可以为P型薄膜晶体管。当晶体管M1至M16的晶体管类型相同时，可以统一工艺流程，减少工艺制程，有助于提高产品的良率。
一种示例性实施例中，所有晶体管可以为低温多晶硅薄膜晶体管。所有晶体管为低温多晶硅薄膜晶体管可以减少移位寄存器中的漏电流。
一种示例性实施例中，薄膜晶体管可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管。
一种示例性实施例中，第一电容C1和第二电容C2可以为晶体管的寄生电容，或者可以为外接电容。
下面通过移位寄存器的工作过程说明一种示例性实施例提供的移位寄存器。
以一种示例性实施例提供的移位寄存器中的晶体管M1至M16均为N 型薄膜晶体管为例，图12A为一种示例性实施例提供的移位寄存器的工作时序图一，图12B为一种示例性实施例提供的移位寄存器的工作时序图二，图12C为一种示例性实施例提供的移位寄存器的工作时序图三。如图11和图12所示，一种示例性实施例提供的移位寄存器包括16个晶体管单元(M1至M16)、2个电容(C1和C2)、7个信号输入端(INPUT、RST1、RST2、OE、CLKA、CLKB和CLKC)、2个信号输出端(OUT1和OUT2)和3个电源端(VDD、VGL1和VGL2)。
第一电源端VDD持续提供高电平信号。第二电源端VGL1和第二电源端VGL2持续提供低电平信号。
显示面板包括：显示阶段Display和检测阶段Sense。在显示阶段Display，第二复位端RST2和第一时钟信号端CLKA的输入信号始终为低电平。在检测阶段Sense，第一复位端RST1、信号输入端INPUT、随机检测信号端OE和第二时钟信号端CLKB的输入信号始终为低电平。
在显示阶段Display之前，第二复位端RST2的输入信号为高电平，可以使得移位寄存器中的第十五晶体管M15和第十六晶体管M16导通，以将上拉节点PU和检测节点PS的电位初始化。
在显示阶段，一种示例性实施例提供的移位寄存器的工作过程包括：
第一阶段D1，即输入阶段，信号输入端INPUT和随机检测信号端OE的输入信号为高电平，第一晶体管M1和第二晶体管M2导通，将检测节点PS的电位拉高，对第一电容C1进行充电，第四晶体管M4导通，但是由于第一时钟信号端CLKA的时钟信号为低电平，上拉节点PU的电位不会被第一时钟信号端CLKA的时钟信号影响。第六晶体管M6导通，将上拉节点PU的电位拉高，对第二电容C2进行充电，第七晶体管M7和第八晶体管M8导通，但是由于第二时钟信号端CLKB和第三时钟信号端CLKC的时钟信号为低电平，因此，第一输出端OUT1和第二输出端OUT2没有输出。虽然第九晶体管M9在第一电源端VDD的控制下导通，但是由于第十晶体管M10在上拉节点PU的控制下导通，将下拉节点PD的电位拉低，使得第十一晶体管M11、第十二晶体管M12和第十三晶体管M13截止，第一复位端RST1的输入信号为低电平，第三晶体管M3和第十四晶体管M14截止，因此，上 拉节点PU保持高电平。
第二阶段D2，即输出阶段，随机检测信号端OE的输入信号持续为高电平，第二晶体管M2导通，信号输入端INPUT的输入信号为低电平，第一晶体管M1和第六晶体管M6截止，在第一电容C1自举的作用下，检测节点PS的电位被拉高，第四晶体管M4导通。但是由于第一时钟信号端CLKA的时钟信号为低电平，上拉节点PU的电位不会被第一时钟信号端CLKA的时钟信号影响，在第二电容C2自举的作用下，上拉节点PU的电位被拉高，第七晶体管M7和第八晶体管M8导通。第二时钟信号端CLKB和第三时钟信号端CLKC的时钟信号为高电平，第一输出端OUT1和第二输出端OUT2输出高电平信号。虽然第九晶体管M9在第一电源端VDD的控制下导通，但是由于第十晶体管M10在上拉节点PU的控制下导通，将下拉节点PD的电位拉低，使得第十一晶体管M11、第十二晶体管M12和第十三晶体管M13截止，第一复位端RST1的输入信号为低电平，第三晶体管M3和第十四晶体管M14截止，因此，上拉节点PU保持高电平。
第三阶段D3、随机检测信号端OE的输入信号仍为高电平，第二晶体管M2导通，信号输入端INPUT的输入信号仍为低电平，第一晶体管M1和第六晶体管M6截止，检测节点PS的电位开始下降，但是仍能导通第四晶体管M4。由于第一时钟信号端CLKA的时钟信号为低电平，上拉节点PU的电位不会被第一时钟信号端CLKA的时钟信号影响。上拉节点PU的电位开始下降，但是仍可以导通第七晶体管M7和第八晶体管M8。由于第二时钟信号端CLKB和第三时钟信号端CLKC的时钟信号为低电平，因此，第一输出端OUT1和第二输出端OUT2没有输出。虽然第九晶体管M9在第一电源端VDD的控制下导通，但是由于第十晶体管M10在上拉节点PU的控制下仍能导通，将下拉节点PD的电位拉低，使得第十一晶体管M11、第十二晶体管M12和第十三晶体管M13仍截止，第一复位端RST1的输入信号为低电平，第三晶体管M3和第十四晶体管M14仍截止。
第四阶段D4、即复位阶段，随机检测信号端OE的输入信号仍为高电平，第二晶体管M2导通，第一复位端RST1的输入信号为高电平，第三晶体管M3和第十四晶体管M14导通，将上拉节点PU和检测节点PS的电位拉低， 第九晶体管M9在第一电源端VDD的控制下导通，将下拉节点PD的电位拉高，第十晶体管M10在上拉节点PU的控制下截止，第十一晶体管M11、第十二晶体管M12和第十三晶体管M13导通，将上拉节点PU、第一输出端OUT1和第二输出端OUT2的信号拉低，以降低噪声。
在显示阶段，信号输入端INPUT的输入信号为脉冲信号，仅在输入阶段为高电平。第一输出端OUT1和第二输出端OUT2的输出信号为脉冲信号，仅在输出阶段为高电平。第一复位端RST1的信号为脉冲信号，只在复位阶段为高电平。
随机检测信号端OE输出的随机信号与某一级移位寄存器在显示阶段的输出信号为反相信号。以随机信号与第N级移位寄存器的输出信号为反相信号为例来说，从第1级移位寄存器至第N级移位寄存器中除第N-3级移位寄存器之外的所有移位寄存器在复位阶段中随机检测信号端OE的随机信号始终为高电平，即在复位阶段，第二晶体管M2和第三晶体管M3导通，检测节点PS的电位被拉低，其他工作过程与前述工作过程相同。第N-3级移位寄存器的工作过程与上述工作过程不同之处在于复位阶段中随机检测信号端OE的输入信号为低电平，第二晶体管M2截止，第三晶体管M3导通，使得检测节点PS的电位没有被拉低，因此，第N-3级移位寄存器中的检测节点PS的电位始终为高。图12是以N＝7为例进行说明，其中，图12A是以第1级至第N-4级移位寄存器的工作过程为例进行说明的，图12B是以第N-2级和第N级移位寄存器的工作过程为例进行说明的，图12C是以第N-3级移位寄存器为例进行说明的。
待检测的像素电路取决于随机检测信号端OE的输入信号。若随机检测信号端OE的输入信号与第N级移位寄存器的输出信号为反相信号，则待检测的像素电路为第N-3级移位寄存器连接的像素电路。
在检测阶段，与待检测的像素电路连接的移位寄存器的工作过程包括：
第一阶段S1、检测节点PS的信号为高电平，第四晶体管M4导通，第一时钟信号端CLKA的时钟信号为高电平，第五晶体管M5导通，上拉节点PU的电位被第一时钟信号端CLKA的时钟信号拉高，第七晶体管M7和第八晶体管M8导通，但是由于第三时钟信号端CLKC的时钟信号为低电平， 因此，第一输出端OUT1没有输出。虽然第九晶体管M9在第一电源端VDD的控制下导通，但是由于第十晶体管M10在上拉节点PU的控制下导通，将下拉节点PD的电位拉低，使得第十一晶体管M11、第十二晶体管M12和第十三晶体管M13截止，上拉节点PU的电位保持高电平。
第二阶段S2、第一时钟信号端CLKA的时钟信号为低电平，第五晶体管M5截止，在第二电容C2自举的作用下，上拉节点PU的电位被拉高，第七晶体管M7和第八晶体管M8导通，第三时钟信号端CLKC的时钟信号为高电平，第一输出端OUT1输出高电平信号。虽然第九晶体管M9在第一电源端VDD的控制下导通，但是由于第十晶体管M10在上拉节点PU的控制下导通，将下拉节点PD的电位拉低，使得第十一晶体管M11、第十二晶体管M12和第十三晶体管M13截止，因此，上拉节点PU的电位保持高电平。
第三阶段S3、上拉节点PU的电位开始下降，但是仍可以导通第七晶体管M7和第八晶体管M8。由于第三时钟信号端CLKC的时钟信号为低电平，因此，第一输出端OUT1没有输出。虽然第九晶体管M9在第一电源端VDD的控制下导通，但是由于第十晶体管M10在上拉节点PU的控制下仍能导通，将下拉节点PD的电位拉低，使得第十一晶体管M11、第十二晶体管M12和第十三晶体管M13仍截止。
第四阶段S4、第二复位端RST2的输入信号为高电平，第十五晶体管M15和第十六晶体管M16导通，将上拉节点PU和检测节点PS的电位拉低。虽然第九晶体管M9在第一电源端VDD的控制下导通，将下拉节点PD的电位拉高，第十晶体管M10在上拉节点PU的控制下截止，第十一晶体管M11、第十二晶体管M12和第十三晶体管M13导通，可以拉低上拉节点PU、第一输出端OUT1和第二输出端OUT2，以降低噪声。
在一种示例性实施例中，如图12所示，除第N-3级移位寄存器之外的其他级移位寄存器在检测阶段均没有输出。
根据图12C可知，移位寄存器实现了多次脉冲输出，不仅可以在显示阶段输出驱动信号，还可以在检测阶段输出驱动信号。
本公开实施例还提供了一种栅极驱动电路。图13为本公开实施例提供的栅极驱动电路的结构示意图。如图13所示，本公开实施例提供的栅极驱动电 路包括：多个移位寄存器。第一级移位寄存器GOA(1)的信号输入端INPUT与初始信号端STV连接，第二级移位寄存器GOA(2)的信号输入端INPUT与初始信号端STV连接，第N+2级移位寄存器GOA(N+2)的信号输入端与第N级移位寄存器的第二输出端OUT2连接，第N级移位寄存器的第一复位端RST1与第N+3级移位寄存器的第二输出端OUT2连接，N≥1，且N为整数。
第三级移位寄存器GOA(3)的信号输入端INPUT与第一级移位寄存器GOA(1)的第二输出端OUT2连接，第四级移位寄存器GOA(4)的信号输入端INPUT与第二级移位寄存器GOA(2)的第二输出端OUT2连接，依次类推，第一级移位寄存器GOA(1)的第一复位端RST1与第四级移位寄存器GOA(4)的第二输出端OUT2连接，第二级移位寄存器GOA(2)的第一复位端RST1与第五级移位寄存器GOA(5)的第二输出端OUT2连接，依次类推。
在一种示例性实施例中，所有移位寄存器的第二复位端RST2可以连接同一信号线。所有移位寄存器的第一时钟信号端CLKA可以连接同一信号线CKA。所有移位寄存器的随机检测信号端OE可以连接同一信号线。
如图13所示，本公开实施例提供的栅极驱动电路还可以包括：第一时钟端CK1、第二时钟端CK2、第三时钟端CK3、第四时钟端CK4、第五时钟端CK5、第六时钟端CK6、第七时钟端CK7和第八时钟端CK8。
第4i+1级移位寄存器GOA(4i+1)的第二时钟信号端CLKB与第一时钟端CK1连接，第4i+1级移位寄存器GOA(4i+1)的第三时钟信号端CLKC与第五时钟端CK5连接，第4i+2级移位寄存器GOA(4i+2)的第二时钟信号端CLKB与第二时钟端CK2连接，第4i+2级移位寄存器GOA(4i+2)的第三时钟信号端CLKC与第六时钟端CK6连接，第4i+3级移位寄存器GOA(4i+3)的第二时钟信号端CLKB与第三时钟端CK3连接，第4i+3级移位寄存器GOA(4i+3)的第三时钟信号端CLKC与第七时钟端CK7连接，第4i+4级移位寄存器GOA(4i+4)的第二时钟信号端CLKB与第四时钟端CK4连接，第4i+4级移位寄存器GOA(4i+4)的第三时钟信号端CLKC与第八时钟端CK8连接。
移位寄存器为前述任一个实施例提供的移位寄存器，实现原理和实现效果类似，在此不再赘述。
图14为一种示例性实施例提供的栅极驱动电路的工作时序图。图14是以对第四行像素电路进行检测为例进行说明的，OUT1(i)表示第i级移位寄存器的第一输出端。
如图14所示，在显示阶段，第一时钟端CK1和第五时钟端CK5的时钟信号相同，第二时钟端CK2和第六时钟端CK6的时钟信号相同，第三时钟端CK3和第七时钟端CK7的时钟信号相同，第四时钟端CK4和第八时钟端CK8的时钟信号相同，第一时钟端CK1和第三时钟端CK3的时钟信号互为反向信号，第二时钟端CK2和第四时钟端CK4的时钟信号互为反向信号。在检测阶段，待检测的像素电路连接的移位寄存器所连接的时钟端的时钟信号为高电平，其余的移位寄存器所连接的时钟端的时钟信号均为低电平。仅待检测的像素电路连接的移位寄存器的第一输出端输出多次脉冲，其余移位寄存器仅输出单次脉冲。
本公开实施例还提供了一种移位寄存器的驱动方法，应用于移位寄存器中，移位寄存器设置在显示面板中，显示面板包括：显示阶段和检测阶段。本公开实施例提供的移位寄存器的驱动方法包括以下步骤：
步骤100、在显示阶段，在信号输入端的控制下，输入子电路向上拉节点提供第一电源端的信号；在上拉节点的控制下，输出子电路向第一输出端提供第三时钟信号端的信号，向第二输出端提供第二时钟信号端的信号；在第一电源端和上拉节点的控制下，在第一复位端的控制下，第一复位子电路向上拉节点提供第二电源端的信号；在第一电源端和上拉节点的控制下，下拉子电路向上拉节点和第二输出端提供第二电源端的信号，向第一输出端提供第三电源端的信号。
步骤200、在检测阶段，在信号输入端、随机检测信号端、第一时钟信号端和第一复位端的控制下，检测控制子电路向上拉节点提供第一时钟信号端的信号，在上拉节点的控制下，输出子电路向第一输出端提供第三时钟信号端的信号。
移位寄存器为前述任一个实施例提供的移位寄存器，实现原理和实现效 果类似，在此不再赘述。
在一种示例性实施例中，在检测阶段，一种示例性实施例提供的移位寄存器的驱动方法还可以包括：在第二复位端的控制下，第二复位子电路向上拉节点和检测节点提供第二电源端的信号。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种移位寄存器，包括：输入子电路、检测控制子电路、输出子电路、第一复位子电路和下拉子电路；
    所述输入子电路，分别与信号输入端、第一电源端和上拉节点连接，设置为在信号输入端的控制下，向上拉节点提供第一电源端的信号；
    所述检测控制子电路，分别与随机检测信号端、信号输入端、第一时钟信号端、第一复位端和上拉节点连接，设置为在信号输入端、随机检测信号端、第一时钟信号端和第一复位端的控制下，向上拉节点提供第一时钟信号端的信号；
    所述第一复位子电路，分别与第一复位端、上拉节点和第二电源端连接，设置为在第一复位端的控制下，向上拉节点提供第二电源端的信号；
    所述输出子电路，分别与第二时钟信号端、第三时钟信号端、上拉节点、第一输出端和第二输出端连接，设置为在上拉节点的控制下，向第一输出端提供第三时钟信号端的信号，向第二输出端提供第二时钟信号端的信号；
    所述下拉子电路，分别与第一电源端、第二电源端、第三电源端、上拉节点、第一输出端和第二输出端连接，设置为在第一电源端和上拉节点的控制下，向上拉节点和第二输出端提供第二电源端的信号，向第一输出端提供第三电源端的信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述检测控制子电路包括：检测节点控制子电路和检测输出子电路；
    所述检测节点控制子电路，分别与信号输入端、检测节点、随机检测信号、上拉节点和第一复位端连接，设置为在信号输入端、随机检测信号端和第一复位端的控制下，向检测节点提供信号输入端或上拉节点的信号；
    所述检测输出子电路，分别与检测节点、第一时钟信号端和上拉节点连接，设置为在第一时钟信号端和检测节点的控制下，向上拉节点提供第一时钟信号端的信号。
  3. 根据权利要求2所述的移位寄存器，还包括：第二复位子电路；
    所述第二复位子电路，分别与第二复位端、上拉节点、检测节点和第二电源端连接，设置为在第二复位端的控制下，向上拉节点和检测节点提供第二电源端的信号。
  4. 根据权利要求2所述的移位寄存器，其中，所述检测节点控制子电路包括：第一晶体管、第二晶体管和第三晶体管；
    第一晶体管的控制极和第一极与信号输入端连接，第一晶体管的第二极与检测节点连接；
    第二晶体管的控制极与随机检测信号端连接，第二晶体管的第一极与检测节点连接，第二晶体管的第二极与第三晶体管的第一极连接；
    第三晶体管的控制极与第一复位端连接，第三晶体管的第二极与上拉节点连接。
  5. 根据权利要求2所述的移位寄存器，其中，所述检测输出子电路包括：第四晶体管、第五晶体管和第一电容；
    第四晶体管的控制极与检测节点连接，第四晶体管的第一极与第一时钟信号端连接，第四晶体管的第二极与第五晶体管的第一极连接；
    第五晶体管的控制极与第一时钟信号端连接，第五晶体管的第二极与上拉节点连接；
    第一电容的第一端与检测节点连接，第一电容的第二端与第四晶体管的第二极连接。
  6. 根据权利要求1所述的移位寄存器，其中，所述输入子电路包括：第六晶体管；
    第六晶体管的控制极与信号输入端连接，第六晶体管的第一极与第一电源端连接，第六晶体管的第二极与上拉节点连接。
  7. 根据权利要求1所述的移位寄存器，其中，所述输出子电路包括：第七晶体管、第八晶体管和第二电容；
    第七晶体管的控制极与上拉节点连接，第七晶体管的第一极与第二时钟信号端连接，第七晶体管的第二极与第二输出端连接；
    第八晶体管的控制极与上拉节点连接，第八晶体管的第一极与第三时钟信号端连接，第八晶体管的第二极与第一输出端连接；
    第二电容的第一端与上拉节点连接，第二电容的第二端与第一输出端连接。
  8. 根据权利要求1所述的移位寄存器，其中，所述下拉子电路包括：第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
    第九晶体管的控制极和第一极与第一电源端连接，第九晶体管的第二极与下拉节点连接；
    第十晶体管的控制极与上拉节点连接，第十晶体管的第一极与下拉节点连接，第十晶体管的第二极与第二电源端连接；
    第十一晶体管的控制极与下拉节点连接，第十一晶体管的第一极与上拉节点连接，第十一晶体管的第二极与第二电源端连接；
    第十二晶体管的控制极与下拉节点连接，第十二晶体管的第一极与第二输出端连接，第十二晶体管的第二极与第二电源端连接；
    第十三晶体管的控制极与下拉节点连接，第十三晶体管的第一极与第一输出端连接，第十三晶体管的第二极与第三电源端连接。
  9. 根据权利要求1所述的移位寄存器，其中，所述第一复位子电路包括：第十四晶体管；
    第十四晶体管的控制极与第一复位端连接，第十四晶体管的第一极与上拉节点连接，第十四晶体管的第二极与第二电源端连接。
  10. 根据权利要求3所述的移位寄存器，其中，所述第二复位子电路包括：第十五晶体管和第十六晶体管；
    第十五晶体管的控制极与第二复位端连接，第十五晶体管的第一极与检测节点连接，第十五晶体管的第二极与上拉节点连接；
    第十六晶体管的控制极与第二复位端连接，第十六晶体管的第一极与上拉节点连接，第十六晶体管的第二极与第二电源端连接。
  11. 根据权利要求1所述的移位寄存器，还包括：第二复位子电路；
    其中，所述检测控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第一电容；所述输入子电路包括：第六晶体管；所述输出子电路包括：第七晶体管、第八晶体管和第二电容；所述下拉子电路包括：第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；所述第一复位子电路包括：第十四晶体管；所述第二复位子电路包括：第十五晶体管和第十六晶体管；
    第一晶体管的控制极和第一极与信号输入端连接，第一晶体管的第二极与检测节点连接；
    第二晶体管的控制极与随机检测信号端连接，第二晶体管的第一极与检测节点连接，第二晶体管的第二极与第三晶体管的第一极连接；
    第三晶体管的控制极与第一复位端连接，第三晶体管的第二极与上拉节点连接；
    第四晶体管的控制极与检测节点连接，第四晶体管的第一极与第一时钟信号端连接，第四晶体管的第二极与第五晶体管的第一极连接；
    第五晶体管的控制极与第一时钟信号端连接，第五晶体管的第二极与上拉节点连接；
    第一电容的第一端与检测节点连接，第一电容的第二端与第四晶体管的第二极连接；
    第六晶体管的控制极与信号输入端连接，第六晶体管的第一极与第一电源端连接，第六晶体管的第二极与上拉节点连接；
    第七晶体管的控制极与上拉节点连接，第七晶体管的第一极与第二时钟信号端连接，第七晶体管的第二极与第二输出端连接；
    第八晶体管的控制极与上拉节点连接，第八晶体管的第一极与第三时钟信号端连接，第八晶体管的第二极与第一输出端连接；
    第二电容的第一端与上拉节点连接，第二电容的第二端与第一输出端连接；
    第九晶体管的控制极和第一极与第一电源端连接，第九晶体管的第二极与下拉节点连接；
    第十晶体管的控制极与上拉节点连接，第十晶体管的第一极与下拉节点连接，第十晶体管的第二极与第二电源端连接；
    第十一晶体管的控制极与下拉节点连接，第十一晶体管的第一极与上拉节点连接，第十一晶体管的第二极与第二电源端连接；
    第十二晶体管的控制极与下拉节点连接，第十二晶体管的第一极与第二输出端连接，第十二晶体管的第二极与第二电源端连接；
    第十三晶体管的控制极与下拉节点连接，第十三晶体管的第一极与第一输出端连接，第十三晶体管的第二极与第三电源端连接；
    第十四晶体管的控制极与第一复位端连接，第十四晶体管的第一极与上拉节点连接，第十四晶体管的第二极与第二电源端连接；
    第十五晶体管的控制极与第二复位端连接，第十五晶体管的第一极与检测节点连接，第十五晶体管的第二极与上拉节点连接；
    第十六晶体管的控制极与第二复位端连接，第十六晶体管的第一极与上拉节点连接，第十六晶体管的第二极与第二电源端连接。
  12. 一种栅极驱动电路，包括：多个级联的如权利要求1至11任一项所述的移位寄存器；
    第一级移位寄存器的信号输入端与初始信号端连接，第二级移位寄存器的信号输入端与初始信号端连接，第N+2级移位寄存器的信号输入端与第N级移位寄存器的第二输出端连接，第N级移位寄存器的第一复位端与第N+3级移位寄存器的第二输出端连接，N≥1。
  13. 根据权利要求12所述的栅极驱动电路，其中，所述栅极驱动电路包括：第一时钟端、第二时钟端、第三时钟端、第四时钟端、第五时钟端、第六时钟端、第七时钟端和第八时钟端；
    第4i+1级移位寄存器的第二时钟信号端与第一时钟端连接，第4i+1级移位寄存器的第三时钟信号端与第五时钟端连接，第4i+2级移位寄存器的第二时钟信号端与第二时钟端连接，第4i+2级移位寄存器的第三时钟信号端与第六时钟端连接，第4i+3级移位寄存器的第二时钟信号端与第三时钟端连接，第4i+3级移位寄存器的第三时钟信号端与第七时钟端连接，第4i+4级移位 寄存器的第二时钟信号端与第四时钟端连接，第4i+4级移位寄存器的第三时钟信号端与第八时钟端连接。
  14. 一种移位寄存器的驱动方法，应用于权利要求1至11任一项所述的移位寄存器中，所述移位寄存器设置在显示面板中，所述显示面板包括：显示阶段和检测阶段，所述方法包括：
    在显示阶段，在信号输入端的控制下，输入子电路向上拉节点提供第一电源端的信号；在上拉节点的控制下，输出子电路向第一输出端提供第三时钟信号端的信号，向第二输出端提供第二时钟信号端的信号；在第一电源端和上拉节点的控制下，在第一复位端的控制下，第一复位子电路向上拉节点提供第二电源端的信号；在第一电源端和上拉节点的控制下，下拉子电路向上拉节点和第二输出端提供第二电源端的信号，向第一输出端提供第三电源端的信号；
    在检测阶段，在信号输入端、随机检测信号端、第一时钟信号端和第一复位端的控制下，检测控制子电路向上拉节点提供第一时钟信号端的信号，在上拉节点的控制下，输出子电路向第一输出端提供第三时钟信号端的信号。
  15. 根据权利要求14所述的方法，在检测阶段，所述方法还包括：在第二复位端的控制下，第二复位子电路向上拉节点和检测节点提供第二电源端的信号。
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