WO2021022782A1 - 存储器与其读写方法 - Google Patents

存储器与其读写方法 Download PDF

Info

Publication number
WO2021022782A1
WO2021022782A1 PCT/CN2019/130601 CN2019130601W WO2021022782A1 WO 2021022782 A1 WO2021022782 A1 WO 2021022782A1 CN 2019130601 W CN2019130601 W CN 2019130601W WO 2021022782 A1 WO2021022782 A1 WO 2021022782A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage
memory
switch
bit
voltage
Prior art date
Application number
PCT/CN2019/130601
Other languages
English (en)
French (fr)
Inventor
熊保玉
何世坤
陆宇
Original Assignee
浙江驰拓科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浙江驰拓科技有限公司 filed Critical 浙江驰拓科技有限公司
Publication of WO2021022782A1 publication Critical patent/WO2021022782A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • the present disclosure relates to the field of memory, and in particular, to a memory and a reading and writing method thereof.
  • the main purpose of the present disclosure is to provide a memory and a reading and writing method thereof to solve the problem of large leakage current of the memory caused by the 3D stacking technology in the prior art.
  • a memory includes a plurality of storage layers arranged along a first direction, each of the storage layers includes: a storage array, including a plurality of arrays arranged The row direction and the column direction of the memory cell array are respectively perpendicular to the first direction, and the first direction is perpendicular to the thickness direction of each memory cell.
  • the memory cell includes a first terminal and a second terminal. The first terminals of each memory cell in the same row are respectively electrically connected to the same bit line, and the memory cells in any two rows are correspondingly connected to the bit lines.
  • the line is different; the switch unit includes a plurality of switches, a plurality of spaced word lines, and at least one source line, wherein each switch includes a first end, a second end and a control end, and the control end of the switch is connected to the
  • the word line is electrically connected, the second end of the switch is electrically connected to the source line, and the first end of the switch is electrically connected to the second end of the memory cell.
  • the second ends of the storage cells in the same column are electrically connected to the first ends of the same switch, and the storage cells in any two columns are correspondingly connected to the switches Differently, the control terminals of the switches are connected to the word lines in a one-to-one correspondence.
  • each of the switch units of the storage layer there is one source line.
  • each of the storage layers is the same, and a line connecting the center points of each of the storage layers is parallel to the first direction.
  • the word lines corresponding to the positions in a plurality of the storage layers are electrically connected to form a word line bus, and the number of the word line buses in the memory and the column of the memory cells in each storage layer The numbers are the same.
  • the switch is a transistor
  • the first terminal of the switch is the source of the transistor
  • the control terminal of the switch is the source of the transistor. Grid.
  • the storage unit includes a storage bit and a selector connected in series with the storage bit.
  • the end of the storage bit far from the selector is the first end of the storage unit.
  • the end far from the storage bit is the second end of the storage unit.
  • the storage bit is MTJ
  • the selector is a bidirectional switch.
  • a method for reading and writing a memory includes a writing process, the writing process including a first writing process, and the first writing process It includes: applying a first voltage to the selected word line to turn on the switch electrically connected to the selected word line; applying a second voltage to the selected bit line, the second voltage being used to write the memory cell as the first One state; no voltage is applied to the unselected bit line.
  • one storage layer of the memory includes one source line, and the source line in one storage layer is electrically connected to the second end of each switch, and the storage cell of the storage layer includes The storage bit and the selector connected in series with the storage bit, the writing process further includes a second writing process, the second writing process includes: applying a first voltage to the selected word line so that the The switch electrically connected to the selected word line is turned on; applying a third voltage to the source line, the third voltage being greater than the turn-on voltage of the selector; applying 0V to the selected bit line, The storage bit is written in the second state, and the resistance of the storage bit in the first state is greater than the resistance in the second state; no voltage is applied to the unselected bit line.
  • the storage unit of the storage layer includes a storage bit and a selector connected in series with the storage bit.
  • the read-write method further includes a read-out process, and the read-out process includes: The first voltage is applied to the selected word line to turn on the switch electrically connected to the selected word line; a fourth voltage is applied to the selected bit line, the fourth voltage is greater than the turn-on voltage of the selector and less than The second voltage; no voltage is applied to the unselected bit line.
  • the above-mentioned memory includes a plurality of memory layers arranged along a first direction, and the first direction is perpendicular to the thickness direction of the memory cell, that is, the memory layers in the memory are arranged in a horizontal direction.
  • the arrangement is different from the arrangement direction of the storage layers in the X-Piont technology in the prior art, and this arrangement of the present disclosure makes the bit lines and source lines of adjacent storage layers independent of each other, Voltage can be applied separately, and when one of the layers is selected, there is no voltage difference between the bit line and the source line of the adjacent storage layer, so there is no leakage phenomenon, so that the leakage of the memory is small.
  • the memory of the present disclosure can increase the storage capacity mainly by increasing the number of storage layers, so that each storage layer The capacity can be small, so that the leakage of each storage layer is small.
  • Figure 1 shows a schematic structural diagram of an embodiment of a memory according to the present disclosure
  • Fig. 2 shows a schematic diagram of a partial structure in Fig. 1;
  • FIG. 3 shows a schematic structural diagram of a storage layer of an embodiment of the present disclosure
  • Figure 4 shows a schematic diagram of an equivalent structure of the memory
  • Figure 5 shows a schematic diagram of a partial structure of the memory of the embodiment.
  • Figure 6 shows a schematic structural diagram of a comparative example.
  • the memory formed by the 3D stacking technology in the prior art has a relatively large leakage current.
  • the present disclosure proposes a memory and a reading and writing method thereof.
  • a memory is provided. As shown in FIG. 1, the memory includes a plurality of storage layers 10 arranged along a first direction, as shown in FIG. 1 and FIG. Storage layer 10 includes:
  • the memory array includes a plurality of memory cells 11 arranged in an array and a plurality of bit lines 14 arranged at intervals.
  • the row direction and column direction of the memory cells 11 are arranged perpendicular to the first direction, and the first direction is connected to each of the memory cells.
  • the thickness direction of the cell 11 is vertical.
  • Each of the memory cells 11 includes a first end and a second end. The first ends of the memory cells 11 in the same row are electrically connected to the same bit line 14, and any two rows of the above
  • the aforementioned bit lines 14 corresponding to the storage unit 11 are different;
  • the switch 12 unit includes a plurality of switches 12, a plurality of spaced word lines 13, and at least one source line 15.
  • Each of the switches 12 includes a first terminal, a second terminal, and a control terminal.
  • the control terminal of the switch 12 is connected to The word line 13 is electrically connected, the second end of the switch 12 is electrically connected to the source line 15, and the first end of the switch 12 is electrically connected to the second end of the memory cell 11.
  • the above-mentioned memory includes a plurality of memory layers 10 arranged along a first direction, and the first direction is perpendicular to the thickness direction of the memory cell 11, that is, the memory layers 10 in the memory are arranged in a horizontal direction.
  • the arrangement direction of the storage layer 10 in the X-Piont technology in the prior art is different, and the arrangement of the present disclosure makes the bit lines 14 and the source lines 15 of the adjacent storage layers 10 independent of each other, Voltages can be applied separately. When one of the layers is selected, there is no voltage difference between the bit line 14 and the source line 15 of the adjacent storage layer 10, so there is no leakage phenomenon, so that the leakage of the memory is small.
  • multiple storage layers 10 formed by the X-Piont technology in the prior art share the word line 13 or the bit line 14.
  • the adjacent storage layer 10 will have the problem of leakage.
  • different storage layers 10 do not share bit lines 14 and source lines 15 in the memory, random read and write operations can be implemented, which improves the performance of the memory and avoids multiple memories formed by the X-Piont technology in the prior art.
  • the layer 10 shares the word line 13 or the bit line 14, which causes the problem that different memory layers 10 cannot be operated randomly, and can only be programmed or erased at the same time.
  • the memory of the present disclosure can increase the storage capacity mainly by increasing the number of storage layers.
  • the capacity of each storage layer can be small, so that the leakage of each storage layer is small.
  • the number of columns of memory cells 11 and the number of switches 12 in the memory layer 10 are the same, and the two are connected in a one-to-one correspondence, and the number of switches 12 and the number of word lines 13 are also the same, and the two are also in one-to-one correspondence connection.
  • This can reduce the number of switches 12 and word lines 13, simplify the structure and manufacturing process of the memory, and because the number of word lines 13 is positively correlated with the size of the memory leakage current, the less the number of word lines 13, the memory leakage current The smaller.
  • each memory cell may be connected to a switch correspondingly, and each switch is correspondingly connected to a word line, that is, the number of switches and the number of word lines are the same as the number of memory cells.
  • Those skilled in the art can select a suitable structure according to actual conditions to form the memory corresponding to the present disclosure.
  • the number of source lines can be set according to actual conditions, for example, it can be set according to the switching conditions, and those skilled in the art can set an appropriate number of source lines and Corresponding switch connection.
  • each of the above-mentioned storage layers 10 there is one above-mentioned source line 15.
  • the arrangement direction of the multiple storage layers of the memory in the present disclosure only represents the positional relationship of adjacent layers.
  • the memory shown in FIG. 1 includes four storage layers 10, and the four storage layers 10 follow from Arrange from left to right or right to left (judged when a person faces a computer screen or paper).
  • the above-mentioned storage layers 10 are the same, and the line of the center points of the above-mentioned storage layers 10 is parallel to the above-mentioned first direction, as shown in FIG. 1.
  • the word lines 13 corresponding to the positions in the plurality of the memory layers 10 are electrically connected to form a word Line 13 bus, it can be said that multiple storage layers 10 share one word line 13 bus.
  • the number of word line 13 buses in the above-mentioned memory and the column of memory cells 11 in each above-mentioned storage layer 10 The numbers are the same.
  • the switch of the present disclosure may be any applicable switch in the prior art, such as a triode or a diode.
  • the switch is a transistor
  • the first switch is a transistor.
  • the terminal 121 is the source of the transistor
  • the second terminal 122 of the switch and the drain of the transistor and the control terminal of the switch (the third terminal 123 of the switch) is the gate of the transistor.
  • the storage unit of the present disclosure may be any storage unit in the prior art, and those skilled in the art can select a suitable storage unit according to actual conditions to form the storage array of the present disclosure.
  • the storage unit includes a storage bit and a selector connected in series with the storage bit, and the end of the storage bit far from the selector is the end of the storage unit. At the first end, the end of the selector far from the storage bit is the second end of the storage unit.
  • the above-mentioned storage bit may be any bit with a storage function in the prior art, and the selector may also be any device in the prior art that can realize the bidirectional communication function.
  • the above-mentioned storage bit is MTJ, and the selector is a bidirectional switch.
  • the reading and writing method includes a writing process, the writing process includes a first writing process, and the first writing process includes: A first voltage is applied to the selected word line to turn on the switch electrically connected to the selected word line; a second voltage is applied to the selected bit line, and the second voltage is used to write the memory cell to the first state.
  • the second voltage should be greater than the turn-on voltage of the selector and the write voltage of the storage bit; no voltage is applied to the unselected bit line, that is, the unselected bit The line is floating.
  • the reading and writing method by applying voltage to the word line and the bit line, the first writing process to the selected memory cell can be realized, and the writing process of the memory cell does not affect the memory cells of other memory layers That is, the other storage layers will not leak electricity, and the read and write method can perform random write operations.
  • one storage layer of the above-mentioned memory includes one source line, and the above-mentioned source line in one of the above-mentioned storage layers is electrically connected to the second terminal 122 of each of the above-mentioned switches.
  • the storage unit of the storage layer includes a storage bit and a selector connected in series with the storage bit
  • the writing process further includes a second writing process
  • the second writing process includes: applying a second write to the selected word line A voltage to turn on the switch electrically connected to the selected word line; apply a third voltage to the source line, and the third voltage is greater than the turn-on voltage of the selector; apply 0V to the selected bit line
  • the storage bit is written in the second state, and the resistance corresponding to the storage bit in the first state is greater than the resistance in the second state, that is, the first state is a high resistance state, and the second state is a low resistance state;
  • the unselected bit lines are not applied with any voltage, that is, they are floating. In the writing process, only the selected memory cell is written, and there is no impact on the memory cell of the unselected memory layer, and no leakage problem will occur.
  • the storage unit of the storage layer includes a storage bit and a selector connected in series with the storage bit
  • the reading and writing method further includes a reading process
  • the reading process includes: The word line applies the first voltage to turn on the switch electrically connected to the selected word line; applies a fourth voltage to the selected bit line, and the fourth voltage is greater than the turn-on voltage of the selector and less than the second Voltage, so that the storage state of the memory cell can be read but not changed; no voltage is applied to the unselected bit line.
  • the structure of the memory is shown in Figure 1.
  • the memory is composed of 512 storage layers 10 arranged in the first direction. Only four storage layers 10 are shown in the figure, and each storage layer 10 consists of a storage array, multiple switches 12, multiple word lines 13, and more. One bit line 14 and one source line 15 are formed.
  • the number of switches 12 is the same as the number of columns of the memory cell 11
  • the number of bit lines 14 is the same as the number of rows of the memory cell 11
  • the number of word lines 13 is the same as the number of switches 12, where the switch 12 is a transistor
  • the storage unit 11 includes a selector and an MTJ.
  • the specific connection relationship is shown in Figure 1. Specifically, as shown in FIG. 3 and FIG.
  • the storage bit 111 is a CoFeB/MgO system of MTJ, which specifically includes a free layer, a barrier insulating layer and a fixed layer
  • the selector 112 is a doped HfOx system
  • MTJ and selection The devices are separated by a metal isolation layer 113, and each memory cell 11 is selected by a WL and a BL.
  • the memory of this embodiment has a leakage channel by selecting any cell on the BL ⁇ the cell corresponding to the Z connection line ⁇ any cell in the column ⁇ selecting the corresponding cell in the column.
  • the structure of the memory is shown in Figure 5.
  • the memory is composed of 512 memory layers arranged in a second direction, the second direction is parallel to the thickness direction of the memory cell and perpendicular to the first direction. Only three layers are shown in the figure.
  • the switch is a transistor, and the memory cell includes a selector and an MTJ.
  • the specific connection relationship is shown in Figure 3.
  • W represents the number of WL
  • IO represents the width of IO
  • L Min(LP, 5), Wherein, LP represents the number of storage layers in the comparative example, and LV represents the number of storage layers in the embodiment.
  • I sneak represents the maximum leakage of a single leakage path.
  • I leakage_V L*(B-1)*(W-1)*IO*I sneak
  • I leakage_P L*(W-1)*(B-1)*IO*I sneak
  • I leakage_V /I leakage_P 1/62
  • the leakage current of the embodiment is 1/62 of the leakage current of the comparative example.
  • the BL and SL of the different storage layers of the embodiment are independent, random writing can be realized and the performance of the memory can be improved.
  • different storage layers share the BL, different layers cannot operate randomly, and can only be programmed or erased at the same time. .
  • the memory of the present disclosure includes a plurality of memory layers arranged along a first direction, and the first direction is perpendicular to the thickness direction of the memory cell, that is, the memory layers in the memory are arranged in a horizontal direction, This is different from the arrangement direction of the storage layers in the X-Piont technology in the prior art, and the arrangement of the present disclosure makes the bit lines and source lines of adjacent storage layers independent of each other and can be added separately. Voltage, when one of the layers is selected, there is no voltage difference between the bit line and the source line of the adjacent storage layer, so there is no leakage phenomenon, so that the leakage of the memory is small.
  • the memory of the present disclosure can increase the storage capacity mainly by increasing the number of storage layers.
  • the capacity of each storage layer can be small, so that the leakage of each storage layer is small.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种存储器与其读写方法。该存储器包括多个沿着第一方向排列的存储层，各存储层包括：存储阵列，包括多个阵列方式排列的存储单元（11）和多个间隔设置的位线（14）；开关单元，包括多个开关（12）、多个间隔的字线（13）以及至少一个源极线（15）。这种排列方式使得相邻的存储层的位线（14）和源极线（15）相互之间独立，可以单独加电压，当其中的一层被选中时，其相邻的存储层的位线和源极线之间没有压差，所以不存在漏电现象，使得该存储器的漏电较小。该存储器由于不同的存储层不共用位线（14）和源极线（15），因此，可以实现随机读写操作，提高存储器的性能。

Description

存储器与其读写方法
本公开以2019年8月8日递交的、申请号为201910731330.0且名称为“存储器与其读写方法”的专利文件为优先权文件，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储器领域，具体而言，涉及一种存储器与其读写方法。
背景技术
现有技术中，为了提升存储器的存储容量，需要提供存储器的存储密度。
现有技术中，通常有三种方式来提升存储密度，一种为减小存储单元的尺寸，但是，这种方式受到制作仪器、工艺水平以及存储单元的特性的限制，已经基本达到了极限；另一种为增加存储单元的存储状态，这种方案中虽然在实验室中有各种报导，但在大量晶圆中让每个die都具备一致的多态特性参数，实现多态的写入和读取非常困难；第三种为3D堆叠技术，例如NAND flash以及X-point技术，其中，NAND flash型堆叠技术写入速度慢，不适合用作MRAM的3D堆叠，X-point类似技术为在垂直方向上堆叠多个结构层，该技术现在并未商业化，存在的问题如漏电流大和不能随机读写等。
在背景技术部分中公开的以上信息只是用来加强对本文所描述技术的背景技术的理解，因此，背景技术中可能包含某些信息，这些信息对于本领域技术人员来说并未形成在本国已知的现有技术。
发明内容
本公开的主要目的在于提供一种存储器与其读写方法，以解决现有技术中的3D堆叠技术导致的存储器漏电流较大的问题。
为了实现上述目的，根据本公开的一个方面，提供了一种存储器，所述存储器包括多个沿着第一方向排列的存储层，各所述存储层包括：存储阵列，包括多个阵列方式排列的存储单元和多个间隔设置的位线，所述存储单元排列的行方向和列方向分别与所述第一方向垂直，所述第一方向与各所述存储单元的厚度方向垂直，各所述存储单元包括第一端和第二端，同一行的各所述存储单元的第一端分别与同一个所述位线电连接，且任意两行的所述存储单元对应连接的所述位线不同；开关单元，包括多个开关、多个间隔的字线以及至少一个源极线，其中，各所述开关包括第一端、第二端和控制端，所述开关的控制端与所述字线电连接，所述开关的第二端与所述源极线电连接，所述开关的第一端与所述存储单元的第二端电连接。
进一步地，在各所述存储层中，同一列的所述存储单元的第二端与同一个所述开关的第一端电连接，且任意两列的所述存储单元对应连接的所述开关不同，所述开关的控制端与所述字线一一对应连接。
进一步地，每个所述存储层的所述开关单元中，所述源极线有一个。
进一步地，各所述存储层相同，且各所述存储层的中心点的连线平行于所述第一方向。
进一步地，多个所述存储层中位置对应的所述字线电连接形成一个字线总线，所述存储器中的所述字线总线的个数与各所述存储层中的存储单元的列数相同。
进一步地，所述开关为晶体管，所述开关的第一端为所述晶体管的源极，所述开关的第二端与所述晶体管的漏极，所述开关的控制端为所述晶体管的栅极。
进一步地，所述存储单元包括存储位元和与所述存储位元串联的选择器，所述存储位元远离所述选择器的一端为所述存储单元的第一端，所述选择器的远离所述存储位元的一端为所述存储单元的第二端。
进一步地，所述存储位元为MTJ，所述选择器为双向导通开关。
为了实现上述目的，根据本公开的另一个方面，提供了一种存储器的读写方法，所述读写方法包括写过程，所述写过程包括第一写入过程，所述第一写入过程包括：对选中的字线施加第一电压，使得与选中的所述字线电连接的开关导通；对选中的位线施加第二电压，所述第二电压用于将存储单元写为第一状态；对未选中的所述位线不施加任何电压。
进一步地，所述存储器的一个存储层中包括一个源极线，且一个所述存储层中的所述源极线与各所述开关的第二端电连接，所述存储层的存储单元包括存储位元和与所述存储位元串联的选择器，所述写过程还包括第二写入过程，所述第二写入过程包括：对选中的所述字线施加第一电压，使得与选中的所述字线电连接的所述开关导通；对所述源极线施加第三电压，所述第三电压大于所述选择器的开启电压；对选中的所述位线施加0V，将所述存储位元写为第二状态，所述存储位元在所述第一状态对应的电阻大于在所述第二状态对应的电阻；对未选中的所述位线不施加任何电压。
进一步地，所述存储层的存储单元包括存储位元和与所述存储位元串联的选择器，所述读写方法还包括读出过程，所述读出过程包括：对选中的所述字线施加所述第一电压，使得与选中的所述字线电连接的所述开关导通；对选中的位线施加第四电压，所述第四电压大于所述选择器的开启电压且小于所述第二电压；对未选中的所述位线不施加任何电压。
应用本公开的技术方案，上述的存储器中包括多个沿着第一方向排列的存储层，且第一方向与存储单元的厚度方向垂直，也就是说，该存储器中的存储层是按照水平方向排列的，这与现有技术中的X-Piont技术中的存储层的排列方向不同，并且，本公开的这种排列方式使得相邻的存储层的位线和源极线相互之间独立，可以单独加电压，当其中的一层被选中时，其相邻的存储层的位线和源极线之间没有压差，所以不存在漏电现象，使得该存储器的漏电 较小。避免了现有技术中的X-Piont技术形成的多个存储层共用字线或者位线，当其中的一层被选中时，相邻的存储层会有漏电的问题。并且，该存储器由于不同的存储层不共用位线和源极线，因此，可以实现随机读写操作，提高存储器的性能，避免现有技术中的X-Piont技术形成的多个存储层公用字线或者位线，导致不同存储层不能随机操作，只能同时编程或擦除的问题。
并且，与现有技术中的X-Piont技术形成的存储器依靠增加每个存储层的密度来提升存储容量的方式不同(该X-Piont技术中如果依赖增加存储层的个数来提高存储容量的话，漏电流会非常大，难以实现，所以只能依靠增加每个存储层的密度来提升存储容量)，本公开的存储器可以主要靠增加存储层的个数来增加存储容量，这样每个存储层的容量可以较小，从而使得每个存储层的漏电较小。
附图说明
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1示出了根据本公开的存储器的实施例的结构示意图；
图2示出了图1中的局部结构示意图；
图3示出了本公开的实施例的存储层的结构示意图；
图4示出了存储器的等效结构示意图；
图5示出了实施例的存储器的局部结构示意图；以及
图6示出了对比例的结构示意图。
其中，上述附图包括以下附图标记：
10、存储层；11、存储单元；12、开关；13、字线；14、位线；15、源极线；16、字线总线；111、存储位元；112、选择器；113、金属隔离层；121、开关的第一端；122、开关的第二端；123、开关的第三端。
具体实施方式
应该指出，以下详细说明都是例示性的，旨在对本公开提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本公开所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本公开的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括” 时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
正如背景技术所介绍的，现有技术中的3D堆叠技术形成的存储器的漏电流较大，为了解决如上的技术问题，本公开提出了一种存储器与其读写方法。
本公开的一种典型的实施方式中，提供了一种存储器，如图1所示，该存储器包括多个沿着第一方向排列的存储层10，如图1和图2所示，各上述存储层10包括：
存储阵列，包括多个阵列方式排列的存储单元11和多个间隔设置的位线14，上述存储单元11排列的行方向和列方向分别与上述第一方向垂直，上述第一方向与各上述存储单元11的厚度方向垂直，各上述存储单元11包括第一端和第二端，同一行的各上述存储单元11的第一端分别与同一个上述位线14电连接，且任意两行的上述存储单元11对应连接的上述位线14不同；
开关12单元，包括多个开关12、多个间隔的字线13以及至少一个源极线15，其中，各上述开关12包括第一端、第二端和控制端，上述开关12的控制端与上述字线13电连接，上述开关12的第二端与上述源极线15电连接，上述开关12的第一端与上述存储单元11的第二端电连接。
上述的存储器中包括多个沿着第一方向排列的存储层10，且第一方向与存储单元11的厚度方向垂直，也就是说，该存储器中的存储层10是按照水平方向排列的，这与现有技术中的X-Piont技术中的存储层10的排列方向不同，并且，本公开的这种排列方式使得相邻的存储层10的位线14和源极线15相互之间独立，可以单独加电压，当其中的一层被选中时，其相邻的存储层10的位线14和源极线15之间没有压差，所以不存在漏电现象，使得该存储器的漏电较小。避免了现有技术中的X-Piont技术形成的多个存储层10共用字线13或者位线14，当其中的一层被选中时，相邻的存储层10会有漏电的问题。并且，该存储器由于不同的存储层10不共用位线14和源极线15，因此，可以实现随机读写操作，提高存储器的性能，避免现有技术中的X-Piont技术形成的多个存储层10公用字线13或者位线14，导致不同存储层10不能随机操作，只能同时编程或擦除的问题。
并且，与现有技术中的X-Piont技术形成的存储器依靠增加每个存储层的密度来提升存储容量的方式不同，本公开的存储器可以主要靠增加存储层的个数来增加存储容量，这样每个存储层的容量可以较小，从而使得每个存储层的漏电较小。
为了简化存储器的结构，同时减小存储器的漏电，本公开的一种实施例中，如图1和图2所示，在各上述存储层10中，同一列的上述存储单元11的第二端与同一个上述开关12的第一端电连接，且任意两列的上述存储单元11对应连接的上述开关12不同，上述开关12的控 制端与上述字线13一一对应连接。也就是说，存储层10中的存储单元11的列数和开关12的数量相同，且二者一一对应地连接，开关12的数量和字线13的数量也相同，二者也是一一对应连接。这样可以减少开关12和字线13的数量，简化存储器的结构和制作工艺难度，且由于字线13的数量和存储器漏电流的大小成正相关，所以字线13的数量越少，存储器的漏电流越小。
当然，本公开的存储器并限于上述情况，还可以为每个存储单元对应连接一个开关，每一个开关与一个字线对应连接，即开关的数量、字线的数量均和存储单元的数量相同。本领域技术人员可以根据实际情况选择合适的结构形成本公开对应的存储器。
本公开的每个存储层的开关单元中，源极线的个数可以根据实际情况来设置，比如可以根据开关的情况来设置，本领域技术人员可以根据实际情况设置合适数量的源极线与对应的开关连接。
在每个存储层中的存储单元的列数与开关的数量相同，且一列对应一个开关的情况下，即图1和图2的情况中，为了简化存储器的结构，降低其制作工艺的难度，本公开的一种实施例中，如图1和图2所示，每个上述存储层10中，上述源极线15有一个。
需要说明的是，本公开中的存储器的多个存储层的排列方向只表征相邻层的位置关系，例如图1所示的存储器中包括四个存储层10，且四个存储层10按照从左向右或者从右向左(人面对电脑屏幕或者纸的情况下判断得出)的方向排列。
为了进一步提高存储密度，本公开的一种实施例中，各上述存储层10相同，且各上述存储层10的中心点的连线平行于上述第一方向，如图1所示。
为了进一步简化存储器的结构，减小存储器的漏电流，且方便存储器的读写操作，本公开的一种实施例中，多个上述存储层10中位置对应的上述字线13电连接形成一个字线13总线，即可以说多个存储层10共用一个字线13总线，如图1所示，上述存储器中的上述字线13总线的个数与各上述存储层10中的存储单元11的列数相同。
本公开的开关可以为现有技术中的任何可应用的开关，例如三极管或者二极管等，本公开的一种具体的实施例中，如图1所示，上述开关为晶体管，上述开关的第一端121为上述晶体管的源极，上述开关的第二端122与上述晶体管的漏极，上述开关的控制端(开关的第三端123)为上述晶体管的栅极。
需要说明的是，本公开的存储单元可以为现有技术中的任何存储单元，本领域技术人员可以根据实际情况选择合适的存储单元形成本公开的存储阵列。
本公开的一种具体的实施例中，如图2所示，上述存储单元包括存储位元和与上述存储位元串联的选择器，上述存储位元远离上述选择器的一端为上述存储单元的第一端，上述选择器的远离上述存储位元的一端为上述存储单元的第二端。
上述存储位元可以为现有技术中的任何具有存储功能的位元，选择器也可以为现有技术 中的任何可以实现双向导通功能的器件，本公开的一种具体的实施例中，上述存储位元为MTJ，且选择器为双向导通开关。
本公开的另一种典型的实施方式中，提供了一种上述的存储器的读写方法，该读写方法包括写过程，上述写过程包括第一写入过程，上述第一写入过程包括：对选中的字线施加第一电压，使得与选中的上述字线电连接的开关导通；对选中的位线施加第二电压，上述第二电压用于将存储单元写为第一状态，对于包括选择器和存储位元的存储单元来说，该第二电压应该大于选择器的开启电压和存储位元的写入电压；对未选中的上述位线不施加任何电压，即未选中的位线浮空。
该读写方法中，通过对字线和位线施加电压，就能够实现对选中的存储单元进行第一写入过程，并且，该存储单元的写入过程并不会影响其他存储层的存储单元的状态，即其他的存储层不会产生漏电，并且该读写方法可以进行随机的写入操作。
本公开的另一种实施例中，如图1所示，上述存储器的一个存储层中包括一个源极线，且一个上述存储层中的上述源极线与各上述开关的第二端122电连接，上述存储层的存储单元包括存储位元和与上述存储位元串联的选择器，上述写过程还包括第二写入过程，上述第二写入过程包括：对选中的上述字线施加第一电压，使得与选中的上述字线电连接的上述开关导通；对上述源极线施加第三电压，上述第三电压大于上述选择器的开启电压；对选中的上述位线施加0V，将上述存储位元写为第二状态，上述存储位元在上述第一状态对应的电阻大于在上述第二状态对应的电阻，即第一状态为高阻态，第二状态为低阻态；对未选中的上述位线不施加任何电压，即浮空。该写入过程中只写入选中的存储单元，对于未选中的存储层的存储单元没有任何的影响，也不会产生漏电问题。
本公开的再一种实施例中，上述存储层的存储单元包括存储位元和与上述存储位元串联的选择器，上述读写方法还包括读出过程，上述读出过程包括：对选中的上述字线施加上述第一电压，使得与选中的上述字线电连接的上述开关导通；对选中的位线施加第四电压，上述第四电压大于上述选择器的开启电压且小于上述第二电压，从而使得可以读取但不改变存储单元的存储状态；对未选中的上述位线不施加任何电压。
为了使得本领域技术人员能够更加清楚地了解本公开的技术方案，以下将结合具体的实施例来说明本公开的技术方案和技术效果。
实施例
该存储器的结构如图1所示。该存储器由512个按照第一方向排列的存储层10构成，图中只示出了四个存储层10，且每个存储层10由存储阵列、多个开关12、多个字线13、多个位线14和一个源极线15构成。存储层10中，开关12的数量和存储单元11的列数相同，位线14的数量和存储单元11的行数相同，字线13的数量和开关12的数量相同，其中，开关12为晶体管，存储单元11包括一个选择器和一个MTJ。具体的连接关系如图1所示。具体地，如图3和图1所示，存储位元111为MTJ的CoFeB/MgO体系，具体包括自由层、势垒绝缘层和固定层，选择器112为掺杂的HfOx体系，MTJ和选择器间用金属隔离层113隔开， 每一存储单元11通过WL和一条BL选定。
如图4所示，该实施例的存储器存在通过选中BL上任一单元→该单元对应Z连接线→该列任一单元→选中列中对应单元的漏电通道。
对比例
该存储器的结构如图5所示，该存储器由512个按照第二方向排列的存储层构成，第二方向与存储单元的厚度方向平行，且与第一方向垂直，图中只示出了三个存储层，且每个存储层由存储阵列、开关、字线、位线和源极线构成。开关为晶体管，存储单元包括一个选择器和一个MTJ。具体的连接关系如图3所示。
这两个存储器中的非严格等效模型如图6所示，对应地，存储器的漏电流的计算公式为
Figure PCTCN2019130601-appb-000001
其中，具体地，漏电流的技术公式为：I leakage＝L*(B-1)*(W-1)*IO*I sneak
B表示BL的数量，
W表示WL的数量，
IO表示IO的宽度，
L表示漏电层数，且实施例中，L＝1(未选中的相邻层无漏电，选中的存储层有漏电，所以L＝1)，对比例中，L＝Min(LP，5)，其中，LP表示对比例存储层的个数，LV表示实施例中的存储层的个数。
I sneak表示单个漏电路径最大漏电。
实施例中，B＝2，W＝1k，IO＝16，L＝1，LV＝512；
I leakage_V＝L*(B-1)*(W-1)*IO*I sneak
＝1*(2-1)*(1000-1)*16*I sneak
＝(1000-1)*16*I sneak
对比例中，B＝32，W＝1k，IO＝16，L＝2，LV＝512
I leakage_P＝L*(W-1)*(B-1)*IO*I sneak
＝2*(1000-1)*(32-1)*16*I sneak
＝62*(1000-1)*16*I sneak
因此，I leakage_V/I leakage_P＝1/62，实施例的漏电流为对比例的漏电的1/62。
另外，由于实施例不同存储层的BL和SL独立，因而可以实现随机写，提高存储器的性能；而对比例中，由于不同存储层共用BL，不同层不能随机操作，只能同时编程或擦除。
从以上的描述中，可以看出，本公开上述的实施例实现了如下技术效果：
1)、本公开的存储器中包括多个沿着第一方向排列的存储层，且第一方向与存储单元的厚度方向垂直，也就是说，该存储器中的存储层是按照水平方向排列的，这与现有技术中的X-Piont技术中的存储层的排列方向不同，并且，本公开的这种排列方式使得相邻的存储层的位线和源极线相互之间独立，可以单独加电压，当其中的一层被选中时，其相邻的存储层的位线和源极线之间没有压差，所以不存在漏电现象，使得该存储器的漏电较小。避免了现有技术中的X-Piont技术形成的多个存储层共用字线或者位线，当其中的一层被选中时，相邻的存储层会有漏电的问题。并且，该存储器由于不同的存储层不共用位线和源极线，因此，可以实现随机读写操作，提高存储器的性能，避免现有技术中的X-Piont技术形成的多个存储层公用字线或者位线，导致不同存储层不能随机操作，只能同时编程或擦除的问题。
并且，与现有技术中的X-Piont技术形成的存储器依靠增加每个存储层的密度来提升存储容量的方式不同，本公开的存储器可以主要靠增加存储层的个数来增加存储容量，这样每个存储层的容量可以较小，从而使得每个存储层的漏电较小。
2)、本公开的读写方法中，通过对字线和位线施加电压，就能够实现对选中的存储单元进行第一写入过程，并且，该存储单元的写入过程并不会影响其他存储层的存储单元的状态，即其他的存储层不会产生漏电。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (11)

  1. 一种存储器，其特征在于，所述存储器包括多个沿着第一方向排列的存储层，各所述存储层包括：
    存储阵列，包括多个阵列方式排列的存储单元和多个间隔设置的位线，所述存储单元排列的行方向和列方向分别与所述第一方向垂直，所述第一方向与各所述存储单元的厚度方向垂直，各所述存储单元包括第一端和第二端，同一行的各所述存储单元的第一端分别与同一个所述位线电连接，且任意两行的所述存储单元对应连接的所述位线不同；
    开关单元，包括多个开关、多个间隔的字线以及至少一个源极线，其中，各所述开关包括第一端、第二端和控制端，所述开关的控制端与所述字线电连接，所述开关的第二端与所述源极线电连接，所述开关的第一端与所述存储单元的第二端电连接。
  2. 根据权利要求1所述的存储器，其特征在于，在各所述存储层中，同一列的所述存储单元的第二端与同一个所述开关的第一端电连接，且任意两列的所述存储单元对应连接的所述开关不同，所述开关的控制端与所述字线一一对应连接。
  3. 根据权利要求2所述的存储器，其特征在于，每个所述存储层的所述开关单元中，所述源极线有一个。
  4. 根据权利要求2所述的存储器，其特征在于，各所述存储层相同，且各所述存储层的中心点的连线平行于所述第一方向。
  5. 根据权利要求4所述的存储器，其特征在于，多个所述存储层中位置对应的所述字线电连接形成一个字线总线，所述存储器中的所述字线总线的个数与各所述存储层中的存储单元的列数相同。
  6. 根据权利要求1至5中任一项所述的存储器，其特征在于，所述开关为晶体管，所述开关的第一端为所述晶体管的源极，所述开关的第二端与所述晶体管的漏极，所述开关的控制端为所述晶体管的栅极。
  7. 根据权利要求1至5中任一项所述的存储器，其特征在于，所述存储单元包括存储位元和与所述存储位元串联的选择器，所述存储位元远离所述选择器的一端为所述存储单元的第一端，所述选择器的远离所述存储位元的一端为所述存储单元的第二端。
  8. 根据权利要求7所述的存储器，其特征在于，所述存储位元为MTJ，所述选择器为双向导通开关。
  9. 一种权利要求1至8中任一项所述的存储器的读写方法，其特征在于，所述读写方法包括写过程，所述写过程包括第一写入过程，所述第一写入过程包括：
    对选中的字线施加第一电压，使得与选中的所述字线电连接的开关导通；
    对选中的位线施加第二电压，所述第二电压用于将存储单元写为第一状态；
    对未选中的所述位线不施加任何电压。
  10. 根据权利要求9所述的读写方法，其特征在于，所述存储器的一个存储层中包括一个源极线，且一个所述存储层中的所述源极线与各所述开关的第二端电连接，所述存储层的存储单元包括存储位元和与所述存储位元串联的选择器，所述写过程还包括第二写入过程，所述第二写入过程包括：
    对选中的所述字线施加第一电压，使得与选中的所述字线电连接的所述开关导通；
    对所述源极线施加第三电压，所述第三电压大于所述选择器的开启电压；
    对选中的所述位线施加0V，将所述存储位元写为第二状态，所述存储位元在所述第一状态对应的电阻大于在所述第二状态对应的电阻；
    对未选中的所述位线不施加任何电压。
  11. 根据权利要求9或10所述的读写方法，其特征在于，所述存储层的存储单元包括存储位元和与所述存储位元串联的选择器，所述读写方法还包括读出过程，所述读出过程包括：
    对选中的所述字线施加所述第一电压，使得与选中的所述字线电连接的所述开关导通；
    对选中的位线施加第四电压，所述第四电压大于所述选择器的开启电压且小于所述第二电压；
    对未选中的所述位线不施加任何电压。
PCT/CN2019/130601 2019-08-08 2019-12-31 存储器与其读写方法 WO2021022782A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910731330.0 2019-08-08
CN201910731330.0A CN112349311B (zh) 2019-08-08 2019-08-08 存储器与其读写方法

Publications (1)

Publication Number Publication Date
WO2021022782A1 true WO2021022782A1 (zh) 2021-02-11

Family

ID=74366796

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/130601 WO2021022782A1 (zh) 2019-08-08 2019-12-31 存储器与其读写方法

Country Status (2)

Country Link
CN (1) CN112349311B (zh)
WO (1) WO2021022782A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117012250A (zh) * 2022-04-28 2023-11-07 华为技术有限公司 存储芯片、存储装置和电子设备
CN118119176A (zh) * 2022-11-30 2024-05-31 华为技术有限公司 一种存储阵列、存储器及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120281465A1 (en) * 2011-04-07 2012-11-08 Agan Tom A High Density Magnetic Random Access Memory
CN103633108A (zh) * 2012-08-23 2014-03-12 爱思开海力士有限公司 三维层叠存储器件
CN107086202A (zh) * 2016-02-14 2017-08-22 复旦大学 一种可抑制三维水平交叉点式电阻转换存储器漏电流的集成结构
CN107112041A (zh) * 2014-10-26 2017-08-29 Neo半导体公司 用于提供三维非挥发性集成存储器和动态随机存取存储器的方法与设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102314927B (zh) * 2010-07-06 2014-02-05 中国科学院物理研究所 一种磁性随机存储单元阵列、存储器及其读写方法
CN109859784A (zh) * 2017-11-30 2019-06-07 上海磁宇信息科技有限公司 一种mram芯片的阵列结构
CN109873010A (zh) * 2017-12-04 2019-06-11 中电海康集团有限公司 Stt-mram存储器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120281465A1 (en) * 2011-04-07 2012-11-08 Agan Tom A High Density Magnetic Random Access Memory
CN103633108A (zh) * 2012-08-23 2014-03-12 爱思开海力士有限公司 三维层叠存储器件
CN107112041A (zh) * 2014-10-26 2017-08-29 Neo半导体公司 用于提供三维非挥发性集成存储器和动态随机存取存储器的方法与设备
CN107086202A (zh) * 2016-02-14 2017-08-22 复旦大学 一种可抑制三维水平交叉点式电阻转换存储器漏电流的集成结构

Also Published As

Publication number Publication date
CN112349311A (zh) 2021-02-09
CN112349311B (zh) 2023-01-31

Similar Documents

Publication Publication Date Title
US10510773B2 (en) Apparatuses having a ferroelectric field-effect transistor memory array and related method
US9251860B2 (en) Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
KR102106726B1 (ko) 3차원 메모리 장치 및 사용 방법
US9036419B2 (en) 3D stacked NAND flash memory array having SSL status check buildings for monitoring threshold voltages of string selection transistors and methods for monitoring and operating the same
CN107810534B (zh) 操作具有抹除去偏压的存储器的设备及方法
US9165628B2 (en) Semiconductor memory device
JP2016167332A (ja) 記憶装置
TW201347146A (zh) 半導體記憶裝置
US9905611B2 (en) Variable resistance memory
JP2013200929A (ja) 半導体記憶装置
CN103715197A (zh) 具有单位单元作为单一器件的存储器件及其制造方法
WO2021022782A1 (zh) 存储器与其读写方法
JP2013200930A (ja) 半導体記憶装置
US11744088B2 (en) Memory device
US11152037B2 (en) Semiconductor memory device
CN112151089B (zh) 存储器
US10056128B2 (en) Semiconductor storage device
US20140313809A1 (en) Semiconductor apparatus
US9214495B1 (en) Memory cell structure and formation method thereof
WO2020189147A1 (ja) 半導体回路および電子機器
US9941331B1 (en) Device with sub-minimum pitch and method of making

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19940422

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19940422

Country of ref document: EP

Kind code of ref document: A1