WO2021017493A1 - 发光二极管芯片阵列及其制作方法和显示面板 - Google Patents

发光二极管芯片阵列及其制作方法和显示面板 Download PDF

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Publication number
WO2021017493A1
WO2021017493A1 PCT/CN2020/080661 CN2020080661W WO2021017493A1 WO 2021017493 A1 WO2021017493 A1 WO 2021017493A1 CN 2020080661 W CN2020080661 W CN 2020080661W WO 2021017493 A1 WO2021017493 A1 WO 2021017493A1
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Prior art keywords
emitting diode
light emitting
light
chip array
diode chip
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PCT/CN2020/080661
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English (en)
French (fr)
Inventor
郭恩卿
王程功
田文亚
盖翠丽
李之升
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成都辰显光电有限公司
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Priority to KR1020227002705A priority Critical patent/KR20220027178A/ko
Publication of WO2021017493A1 publication Critical patent/WO2021017493A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes

Definitions

  • This application relates to the field of display technology, for example, to a light-emitting diode chip array, a manufacturing method thereof, and a display panel.
  • the Micro Light Emitting Diode (micro-LED/ ⁇ LED) display panel integrates Light Emitting Diode (LED) chips with a size of less than 100 microns on a substrate as display pixels to realize image display. Each display pixel can be addressed and individually driven to light up, so the Micro-LED display panel is a self-luminous display panel.
  • LED Light Emitting Diode
  • the Micro-LED display panel includes an LED chip array and a driving backplane. Since the number of pixels (Pixels Per Inch, PPI) of the Micro-LED display panel is very high, the display pixels are usually small and the distance between adjacent LED chips is small. Therefore, the related LED chip array and the driving backplane are bonded (bonding). ), there is a problem that the electrodes between adjacent LED chips are prone to short-circuit.
  • PPI Pixel Per Inch
  • the present application provides a light-emitting diode chip array, a manufacturing method thereof, and a display panel, so as to avoid short circuit of electrodes between adjacent LED chips.
  • a light emitting diode chip array comprising: a substrate; a plurality of light emitting diode chips located on the substrate, the light emitting diode chip includes a light emitting diode epitaxial structure on the substrate and a light emitting diode epitaxial structure
  • the present application also provides a display panel, including: a driving backplane and the light-emitting diode chip array according to any embodiment of the present application; the driving backplane is bonded to the light-emitting diode chip array.
  • the present application further provides a method for manufacturing a light emitting diode chip array, including the following steps: providing an epitaxial wafer, the epitaxial wafer including a substrate and a semiconductor film layer grown on the substrate; etching the semiconductor film layer, Forming a plurality of light emitting diode epitaxial structures; fabricating a first electrode on the mesa of the light emitting diode epitaxial structure to form a plurality of light emitting diode chips; fabricating solder joints on the first electrode.
  • an isolation wall is arranged between the light-emitting diodes and a trench is formed between the isolation wall and the light-emitting diode.
  • the structure of the isolation wall and the trench can prevent the solder of the solder joint from expanding into the adjacent trench during the bonding process (Outside the separation wall), thereby blocking the lateral expansion of the solder, which is beneficial to prevent the short connection of the solder between adjacent solder joints.
  • the present application achieves the effect of avoiding the short circuit of the electrodes between adjacent LED chips and improves the yield of bonding; and the light-emitting diode chip array provided by the present application has a simple structure, simple and easy process, which is beneficial to improve the light-emitting diode The process feasibility of the chip array and the reliability of the display panel.
  • FIG. 1 is a schematic diagram of a top view structure of a light emitting diode chip array provided by an embodiment of the application;
  • Figure 2 is a schematic view of the cross-sectional structure along A-A in Figure 1;
  • FIG. 3 is a schematic flowchart of a method for manufacturing a light-emitting diode chip array provided by an embodiment of the application;
  • FIG. 4 is a schematic flowchart of another method for manufacturing a light-emitting diode chip array provided by an embodiment of the application;
  • FIG. 5 is a schematic structural diagram of another light-emitting diode chip array provided by an embodiment of the application.
  • FIG. 6 is a schematic flowchart of another method for manufacturing a light-emitting diode chip array provided by an embodiment of the application;
  • FIG. 7 is a schematic structural diagram of another light-emitting diode chip array provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of another light emitting diode chip array provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of yet another light-emitting diode chip array provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of another light emitting diode chip array provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • FIG. 12 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of another display panel provided by an embodiment of the application.
  • FIG. 14 is a schematic flowchart of another method for manufacturing a display panel according to an embodiment of the application.
  • 15-19 are schematic diagrams of the structure of a display panel formed in each step of a method for manufacturing a display panel according to an embodiment of the application.
  • FIG. 1 is a schematic diagram of a top view structure of a light emitting diode chip array provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a cross-sectional structure along A-A in FIG. 1.
  • the LED chip array includes: a substrate 10, a plurality of LED chips 20, an isolation wall 30 and solder joints 40.
  • a plurality of light-emitting diode chips 20 and an isolation wall 30 are located on the substrate 10, the isolation wall 30 is located between two adjacent light-emitting diode chips, and a trench 50 is formed between the isolation wall 30 and the light-emitting diode chip 20.
  • the light emitting diode chip 20 includes a first electrode 21, and the solder joint 40 is located on the first electrode 21.
  • the structure of the light emitting diode chip (hereinafter referred to as the LED chip) 20 may include, for example, a first electrode 21 and an LED epitaxial structure.
  • the LED epitaxial structure includes a first semiconductor layer 24, a multiple quantum well layer 23, and a first semiconductor layer 24 epitaxially grown sequentially from the substrate 10
  • the second semiconductor layer 22 The first semiconductor layer 24 may be n-GaN, and the second semiconductor layer 22 may be p-GaN.
  • the first semiconductor layer 24 may be, for example, a common layer of a plurality of LED chips 20, thereby facilitating the connection of the second electrode of the LED chip 20 to the common electrode.
  • the LED epitaxial structure may further include, for example, a buffer layer, which is located between the first semiconductor layer 24 and the substrate 10 to facilitate the lattice matching of the first semiconductor layer 24 and the substrate 10.
  • a buffer layer which is located between the first semiconductor layer 24 and the substrate 10 to facilitate the lattice matching of the first semiconductor layer 24 and the substrate 10.
  • the surface of the first electrode 21 has solder joints 40, and the solder joints 40 are arranged to bond the LED chip array and the driving backplane.
  • the solder of the solder joint 40 may be, for example, a low-temperature solder containing indium (In) or tin (Sn). The solder is relatively soft during bonding, which facilitates the bonding of the solder joint 40 and the driving backplane.
  • a trench 50 is formed between the isolation wall 30 and the LED chip 20, that is, there is at least one isolation wall 30 and two trenches 50 between adjacent LED chips 20.
  • the structure of the isolation wall 30 and the trench 50 can be in the bonding process
  • the solder of the blocking solder joint 40 is expanded to contact with the solder of the adjacent solder joint 40. This arrangement effectively prevents the lateral expansion of the solder and prevents the short connection of the solder between the adjacent solder joints 40.
  • the material of the isolation wall 30 may be the same material as the LED epitaxial structure, or other materials different from the LED epitaxial structure. If the material of the isolation wall 30 is the same as the material of the LED epitaxial structure, the LED epitaxial structure and the isolation wall 30 can be formed at the same time through a patterned etching process, which is beneficial to simplify the process. If the separation wall 30 is made separately, the height of the separation wall 30 can be set as required. Based on this, there may be multiple manufacturing methods for implementing the LED chip array provided by the embodiments of the present application. Two of them are described below, but they are not intended to limit the present application.
  • FIG. 3 is a schematic flowchart of a manufacturing method of a light-emitting diode chip array provided by an embodiment of the application.
  • the manufacturing method of the light emitting diode chip array includes the following steps.
  • S110 Provide an epitaxial wafer, which includes a substrate 10 and a semiconductor film layer grown on the substrate 10;
  • FIG. 4 is a schematic flowchart of another method for manufacturing a light-emitting diode chip array according to an embodiment of the application; referring to FIG. 4, exemplary, the method for manufacturing a light-emitting diode chip array includes the following steps:
  • S210 Provide an epitaxial wafer, which includes a substrate 10 and a semiconductor film layer grown on the substrate 10;
  • an isolation wall 30 is provided between the LED chips 20 and a trench 50 is formed between the isolation wall 30 and the LED chip 20.
  • the structure of the isolation wall 30 and the trench 50 can block the solder of the solder joint 40 during the bonding process. Extending to contact with the solder of the adjacent solder joint 40, the arrangement of the groove 50 prevents the lateral expansion of the solder, which is beneficial to prevent the short connection of the solder between the adjacent solder joints 40. Therefore, the present application achieves the effect of avoiding the short circuit of the electrodes between adjacent LED chips, and improves the yield of bonding; and the LED chip array provided by the present application has a simple structure and simple process, which is beneficial to improve the LED chip array. Process feasibility and reliability of the display panel.
  • FIG. 5 is a schematic structural diagram of another light-emitting diode chip array provided by an embodiment of the application.
  • multiple LED chips 20 are independent of each other.
  • the plurality of LED chips 20 being independent of each other means that there is no common layer between the plurality of LED chips 20 and they are sufficiently isolated.
  • the LED epitaxial structure includes the first semiconductor layer 24, the multiple quantum well layer 23, and the second semiconductor layer 22, the first semiconductor layers 24 of the multiple LED chips 20 are not connected, and the multiple LED chips 20 The second semiconductor layer 22 is not connected.
  • FIG. 6 is a schematic flowchart of another method for manufacturing a light emitting diode chip array provided by an embodiment of the application. Referring to FIG. 6, illustratively, the manufacturing method of the light-emitting diode chip array includes the following steps.
  • S310 Provide an epitaxial wafer, which includes a substrate 10 and a semiconductor film layer grown on the substrate 10;
  • the semiconductor film layer is etched, and the etched part of the semiconductor film layer exposes the substrate 10 to form multiple LED epitaxial structures and isolation walls 30;
  • the semiconductor film layer includes a first semiconductor layer 24, a multiple quantum well layer 23, and a second semiconductor layer 22 that are epitaxially grown from a substrate in sequence.
  • the etched part of the semiconductor film layer exposes the substrate, that is, the semiconductor film layer is deeply etched, and the semiconductor film layer is etched to stop at the substrate 10, so that the second semiconductor layers 22 of the multiple LED chips are not connected , And the first semiconductor layer 24 of the plurality of LED chips is disconnected, sufficiently isolating the plurality of LED chips 20;
  • a plurality of LED chips 20 are arranged independently of each other, so that the depth of the first groove 50 between adjacent LED chips 20 is larger, which is beneficial to the first groove 50 to accommodate more squeezed during the bonding process.
  • the solder of the solder joint 40 is beneficial to prevent short-circuit of the solder between adjacent solder joints 40 and to avoid short-circuit of the electrodes between adjacent LED chips.
  • FIG. 7 is a schematic structural diagram of yet another light emitting diode chip array provided by an embodiment of the application.
  • a first insulating layer 60 is further included.
  • the first insulating layer 60 is located on a side of the LED chip 20 away from the substrate 10; the first insulating layer 60 includes a first opening, and the first opening exposes the first electrode 21.
  • the first insulating layer 60 can be arranged in many ways.
  • the first insulating layer 60 may only cover the sidewall of the LED chip 20, thereby reducing the leakage current of the LED chip 20.
  • the first insulating layer 60 can also cover the sidewalls of the LED chip 20, cover the mesa and sidewalls of the isolation wall 30, and cover the trench 50, which can be set as required in practical applications.
  • a first insulating layer 60 is provided on the sidewall of the LED chip 20, which helps to match the surface lattice of each film layer of the LED chip 20, such as dangling bonds.
  • the dangling bonds on the surface of the film layer will cause leakage of the LED chip 20, thereby reducing
  • the surface lattice defects reduce the leakage current of the LED chip 20; and the arrangement of the first insulating layer 60 can prevent particles in the air from attaching to the side wall of the LED chip 20 and cause the LED chip 20 to short circuit, thereby helping to avoid the occurrence of the LED chip 20 Short circuit.
  • FIG. 8 is a schematic structural diagram of another light emitting diode chip array provided by an embodiment of the application.
  • the LED chip array further includes a reflective layer 70.
  • the LED chip 20 includes a mesa and a side wall, and the reflective layer 70 is located on the surface of the first insulating layer 60 on the side wall of the LED chip 20. Wherein, the sidewall of the LED chip 20 is also the sidewall of the trench 50.
  • the reflective layer 70 located on the sidewall of the LED chip 20 can block the light emitted by the LED chip 20 from being emitted to the adjacent LED chip 20, reducing the light crosstalk between the LED chips 20, that is, reducing the light crosstalk between pixels.
  • the reflective layer 70 reflects the light emitted from the LED chip 20 to the reflective layer 70, avoids the light from being emitted from the side wall of the LED chip 20, and helps to emit the light from the LED chip 20 more from the light-emitting surface, thereby improving the LED The light output efficiency of the chip 20.
  • a plurality of LED chips 20 are independent of each other, and the reflective layer 70 is located on the surface of the first insulating layer 60 on the sidewall of the LED chip 20.
  • the LED chips 20 are sufficiently isolated by etching and the reflective layer 70 is made, so that the length of the reflective layer 70 is longer and can cover more area of the side wall of the LED chip 20, thereby further reducing the light between the LED chips 20.
  • Crosstalk which reduces the optical crosstalk between pixels.
  • FIG. 9 is a schematic structural diagram of another light-emitting diode chip array provided by an embodiment of the application. 9, on the basis of the foregoing embodiments, optionally, the LED chip 20 includes a mesa and sidewalls.
  • the mesa and sidewalls of the LED chip 20 may be the mesa and sidewalls of the above-mentioned LED epitaxial structure;
  • An electrode 21 covers the mesa and covers the part of the first insulating layer 60 on the side wall.
  • the first electrode 21 is provided to cover the mesa and the part of the first insulating layer 60 on the sidewall, which is equivalent to combining the reflective layer with the first electrode 21.
  • the first electrode 21 also serves as a reflective layer, so the first electrode 21 serves as an electrode. On the basis of the function, it can also block the light emitted by the LED chip 20 from emitting to the adjacent LED chip 20, reduce the light crosstalk between the LED chips 20, and can prevent the light from emitting from the side wall of the LED chip 20, which is beneficial to the LED The light emitted by the chip 20 is more emitted from the light-emitting surface, thereby improving the light-emitting efficiency of the LED chip 20. In addition, compared with the production of the first electrode and the reflective layer separately, the present application reduces the production process of the reflective layer, thereby simplifying the process steps.
  • the solder joint 40 covers the first electrode 21, that is, the solder joint 40 extends to the side wall under the mesa of the LED chip 20, increasing the solder joint 40 In the bonding process, the first electrode 21 and the driving back plate can be firmly welded, thereby helping to improve the yield of the bonding.
  • the shape of the surface of the solder joint 40 includes at least one of a hemispherical shape, a circular pie shape, or a square pie shape.
  • the solder joint 40 has a hemispherical shape, and setting the solder joint 40 into a hemispherical shape is beneficial to improve the wettability of the solder joint 40 and the metal layer.
  • FIG. 10 is a schematic structural diagram of another light-emitting diode chip array provided by an embodiment of the application.
  • the LED chip array further includes a support 80, and the support 80 is located on the side of the partition wall 30 away from the substrate 10.
  • the support member 80 may specifically be a support column, and the height of the support member 80 can be adjusted according to the thickness of the first electrode 21 and the thickness of the solder joint 40, so as to adjust the height of the partition wall 30 to limit the solder joint during the bonding process. 40 is squeezed, so as to help avoid excessive solder lateral expansion.
  • an isolation wall 30 and two trenches 50 are included between adjacent LED chips 20, which is not a limitation of the present application.
  • a plurality of isolation walls 30 and a plurality of trenches 50 between the isolation wall 30 and the isolation wall 30, and between the isolation wall 30 and the LED chip 20 may be provided to further prevent the lateral expansion of the solder.
  • the number of isolation walls 30 and trenches 50 can be set as required.
  • the structure of the LED chip array shown in the above embodiment is the structure before bonding with the driving backplane.
  • the first electrode is described.
  • the LED chip array includes the second electrode, and the common electrode that forms an LED chip array can also be fabricated after the bonding is completed, and it can be set as required in actual applications.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes: a driving backplane 2 and a light-emitting diode chip array 1 as provided in any embodiment of the present application.
  • the driving backplane 2 and the light emitting diode chip array 1 are bonded.
  • the driving backplane 2 includes a plurality of bonding pads 201, and the bonding pads 201 are soldered to the solder joints 40 of the LED chip array 1.
  • the display panel includes the light-emitting diode chip array 1 provided by any embodiment of the present application, and its technical principles and technical effects are similar, and will not be repeated here.
  • the display panel further includes: a second insulating layer 3 and a second electrode 4, the second insulating layer 3 is located on the side of the LED chip 20 away from the driving backplane 2; the second insulating layer 3 includes There are a plurality of second openings 301, and the second openings 301 are located on the surface of the LED chip 20 away from the driving backplane 2.
  • the second electrode 4 is located on the side of the second insulating layer 3 away from the driving backplane 2, and the second electrode 4 is electrically connected to the plurality of LED chips 20 through the second opening 301.
  • the second electrode 4 is the common electrode of the LED chip 20.
  • FIG. 12 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the application. Referring to FIG. 12, illustratively, the manufacturing method of the display panel includes the following steps:
  • the light emitting diode chip array 1 includes: a substrate 10, a plurality of LED chips 20, an isolation wall 30 and solder joints 40.
  • a plurality of LED chips 20 are located on the substrate 10 and the LED chips 20 include first electrodes 21.
  • a trench 50 is formed between the isolation wall 30 and the LED chip 20.
  • the solder joint 40 is located on the first electrode 21.
  • the driving backplane 2 may be, for example, a silicon-based CMOS backplane.
  • the bonding method of the light emitting diode chip array 1 and the driving backplane 2 may be flip-chip bonding, for example.
  • the substrate 10 is a sapphire substrate
  • the sapphire substrate can be removed by laser lift-off.
  • the substrate 10 is a silicon substrate
  • the silicon substrate can be removed by wet etching.
  • the second opening 301 is located on the surface of the LED chip 20 away from the driving backplane 2, and the first semiconductor layer 24 of the LED chip 20 is exposed in the second opening 301;
  • the second electrode 4 may be metal, for example, and the production of the second electrode 4 may be, for example, metal wiring.
  • the second electrode 4 is connected to the first semiconductor layer 24 of a plurality of LED chips 20 to form a grid-shaped common electrode to enhance the light output. effectiveness.
  • FIG. 13 is a schematic structural diagram of another display panel provided by an embodiment of the application.
  • the display panel further includes an underfill layer 5, and the underfill layer 5 is located between the groove and the driving backplane 2.
  • FIGS. 14-19 are schematic diagrams of a display panel formed in each step of the method for manufacturing a display panel provided by an embodiment of the application.
  • the manufacturing method of the display panel includes the following steps.
  • the bonding method of the LED chip array 1 and the driving backplane 2 adopts flip-chip bonding.
  • the driving backplane 2 includes a plurality of pads 201, and the pads 201 are soldered to the solder joints 40 of the LED chip array 1.
  • an underfill layer 5 is filled and cured between the LED chip array 1 and the driving backplane 2 to strengthen the bonding strength.
  • the substrate is a sapphire substrate
  • the sapphire substrate can be removed by laser lift-off.
  • the substrate is a silicon substrate
  • the silicon substrate can be removed by wet etching.
  • a second insulating layer 3 is fabricated on the side of the LED chip array 1 away from the driving backplane 2.
  • the second insulating layer 3 includes a plurality of second openings 301, and the second openings 301 are located at the LED chip 20 away from the driving On the surface of one side of the back plate 2, the first semiconductor layer 24 of the LED chip 20 is exposed in the second opening 301.
  • S560 Fabricate a second electrode 4 on the side of the second insulating layer 3 away from the driving backplane 1; the second electrode 4 is electrically connected to the plurality of LED chips 20 through the second opening 301.
  • a second electrode 4 is fabricated on the side of the second insulating layer 3 away from the driving backplane 2; the second electrode 4 is electrically connected to a plurality of LED chips 20 through the second opening 301.
  • the second electrode 4 can be metal, for example, and the second electrode 4 can be made of metal wiring.
  • the second electrode 4 is connected to the first semiconductor layer 24 of a plurality of LED chips 20 to form a grid-shaped common electrode to improve light efficiency.
  • the underfill layer 5 is arranged between the groove 50 and the driving back plate 2 to strengthen the bonding strength, which is beneficial to improve the yield and service life of the display panel.

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Abstract

本申请公开了一种发光二极管芯片阵列及其制作方法和显示面板。该发光二极管芯片阵列，包括：衬底；位于所述衬底上的多个发光二极管，所述发光二极管包括位于所述衬底上的发光二极管外延结构和位于所述发光二极管外延结构远离所述衬底一侧的台面上的第一电极；至少一个隔离墙，所述至少一个隔离墙位于所述衬底上相邻的两个发光二极管芯片之间，所述隔离墙和所述发光二极管之间形成沟槽；以及焊点，位于所述第一电极上。

Description

发光二极管芯片阵列及其制作方法和显示面板
本申请要求在2019年07月31日提交中国专利局、申请号为201910702462.0的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种发光二极管芯片阵列及其制作方法和显示面板。
背景技术
微发光二极管(Micro Light Emitting Diode，micro-LED/μLED)显示面板将一个基板上集成百微米以下尺寸的发光二极管(Light Emitting Diode，LED)芯片作为显示像素，实现图像显示。每一个显示像素可定址和单独驱动点亮，因此Micro-LED显示面板属于自发光型显示面板。
在相关技术中，Micro-LED显示面板包括LED芯片阵列和驱动背板。由于Micro-LED显示面板的像素数目(Pixels Per Inch，PPI)要求很高，显示像素通常很小，相邻LED芯片的间距很小，因此，相关的LED芯片阵列与驱动背板邦定(bonding)时，存在相邻LED芯片之间的电极容易发生短路的问题。
发明内容
本申请提供一种发光二极管芯片阵列及其制作方法和显示面板，以避免相邻LED芯片之间的电极短路。
一种发光二极管芯片阵列，包括：衬底；位于所述衬底上的多个发光二极管芯片，所述发光二极管芯片包括位于所述衬底上的发光二极管外延结构和位于所述发光二极管外延结构远离所述衬底一侧的台面上的第一电极；至少一个隔离墙，所述至少一个隔离墙位于所述衬底上相邻的两个发光二极管芯片之 间，所述隔离墙和所述发光二极管芯片之间形成沟槽；以及焊点，位于所述第一电极上。
本申请还提供了一种显示面板，包括：驱动背板和如本申请任意实施例所述的发光二极管芯片阵列；所述驱动背板与所述发光二极管芯片阵列邦定。
本申请又提供了一种发光二极管芯片阵列的制作方法，包括以下步骤：提供外延片，所述外延片包括衬底和生长于所述衬底的半导体膜层；刻蚀所述半导体膜层，形成多个发光二极管外延结构；在所述发光二极管外延结构的台面上制作第一电极，形成多个发光二极管芯片；在所述第一电极上制作焊点。
本申请通过在发光二极管之间设置隔离墙，以及隔离墙和发光二极管之间形成沟槽，隔离墙和沟槽的结构能够在邦定过程中阻挡焊点的焊料扩张至相邻的沟槽内(隔离墙之外)，从而阻挡了焊料的横向扩张，有利于防止相邻焊点间焊料的短接。因此，本申请实现了避免相邻LED芯片之间的电极短路的效果，提升了邦定的良率；以及本申请提供的发光二极管芯片阵列的结构简单，工艺简单易行，有利于提高发光二极管芯片阵列的工艺可行性及显示面板的可靠性。
附图说明
图1为本申请实施例提供的一种发光二极管芯片阵列的俯视结构示意图；
图2为沿图1中A-A的剖面结构示意图；
图3为本申请实施例提供的一种发光二极管芯片阵列的制作方法的流程示意图；
图4为本申请实施例提供的另一种发光二极管芯片阵列的制作方法的流程示意图；
图5为本申请实施例提供的另一种发光二极管芯片阵列的结构示意图；
图6为本申请实施例提供的又一种发光二极管芯片阵列的制作方法的流程示意图；
图7为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图；
图8为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图；
图9为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图；
图10为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图；
图11为本申请实施例提供的一种显示面板的结构示意图；
图12为本申请实施例提供的一种显示面板的制作方法的流程示意图；
图13为本申请实施例提供的另一种显示面板的结构示意图；
图14为本申请实施例提供的另一种显示面板的制作方法的流程示意图；
图15-图19为本申请实施例提供的一种显示面板的制作方法各步骤形成的显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
图1为本申请实施例提供的一种发光二极管芯片阵列的俯视结构示意图，图2为沿图1中A-A的剖面结构示意图。参见图1和图2，该发光二极管芯片阵列包括：衬底10、多个发光二极管芯片20、隔离墙30和焊点40。多个发光二极管芯片20和隔离墙30位于衬底10上，隔离墙30位于相邻的两个发光二极管芯片之间，隔离墙30和发光二极管芯片20之间形成沟槽50。发光二极管芯片20包括第一电极21，焊点40位于第一电极21上。
其中，发光二极管芯片(以下简称LED芯片)20的结构例如可以包括第一电极21和LED外延结构，LED外延结构包括由衬底10依次外延生长的第一半导体层24、多量子阱层23和第二半导体层22。所述第一半导体层24可以为n-GaN，所述第二半导体层22可以为p-GaN。
第一半导体层24例如可以是多个LED芯片20的共通层，从而有利于LED芯片20的第二电极连接公共电极。
LED外延结构例如还可以包括缓冲层，缓冲层位于第一半导体层24和衬底10之间，有利于第一半导体层24和衬底10的晶格匹配。
第一电极21的表面具有焊点40，焊点40被设置为将发光二极管芯片阵列与驱动背板的邦定(bonding)。焊点40的焊料例如可以是含铟(In)或锡(Sn)的低温焊料，在邦定时该焊料比较柔软，有利于焊点40与驱动背板的邦定。
隔离墙30和LED芯片20之间形成沟槽50，即相邻LED芯片20之间至少包括一隔离墙30和两个沟槽50，隔离墙30和沟槽50的结构能够在邦定过程中阻挡焊点40的焊料扩展至与相邻焊点40的焊料相接触，此种设置方式，有效阻挡了焊料的横向扩张，防止相邻焊点40间焊料的短接。
隔离墙30的材料例如可以是与LED外延结构相同的材料，也可以是与LED外延结构不同的其他材料。若隔离墙30的材料与LED外延结构的材料相同，则通过图形化刻蚀工艺可以同时形成LED外延结构与隔离墙30，从而有利于简化工艺。若隔离墙30单独制作，则可以根据需要设置隔离墙30的高度。基于此，实现本申请实施例所提供的LED芯片阵列的制作方法可以有多种，下面就其中两种进行说明，但不作为对本申请的限定。
图3为本申请实施例提供的一种发光二极管芯片阵列的制作方法的流程示意图。参见图3，示例性地，该发光二极管芯片阵列的制作方法包括以下步骤。
S110、提供外延片，外延片包括衬底10和生长于衬底10的半导体膜层；
S120、刻蚀半导体膜层，形成多个LED外延结构和隔离墙30；
S130、在LED外延结构的台面上制作第一电极21，形成多个LED芯片20，隔离墙30和LED芯片之间形成沟槽50；
S140、在第一电极21上制作焊点40。
图4为本申请实施例提供的另一种发光二极管芯片阵列的制作方法的流程示意图；参见图4，示例性地，该发光二极管芯片阵列的制作方法包括以下步骤：
S210、提供外延片，外延片包括衬底10和生长于衬底10的半导体膜层；
S220、刻蚀半导体膜层，形成多个LED外延结构；
S230、在相邻LED外延结构之间制作隔离墙30，隔离墙30与LED外延结构之间形成沟槽50；
S240、在LED外延结构的台面上制作第一电极21，形成多个LED芯片20，隔离墙30和LED芯片之间形成沟槽50；
S250、在第一电极21上制作焊点40。
本申请通过在LED芯片20之间设置隔离墙30，以及隔离墙30和LED芯片20之间形成沟槽50，隔离墙30和沟槽50的结构能够在邦定过程中阻挡焊点40的焊料扩展至与相邻焊点40的焊料相接触，沟槽50的设置阻挡了焊料的横向扩张，有利于防止相邻焊点40间焊料的短接。因此，本申请实现了避免相邻LED芯片之间的电极短路的效果，提升了邦定的良率；以及本申请提供的LED芯片阵列的结构简单，工艺简单易行，有利于提高LED芯片阵列的工艺可行性及显示面板的可靠性。
图5为本申请实施例提供的另一种发光二极管芯片阵列的结构示意图。参见图5，在上述各实施例的基础上，可选地，多个LED芯片20相互独立。多个LED芯片20相互独立是指，多个LED芯片20之间没有共通层，充分隔离。示例性地，若LED外延结构包括第一半导体层24、多量子阱层23和第二半导体层22，多个LED芯片20的第一半导体层24之间不联通，以及多个LED芯片20的第二半导体层22不联通。
实现本申请所提供的LED芯片阵列的制作方法可以有多种。图6为本申请实施例提供的又一种发光二极管芯片阵列的制作方法的流程示意图。参见图6，示例性地，该发光二极管芯片阵列的制作方法包括以下步骤。
S310、提供外延片，外延片包括衬底10和生长于衬底10的半导体膜层；
S320、刻蚀半导体膜层，半导体膜层中被刻蚀掉的部分露出衬底10，形成多个LED外延结构和隔离墙30；
其中，示例性地，半导体膜层包括由衬底依次外延生长的第一半导体层24、多量子阱层23和第二半导体层22。半导体膜层中被刻蚀掉的部分露出衬底，即对半导体膜层进行深刻蚀，刻蚀半导体膜层停止在衬底10，以使多个LED芯片的第二半导体层22之间不联通，以及多个LED芯片的第一半导体层 24不联通，充分隔离多个LED芯片20；
S330、在LED外延结构的台面上制作第一电极21，形成多个LED芯片20，隔离墙30和LED芯片20之间形成沟槽50；
S340、在第一电极21上制作焊点40。
本申请设置多个LED芯片20相互独立，以使相邻LED芯片20之间的第一沟槽50的深度较大，有利于第一沟槽50在邦定过程中容纳更多的被挤压出的焊点40的焊料，有利于防止相邻焊点40间焊料的短接，以及避免相邻LED芯片之间的电极短路。
图7为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图。参见图7，在上述各实施例的基础上，可选地，还包括第一绝缘层60。第一绝缘层60位于LED芯片20远离衬底10的一侧；第一绝缘层60包括第一开孔，第一开孔暴露第一电极21。
其中，第一绝缘层60的设置方式有多种，例如，第一绝缘层60可以仅覆盖LED芯片20的侧壁，从而降低LED芯片20的漏电流。又如，第一绝缘层60还可以覆盖LED芯片20的侧壁，覆盖隔离墙30的台面和侧壁，以及覆盖沟槽50，在实际应用中可以根据需要设定。本申请在LED芯片20的侧壁设置第一绝缘层60，有助于匹配LED芯片20各膜层的表面晶格例如悬挂键，膜层表面的悬挂键会引起LED芯片20漏电，从而减少了表面晶格缺陷，降低了LED芯片20的漏电流；以及第一绝缘层60的设置可以防止空气中的粒子贴附在LED芯片20侧壁引起LED芯片20短路，从而有利于避免LED芯片20发生短路。
图8为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图。参见图8，在上述各实施例的基础上，可选地，LED芯片阵列还包括反射层70。LED芯片20包括台面和侧壁，反射层70位于LED芯片20侧壁上的第一绝缘层60的表面。其中，LED芯片20的侧壁也为沟槽50的侧壁。反射层70位于LED芯片20的侧壁可以阻挡LED芯片20发出的光线向相邻LED芯片20射出，减少了LED芯片20之间的光串扰，即减少了像素之间的光串扰。反射层70将LED芯片20发射至反射层70的光线进行反射，避免了光线从LED芯片20的侧壁射出，有利于将LED芯片20发出的光线更多地从出光面射出，从而提高 了LED芯片20的出光效率。
继续参见图8，可选地，多个LED芯片20相互独立，反射层70位于LED芯片20侧壁上的第一绝缘层60的表面。本申请通过刻蚀充分隔离LED芯片20，并制作反射层70，使得反射层70的长度更长，能够覆盖LED芯片20侧壁的更多的面积，从而进一步减少了LED芯片20之间的光串扰，即减少了像素之间的光串扰。
图9为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图。参见图9，在上述各实施例的基础上，可选地，LED芯片20包括台面和侧壁本实施例中LED芯片20的台面和侧壁可以为上述LED外延结构的台面和侧壁；第一电极21覆盖台面，以及覆盖第一绝缘层60位于侧壁上的部分。本申请设置第一电极21覆盖台面以及第一绝缘层60位于侧壁上的部分，相当于将反射层与第一电极21合并，第一电极21同时作为反射层，因此第一电极21作为电极作用的基础上，还能够阻挡LED芯片20发出的光线向相邻LED芯片20射出，减少了LED芯片20之间的光串扰，以及能够避免光线从LED芯片20的侧壁射出，有利于将LED芯片20发出的光线更多地从出光面射出，从而提高了LED芯片20的出光效率。另外，与第一电极和反射层分别制作相比，本申请减少了反射层的制作工艺，从而简化了工艺步骤。
继续参见图9，在上述各实施例的基础上，可选地，焊点40覆盖第一电极21，即焊点40扩展到LED芯片20的台面下的侧壁处，增大了焊点40的面积，在邦定工艺中，有利于第一电极21和驱动背板进行稳固的焊接，从而有利于提升邦定的良率。
在上述各实施例的基础上，可选地，焊点40表面的形状包括半球形、圆饼形或方饼形中的至少一种。本实施例中，焊点40呈半球状，将焊点40设置为半球形有利于提升焊点40与金属层浸润性。
图10为本申请实施例提供的又一种发光二极管芯片阵列的结构示意图。参见图10，在上述各实施例的基础上，可选地，发光二极管芯片阵列还包括支撑件80，支撑件80位于隔离墙30远离衬底10的一侧。其中，支撑件80具体可以为支撑柱，支撑件80的高度可以根据第一电极21的厚度和焊点40的厚度进行调整，从而调整隔离墙30的高度，以限制在邦定过程中焊点40受挤压的幅 度，从而有利于避免过多的焊料横向扩张。
需要说明的是，在上述实施例中示例性地示出了相邻LED芯片20之间包括一个隔离墙30和两个沟槽50，并非对本申请的限定。可选的，还可以设置多个隔离墙30、以及隔离墙30和隔离墙30之间、隔离墙30和LED芯片20之间的多个沟槽50，以进一步阻挡焊料的横向扩张。在实际应用中可以根据需要设置隔离墙30和沟槽50的数量。
还需要说明的是，在上述实施例中示出的LED芯片阵列的结构为与驱动背板邦定之前的结构，在上述实施中仅对第一电极进行了说明，可选的，还可以设置LED芯片阵列包括第二电极，也可以在完成邦定后再制作形成一个LED芯片阵列的公共电极，在实际应用中可以根据需要进行设定。
本申请还提供了一种显示面板。图11为本申请实施例提供的一种显示面板的结构示意图。参见图11，该显示面板包括：驱动背板2和如本申请任意实施例所提供的发光二极管芯片阵列1。驱动背板2与发光二极管芯片阵列1邦定。其中，驱动背板2包括多个焊盘201，焊盘201与发光二极管芯片阵列1的焊点40焊接。该显示面板包括本申请任意实施例所提供的发光二极管芯片阵列1，其技术原理和产生的技术效果类似，这里不再赘述。
继续参见图11，可选地，该显示面板还包括：第二绝缘层3和第二电极4，第二绝缘层3位于LED芯片20远离驱动背板2的一侧；第二绝缘层3包括多个第二开孔301，第二开孔301位于LED芯片20远离驱动背板2一侧的表面。第二电极4位于第二绝缘层3远离驱动背板2的一侧，第二电极4通过第二开孔301与多个LED芯片20电连接。其中，第二电极4为LED芯片20的公共电极。
实现本申请所提供的显示面板的制作方法可以有多种。图12为本申请实施例提供的一种显示面板的制作方法的流程示意图。参见图12，示例性地，该显示面板的制作方法包括以下步骤：
S410、提供发光二极管芯片阵列1和驱动背板2；
其中，发光二极管芯片阵列1包括：衬底10、多个LED芯片20、隔离墙30和焊点40。多个LED芯片20位于衬底10上，LED芯片20包括第一电极21。隔离墙30和LED芯片20之间形成沟槽50。焊点40位于第一电极21上。驱动 背板2例如可以是硅基CMOS背板。
S420、将发光二极管芯片阵列1与驱动背板邦定2；
其中，发光二极管芯片阵列1与驱动背板2的邦定方式例如可以是倒装焊(flip-chip bonding)。
S430、去除发光二极管芯片阵列的衬底10；
其中，若衬底10为蓝宝石衬底，则可以采用激光剥离将蓝宝石衬底去除。若衬底10为硅衬底，则可以采用湿法腐蚀将硅衬底去除。
S440、在发光二极管芯片阵列1远离驱动背板2的一侧制作第二绝缘层3，第二绝缘层3包括多个第二开孔301；
其中，第二开孔301位于LED芯片20远离驱动背板2一侧的表面，第二开孔301中暴露LED芯片20的第一半导体层24；
S450、在第二绝缘层3远离驱动背板2的一侧制作第二电极4；第二电极4通过第二开孔301与多个LED芯片20电连接。
其中，第二电极4例如可是金属，制作第二电极4例如可以是进行金属布线，第二电极4连接多个LED芯片20的第一半导体层24，形成网格状的公共电极，以提升出光效率。
图13为本申请实施例提供的另一种显示面板的结构示意图。参见图13，在上述各实施例的基础上，可选地，显示面板还包括底填胶层5，底填胶层5位于沟槽和驱动背板2之间。
实现本申请所提供的显示面板的制作方法可以有多种。图14为本申请实施例提供的另一种显示面板的制作方法的流程示意图，图15-图19为本申请实施例提供的一种显示面板的制作方法各步骤形成的显示面板的结构示意图。参见图14-图19，示例性地，该显示面板的制作方法包括以下步骤。
S510、提供发光二极管芯片阵列1和驱动背板2；
S520、将发光二极管芯片阵列1与驱动背板2邦定；
参见图15，发光二极管芯片阵列1与驱动背板2的邦定方式采用倒装焊(flip-chip bonding)。驱动背板2包括多个焊盘201，焊盘201与发光二极管芯 片阵列1的焊点40焊接。
S530、在发光二极管芯片阵列1和驱动背板2之间填充并固化底填胶层5；
参见图16，在发光二极管芯片阵列1和驱动背板2之间填充并固化底填胶层5，以加强邦定的强度。
S540、去除发光二极管芯片阵列1的衬底10；
继续参见图16，去除发光二极管芯片阵列的衬底10，去除衬底后参见图17。若衬底为蓝宝石衬底，则可以采用激光剥离将蓝宝石衬底去除。若衬底为硅衬底，则可以采用湿法腐蚀将硅衬底去除。
S550、在发光二极管芯片阵列1远离驱动背板2的一侧制作第二绝缘层3，第二绝缘层3包括多个第二开孔301；
参见图18，在发光二极管芯片阵列1远离驱动背板2的一侧制作第二绝缘层3，第二绝缘层3包括多个第二开孔301，第二开孔301位于LED芯片20远离驱动背板2一侧的表面，第二开孔301中暴露LED芯片20的第一半导体层24。
S560、在第二绝缘层3远离驱动背板1的一侧制作第二电极4；第二电极4通过第二开孔301与多个LED芯片20电连接。
参见图19，在第二绝缘层3远离驱动背板2的一侧制作第二电极4；第二电极4通过第二开孔301与多个LED芯片20电连接。第二电极4例如可是金属，制作第二电极4例如可以是进行金属布线，第二电极4连接多个LED芯片20的第一半导体层24，形成网格状的公共电极，以提升出光效率。
本申请设置底填胶层5设置于沟槽50和驱动背板2之间可以加强邦定的强度，有利于提升显示面板的良率和使用寿命。

Claims (20)

  1. 一种发光二极管芯片阵列，包括：
    衬底；
    位于所述衬底上的多个发光二极管芯片，所述发光二极管芯片包括位于所述衬底上的发光二极管外延结构和位于所述发光二极管外延结构远离所述衬底一侧的台面上的第一电极；
    至少一个隔离墙，所述至少一个隔离墙位于所述衬底上相邻的两个发光二极管芯片之间，所述隔离墙和所述发光二极管芯片之间形成沟槽；以及
    焊点，位于所述第一电极上。
  2. 根据权利要求1所述的发光二极管芯片阵列，还包括：支撑件；
    所述支撑件位于所述隔离墙远离所述衬底的一侧。
  3. 根据权利要求1所述的发光二极管芯片阵列，其中，所述多个发光二极管芯片相互独立。
  4. 根据权利要求1所述的发光二极管芯片阵列，还包括：反射层；
    所述发光二极管芯片包括台面和侧壁，所述反射层位于所述发光二极管芯片的侧壁。
  5. 根据权利要求1所述的发光二极管芯片阵列，相邻的两个所述发光二极管芯片之间设置多个所述隔离墙，所述隔离墙和所述发光二极管芯片之间以及所述隔离墙与相邻隔离墙之间形成沟槽。
  6. 根据权利要求1所述的发光二极管芯片阵列，还包括：
    第一绝缘层；
    所述发光二极管芯片包括台面和侧壁，至少部分所述第一绝缘层位于所述发光二极管芯片的侧壁上；所述第一绝缘层包括第一开孔，所述第一开孔暴露所述第一电极。
  7. 根据权利要求1所述的发光二极管芯片阵列，还包括：第一绝缘层，
    所述发光二极管外延结构包括台面和侧壁，至少部分所述第一绝缘层位于所述发光二极管外延结构的侧壁上；所述第一电极覆盖所述发光二极管外延结 构的台面，以及覆盖所述第一绝缘层位于所述发光二极管外延结构的侧壁上的部分。
  8. 根据权利要求7所述的发光二极管芯片阵列，其中，所述焊点覆盖所述第一电极。
  9. 根据权利要求1至8任一项所述的发光二极管芯片阵列，其中，所述焊点表面的形状为半球形、圆饼形或方饼形中的至少一种。
  10. 根据权利要求9所述的发光二极管芯片阵列，其中，所述发光二极管外延结构包括由衬底依次外延生长的第一半导体层、多量子阱层和第二半导体层。
  11. 根据权利要求10所述的发光二极管芯片阵列，其中，所述第一半导体层为n-GaN，所述第二半导体层为p-GaN。
  12. 根据权利要求10所述的发光二极管芯片阵列，其中，所述发光二极管外延结构还包括缓冲层，所述缓冲层位于所述第一半导体层和所述衬底之间。
  13. 一种显示面板，包括：驱动背板和如权利要求1-12任一项所述的发光二极管芯片阵列；所述驱动背板与所述发光二极管芯片阵列邦定。
  14. 根据权利要求13所述的显示面板，还包括：底填胶层，所述底填胶层位于所述沟槽和所述驱动背板之间。
  15. 根据权利要求13或14所述的显示面板，还包括：第二绝缘层和第二电极，所述第二绝缘层位于所述发光二极管芯片远离所述驱动背板的一侧，所述第二电极位于所述第二绝缘层远离所述驱动背板的一侧。
  16. 根据权利要求15所述的显示面板，其中，所述第二绝缘层包括多个第二开孔，所述第二开孔位于所述发光二极管芯片远离所述驱动背板一侧的表面，所述第二电极通过所述第二开孔与多个所述发光二极管芯片电连接。
  17. 根据权利要求16所述的显示面板，其中，所述第二电极为所述发光二极管芯片的公共电极。
  18. 一种如权利要求1至12任一项所述的发光二极管芯片阵列的制作方法，包括以下步骤：
    提供外延片，所述外延片包括衬底和生长于所述衬底的半导体膜层；
    刻蚀所述半导体膜层，形成多个发光二极管外延结构；
    在所述发光二极管外延结构的台面上制作第一电极，形成多个发光二极管芯片；
    在所述第一电极上制作焊点。
  19. 如权利要求18所述的发光二极管芯片阵列的制作方法，其中，
    所述刻蚀所述半导体膜层，形成多个发光二极管外延结构的同时，形成隔离墙；所述隔离墙与所述发光二极管外延结构之间形成沟槽。
  20. 如权利要求18所述的发光二极管芯片阵列的制作方法，其中，
    所述刻蚀所述半导体膜层，形成多个发光二极管外延结构之后，在相邻发光二极管外延结构之间制作隔离墙；所述隔离墙与所述发光二极管外延结构之间形成沟槽。
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