WO2022099501A1 - 垂直结构发光二极管及其制备方法 - Google Patents

垂直结构发光二极管及其制备方法 Download PDF

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WO2022099501A1
WO2022099501A1 PCT/CN2020/128095 CN2020128095W WO2022099501A1 WO 2022099501 A1 WO2022099501 A1 WO 2022099501A1 CN 2020128095 W CN2020128095 W CN 2020128095W WO 2022099501 A1 WO2022099501 A1 WO 2022099501A1
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substrate
atomic layer
metal atomic
light
layer
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PCT/CN2020/128095
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to PCT/CN2020/128095 priority Critical patent/WO2022099501A1/zh
Priority to CN202080106651.2A priority patent/CN116438641A/zh
Publication of WO2022099501A1 publication Critical patent/WO2022099501A1/zh
Priority to US18/175,288 priority patent/US20230207736A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Definitions

  • the present application relates to the technical field of light-emitting diodes, and in particular, to a light-emitting diode with a vertical structure and a method for preparing the same.
  • the vertical structure light emitting diode (Light Emitting Diode, LED) has great advantages in light extraction efficiency and heat dissipation speed.
  • the fabrication method of the vertical structure light-emitting diode is very complicated. After the light-emitting structure is formed, the substrate used to grow the epitaxial layer usually needs to be peeled off, and then the epitaxial layer is bonded to a new substrate with high conductivity. This complicated preparation process directly leads to the difficulty in improving the production efficiency of vertical structure light-emitting diodes. In addition, there are various problems in the lift-off process, which seriously affect the fabrication cost and yield of light-emitting diodes. For example, the laser lift-off method (mainly used for sapphire substrates) is costly, and the chemical etching lift-off method (mainly used for silicon substrates) results in poor efficiency and yield, and the peeled-off substrate cannot be reused.
  • the laser lift-off method mainly used for sapphire substrates
  • the chemical etching lift-off method mainly used for silicon substrates
  • the substrate in the prior art does not have good electrical conductivity, and the power of the device will be seriously affected if it is not peeled off.
  • the present application is devoted to providing a preparation method without stripping and bonding, for preparing a vertical structure light emitting diode.
  • the method includes: forming a metal atomic layer on a substrate, wherein the substrate is an n-type substrate; forming an n-type buffer layer on the metal atomic layer; forming a light-emitting structure on the n-type buffer layer, and the light-emitting structure from bottom to top includes An n-type semiconductor layer, an active layer and a p-type semiconductor layer; a p-electrode is arranged on the light-emitting structure; an n-electrode is arranged on the side of the substrate away from the metal atomic layer.
  • the metal atomic layer is an Al atomic layer.
  • forming a metal atomic layer on a substrate includes: forming a metal atomic layer with a patterned structure on the substrate, and the patterned structure includes a continuous pattern and a discontinuous pattern.
  • forming a metal atomic layer with a patterned structure on a substrate includes: patterning an upper surface of the substrate; forming a metal atomic layer on the upper surface of the substrate with a patterned structure, So that the metal atomic layer has a patterned structure.
  • the metal atomic layer is partially formed on the substrate.
  • the metal atomic layer is partially formed on the substrate, including: patterning the upper surface of the substrate; forming metal on a partial area of the upper surface of the substrate having a patterned structure atomic layer.
  • the method before disposing the n-electrode on the side of the substrate away from the metal atomic layer, the method further includes: thinning the substrate on the side of the substrate away from the metal atomic layer.
  • the thinning process includes etching and/or grinding.
  • the substrate is provided with at least one deep groove for separating the substrate into a plurality of pre-discrete structures; the thinning process makes the thickness of the thinned substrate less than or equal to the depth of the deep groove, so as to separate the substrate into a plurality of pre-discrete structures; The plurality of pre-discrete structures are separated into a plurality of light emitting units independent of each other.
  • At least one of the deep trenches is filled with insulating material.
  • arranging an n-electrode on a side of the substrate away from the metal atomic layer includes: arranging an n-electrode on a side away from the metal atomic layer of each light-emitting unit in the plurality of light-emitting units.
  • the present application also provides a vertical structure light emitting diode prepared by the above preparation method.
  • the vertical structure light-emitting diode comprises: a substrate, which is an n-type substrate; a metal atomic layer formed on the substrate; an n-type buffer layer formed on the metal atomic layer;
  • the light-emitting structure includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer in sequence from bottom to top; a p-electrode disposed on the light-emitting structure; and an n-electrode disposed on the side of the substrate away from the metal atomic layer.
  • the metal atomic layer is an Al atomic layer.
  • the metal atomic layer has a patterned structure, and the patterned structure includes a continuous pattern and a discontinuous pattern.
  • the upper surface of the substrate has a patterned structure corresponding to the metal atomic layer.
  • the materials of the n-type semiconductor layer and the p-type semiconductor layer are group III nitrides.
  • the horizontal width of the vertical structure light-emitting diode is less than 500um.
  • the horizontal width of the vertical structure light-emitting diode is less than 100um.
  • the present application further provides an LED display panel, including the vertical structure light emitting diode provided in any of the above embodiments.
  • the conductivity of the device with a vertical structure can be ensured It is not necessary to carry out peeling and bonding after forming the layer structure, which reduces the preparation steps, effectively saves the preparation cost of the vertical structure light-emitting diode, and improves the preparation efficiency; in addition, by setting the metal atomic layer, the metal atomic layer can also With a patterned structure, the process flow of the vertical light-emitting diode structure can be simplified, and the light-lifting efficiency of the vertical light-emitting diode structure can also be effectively improved.
  • FIG. 1 is a schematic flowchart of a method for fabricating a vertical structure light-emitting diode according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a method for fabricating a vertical structure light-emitting diode according to another embodiment of the present application.
  • FIGS. 3A to 3F are schematic flowcharts of an exemplary process for fabricating a vertical structure light-emitting diode provided by the present application.
  • FIG. 4 is a schematic structural diagram of a vertical structure light emitting diode according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • FIG. 1 is a schematic flowchart of a method for fabricating a vertical structure light-emitting diode according to an embodiment of the present application. As shown in Figure 1, the method includes:
  • the substrate is an n-type substrate. Since the n-type substrate has good electrical and thermal conductivity, in the embodiments of the present application, by using the n-type substrate, the epitaxial layer can be grown directly on the substrate and the n-electrode can be directly arranged on the backside of the substrate. Therefore, there is no need to peel off the substrate, the preparation method is simplified, and the preparation cost is saved.
  • the metal atomic layer disposed under the light-emitting structure can reflect the light emitted by the light-emitting structure, thereby effectively increasing the light-extraction efficiency of the vertical structure light-emitting diode;
  • the metal atomic layer By arranging the metal atomic layer above it, the adverse effect of the substrate on the light-emitting effect of the vertical structure light-emitting diode can be effectively prevented.
  • the metal atomic layer may be a tiled layer.
  • the metal atomic layer may have a patterned structure.
  • the metal atomic layer with the patterned structure can reflect the light emitted by the light emitting structure in more directions, so that the light extraction efficiency of the vertical structure light emitting diode can be further improved.
  • the patterned structure of the metal atomic layer can be realized in various ways.
  • patterning may be performed on its surface to obtain a metal atomic layer having a continuous patterned structure.
  • the metal atomic layer is patterned to obtain a metal atomic layer having a discontinuous patterned structure.
  • a patterning process may be performed on the upper surface of the substrate, and then a uniform metal atomic layer may be formed on the upper surface of the substrate having the patterned structure.
  • the metal atomic layer will have a patterned structure corresponding to the patterned structure on the substrate.
  • the upper surface of the substrate may be patterned, and the metal atomic layer is formed only between the recessed regions on the patterned structure of the substrate, thereby A discontinuous metal atomic layer corresponding to the patterned structure on the substrate is obtained.
  • the upper surface of the substrate may be patterned, and the metal atomic layer may be formed only in the recessed area on the patterned structure of the substrate, thereby obtaining A discontinuous metal atomic layer corresponding to a patterned structure on a substrate.
  • the operation of patterning the substrate is less difficult and the effect is better. Therefore, by using the method of this embodiment, the patterning of the metal atomic layer can be more easily realized, and the product quality of the device can be improved at the same time.
  • the metal atomic layer may be an Al atomic layer. Since Al element and Ga element are elements of the same group, in the case of preparing the Group III nitride buffer layer on the Al atomic layer, the buffer layer can be better grown and the quality of the buffer layer can be improved.
  • the material of the n-type buffer layer can be selected from group III nitrides, such as gallium nitride, aluminum gallium nitride, and the like.
  • the buffer layer can greatly relieve the stress that occurs when the epitaxial layer is grown on the substrate, and realize dislocation filtering, which can improve the crystal quality of the epitaxial layer.
  • the light emitting structure includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer from bottom to top.
  • the n-type semiconductor layer may be composed of group III nitrides, such as gallium nitride, aluminum gallium nitride, etc.
  • the p-type semiconductor layer may be composed of group III nitrides, such as gallium nitride, aluminum gallium nitride, and the like.
  • the electrons from the n-type semiconductor layer and the holes from the p-type semiconductor layer recombine in the active layer to release energy, thereby realizing light emission.
  • the active layer may be a multi-quantum well (MQW, Multi-quantum Well) layer.
  • MQW Multi-quantum Well
  • S140 Disposing a p electrode on the light emitting structure.
  • S150 Disposing an n-electrode on the side of the substrate away from the metal atomic layer.
  • the device with a vertical structure can be guaranteed.
  • Conductivity without peeling and bonding after forming the layer structure, reducing the preparation steps, effectively saving the preparation cost of the vertical structure light-emitting diode, and improving the preparation efficiency; in addition, by setting the metal atomic layer, the metal atomic layer also It can have a patterned structure, which can effectively improve the light-lifting efficiency of the vertical light-emitting diode while ensuring the simplification of the process flow of the vertical light-emitting diode structure.
  • the method shown in FIG. 1 may further include: thinning the substrate on a side of the substrate away from the metal atomic layer.
  • the thinning treatment may include a combination of one or more of methods such as etching and grinding.
  • the resistance of the substrate can be further reduced, the conductivity of the overall layer structure can be improved, and the luminous efficiency of the vertical structure light-emitting diode can be further improved.
  • FIG. 2 is a schematic flowchart of a method for fabricating a vertical structure light-emitting diode according to another embodiment of the present application.
  • FIGS. 3A to 3F are schematic flowcharts of an exemplary process for fabricating a vertical structure light-emitting diode provided by the present application. As shown in Figure 2 and Figures 3A-3F, the method includes:
  • S210 Form a metal atomic layer on the substrate provided with at least one deep groove.
  • At least one deep groove 10 may be provided on the substrate 310 used to separate the substrate 310 into a plurality of pre-discrete structures.
  • Metal atomic layers are formed on the substrate provided with the deep trenches 10 , that is, metal atomic layers are respectively formed on a plurality of pre-discrete structures of the substrate.
  • the upper surface of the substrate 310 may be patterned first, and then the upper surface of the substrate 310 with the patterned structure may be patterned.
  • a uniform metal atomic layer 350 is formed on the surface, so that the metal atomic layer 350 directly has a patterned structure corresponding to the patterned structure on the substrate 310 .
  • S240 Disposing a p electrode on the light emitting structure.
  • an n-type buffer layer 360 , a light-emitting structure 320 and a p-electrode 340 may be sequentially formed on the metal atomic layer 350 .
  • the thinned thickness is greater than or equal to the distance between the bottom surface of the deep groove and the bottom surface of the substrate, that is, the thickness of the thinned substrate is less than or equal to the thickness of the deep groove. depth, then it is possible to remove the bottom of the deep groove. That is, the connecting portions between the plurality of pre-discrete structures separated by the deep grooves are removed. In this way, the multiple pre-discrete structures will be completely separated to form multiple discrete structures (ie, multiple light emitting units) that are independent of each other.
  • the depth of the at least one deep groove is greater than half the thickness of the substrate. In order to more easily separate the multiple pre-discrete structures into multiple discrete structures independent of each other in the subsequent thinning process.
  • the at least one deep groove includes a plurality of deep grooves
  • the depths of the plurality of deep grooves are all equal.
  • the preparation process can be simplified.
  • At least one deep groove on the substrate 310 may be filled with an insulating material, such as silicon dioxide or silicon nitride.
  • an insulating material such as silicon dioxide or silicon nitride.
  • S260 Disposing an n-electrode on a side of each light-emitting unit in the plurality of light-emitting units away from the metal atomic layer.
  • an n-electrode 330 may be disposed under each light-emitting unit to obtain a complete discrete device.
  • a vertical structure light-emitting diode Based on the method for fabricating a vertical structure light-emitting diode provided by the embodiments of the present application, by using a substrate with deep grooves, a vertical structure is fabricated on a plurality of pre-discrete structures separated by deep grooves, so that the thinning is realized only by thinning A plurality of discrete devices can be obtained by the processing, the cutting step is avoided, the damage to the devices is reduced, and the quality of the vertical structure light-emitting diode can be improved.
  • FIG. 4 is a schematic structural diagram of a vertical structure light emitting diode according to an embodiment of the present application.
  • the vertical structure light-emitting diode can be obtained by the preparation method shown in FIG. 1 .
  • the vertical structure light-emitting diode includes: a substrate 410 , which is an n-type substrate; a metal atomic layer 450 formed on the substrate 410 ; an n-type buffer layer formed on the metal atomic layer 450 460; a light-emitting structure 420 formed on the n-type buffer layer 460, wherein the light-emitting structure 420 sequentially includes an n-type semiconductor layer 421, an active layer 422 and a p-type semiconductor layer 423 from bottom to top; electrode 440; and an n-electrode 430 disposed on the side of the substrate away from the metal atomic layer.
  • the metal atomic layer 450 is an Al atomic layer.
  • FIG. 5 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • the vertical structure light-emitting diode includes: a substrate 510, which is an n-type substrate; a metal atomic layer 550 formed on the substrate 510, and the metal atomic layer 550 has a continuous patterned structure; formed on the metal atomic layer 550 The n-type buffer layer 560; the light-emitting structure 520 formed on the n-type buffer layer 560, wherein the light-emitting structure 520 sequentially includes an n-type semiconductor layer 521, an active layer 522 and a p-type semiconductor layer 523 from bottom to top; The p-electrode 540 on the structure 520; and the n-electrode 530 disposed on the side of the substrate away from the metal atomic layer.
  • FIG. 6 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • the vertical structure light-emitting diode includes: a substrate 610, which is an n-type substrate; a metal atomic layer 650 formed on the substrate 610, and the metal atomic layer 650 has a discontinuous patterned structure; formed on the metal atomic layer 650 The n-type buffer layer 660 on the top; the light-emitting structure 620 formed on the n-type buffer layer 660, wherein the light-emitting structure 620 sequentially includes an n-type semiconductor layer 621, an active layer 622 and a p-type semiconductor layer 623 from bottom to top; The p-electrode 640 on the light-emitting structure 620; and the n-electrode 630 disposed on the side of the substrate away from the metal atomic layer.
  • FIG. 7 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • the vertical structure light-emitting diode includes: a substrate 710, the substrate 710 is an n-type substrate, and the upper surface of the substrate 710 has a patterned structure; a metal atomic layer 750 formed on the substrate 710, the metal atomic layer 750 has a The patterned structure corresponding to the substrate 710; the n-type buffer layer 760 formed on the metal atomic layer 750; the light-emitting structure 720 formed on the n-type buffer layer 760, wherein the light-emitting structure 720 sequentially includes n-type semiconductors from bottom to top The layer 721, the active layer 722 and the p-type semiconductor layer 723; the p-electrode 740 disposed on the light-emitting structure 720; and the n-electrode 730 disposed on the side of the substrate away from the metal atomic layer.
  • the metal atomic layer 750 by making the metal atomic layer 750 have a patterned structure corresponding to the substrate and the upper surface of the substrate 710, the metal atomic layer can be made more uniform, and the patterned structure is more stable, and the improvement of the vertical structure light-emitting diode can be better improved. light efficiency.
  • FIG. 8 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • the vertical structure light-emitting diode includes: a substrate 810, the substrate 810 is an n-type substrate, and the upper surface of the substrate 810 has a patterned structure; metal atoms formed between the recessed regions on the patterned structure of the substrate 810 layer 850; the n-type buffer layer 860 formed on the metal atomic layer 850; the light-emitting structure 820 formed on the n-type buffer layer 860, wherein the light-emitting structure 820 sequentially includes an n-type semiconductor layer 821 and an active layer 822 from bottom to top and a p-type semiconductor layer 823; a p-electrode 840 disposed on the light-emitting structure 820; and an n-electrode 830 disposed on the side of the substrate away from the metal atomic layer.
  • the metal atomic layer 850 is partially formed on the substrate 810 .
  • the metal atomic layer 850 may be formed on the protruding regions between the recessed regions in the patterned structure on the upper surface of the substrate 810 without disposing the metal atomic layer 850 in the recessed regions.
  • FIG. 9 is a schematic structural diagram of a vertical structure light emitting diode according to another embodiment of the present application.
  • the vertical structure light-emitting diode includes: a substrate 910, the substrate 910 is an n-type substrate, and the upper surface of the substrate 910 has a patterned structure; a metal atomic layer formed in a recessed area on the patterned structure of the substrate 910 950; the n-type buffer layer 960 formed on the metal atomic layer 950; the light-emitting structure 920 formed on the n-type buffer layer 960, wherein the light-emitting structure 920 sequentially includes the n-type semiconductor layer 921, the active layer 922 and the The p-type semiconductor layer 923; the p-electrode 940 disposed on the light-emitting structure 920; and the n-electrode 930 disposed on the side of the substrate away from the metal atomic layer.
  • the metal atomic layer 950 is partially formed on the substrate 910 .
  • the metal atomic layer 950 may be formed in the recessed areas in the patterned structure on the upper surface of the substrate 910, and the metal atomic layer 950 may not be provided on the raised areas between the recessed areas.
  • the conductivity of the device can be ensured
  • This device does not need to replace the substrate after the layer structure is formed, that is, the substrate is the substrate for growing the epitaxial layer, so the preparation cost is low, the preparation efficiency is high, and the device quality is better;
  • a metal atomic layer is provided on the metal atomic layer, and the metal atomic layer can also have a patterned structure, which can effectively improve the light-lifting efficiency of the vertical light-emitting diode structure while ensuring the simplification of the process flow of the vertical light-emitting diode structure.
  • FIG. 4 to FIG. 9 correspond to the method embodiment shown in FIG. 1 , and details and effects thereof will not be repeated here.
  • an LED display panel is further provided, including the vertical structure light emitting diode shown in any of the above embodiments in FIGS. 4 to 8 .
  • orientation or positional relationship indicated by the terms “upper”, “lower”, “inner”, “outer”, etc. is based on the orientation or positional relationship shown in the accompanying drawings, or is the customary pendulum when the product of the invention is used.
  • the orientation or positional relationship placed is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a reference to the application. limit.

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Abstract

一种垂直结构发光二极管及其制备方法，该方法包括：在衬底上形成金属原子层，其中，衬底为n型衬底（110）；在金属原子层上形成n型缓冲层（120）；在n型缓冲层上形成发光结构，发光结构自下向上包括n型半导体层、有源层以及p型半导体层（130）；在发光结构上设置p电极（140）；在衬底的远离金属原子层的一侧设置n电极（150）。通过采用具有导电性的n型衬底，并在其上依次形成金属原子层、n型缓冲层，能够确保具有垂直结构的器件的导电性，无需进行剥离与键合，减少了制备步骤，有效节省了垂直结构发光二极管的制备成本、提高了制备效率。

Description

垂直结构发光二极管及其制备方法 技术领域
本申请涉及发光二极管技术领域，具体涉及一种具有垂直结构的发光二极管及其制备方法。
背景技术
与传统的平面结构发光二极管相比，垂直结构的发光二极管(Light Emitting Diode,LED)在出光效率、散热速度等方面具有极大的优势。
然而，在现有技术中，垂直结构发光二极管的制备方法十分复杂。在形成发光结构之后，通常需要将用于生长外延层的衬底进行剥离，再将外延层键合到具有高导电性的新衬底上。这种复杂的制备过程直接导致了垂直结构发光二极管的生产效率难以提升。此外，剥离工艺还存在各种各样的问题，严重影响发光二极管的制备成本及良品率。例如，激光剥离方式(主要用于蓝宝石衬底)成本较高，化学腐蚀剥离方式(主要用于硅衬底)会导致效率和良率较差，且剥离掉的衬底无法重复使用。
发明内容
现有技术中，采用上述复杂的制备方法的主要原因在于：现有技术中的衬底不具备良好的导电性，如不进行剥离，则会严重影响器件的功率。
为了克服上述技术问题，人们一直在钻研如何改进剥离工艺，提高剥离效率、降低成本以及对器件的影响等。然而，这些方法均局限于剥离工艺，无法从根本上提高垂直结构发光二极管的生产效率。
有鉴于此，本申请致力于提供一种无需进行剥离与键合的制备方法，用于制备垂直结构发光二极管。该方法包括：在衬底上形成金属原子层，其中， 衬底为n型衬底；在金属原子层上形成n型缓冲层；在n型缓冲层上形成发光结构，发光结构自下向上包括n型半导体层、有源层以及p型半导体层；在发光结构上设置p电极；在衬底的远离金属原子层的一侧设置n电极。
在一实施方式中，金属原子层为Al原子层。
在一实施方式中，在衬底上形成金属原子层，包括：在衬底上形成具有图形化结构的金属原子层，图形化结构包括连续型图形和非连续型图形。
在一实施方式中，在衬底上形成具有图形化结构的金属原子层，包括：对衬底的上表面进行图形化处理；在具有图形化结构的衬底的上表面上形成金属原子层，以使金属原子层具备图形化结构。
在一实施方式中，金属原子层部分形成于衬底上。
在一实施方式中，金属原子层部分形成于衬底上，包括：对所述衬底的上表面进行图形化处理；在具有图形化结构的所述衬底的上表面的部分区域上形成金属原子层。
在一实施方式中，在衬底的远离金属原子层的一侧设置n电极之前，该方法还包括：在衬底的远离金属原子层的一侧对衬底进行减薄处理。
在一实施方式中，减薄处理包括蚀刻和/或打磨。
在一实施方式中，衬底上设有至少一个深槽，用于将衬底分隔为多个预分立结构；减薄处理使得减薄后的衬底的厚度小于等于深槽的深度，以将多个预分立结构分离为相互独立的多个发光单元。
在一实施方式中，至少一个深槽中填充有绝缘材料。
在一实施方式中，在衬底的远离金属原子层的一侧设置n电极，包括：在多个发光单元中的每个发光单元的远离金属原子层的一侧设置n电极。
同时，本申请还提供一种利用上述制备方法制备得到的垂直结构发光二极管。该垂直结构发光二极管包括：衬底，该衬底为n型衬底；形成于衬底上的金属原子层；形成于金属原子层上的n型缓冲层；形成于n型缓冲层上的发光结构，其中，发光结构自下向上依次包括n型半导体层、有源层以及p型半导体层；设置于发光结构上的p电极；以及设置于衬底的远离金属原子层一侧的n电极。
在一实施方式中，金属原子层为Al原子层。
在一实施方式中，金属原子层具有图形化结构，图形化结构包括连续型图形和非连续型图形。
在一实施方式中，衬底的上表面具有与金属原子层相对应的图形化结构。
在一实施方式中，n型半导体层以及p型半导体层的材料为三族氮化物。
在一实施方式中，垂直结构发光二极管水平方向宽度小于500um。
在一实施方式中，垂直结构发光二极管水平方向宽度小于100um。
衬底进一步地，本申请还提供一种LED显示面板，包括上述任一实施方式所提供的垂直结构发光二极管。
基于本申请所提供的垂直结构发光二极管及其制备方法，通过采用具有导电性的n型衬底，并在其上依次形成金属原子层、n型缓冲层，能够确保具有垂直结构的器件的导电性，无需在形成层结构之后进行剥离与键合，减少了制备步骤，有效节省了垂直结构发光二极管的制备成本、提高了制备效率；此外，通过设置金属原子层，且该金属原子层还可具有图形化结构，在保证简化垂直发光二极管结构的工艺流程的同时，还能够有效提升垂直结构发光二极管的提光效率。
附图说明
图1所示为本申请一实施例所提供的垂直结构发光二极管的制备方法的流程示意图。
图2所示为本申请另一实施例所提供的垂直结构发光二极管的制备方法的流程示意图。
图3A～3F为本申请所提供的垂直结构发光二极管的制备方法的一示例性流程示意图。
图4所示为本申请一实施例所提供的垂直结构发光二极管的结构示意图。
图5所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。
图6所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。
图7所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。
图8所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。
图9所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本申请保护的范围。
图1所示为本申请一实施例所提供的垂直结构发光二极管的制备方法的流程示意图。如图1所示，该方法包括：
S110：在衬底上形成金属原子层。
其中，衬底为n型衬底。由于n型衬底具有较好的导电性及导热性，在本申请的实施例中，通过采用n型衬底，可以实现直接在衬底上生长外延层并直接在衬底背面设置n电极，从而无需对衬底进行剥离，简化了制备方法，节省了制备成本。
由于金属具有不透明性，设于发光结构下方的金属原子层能够对发光结构所发出的光线进行反射，从而有效增加垂直结构发光二极管的提光效率；同时，由于衬底具有较强的吸光作用，通过在其上方设置金属原子层，可以有效防止衬底对垂直结构发光二极管的发光效果的不良影响。
具体地，如图4所示，在一实施例中，金属原子层可以是平铺的一层。
在另一实施例中，金属原子层可以具有图形化结构。具有图形化结构的金属原子层能够将发光结构所发出的光线向更多的方向进行反射，从而能够进一步提高垂直结构发光二极管的提光效率。
具体地，金属原子层的图形化结构可以通过多种方式来实现。
例如，如图5所示，可以在形成金属原子层后在其表面进行图形化处理以得到具有连续型图形化结构的金属原子层。
再例如，如图6所示，对金属原子层进行图形化处理以得到具有非连续型图形化结构的金属原子层。
又例如，如图7所示，在形成金属原子层之前，可以先对衬底的上表面进行图形化处理，再在具有图形化结构的衬底的上表面上形成均匀的金属原子层。这样一来，金属原子层就会具备与衬底上的图形化结构相对应的图形化结构。
又例如，如图8所示，在形成金属原子层之前，可以先对衬底的上表面进行 图形化处理，并仅在衬底的图形化结构上的凹陷区域之间形成金属原子层，从而得到与衬底上的图形化结构相对应的、非连续的金属原子层。
又例如，如图9所示，在形成金属原子层之前，可以先对衬底的上表面进行图形化处理，并仅在衬底的图形化结构上的凹陷区域内形成金属原子层，从而得到与衬底上的图形化结构相对应的、非连续的金属原子层。
相较于对金属原子层直接进行图形化处理，对衬底进行图形化处理的操作难度更低、效果更佳。因此，采用本实施例的方法，能够更加容易地实现金属原子层的图形化，同时提高器件的产品质量。
应当理解，本申请的实施例对于使金属原子层具有图形化结构的方法不进行限定，本领域技术人员可根据实际需求进行选择。
进一步地，在一实施例中，金属原子层可以是Al原子层。由于Al元素与Ga元素为同族元素，在Al原子层上制备三族氮化物缓冲层的情况下，能够更好地生长缓冲层并提高缓冲层的质量。
S120：在金属原子层上形成n型缓冲层。
具体地，n型缓冲层的材料可选择三族氮化物，如氮化镓、铝镓氮等。
在这里，缓冲层可以极大地缓解衬底上生长外延层时所发生的应力，并实现位错过滤，从而能够提高外延层的晶体质量。
S130：在n型缓冲层上形成发光结构。
具体地，发光结构自下向上包括n型半导体层、有源层以及p型半导体层。n型半导体层可以由三族氮化物构成，如氮化镓、铝镓氮等；p型半导体层可以由三族氮化物构成，如氮化镓、铝镓氮等。来自n型半导体层的电子与来自p型半导体层的空穴在有源层中复合释放出能量，从而实现发光。
在一实施例中，有源层可以是多量子阱(MQW,Multi-quantum Well)层。
S140：在发光结构上设置p电极。
S150：在衬底的远离金属原子层的一侧设置n电极。
基于本申请实施例所提供的垂直结构发光二极管的制备方法，通过采用具有导电性的n型衬底，并在其上依次形成金属原子层、n型缓冲层，能够确保具有垂直结构的器件的导电性，无需在形成层结构之后进行剥离与键合，减少了制备步骤，有效节省了垂直结构发光二极管的制备成本、提高了制备效率；此外，通 过设置金属原子层，且该金属原子层还可具有图形化结构，在保证简化垂直发光二极管结构的工艺流程的同时，还能够有效提升垂直结构发光二极管的提光效率。
可选地，在另一实施例中，图1所示方法在S150之前还可以包括：在衬底的远离金属原子层的一侧对衬底进行减薄处理。
其中，减薄处理可以包括蚀刻、打磨等方法中的一种或多种的结合。通过对衬底进行减薄处理，可以进一步降低衬底的电阻，提高整体层结构的导电性，进而提高垂直结构发光二极管的发光效率。
图2所示为本申请另一实施例所提供的垂直结构发光二极管的制备方法的流程示意图。图3A～3F为本申请所提供的垂直结构发光二极管的制备方法的一示例性流程示意图。如图2及图3A～3F所示，该方法包括：
S210：在设有至少一个深槽的衬底上形成金属原子层。
具体地，如图3A所示，在一实施例中，采用的衬底310上可以设有至少一个深槽10，用于将衬底310分隔为多个预分立结构。在这种设有深槽10的衬底上形成金属原子层，也就是在衬底的多个预分立结构上分别形成金属原子层。
优选地，如图3B～3C所示，在一实施例中，在形成金属原子层之前，可以先对衬底310的上表面进行图形化处理，再在具有图形化结构的衬底310的上表面上形成均匀的金属原子层350，以使金属原子层350直接具备与衬底310上的图形化结构相对应的图形化结构。
S220：在金属原子层上形成n型缓冲层。
S230：在n型缓冲层上形成发光结构。
S240：在发光结构上设置p电极。
如图3D所示，在一实施例中，可以在金属原子层350上依次形成n型缓冲层360、发光结构320以及p电极340。
S250：在衬底的远离金属原子层的一侧对衬底进行减薄处理，以使得减薄后的衬底的厚度小于等于深槽的深度，从而将多个预分立结构分离为相互独立的多个发光单元。
如图3E所示，通过从衬底310下方对衬底310进行减薄处理，能够直接获得相互独立的多个发光单元，避免了切割等步骤，提高了器件质量。
具体地，在对具有深槽的衬底进行减薄处理时，如果减薄的厚度大于等于深 槽底面与衬底底面之间的距离，即减薄后的衬底的厚度小于等于深槽的深度，那么就可以实现去除深槽的底部。也就是说，被深槽分隔的多个预分立结构之间的连接部分会被去除。这样一来，多个预分立结构将被彻底分离，形成相互独立的多个分立结构(即多个发光单元)。
优选地，在一实施例中，至少一个深槽的深度大于衬底厚度的一半。以便在后续的减薄处理中能够更加容易地将多个预分立结构分离为相互独立的多个分立结构。
优选地，在另一实施例中，当至少一个深槽包括多个深槽时，多个深槽的深度全部相等。以便在后续的减薄处理中能够实现将所有的预分立结构同时进行分离，简化制备流程。
进一步地，在另一实施例中，衬底310上的至少一个深槽中可以填充有绝缘材料，例如二氧化硅或者氮化硅等。通过在深槽中设置绝缘材料，能够实现更好的隔离效果，使后续的工艺更加易于实现，并且使最终得到的分立器件质量更佳。
S260：在多个发光单元中的每个发光单元的远离金属原子层的一侧设置n电极。
如图3F所示，在得到多个相互独立的发光单元后，可以在每个发光单元的下方设置n电极330，得到完整的分立器件。
基于本申请实施例所提供的垂直结构发光二极管的制备方法，通过采用设有深槽的衬底，在被深槽分隔成的多个预分立结构上制作垂直结构，从而实现了仅通过减薄处理就能够得到多个分立器件，避免了切割步骤，减少了对器件的损伤，进而能够提高垂直结构发光二极管的质量。
应当理解，图2所示实施例的方法中的部分步骤与图1所示方法相同，在此对其细节与效果不再进行赘述。
图4所示为本申请一实施例所提供的垂直结构发光二极管的结构示意图。该垂直结构发光二极管可通过图1所示的制备方法得到。如图4所示，该垂直结构发光二极管包括：衬底410，衬底410为n型衬底；形成于衬底410上的金属原子层450；形成于金属原子层450上的n型缓冲层460；形成于n型缓冲层460上的发光结构420，其中，发光结构420自下向上依次包括n型半导体层421、有源层422以及p型半导体层423；设置于发光结构420上的p电极440；以及 设置于衬底的远离金属原子层一侧的n电极430。
优选地，在一实施例中，金属原子层450为Al原子层。
图5所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。该垂直结构发光二极管包括：衬底510，衬底510为n型衬底；形成于衬底510上的金属原子层550，金属原子层550具有连续型图形化结构；形成于金属原子层550上的n型缓冲层560；形成于n型缓冲层560上的发光结构520，其中，发光结构520自下向上依次包括n型半导体层521、有源层522以及p型半导体层523；设置于发光结构520上的p电极540；以及设置于衬底的远离金属原子层一侧的n电极530。
图6所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。该垂直结构发光二极管包括：衬底610，衬底610为n型衬底；形成于衬底610上的金属原子层650，金属原子层650具有非连续型图形化结构；形成于金属原子层650上的n型缓冲层660；形成于n型缓冲层660上的发光结构620，其中，发光结构620自下向上依次包括n型半导体层621、有源层622以及p型半导体层623；设置于发光结构620上的p电极640；以及设置于衬底的远离金属原子层一侧的n电极630。
图7所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。该垂直结构发光二极管包括：衬底710，衬底710为n型衬底，且衬底710的上表面具有图形化结构；形成于衬底710上的金属原子层750，金属原子层750具有与衬底710相对应的图形化结构；形成于金属原子层750上的n型缓冲层760；形成于n型缓冲层760上的发光结构720，其中，发光结构720自下向上依次包括n型半导体层721、有源层722以及p型半导体层723；设置于发光结构720上的p电极740；以及设置于衬底的远离金属原子层一侧的n电极730。
其中，通过使金属原子层750具有衬底与衬底710的上表面相对应的图形化结构，能够使金属原子层更加均匀，且图形化结构更加稳定，更好地提升垂直结构发光二极管的提光效率。
图8所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。该垂直结构发光二极管包括：衬底810，衬底810为n型衬底，且衬底810的上表面具有图形化结构；形成于衬底810的图形化结构上的凹陷区域之间的金属原 子层850；形成于金属原子层850上的n型缓冲层860；形成于n型缓冲层860上的发光结构820，其中，发光结构820自下向上依次包括n型半导体层821、有源层822以及p型半导体层823；设置于发光结构820上的p电极840；以及设置于衬底的远离金属原子层一侧的n电极830。
也就是说，在图8所示实施例中，金属原子层850是部分形成于衬底810上的。具体地，可以将金属原子层850形成在衬底810上表面的图形化结构中的凹陷区域之间的凸起区域上，而在凹陷区域内不设置金属原子层850。
图9所示为本申请另一实施例所提供的垂直结构发光二极管的结构示意图。该垂直结构发光二极管包括：衬底910，衬底910为n型衬底，且衬底910的上表面具有图形化结构；形成于衬底910的图形化结构上的凹陷区域内的金属原子层950；形成于金属原子层950上的n型缓冲层960；形成于n型缓冲层960上的发光结构920，其中，发光结构920自下向上依次包括n型半导体层921、有源层922以及p型半导体层923；设置于发光结构920上的p电极940；以及设置于衬底的远离金属原子层一侧的n电极930。
也就是说，在图9所示实施例中，金属原子层950是部分形成于衬底910上的。具体地，可以将金属原子层950形成在衬底910上表面的图形化结构中的凹陷区域内，而在凹陷区域之间的凸起区域上不设置金属原子层950。
基于本申请实施例所提供的垂直结构发光二极管，通过采用具有导电性的n型衬底，并包括依次形成于n型衬底上的金属原子层、n型缓冲层，从而能够确保器件的导电性，这种器件无需在形成层结构之后替换衬底，即其衬底即为用于生长外延层的衬底，因此制备成本低、制备效率高，并且器件质量更好；此外，由于衬底上设有金属原子层，且该金属原子层还可具有图形化结构，在保证简化垂直发光二极管结构的工艺流程的同时，还能够有效提升垂直结构发光二极管的提光效率。
应当理解，图4～图9所示的结构实施例与图1所示的方法实施例相对应，在此对其中的各细节与效果不再进行赘述。
本申请的一实施例中，还提供一种LED显示面板，包括上述图4～图8中任一实施例所示出的垂直结构发光二极管。
需要说明的是，在本申请的描述中，除非另有明确的规定和限定，术语“设 置”、“形成”、“具备”等应做广义理解，对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
还需要说明的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种垂直结构发光二极管的制备方法，其特征在于，包括：
    在衬底上形成金属原子层，其中，所述衬底为n型衬底；
    在所述金属原子层上形成n型缓冲层；
    在所述n型缓冲层上形成发光结构，所述发光结构自下向上包括n型半导体层、有源层以及p型半导体层；
    在所述发光结构上设置p电极；
    在所述衬底的远离所述金属原子层的一侧设置n电极。
  2. 根据权利要求1所述的制备方法，其特征在于：
    所述金属原子层为Al原子层。
  3. 根据权利要求1所述的制备方法，其特征在于，所述在衬底上形成金属原子层，包括：
    在所述衬底上形成具有图形化结构的金属原子层，所述图形化结构包括连续型图形和非连续型图形。
  4. 根据权利要求3所述的制备方法，其特征在于，在所述衬底上形成具有图形化结构的金属原子层，包括：
    对所述衬底的上表面进行图形化处理；
    在具有图形化结构的所述衬底的上表面上形成金属原子层，以使所述金属原子层具备图形化结构。
  5. 根据权利要求1所述的制备方法，其特征在于，所述金属原子层部分形成于所述衬底上。
  6. 根据权利要求5所述的制备方法，其特征在于，所述金属原子层部分形成于所述衬底上，包括：
    对所述衬底的上表面进行图形化处理；
    在具有图形化结构的所述衬底的上表面的部分区域上形成所述金属原子层。
  7. 根据权利要求1所述的制备方法，其特征在于，在所述衬底的远离所述金属原子层的一侧设置n电极之前，还包括：
    对所述衬底的远离所述金属原子层的一侧对所述衬底进行减薄处理。
  8. 根据权利要求7中所述的制备方法，其特征在于：
    所述减薄处理包括蚀刻和/或打磨。
  9. 根据权利要求7或8所述的制备方法，其特征在于，所述衬底上设有至少一个深槽，用于将所述衬底分隔为多个预分立结构；
    所述减薄处理使得减薄后的所述衬底的厚度小于等于所述深槽的深度，以将所述多个预分立结构分离为相互独立的多个发光单元。
  10. 根据权利要求9所述的制备方法，其特征在于，所述至少一个深槽中填充有绝缘材料。
  11. 根据权利要求9所述的制备方法，其特征在于，在所述衬底的远离所述金属原子层的一侧设置n电极，包括：
    在所述多个发光单元中的每个发光单元的远离所述金属原子层的一侧设置n电极。
  12. 一种垂直结构发光二极管，其特征在于，包括：
    衬底，所述衬底为n型衬底；
    形成于所述衬底上的金属原子层；
    形成于所述金属原子层上的n型缓冲层；
    形成于所述n型缓冲层上的发光结构，其中，所述发光结构自下向上依次包括n型半导体层、有源层以及p型半导体层；
    设置于所述发光结构上的p电极；以及
    设置于所述衬底的远离所述金属原子层一侧的n电极。
  13. 根据权利要求12所述的垂直结构发光二极管，其特征在于：
    所述金属原子层为Al原子层。
  14. 根据权利要求12所述的垂直结构发光二极管，其特征在于，所述金属原子层具有图形化结构，图形化结构包括连续型图形和非连续型图形。
  15. 根据权利要求14所述的垂直结构发光二极管，其特征在于：
    所述衬底的上表面具有与所述金属原子层相对应的图形化结构。
  16. 根据权利要求12所述的垂直结构发光二极管，其特征在于：
    所述n型半导体层以及所述p型半导体层的材料为三族氮化物。
  17. 根据权利要求12所述的垂直结构发光二极管，其特征在于：
    所述垂直结构发光二极管水平方向宽度小于500um。
  18. 根据权利要求12所述的垂直结构发光二极管，其特征在于：
    所述垂直结构发光二极管水平方向宽度小于100um。
  19. 一种LED显示面板，其特征在于，包括权利要求12-16中任一项所述的垂直结构发光二极管。
PCT/CN2020/128095 2020-11-11 2020-11-11 垂直结构发光二极管及其制备方法 WO2022099501A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090309126A1 (en) * 2008-06-16 2009-12-17 Toyoda Gosei Co., Ltd. Group III nitride-based compound semiconductor light-emitting device and production method therefor
CN102130245A (zh) * 2010-12-23 2011-07-20 映瑞光电科技(上海)有限公司 发光二极管及其制造方法
CN107342256A (zh) * 2017-06-26 2017-11-10 矽力杰半导体技术(杭州)有限公司 半导体工艺及半导体结构
CN109786515A (zh) * 2018-12-28 2019-05-21 华灿光电（浙江）有限公司 一种发光二极管芯片的制作方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090309126A1 (en) * 2008-06-16 2009-12-17 Toyoda Gosei Co., Ltd. Group III nitride-based compound semiconductor light-emitting device and production method therefor
CN102130245A (zh) * 2010-12-23 2011-07-20 映瑞光电科技(上海)有限公司 发光二极管及其制造方法
CN107342256A (zh) * 2017-06-26 2017-11-10 矽力杰半导体技术(杭州)有限公司 半导体工艺及半导体结构
CN109786515A (zh) * 2018-12-28 2019-05-21 华灿光电（浙江）有限公司 一种发光二极管芯片的制作方法

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