WO2021017368A1 - 绝缘栅双极型晶体管及其制作方法 - Google Patents

绝缘栅双极型晶体管及其制作方法 Download PDF

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WO2021017368A1
WO2021017368A1 PCT/CN2019/124843 CN2019124843W WO2021017368A1 WO 2021017368 A1 WO2021017368 A1 WO 2021017368A1 CN 2019124843 W CN2019124843 W CN 2019124843W WO 2021017368 A1 WO2021017368 A1 WO 2021017368A1
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region
doping
doped
doped region
bipolar transistor
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PCT/CN2019/124843
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English (en)
French (fr)
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刘利书
冯宇翔
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广东美的白色家电技术创新中心有限公司
美的集团股份有限公司
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Publication of WO2021017368A1 publication Critical patent/WO2021017368A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology but are not limited to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor and a manufacturing method thereof.
  • Insulated Gate Bipolar Transistor is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), which also has a MOSFET
  • BJT bipolar transistor
  • MOSFET insulated gate field effect transistor
  • the high input impedance of the device and the low turn-on voltage drop of the power transistor (giant transistor, GTR for short) have the advantages of low driving power and reduced saturation voltage, and are widely used in various fields.
  • the embodiments of the present disclosure provide an insulated gate bipolar transistor and a manufacturing method thereof.
  • the first aspect of the embodiments of the present disclosure provides an insulated gate bipolar transistor, including:
  • a drift region includes a first doped region and a second doped region with the same doping type; wherein the doping concentration of the first doping region is greater than the doping concentration of the second doping region ;
  • a body region, the body region having a doping type different from the drift region includes a first part and a second part;
  • the first part is located between the first doped region and the emitter region, and is in contact with the first doped region;
  • the second part is located between the second doped region and the gate region and is in contact with the second doped region.
  • the first doped region is configured to promote the movement of carriers to the second doped region when the insulated gate bipolar transistor is turned on;
  • the first doped region is configured to recombine carriers in the drift region when the insulated gate bipolar transistor is turned off.
  • the first doped region includes a plurality of doped regions with different doping concentrations
  • the second doped region includes a plurality of doped regions with different doping concentrations.
  • the first doped region includes a first region and a second region, wherein the first region is located above the second region, and the doping concentration of the first region is greater than the doping concentration of the second region.
  • the ratio of the doping concentration of the first region to the doping concentration of the second region is greater than or equal to 10;
  • the ratio of the doping concentration of the second region to the doping concentration of the second doping region is greater than or equal to 10.
  • the doping concentration of the first region is 1*10 19 cm -3 to 1*10 20 cm -3 ; the doping concentration of the second region is 1*10 18 cm -3 to 1*10 19 cm -3 .
  • the doping concentration of the second doping region is 1*10 17 cm -3 to 1*10 18 cm -3 .
  • a second aspect of the embodiments of the present disclosure provides a method for manufacturing an insulated gate bipolar transistor, including:
  • drift region including a first doping region and a second doping region with the same doping type; wherein the doping concentration of the first doping region is greater than the doping concentration of the second doping region;
  • a first part of the body region is formed above the first doped region, and a second part of the body region is formed above the second doped region; wherein the doping type of the body region is related to the drift The doping type of the zone is different;
  • a gate region is formed above the second part.
  • the forming the drift region including the first doped region and the second doped region with the same doping type includes:
  • a plurality of doped regions with different doping concentrations are formed to form the second doped region.
  • the forming the drift region including the first doped region and the second doped region with the same doping type includes:
  • Forming the first doped region including a first region and a second region; wherein the first region is located above the second region, and the doping concentration of the first region is greater than that of the second region Miscellaneous concentration.
  • the insulated gate bipolar transistor includes a drift region, and the drift region includes a first doped region and a second doped region with the same doping type.
  • a doped region; wherein the doping concentration of the first doped region is greater than the doping concentration of the second doped region; the body region, the body region having a different doping type from the drift region includes a first portion And a second part; the first part is located between the first doped region and the emitter region, and is in contact with the first doped region; the second part is located in the second doped region Between the gate region and the gate region and in contact with the second doped region, because the doping concentration of the first doped region is higher than that of the second doped region, it can promote the injection of carriers into the first doped region Moving to the second doped region increases the difference between the carrier concentration injected into the second doped region and the carrier concentration of the second doped region itself, and enhances the conductance modulation effect of the second doped region.
  • the insulated gate bipolar transistor provided by the embodiments of the present disclosure can obtain a better compromise relationship between the turn-on voltage drop and the turn-off time, so that both the turn-on voltage drop and the turn-off time are lower.
  • FIG. 1 is a schematic diagram of an insulated gate bipolar transistor provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of an insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic structural diagram of another insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of energy bands between doped regions with different doping concentrations according to an embodiment of the disclosure
  • FIG. 5 is a schematic structural diagram of yet another insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of yet another insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic structural diagram of another insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • the directional indications are only used to explain each in a certain posture (such as shown in the drawings). If the relative positional relationship between the components, the movement situation, etc., change the specific posture, the directional indication will change accordingly.
  • the term "A is above/under B" means to include a situation where A and B are in contact with each other and one is above/under the other, or between A and B. A situation in which other components are interposed and one is located above/under the other without contact.
  • an embodiment of the present disclosure provides an insulated gate bipolar transistor, including:
  • the drift region 10 includes a first doped region 110 and a second doped region 120 with the same doping type; wherein the doping concentration of the first doped region 110 is greater than that of the second doped region Doping concentration of area 120;
  • a body region 20, the body region 20 having a different doping type from the drift region 10 includes a first portion 210 and a second portion 220;
  • the first portion 210 is located between the first doped region 110 and the emitter region 30, and is in contact with the first doped region 110;
  • the second portion 220 is located between the second doped region 120 and the gate region 40 and is in contact with the second doped region 120.
  • the doping type of the first doping region and the second doping region are the same, and the doping type may be acceptor doping or donor doping.
  • the majority carriers in the first doping region and the second doping region are holes, and the doping type of the body region is donor doping, Most carriers in the body region are electrons.
  • the majority carriers in the first doped region and the second doped region are donor doped, the majority carriers in the first doped region and the second doped region are electrons, and the doping type of the body region is acceptor doping.
  • the majority carriers in the region are holes.
  • the majority carrier here is: a larger number of carriers per unit volume.
  • the doping concentration is the concentration of carriers generated by doping.
  • the first doped region is configured to promote the movement of carriers to the second doped region when the insulated gate bipolar transistor is turned on;
  • the first doped region is configured to recombine carriers in the drift region when the insulated gate bipolar transistor is turned off.
  • the working process of the insulated gate bipolar transistor will be described in detail.
  • a positive voltage is applied to the gate of the insulated gate bipolar transistor.
  • the electrons flow out of the emitter region and flow into the drift region.
  • a channel is formed near the gate region in the second part of the body region, and the collector region will also be in the forward direction.
  • holes are injected into the drift region.
  • the concentration of electrons injected into the drift region in the emitter region increases.
  • the concentration of hole carriers injected from the collector region into the drift region will also increase, causing a large number of electrons and holes to conduct current in the drift region with higher resistance. This increases the conductivity of the drift region and reduces the forward voltage drop of the insulated gate bipolar transistor.
  • the gate voltage drops from a positive value to zero or a negative value. Therefore, the path of electron injection from the emitter region to the drift region is cut off, and the electron current in the insulated gate bipolar transistor decreases rapidly.
  • the holes stored in the drift region in the forward conduction state are difficult to be quickly extracted, especially near the contact surface between the first part of the body region and the drift region.
  • the electron concentration near the contact surface is low.
  • the hole concentration in the region is large, the holes accumulated near the contact surface will cause the insulated gate bipolar transistor to have a longer tail current during the turn-off process, and prolong the turn-off of the insulated gate bipolar transistor. Time increases the turn-off loss of the device.
  • the working process of the insulated gate bipolar transistor is described below.
  • a negative voltage is applied to the gate of the insulated gate bipolar transistor.
  • the holes flow out from the emitter region and flow into the drift region.
  • a channel is formed near the gate region in the second part of the body region.
  • the collector region is also in the negative direction. Electrons are injected into the drift region under the action of voltage, and as the on-current increases, the concentration of holes injected into the drift region in the emitter region increases. In order to maintain the electrical neutrality of the drift region, the concentration of electrons injected from the collector region into the drift region will also increase, causing a large number of electrons and hole conductive carriers to accumulate in the drift region with a higher resistance.
  • the conductivity of the drift region reduces the on-voltage drop of the insulated gate bipolar transistor.
  • the gate voltage changes from negative to zero or positive, so the path of hole injection from the emitter region to the drift region is cut off, and the hole current in the insulated gate bipolar transistor is rapid
  • the electrons stored in the drift region are difficult to be quickly extracted in the on-state, especially in the vicinity of the contact surface between the first part of the body region and the drift region.
  • the hole concentration near the contact surface is low.
  • the electrons accumulated near the contact surface will cause the insulated gate bipolar transistor to have a longer tail current during the turn-off process, and prolong the turn-off time of the insulated gate bipolar transistor. Increase the turn-off loss of the device.
  • a first doped region and a second doped region with the same doping type are provided in the drift region, and the first doped
  • the doping concentration of the impurity region is greater than the doping concentration of the second doping region, which can promote the movement of carriers injected into the first doping region from the drift region to the second doping region, which improves the conduction in the second doping region.
  • the carrier concentration ensures the conduction path and reduces the conduction voltage drop of the insulated gate bipolar transistor; and the carriers injected into the first doped region from the drift region will move to the second doped region, reducing
  • the carrier concentration that needs to be recombined when the first doped region and the contact surface of the body region is turned off is reduced, the turn-off time is reduced, and the turn-off loss is reduced.
  • the first doped region may include a single doped region with a single concentration or a plurality of doped regions with different doping concentrations.
  • the plurality of doped regions with different doping concentrations may be as shown in FIG.
  • a plurality of doped regions with different doping concentrations can also be arranged sequentially in a direction perpendicular to the gate region as shown in FIG. 3.
  • the first doped region includes three doped regions 111, 112, and 113 with different doping concentrations
  • the three doped regions with different doping concentrations are shown in FIG. 2
  • the doping concentration of the doping region 111 is greater than the doping concentration of the doping region 112
  • the doping concentration of the doping region 112 is greater than the doping concentration of the doping region 113.
  • the first doped region includes three doped regions 114 with different doping concentrations, a doped region 115, and a doped region 116, and the three doped regions with different doping concentrations are shown in FIG. 3
  • the doping concentration of the doping region 114 is greater than the doping concentration of the doping region 115
  • the doping concentration of the doping region 115 is greater than the doping concentration of the doping region 116.
  • the first doped region when the first doped region includes three doped regions 111, 112, and 113 with different doping concentrations, and three doped regions with different doping concentrations
  • the doped region is set as shown in FIG. 2 since the doping concentration of the doped region 111 is greater than that of the second doped region 120, the distance between the Fermi level of the doped region 111 and the bottom of the conduction band is , Is smaller than the distance between the Fermi level of the second doped region 120 and the bottom of the conduction band.
  • the doped region 111 and the second doped region 120 After the doped region 111 and the second doped region 120 are in thermal equilibrium, the doped region 111 and the second doped region 120 It has a uniform Fermi level, and the potential energy of the holes located near the top of the valence band of the doped region 111 is higher than that of the holes located near the top of the valence band of the second doped region 120.
  • the holes in 120 move to the doped region 111, which reduces the number of holes accumulated at the interface between the doped region 111 and the second part 210 of the body region, shortens the turn-off time, and reduces the turn-off loss; on the other hand, The holes in the doped region 111 are promoted to move to the second doped region 120, the concentration of holes in the second doped region 120 is increased, the conductive path is ensured, and the conduction voltage drop is reduced.
  • the doping region 111, the doping region 112, and the doping region 113 in the first doping region 110 Prevent holes from entering the doped region 111, reduce the number of holes near the contact surface between the first doped region and the body region, reduce the turn-off time and turn-off loss, and promote the direction of holes entering the first doped region
  • the movement of the second doped region increases the hole injection efficiency in the second doped region, ensures a conductive path, and reduces the conduction voltage drop.
  • the first doped region 110 is provided with the doped region 114, the doped region 115, and the doped region 116 with successively lower doping concentrations as shown in FIG.
  • the holes in the region move to the second doped region, which increases the hole injection efficiency in the second doped region, ensures a conductive path, and reduces the conduction voltage drop.
  • the second doped region may include a single doped region with a single concentration or a plurality of doped regions with different doping concentrations.
  • the plurality of doped regions with different doping concentrations may be as shown in FIG.
  • the pole regions 40 are sequentially stacked and arranged in the direction; the multiple doped regions with different doping concentrations can also be arranged sequentially in a direction parallel to the gate region 40 as shown in FIG. 6.
  • the doped region 123 is doped
  • the impurity concentration is greater than the doping concentration of the doping region 122
  • the doping concentration of the doping region 122 is greater than the doping concentration of the doping region 121.
  • the doped region 126 when the second doped region includes three doped regions 124, doped regions 125, and doped regions 126 with different doping concentrations as shown in FIG. 6, the doped region 126 is doped
  • the impurity concentration is greater than the doping concentration of the doping region 125
  • the doping concentration of the doping region 125 is greater than the doping concentration of the doping region 124.
  • the second doping region 120 is provided with a doped region 123, a doped region 122, and a doped region 121 with successively lower doping concentrations, or
  • the doped region 126, doped region 125, and doped region 124 in the second doped region 120 with successively lower doping concentrations holes can be promoted to move from the first doped region to the second doped region, increasing The hole injection efficiency in the second doped region is ensured, the conduction path is ensured, the on-voltage drop is reduced, the hole concentration in the first doped region is reduced, and the turn-off time and turn-off loss are reduced.
  • the volume of a plurality of doping regions with different doping concentrations in the first doping region is the same, and the volume in the second doping region A plurality of doped regions with different doping concentrations have the same volume.
  • the ratio of the doping concentration of the first region to the doping concentration of the second region is greater than or equal to 10;
  • the ratio of the doping concentration of the second region to the doping concentration of the second doping region is greater than or equal to 10.
  • the insulated gate bipolar transistor When the insulated gate bipolar transistor is blocked in the forward direction, it mainly relies on the drift region to bear the forward blocking voltage. The greater the resistivity and thickness of the drift region, the higher the forward blocking voltage of the device and the voltage resistance of the device The better, but it also increases the forward voltage drop of the device, so a compromise is needed.
  • the carrier concentration injected into the drift region is greater than its own doping concentration, the internal conductivity modulation effect of the insulated gate bipolar transistor is obvious, so that the drift region of the insulated gate bipolar transistor has a breakdown voltage and forward voltage drop on the device. The impact is more compromised.
  • the drift region with a lower doping concentration can maintain the voltage resistance of the drift region at a thinner thickness.
  • a drift region with a higher doping concentration will weaken the conductance modulation effect and cannot guarantee a conductive path, making the insulated gate bipolar transistor unable to work normally. Therefore, in order to obtain a compromise relationship between the withstand voltage and the conduction voltage drop, the doping concentration of the first doping region and the second doping region in the drift region should not be too high.
  • the distribution of carriers injected into the drift region can be changed, reducing the accumulation of carriers near the contact surface between the first doping region and the body region, and reducing the turn-off time ;
  • the second doped region By setting the second doped region, the overall doping concentration of the drift region will not be too high, and the compromise relationship between withstand voltage and conduction voltage drop is ensured.
  • the doping concentration of the first region is 1*10 19 cm -3 to 1*10 20 cm -3 ; the doping concentration of the second region is 1*10 18 cm -3 to 1*10 19 cm -3 .
  • the doping concentration of the second doping region is 1*10 17 cm -3 to 1*10 18 cm -3 .
  • the volume ratio and doping concentration of the first doped region and the second doped region can be adjusted to further optimize the turn-on voltage drop and turn-off time of the insulated gate bipolar transistor.
  • the embodiment of the present disclosure provides a manufacturing method of an insulated gate bipolar transistor, including:
  • drift region including a first doping region and a second doping region with the same doping type; wherein the doping concentration of the first doping region is greater than the doping concentration of the second doping region;
  • a first part of the body region is formed above the first doped region, and a second part of the body region is formed above the second doped region; wherein the doping type of the body region is related to the drift The doping type of the zone is different;
  • a gate region is formed above the second part.
  • the method of forming a drift region including a first doped region and a second doped region of the same doping type may include: forming a drift region on one surface of a semiconductor substrate by ion implantation, and By implanting ions of different concentrations, a first doping region and a second doping region are formed in the drift region; wherein the doping concentration of the first doping region is greater than that of the second doping region.
  • the forming the drift region including the first doped region and the second doped region with the same doping type includes:
  • a plurality of doped regions with different doping concentrations are formed to form the second doped region.
  • the forming the drift region including the first doped region and the second doped region with the same doping type includes:
  • Forming the first doped region including a first region and a second region; wherein the first region is located above the second region, and the doping concentration of the first region is greater than that of the second region Miscellaneous concentration.
  • Fig. 7 shows a schematic structural diagram of an insulated gate bipolar transistor.
  • the insulated gate bipolar transistor includes: collector metal 0, P+ collector region 1, N-type main drift region 2, N+ type doped region 3, N-type transfer region 4, P-type body region 5, N+ emitter Polar region 6, emitter metal 7, gate layer 8, gate metal 9.
  • a positive sign (+) indicates a higher doping concentration
  • a negative sign (-) indicates a lower doping concentration.
  • regions with different doping concentrations are set in the drift region, that is, an N-type transfer region, an N-type main drift region, and an N+-type barrier region are formed to ensure the lower part of the P-type body region cell
  • the N-type doping concentration is higher than the N-type doping concentration near the MOS channel part, which can effectively increase the recombination efficiency of holes in the drift region during turn-off, reduce the turn-off time, and thereby reduce the turn-off loss.
  • this structure also promotes the movement of holes in the collector region to the gate layer, ensures a conductive channel for conduction, and ensures a lower conduction loss.
  • the insulated gate bipolar transistor may be a conventional planar gate structure, a trench gate structure, a punch-through structure (PT structure), a field stop-trench structure (FS-Trench structure), and the like.

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Abstract

本公开实施例公开一种绝缘栅双极型晶体管及其制作方法，所述绝缘栅双极型晶体管包括：漂移区，所述漂移区包括掺杂类型相同的第一掺杂区和第二掺杂区；其中，所述第一掺杂区的掺杂浓度大于所述第二掺杂区的掺杂浓度；体区，与所述漂移区的掺杂类型不同的所述体区包括第一部分和第二部分；所述第一部分，位于所述第一掺杂区和发射极区之间，且与所述第一掺杂区接触；所述第二部分，位于所述第二掺杂区和栅极区之间，且与所述第二掺杂区接触。

Description

绝缘栅双极型晶体管及其制作方法
相关申请的交叉引用
本申请基于申请号为201910691521.9、申请日为2019年07月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开实施例涉及半导体技术领域但不限于半导体技术领域，特别涉及一种绝缘栅双极型晶体管及其制作方法。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，简称IGBT)是由双极型三极管(BJT)和绝缘栅型场效应管(MOSFET)组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET器件的高输入阻抗和电力晶体管(即巨型晶体管，简称GTR)的低导通压降两方面的优点，且驱动功率小而饱和压降低，被广泛应用到各个领域。
目前，仍没有合适的方法可以在降低导通压降的同时不增加关断时间，或在降低关断时间的同时不增加导通压降。
发明内容
本公开实施例提供一种绝缘栅双极型晶体管及其制作方法。
本公开实施例的第一方面提供一种绝缘栅双极型晶体管，包括：
漂移区，所述漂移区包括掺杂类型相同的第一掺杂区和第二掺杂区；其中，所述第一掺杂区的掺杂浓度大于所述第二掺杂区的掺杂浓度；
体区，与所述漂移区的掺杂类型不同的所述体区包括第一部分和第二部分；
所述第一部分，位于所述第一掺杂区和发射极区之间，且与所述第一掺杂区接触；
所述第二部分，位于所述第二掺杂区和栅极区之间，且与所述第二掺杂区接触。
在一些实施例中，所述第一掺杂区，配置为当所述绝缘栅双极型晶体管导通时，促进载流子向第二掺杂区移动；
和/或，
所述第一掺杂区，配置为当所述绝缘栅双极型晶体管关断时，复合所述漂移区中的载流子。
在一些实施例中，所述第一掺杂区包括多个不同掺杂浓度的掺杂区域；
和/或，
所述第二掺杂区包括多个不同掺杂浓度的掺杂区域。
在一些实施例中，所述第一掺杂区包括第一区域和第二区域，其中，第一区域位于第二区域上方，第一区域的掺杂浓度大于第二区域的掺杂浓度。
在一些实施例中，所述第一区域的掺杂浓度与所述第二区域的掺杂浓度的比值大于或等于10；
和/或，
所述第二区域的掺杂浓度与所述第二掺杂区的掺杂浓度的比值大于或等于10。
在一些实施例中，所述第一区域的掺杂浓度为1*10 19cm -3至1*10 20cm -3；所述第二区域的掺杂浓度为1*10 18cm -3至1*10 19cm -3。
根据一种实施例，所述第二掺杂区的掺杂浓度为1*10 17cm -3至 1*10 18cm -3。
本公开实施例第二方面提供一种绝缘栅双极型晶体管的制作方法，包括：
形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区；其中，所述第一掺杂区的掺杂浓度大于所述第二掺杂区的掺杂浓度；
在所述第一掺杂区上方形成体区的第一部分，在所述第二掺杂区的上方形成所述体区的第二部分；其中，所述体区的掺杂类型与所述漂移区的掺杂类型不同；
在所述第一部分上方形成发射极区；
在所述第二部分上方形成栅极区。
在一些实施例中，所述形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区，包括：
形成多个不同掺杂浓度的掺杂区域，形成所述第一掺杂区；
和/或，
形成多个不同掺杂浓度的掺杂区域，形成所述第二掺杂区。
在一些实施例中，所述形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区，包括：
形成包括第一区域和第二区域的所述第一掺杂区；其中，所述第一区域位于所述第二区域上方，所述第一区域的掺杂浓度大于所述第二区域的掺杂浓度。
通过本公开实施例提供的上述绝缘栅双极型晶体管及其制作方法，所述绝缘栅双极型晶体管包括漂移区，所述漂移区包括掺杂类型相同的第一掺杂区和第二掺杂区；其中，所述第一掺杂区的掺杂浓度大于所述第二掺杂区的掺杂浓度；体区，与所述漂移区的掺杂类型不同的所述体区包括第一部分和第二部分；所述第一部分，位于所述第一掺杂区和发射极区之间， 且与所述第一掺杂区接触；所述第二部分，位于所述第二掺杂区和栅极区之间，且与所述第二掺杂区接触，因为第一掺杂区的掺杂浓度高于第二掺杂区，因此可促进注入第一掺杂区中的载流子向第二掺杂区运动，提高了注入第二掺杂区的载流子浓度与第二掺杂区自身载流子浓度之间的差值，增强了第二掺杂区的电导调制效应，减小绝缘栅双极型晶体管的导通压降；此外，掺杂浓度高的第一掺杂区在关断时可提高载流子的复合效率，减小关断时间，降低关断损耗，所以，本公开实施例提供的绝缘栅双极型晶体管可获得较好的导通压降和关断时间的折中关系，使其导通压降和关断时间均较低。
附图说明
图1为本公开实施例提供的一种绝缘栅双极晶体管的示意图；
图2为本公开实施例提供的一种绝缘栅双极晶体管的结构示意图；
图3为本公开实施例提供的另一种绝缘栅双极型晶体管的结构示意图；
图4为本公开实施例提供的一种不同掺杂浓度的掺杂区域之间的能带示意图；
图5为本公开实施例提供的又一种绝缘栅双极型晶体管的结构示意图；
图6为本公开实施例提供的又一种绝缘栅双极型晶体管的结构示意图；
图7为本公开实施例提供的又一种绝缘栅双极型晶体管的结构示意图。
具体实施方式
以下结合说明书附图及具体实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施方式的目的。除非特别说明或者指出，否则本公开中的术语“第一”、“第二”等描述仅用于区分本公开中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。
若本公开实施例中涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态(诸如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变，则该方向性指示也相应的随之改变。在本公开实施例中，术语“A在B之上/下”意味着包含A、B两者相互接触地一者在另一者之上/下的情形，或者A、B两者之间还间插有其他部件而一者非接触地位于另一者之上/下的情形。
需要说明的是，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
如图1所示，本公开实施例提供一种绝缘栅双极型晶体管，包括：
漂移区10，所述漂移区10包括掺杂类型相同的第一掺杂区110和第二掺杂区120；其中，所述第一掺杂区110的掺杂浓度大于所述第二掺杂区120的掺杂浓度；
体区20，与所述漂移区10的掺杂类型不同的所述体区20包括第一部分210和第二部分220；
所述第一部分210，位于所述第一掺杂区110和发射极区30之间，且与所述第一掺杂区110接触；
所述第二部分220，位于所述第二掺杂区120和栅极区40之间，且与所述第二掺杂区120接触。
在本公开实施例中，所述第一掺杂区和第二掺杂区的掺杂类型相同， 其掺杂类型可为受主掺杂或施主掺杂。当第一掺杂区和第二掺杂区为受主掺杂时，第一掺杂区和第二掺杂区的多数载流子为空穴，体区的掺杂类型为施主掺杂，体区的多数载流子为电子。当第一掺杂区和第二掺杂区为施主掺杂时，第一掺杂区和第二掺杂区的多数载流子为电子，体区的掺杂类型为受主掺杂，体区的多数载流子为空穴。此处的多数载流子为：单位体积内数量更多的载流子。
在本公开实施例中，所述掺杂浓度为掺杂产生的载流子的浓度。在一些实施例中，所述第一掺杂区，配置为当所述绝缘栅双极型晶体管导通时，促进载流子向第二掺杂区移动；
和/或，
所述第一掺杂区，配置为当所述绝缘栅双极型晶体管关断时，复合所述漂移区中的载流子。
下面以第一掺杂区和第二掺杂区的掺杂类型为施主掺杂，体区的掺杂类型为受主掺杂为例，具体说明绝缘栅双极型晶体管的工作过程。
给绝缘栅双极型晶体管的栅极加正向电压，电子从发射极区流出，流入漂移区，在体区第二部分靠近栅极区附近形成沟道，同时集电极区也会在正向电压的作用下向漂移区注入空穴，随着导通电流的增大，发射极区注入漂移区的电子浓度增大。为了维持漂移区的电中性，由集电极区注入到漂移区的空穴载流子浓度也会增大，使原本电阻值较高的漂移区内聚集了大量的电子和空穴导电载流子，增加了漂移区的电导率，降低了绝缘栅双极型晶体管的正向导通压降。
绝缘栅双极型晶体管在关断时，栅极电压由正值下降为零或负值，因此由发射极区向漂移区注入电子的路径被切断，绝缘栅双极型晶体管中电子电流迅速减小；而正向导通状态时存储在漂移区中的空穴却难以被快速抽取走，尤其是在体区第一部分与漂移区接触面附近，所述接触面附近的 电子浓度低，当注入漂移区的空穴浓度较大时，所述接触面附近聚集的空穴会使得绝缘栅双极型晶体管在关断过程中拖尾电流存在时间较长，延长了绝缘栅双极型晶体管的关断时间，增大了器件的关断损耗。
下面以第一掺杂区和第二掺杂区的掺杂类型为受主掺杂，体区的掺杂类型为施主掺杂为例，说明绝缘栅双极型晶体管的工作过程。
给绝缘栅双极型晶体管的栅极加负向电压，空穴从发射极区流出，流入漂移区，在体区第二部分靠近栅极区附近形成沟道，同时集电极区也会在负向电压的作用下向漂移区注入电子，随着导通电流的增大，发射极区注入漂移区的空穴浓度增大。为了维持漂移区的电中性，由集电极区注入到漂移区的电子浓度也会增大，使原本电阻值较高的漂移区内聚集了大量的电子和空穴导电载流子，增加了漂移区的电导率，降低了绝缘栅双极型晶体管的导通压降。
绝缘栅双极型晶体管在关断时，栅极电压由负值变为零或正值，因此由发射极区向漂移区注入空穴的路径被切断，绝缘栅双极型晶体管中空穴电流迅速减小；而导通状态时存储在漂移区中的电子却难以被快速抽取走，尤其是在体区第一部分与漂移区接触面附近，所述接触面附近的空穴浓度低，当注入漂移区的电子浓度较大时，所述接触面附近聚集的电子会使得绝缘栅双极型晶体管在关断过程中拖尾电流存在时间较长，延长了绝缘栅双极型晶体管的关断时间，增大了器件的关断损耗。
为了实现较低导通压降和较低关断时间的折中，在本公开实施例通过在漂移区中设置掺杂类型相同的第一掺杂区和第二掺杂区，且第一掺杂区的掺杂浓度大于第二掺杂区的掺杂浓度，可促进漂移区注入第一掺杂区的载流子向第二掺杂区移动，提高了导通时第二掺杂区中载流子浓度，保证了导电通路，减小了绝缘栅双极性晶体管的导通压降；并且，由于漂移区注入第一掺杂区的载流子会向第二掺杂区移动，减少了第一掺杂区与体区 接触面附近关断时需要复合的载流子浓度，减少了关断时间，降低了关断损耗。
在一些实施例中，所述第一掺杂区可包括单个单一浓度掺杂区域或多个不同掺杂浓度的掺杂区域。
在本实施例中，当所述第一掺杂区包括多个不同掺杂浓度的掺杂区域时，多个不同掺杂浓度的掺杂区域可如图2所示，在平行于栅极区的方向上层叠设置；多个不同掺杂浓度的掺杂区域也可如图3所示，在垂直于栅极区的方向上依次设置。
在本公开实施例中，当第一掺杂区包括三个不同掺杂浓度的掺杂区域111、掺杂区域112、掺杂区域113，且三个不同掺杂浓度的掺杂区域如图2所示设置时，掺杂区域111的掺杂浓度大于掺杂区域112的掺杂浓度，掺杂区域112的掺杂浓度大于掺杂区域113的掺杂浓度。
在本公开实施例中，当第一掺杂区包括三个不同掺杂浓度的掺杂区域114、掺杂区域115、掺杂区域116，且三个不同掺杂浓度的掺杂区域如图3所示设置时，掺杂区域114的掺杂浓度大于掺杂区域115的掺杂浓度，掺杂区域115的掺杂浓度大于掺杂区域116的掺杂浓度。
如图4所示，在本公开实施例中，当第一掺杂区包括三个不同掺杂浓度的掺杂区域111、掺杂区域112、掺杂区域113，且三个不同掺杂浓度的掺杂区域如图2所示设置时，由于掺杂区域111的掺杂浓度大于第二掺杂区120的掺杂浓度，使得掺杂区域111的费米能级与导带底之间的距离，小于第二掺杂区120的费米能级与导带底之间的距离，在掺杂区域111与第二掺杂区120处于热平衡状态后，掺杂区域111与第二掺杂区120具有统一的费米能级，位于掺杂区域111价带顶附近的空穴的电势能高于位于第二掺杂区120价带顶附近的空穴，一方面，阻止了第二掺杂区120中的空穴向掺杂区域111运动，减少了掺杂区域111与体区第二部分210的界面 处空穴的聚集数量，缩短了关断时间，降低了关断损耗；另一方面，促进了掺杂区域111中的空穴向第二掺杂区120移动，增加了第二掺杂区120中的空穴浓度，保证了导电通路，降低了导通压降。
在本公开实施例中，基于上述类似的原理，通过在第一掺杂区110中如图2所示设置掺杂浓度依次降低的掺杂区域111、掺杂区域112、掺杂区域113，可阻止空穴进入掺杂区域111，减少了在第一掺杂区与体区接触面附近的空穴数量，减少了关断时间和关断损耗，并促使进入第一掺杂区的空穴向第二掺杂区运动，增加了第二掺杂区中的空穴注入效率，保证了导电通路，降低了导通压降。
在本公开实施例中，通过在第一掺杂区110中如图3所示设置掺杂浓度依次降低的掺杂区域114、掺杂区域115、掺杂区域116，可促使进入第一掺杂区的空穴向第二掺杂区运动，增加了第二掺杂区中的空穴注入效率，保证了导电通路，降低了导通压降。
在另一些实施例中，所述第二掺杂区可包括单个单一浓度掺杂区域或多个不同掺杂浓度的掺杂区域。
在本公开实施例中，当第二掺杂区120包括多个不同掺杂浓度的掺杂区域时，所述多个不同掺杂浓度的掺杂区域可如图5所示，在垂直于栅极区40方向上依次层叠设置；所述多个不同掺杂浓度的掺杂区域也可如图6所示，在平行于栅极区40的方向上依次设置。
在本公开实施例中，当第二掺杂区包括如图5所示设置的三个不同掺杂浓度的掺杂区域121、掺杂区域122、掺杂区域123时，掺杂区域123的掺杂浓度大于掺杂区域122的掺杂浓度，掺杂区域122的掺杂浓度大于掺杂区域121的掺杂浓度。
在本公开实施例中，当第二掺杂区包括如图6所示设置的三个不同掺杂浓度的掺杂区域124、掺杂区域125、掺杂区域126时，掺杂区域126的 掺杂浓度大于掺杂区域125的掺杂浓度，掺杂区域125的掺杂浓度大于掺杂区域124的掺杂浓度。
根据上述通过漂移区掺杂浓度影响漂移区中空穴运动的分析可知，通过在第二掺杂区120中设置掺杂浓度依次降低的掺杂区域123、掺杂区域122、掺杂区域121，或过在第二掺杂区120中设置掺杂浓度依次降低的掺杂区域126、掺杂区域125、掺杂区域124，可促使空穴从第一掺杂区向第二掺杂区运动，增加了第二掺杂区中的空穴注入效率，保证了导电通路，降低了导通压降，且降低了第一掺杂区中的空穴浓度，减少了关断时间和关断损耗。
为了便于在生产过程中分别准确控制第一掺杂区与第二掺杂区的掺杂浓度，第一掺杂区中多个不同掺杂浓度的掺杂区域体积相同，第二掺杂区中多个不同掺杂浓度的掺杂区域体积相同。
在一些实施例中，所述第一区域的掺杂浓度与所述第二区域的掺杂浓度的比值大于或等于10；
和/或，
所述第二区域的掺杂浓度与所述第二掺杂区的掺杂浓度的比值大于或等于10。
绝缘栅双极性晶体管在正向阻断时，主要依靠漂移区来承担正向阻断电压，漂移区的电阻率和厚度越大，器件的正向阻断电压越高，器件的耐压性能越好，但是也增大了器件的正向压降，因此需要折中考虑。当注入漂移区的载流子浓度大于其本身的掺杂浓度时，由于绝缘栅双极型晶体管内部的电导调制效果明显，使得绝缘栅双极型晶体管漂移区对器件的耐压和正向压降的影响较为折中。此外，较低掺杂浓度的漂移区能在更薄的厚度下，保持漂移区耐压能力不变。较高掺杂浓度的漂移区会减弱电导调制效应，无法保证导电通路，使得绝缘栅双极型晶体管无法正常工作。因此， 为了获得耐压能力和导通压降的折中关系，漂移区中第一掺杂区和第二掺杂区的掺杂浓度不宜过高。
在漂移区中，通过设置第一掺杂区，可以改变注入漂移区中载流子的分布状况，减少聚集在第一掺杂区和体区接触面附近的载流子聚集，减少关断时间；通过设置第二掺杂区，使得漂移区的整体掺杂浓度不会过高，保证了耐压能力和导通压降的折中关系。
在一些实施例中，所述第一区域的掺杂浓度为1*10 19cm -3至1*10 20cm -3；所述第二区域的掺杂浓度为1*10 18cm -3至1*10 19cm -3。
在本公开实施例中，可以通过调节第一掺杂区的第一区域和第二区域的体积比例、掺杂浓度大小等，进一步优化绝缘栅双极型晶体管的导通压降和关断时间。
在一些公开实施例中，所述第二掺杂区的掺杂浓度为1*10 17cm -3至1*10 18cm -3。
在本实施例中，可以通过调节第一掺杂区、第二掺杂区的体积比例、掺杂浓度大小等，进一步优化绝缘栅双极型晶体管的导通压降和关断时间。
本公开实施例提供一种绝缘栅双极型晶体管的制作方法，包括：
形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区；其中，所述第一掺杂区的掺杂浓度大于所述第二掺杂区的掺杂浓度；
在所述第一掺杂区上方形成体区的第一部分，在所述第二掺杂区的上方形成所述体区的第二部分；其中，所述体区的掺杂类型与所述漂移区的掺杂类型不同；
在所述第一部分上方形成发射极区；
在所述第二部分上方形成栅极区。
在本公开实施例中，所述形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区的方法可包括：在半导体衬底的一个表面通过离子注入形 成漂移区区，并通过注入不同浓度的离子，在漂移区形成第一掺杂区和第二掺杂区；其中，第一掺杂区的掺杂浓度大于第二掺杂区的掺杂浓度。
在一些实施例中，所述形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区，包括：
形成多个不同掺杂浓度的掺杂区域，形成所述第一掺杂区；
和/或，
形成多个不同掺杂浓度的掺杂区域，形成所述第二掺杂区。
在一些实施例中，所述形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区，包括：
形成包括第一区域和第二区域的所述第一掺杂区；其中，所述第一区域位于所述第二区域上方，所述第一区域的掺杂浓度大于所述第二区域的掺杂浓度。
示例1
图7示出了一种绝缘栅双极型晶体管的结构示意图。所述绝缘栅双极型晶体管包括：集电极金属0，P+集电极区1，N-型主漂移区2，N+型掺杂区3，N型转移区4，P型体区5，N+发射极区6，发射极金属7，栅极层8，栅极金属9。其中，正号(+)表示掺杂浓度较高，负号(-)表示掺杂浓度较低。
在本示例中，通过离子注入的方法，在漂移区设置不同掺杂浓度的区域，即形成N型转移区，N-型主漂移区，N+型阻挡区，保证P型体区元胞下面部分的N型掺杂浓度高于靠近MOS沟道部分的N型掺杂浓度，能够在关断时有效增加漂移区中空穴的复合效率，减少关断时间，从而降低关断损耗。同时，该结构也促进了集电极区的空穴向栅极层运动，保证了导通的导电沟道，保证了较低的导通损耗。
在一些实施例中，所述绝缘栅双极型晶体管可为常规平面栅结构、沟 槽栅结构、穿通结构(PT结构)、场终止-沟槽结构(FS-Trench结构)等。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。

Claims (10)

  1. 一种绝缘栅双极型晶体管，包括：
    漂移区，所述漂移区包括掺杂类型相同的第一掺杂区和第二掺杂区；其中，所述第一掺杂区的掺杂浓度大于所述第二掺杂区的掺杂浓度；
    体区，与所述漂移区的掺杂类型不同的所述体区包括第一部分和第二部分；
    所述第一部分，位于所述第一掺杂区和发射极区之间，且与所述第一掺杂区接触；
    所述第二部分，位于所述第二掺杂区和栅极区之间，且与所述第二掺杂区接触。
  2. 根据权利要求1所述的绝缘栅双极型晶体管，其中，
    所述第一掺杂区，配置为当所述绝缘栅双极型晶体管导通时，促进载流子向第二掺杂区移动；
    和/或，
    所述第一掺杂区，配置为当所述绝缘栅双极型晶体管关断时，复合所述漂移区中的载流子。
  3. 根据权利要求1所述的绝缘栅双极型晶体管，其中，
    所述第一掺杂区包括多个不同掺杂浓度的掺杂区域；
    和/或，
    所述第二掺杂区包括多个不同掺杂浓度的掺杂区域。
  4. 根据权利要求1所述的绝缘栅双极型晶体管，其中，
    所述第一掺杂区包括第一区域和第二区域，其中，第一区域位于第二区域上方，第一区域的掺杂浓度大于第二区域的掺杂浓度。
  5. 根据权利要求4所述的绝缘栅双极型晶体管，其中，
    所述第一区域的掺杂浓度与所述第二区域的掺杂浓度的比值大于或 等于10；和/或，
    所述第二区域的掺杂浓度与所述第二掺杂区的掺杂浓度的比值大于或等于10。
  6. 根据权利要求4至5任一项所述的绝缘栅双极型晶体管，其中，
    所述第一区域的掺杂浓度为1*10 19cm -3至1*10 20cm -3；
    所述第二区域的掺杂浓度为1*10 18cm -3至1*10 19cm -3。
  7. 根据权利要求1至5任一项所述的绝缘栅双极型晶体管，其中，
    所述第二掺杂区的掺杂浓度为1*10 17cm -3至1*10 18cm -3。
  8. 一种绝缘栅双极型晶体管的制作方法，包括：
    形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区；其中，所述第一掺杂区的掺杂浓度大于所述第二掺杂区的掺杂浓度；
    在所述第一掺杂区上方形成体区的第一部分，在所述第二掺杂区的上方形成所述体区的第二部分；其中，所述体区的掺杂类型与所述漂移区的掺杂类型不同；
    在所述第一部分上方形成发射极区；
    在所述第二部分上方形成栅极区。
  9. 根据权利要求8所述的制作方法，其中，所述形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区，包括：
    形成多个不同掺杂浓度的掺杂区域，形成所述第一掺杂区；
    和/或，
    形成多个不同掺杂浓度的掺杂区域，形成所述第二掺杂区。
  10. 根据权利要求8所述的制作方法，其中，所述形成包括掺杂类型相同的第一掺杂区和第二掺杂区的漂移区，包括：
    形成包括第一区域和第二区域的所述第一掺杂区；其中，所述第一区域位于所述第二区域上方，所述第一区域的掺杂浓度大于所述第二区 域的掺杂浓度。
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