WO2021011412A1 - Systems and methods for simulating a quantum processor - Google Patents

Systems and methods for simulating a quantum processor Download PDF

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Publication number
WO2021011412A1
WO2021011412A1 PCT/US2020/041703 US2020041703W WO2021011412A1 WO 2021011412 A1 WO2021011412 A1 WO 2021011412A1 US 2020041703 W US2020041703 W US 2020041703W WO 2021011412 A1 WO2021011412 A1 WO 2021011412A1
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WO
WIPO (PCT)
Prior art keywords
processor
representation
digital
waveform
quantum processor
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Ceased
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PCT/US2020/041703
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English (en)
French (fr)
Inventor
Mark W. Johnson
Mauricio REIS FILHO
Mark H. VOLKMANN
Ilya V. PERMINOV
Paul I. Bunyk
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D Wave Systems Inc
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D Wave Systems Inc
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Priority to JP2021571752A priority Critical patent/JP7600149B2/ja
Priority to EP20841331.0A priority patent/EP3997608A4/en
Priority to US17/617,388 priority patent/US12373719B2/en
Publication of WO2021011412A1 publication Critical patent/WO2021011412A1/en
Anticipated expiration legal-status Critical
Priority to JP2024211842A priority patent/JP2025036440A/ja
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/80—Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J3/00—Systems for conjoint operation of complete digital and complete analogue computers

Definitions

  • a common problem Hamiltonian includes a first component proportional to diagonal single qubit terms and a second component proportional to diagonal multiqubit terms, and may be of the following form:
  • a device connectivity representation is generated manually from the intent of a design and the correctness of the device connectivity representation is validated by testing processor structures after fabrication.
  • manual validation methods are time-consuming and highly susceptible to errors.
  • manual validation methods require fabricated processors which are expensive and unsuitable for design verification.
  • Quantum processor calibration can involve calibration rules that are used for dependency resolution and to track progress.
  • calibration rules require describing and validating relationships between programmable devices, device connectivity, and bias mechanisms.
  • One approach is to generate a suitable representation of such data and quantities is to devise a data structure for each calibration rule independently.
  • designing a suitable data structure for each calibration algorithm is time-consuming, especially if there is significant overlap in requirements for a set of calibration algorithms.
  • designing a suitable persistence and version control mechanism for each calibration algorithm is time- consuming, inefficient, and error prone.
  • Aspect 4 The method of aspect 1 wherein identifying a subset of the set of channels in the device connectivity representation includes identifying a subset of the set of channels representing a subset of the set of programmable devices communicatively coupled to a subset of the set of control lines in the quantum processor topology.
  • a method of simulating a quantum processor including a set of programmable devices communicatively coupled to a set of control lines, each one of the set of control lines operable to apply a bias to at least one of the set of programmable devices, the method executed by a digital processor, may be summarized as comprising: generating a digital waveform representation; decomposing the digital waveform representation into a set of waveform values based on a device connectivity representation comprising a set of channels; identifying a subset of the set of channels in the device connectivity representation; selecting a subset of the set of waveform values corresponding to the subset of the set of channels; setting a plurality of physical parameter values characterizing at least one of the set of programmable devices of the quantum processor; and computing a response via a representation model.
  • Aspect 23 The method of aspect 15 wherein computing a response via a representation model includes computing a response based on the plurality of physical parameter values and the subset of the set of waveform values.
  • Aspect 24 The method of aspect 15 wherein computing a response via a representation model includes computing a set of output values.
  • Aspect 25. The method of aspect 15 may further comprise: converting the response into a classical state.
  • a method of extracting a device object model from an integrated circuit layout may be summarized as comprising autonomously by the digital processor: extracting a device schematic from a design schematic; extracting device connectivity data from the device schematic; writing the device connectivity data to a device connectivity representation; extracting a set of biases from the device connectivity data; and writing the set of biases to the device connectivity representation.
  • Aspect 30 The method of aspect 28 wherein extracting a device schematic from a design schematic includes extracting a device schematic corresponding to a directed acyclic graph.
  • the method of aspect 30 wherein extracting a device schematic corresponding to a directed acyclic graph includes extracting a device schematic comprising at least one atomic device node corresponding to a directed acyclic graph.
  • the method of aspect 28 wherein extracting the device connectivity data includes extracting at least one of: a device specification, a property annotation, and at least one neighboring device connection.
  • Aspect 40 The method of aspect 37 wherein identifying a set of rules includes identifying a set of rules checking a number of control devices.
  • waveform 112 follows a sequence illustrated by the dashed arrows in Figure 1. If a problem is to be solved on digital processor 102, waveform 1 12 follows a sequence illustrated by the solid arrows in Figure 1. The sequence illustrated by the solid arrows is described immediately below.
  • Digital processor 102 uses representation model 126 to compute a response in the form of a set of output values 130 based on physical parameter values 114 and waveform values 120.
  • representation model 126 characterizes or represents a respective response of an individual programmable device 118.
  • representation model 126 characterizes a response of multiple programmable devices 118.
  • Annealing parameters of a programmable device can be derived from output values 130.
  • Annealing parameters can provide information about energy scales of quantum processor 106. For example, annealing parameters such as a tunneling energy and a persistent current of a qubit can be derived from output values 130.
  • quantum processor 106 is a theoretical quantum processor or a quantum processor design. In some

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computational Mathematics (AREA)
  • Artificial Intelligence (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
PCT/US2020/041703 2019-07-12 2020-07-10 Systems and methods for simulating a quantum processor Ceased WO2021011412A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2021571752A JP7600149B2 (ja) 2019-07-12 2020-07-10 量子プロセッサをシミュレートするシステム及び方法
EP20841331.0A EP3997608A4 (en) 2019-07-12 2020-07-10 SYSTEMS AND METHODS FOR SIMULATING A QUANTUM PROCESSOR
US17/617,388 US12373719B2 (en) 2019-07-12 2020-07-10 Systems and methods for simulating a quantum processor
JP2024211842A JP2025036440A (ja) 2019-07-12 2024-12-04 量子プロセッサをシミュレートするシステム及び方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962873711P 2019-07-12 2019-07-12
US62/873,711 2019-07-12
US201962879946P 2019-07-29 2019-07-29
US62/879,946 2019-07-29

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EP (1) EP3997608A4 (https=)
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WO (1) WO2021011412A1 (https=)

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