WO2021007883A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2021007883A1
WO2021007883A1 PCT/CN2019/097728 CN2019097728W WO2021007883A1 WO 2021007883 A1 WO2021007883 A1 WO 2021007883A1 CN 2019097728 W CN2019097728 W CN 2019097728W WO 2021007883 A1 WO2021007883 A1 WO 2021007883A1
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WIPO (PCT)
Prior art keywords
film transistor
thin film
gate
goa circuit
goa
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PCT/CN2019/097728
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English (en)
French (fr)
Inventor
薛炎
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2021007883A1 publication Critical patent/WO2021007883A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit.
  • AMOLED (active matrix organic light-emitting diode) display panel horizontal scanning lines are driven by an external integrated circuit.
  • the external integrated circuit can control the step-by-step turn-on of the row scanning lines at all levels, and the array substrate row drive ( GOA (Gate Driver on Array) method can integrate the line scan driving circuit on the display panel substrate, which can reduce the number of external chips (IC), thereby reducing the production cost of the display panel, and can realize the narrow frame of the display device .
  • Indium gallium zinc oxide (IGZO) has high mobility and good device stability, and is currently widely used in indium gallium zinc oxide GOA (IGZO-GOA) circuits.
  • the IGZO-GOA circuit can be used in the design of LCD display panels and OLED display panels.
  • IGZO-TFT Indium Gallium Zinc Oxide Thin Film Transistor
  • process fluctuations will affect the uniformity of the overall panel threshold voltage Vth.
  • IGZO-TFT is affected by external conditions such as electrical stress, light, and temperature variation.
  • the threshold voltage Vth of the device is prone to shift.
  • TFT Thin Film Transistor
  • the number of) is large (usually more than 20), which is not conducive to the narrow frame of the display panel, which is inconsistent with the original intention of the GOA circuit.
  • the single-stage GOA unit consists of six TFTs T1, T2, T31, T32, T41, and T42 and
  • the storage capacitor Cbt is composed of node Q and node QB, and outputs the n-th level horizontal scanning signal G(n); clock signal CK1, clock signal CK2, DC high voltage VGH, DC low voltage VGL, and n-th stage transfer signal
  • the level 1 horizontal scanning signal G (n-1) is input to the GOA unit.
  • the principle of the GOA circuit is correct, the circuit does not have the function of preventing the variation of the threshold voltage Vth.
  • the Q point in the GOA circuit is the gate point of the TFT that controls the high level of the output signal.
  • the Q point is at the high level, the TFT is in the on state and the output signal remains at the high level. Therefore, in the actual working process, the ability to maintain the potential of the Q point is the key to ensuring the stable output of the GOA circuit.
  • FIG 2 is a timing diagram of the circuit shown in Figure 1, showing the output of the circuit. It can be seen from the figure that because the circuit is not equipped with a sub-circuit to prevent the negative bias of the threshold voltage Vth, the potential at the Q point is coupled (couple) At this stage, the potential of point Q is difficult to maintain and gradually decreases. Although the output signal G(n) is still valid, if the threshold voltage Vth of the TFT is negatively biased during the operation of the GOA circuit, the GOA circuit is prone to failure. In addition, the operating pulse width of the GOA circuit in Figure 1 is 15 microseconds (us). Currently, the pixel circuits of AMOLED display panels mainly adopt external compensation methods. External compensation requires millisecond (ms) ultra-wide pulses, because the Q point potential cannot be maintained. , The simplest GOA circuit cannot meet the wide pulse requirement of GOA circuit. Therefore, this circuit is not feasible.
  • ms millisecond
  • the object of the present invention is to provide a GOA circuit that reduces the space occupied by the GOA circuit layout and compensates for the unevenness and variation of the threshold voltage Vth of the TFT in the GOA circuit.
  • the present invention provides a GOA circuit, which includes a plurality of cascaded GOA units, where n is a natural number, and the nth level GOA unit responsible for outputting the nth level horizontal scanning signal includes:
  • the first thin film transistor the gate of which is connected to the first clock signal, and the source and drain are respectively connected to the stage transmission signal from the GOA unit of the previous stage and the first node;
  • the gate of the second thin film transistor is connected to the first node, and the source and drain are respectively connected to the second clock signal and the n-th level horizontal scanning signal output terminal;
  • the third thin film transistor the gate of which is connected to the power supply high voltage, and the source and drain are respectively connected to the power supply high voltage and the second node;
  • a fourth thin film transistor the gate of which is connected to the first node, and the source and drain are respectively connected to the second node and the DC low voltage;
  • a fifth thin film transistor the gate of which is connected to the second node, and the source and drain are respectively connected to the nth level horizontal scanning signal output terminal and the DC low voltage;
  • a sixth thin film transistor the gate of which is connected to the second node, and the source and drain are respectively connected to the first node and the DC low voltage;
  • a storage capacitor both ends of which are respectively connected to the first node and the n-th level horizontal scanning signal output terminal;
  • At least one of the first thin film transistor, the second thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor is a double gate thin film transistor, and the top gate of the double gate thin film transistor serves as The gate is connected to the GOA unit, and the bottom gates of the double-gate thin film transistor are respectively connected to the corresponding potential adjustable bottom gate voltage.
  • the fifth thin film transistor and the sixth thin film transistor are double gate thin film transistors, the bottom gate of which is connected to the first bottom gate voltage.
  • the first thin film transistor is a double gate thin film transistor, and its bottom gate is connected to a second bottom gate voltage.
  • the fourth thin film transistor is a double gate thin film transistor, and its bottom gate is connected to the third bottom gate voltage.
  • the second thin film transistor is a double gate thin film transistor, and its bottom gate is connected to a fourth bottom gate voltage.
  • the nth level horizontal scanning signal is input to the next-level GOA unit as a level transmission signal.
  • the start signal is used as the level transmission signal from the previous level GOA unit.
  • the GOA circuit is an indium gallium zinc oxide GOA circuit.
  • the first clock signal and the second clock signal have the same waveform, the duty cycle is one third, and the phase difference is one third period.
  • the bottom gate voltage is intelligently adjusted once.
  • the GOA circuit of the present invention can reduce the space occupied by the GOA circuit layout, is beneficial to narrow the frame of the display screen, and can compensate for the unevenness and variation of the threshold voltage Vth of the TFT in the GOA circuit, so that the reliability of the GOA circuit is improved; Realize that the threshold voltage Vth of the TFT in the GOA circuit can be adjusted; realize the independent control of the threshold voltage Vth of each TFT; ensure that the threshold voltage Vth of the TFT in the GOA circuit can be compensated in real time, and ensure that the output of the GOA circuit is good.
  • FIG. 1 is a schematic diagram of a single-stage GOA unit structure of a conventional GOA circuit
  • Figure 2 is a timing diagram of the circuit shown in Figure 1;
  • FIG. 3 is a schematic diagram of a single-stage GOA unit structure of a preferred embodiment of the GOA circuit of the present invention
  • FIG. 4 is a schematic diagram of adjusting the threshold voltage through the bottom gate voltage
  • FIG. 5 is a timing diagram of a preferred embodiment of the GOA circuit of the present invention.
  • FIG. 6 is a schematic diagram of the output effect of a preferred embodiment of the GOA circuit of the present invention.
  • FIG. 7 is a schematic diagram of the output effect of the simulation simulation of a preferred embodiment of the GOA circuit of the present invention.
  • FIG. 3 is a schematic diagram of a single-stage GOA unit structure of a preferred embodiment of the GOA circuit of the present invention.
  • the number of TFTs in the GOA unit is six.
  • the TFT can be designed with a double-gate TFT, and the top gate of the TFT can be used for connection In the GOA circuit, the bottom gate can be used to connect an external voltage source.
  • the present invention uses a set of CK clock signals (a total of three clock signals, CK1, CK2, CK3) for driving.
  • the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 have the same waveform, and the duty cycle is three minutes. One of them, and the phases are sequentially different by one-third of the period.
  • the GOA units of each stage input two corresponding clock signals according to the driving timing.
  • the single-stage GOA unit shown in Figure 3 uses the first clock signal CK1 and the second clock signal CK2 as As an example, in fact, the GOA units of each level of the GOA circuit respectively input two of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 to drive the GOA units of each level sequentially, and the previous one
  • the scan signal G(n-1) output by the n-1 level GOA unit is connected to the current level, the nth GOA unit, as the level transmission signal, and the current level is the scan signal G(n) output by the nth GOA unit
  • the start signal STV is connected as the level transmission signal to the first thin film transistor T1 of the first stage of the GOA circuit, and each GOA unit uses 2 direct current (DC) Signal DC high voltage VGH and DC low voltage VGL.
  • the nth level GOA unit responsible for outputting the nth level horizontal scanning signal G(n) includes:
  • the first thin film transistor T1 has its gate connected to the first clock signal CK1, and its source and drain are respectively connected to the stage transfer signal G(n-1) from the previous stage GOA unit and the first node Q; the nth stage horizontal scanning The signal G(n) is input into the next-stage GOA unit as a stage transmission signal;
  • the gate of the second thin film transistor T2 is connected to the first node Q, and the source and drain are respectively connected to the second clock signal CK2 and the n-th level horizontal scanning signal G(n) output terminal;
  • the gate of the third thin film transistor T31 is connected to the power supply high voltage VGH, and the source and drain are respectively connected to the power supply high voltage VGH and the second node QB;
  • the fourth thin film transistor T32 has its gate connected to the first node Q, and its source and drain are respectively connected to the second node QB and the DC low voltage VGL;
  • the fifth thin film transistor T41 has its gate connected to the second node QB, and its source and drain are respectively connected to the n-th level horizontal scanning signal G(n) output terminal and the DC low voltage VGL;
  • the sixth thin film transistor T42 has its gate connected to the second node QB, and its source and drain are respectively connected to the first node Q and the DC low voltage VGL;
  • the storage capacitor Cbt both ends of which are respectively connected to the first node Q and the n-th level horizontal scanning signal G(n) output terminal;
  • At least one of the first thin film transistor T1, the second thin film transistor T2, the fourth thin film transistor T32, the fifth thin film transistor T41, and the sixth thin film transistor T42 is a double gate thin film transistor.
  • the aforementioned The thin film transistors are all double-gate thin film transistors.
  • the top gates of the double-gate thin film transistors are connected to the GOA unit as the gates, and the bottom gates of the double-gate thin film transistors are connected to corresponding potentials. Adjusted bottom gate voltage;
  • the bottom gates of the fifth thin film transistor T41 and the sixth thin film transistor T42 are connected to the first bottom gate voltage V1; the bottom gate of the first thin film transistor T1 is connected to the second bottom gate voltage V2; the bottom gate of the fourth thin film transistor T32 The bottom gate is connected to the third bottom gate voltage V3; the bottom gate of the second thin film transistor T2 is connected to the fourth bottom gate voltage V4.
  • the aforementioned GOA circuit may be an indium gallium zinc oxide GOA circuit.
  • the threshold voltage Vth of the TFT is not only controlled by the top gate (the top gate is connected to the node in the GOA circuit), but also by the bottom gate (adjustable potential control).
  • the design can make the bottom gate realize the controllable threshold voltage Vth of the TFT, and realize the adjustable threshold voltage Vth of the TFT in the GOA circuit.
  • FIG 4 is a schematic diagram of adjusting the threshold voltage by the bottom gate voltage.
  • the horizontal axis represents the bottom gate voltage V BG (unit V)
  • the vertical axis represents the Log drain current (unit A)
  • the bottom gate voltage V BG of the TFT versus the threshold voltage of the TFT Vth is controllable.
  • each curve represents the curve when the top gate voltage V TG is 0V, 2V, 4V, 6V, 8V, 10V, and through the bottom gate
  • the corrected curve obtained by adjusting the threshold voltage of the voltage. If the threshold voltage Vth of the TFT is generally negative after the panel is produced, the bottom gate voltage can be adjusted negative. If the threshold voltage Vth of the TFT is positively biased, the bottom gate voltage can be adjusted positive, and this solution can realize the electrical controllability of the TFT.
  • T31 is basically not affected by voltage pressure. It can be approximated that the threshold voltage Vth of T31 will not shift, so there is no need to add bottom gates. The remaining 5 TFTs are all added with bottom gates to achieve controllable threshold voltage Vth; Different TFTs are subjected to different pressures.
  • T1 is subjected to 50% duty cycle Vgs AC pressure
  • T2 is subjected to Vds AC pressure
  • T32 is subjected to Vgs AC pressure
  • T41 and T42 are subjected to Vgs AC pressure conditions, which can be considered as the working process Among them, the offset of the threshold voltage Vth is the same; this design can add different bottom gate voltages V1 to V4 for different TFTs to achieve independent control of the threshold voltage Vth of each TFT.
  • This architecture can detect the output signal of the GOA circuit before the panel leaves the factory, and determine the electrical offset of the overall TFT and whether the bottom gate voltage needs to be adjusted according to the waveform of the output signal.
  • the GOA circuit can be programmed (pre-set) before the panel leaves the factory.
  • the bottom gate voltage is intelligently adjusted to ensure that the threshold voltage Vth of the TFT in the GOA circuit can be compensated in real time and the GOA is guaranteed The output of the circuit is good.
  • FIG. 5 is a timing diagram of a preferred embodiment of the GOA circuit of the present invention
  • the following table 1 is the signal amplitude of the preferred embodiment
  • FIG. 6 is a schematic diagram of the output effect of a preferred embodiment of the GOA circuit of the present invention
  • the waveforms of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are the same, the duty cycle is one third, and the phases are sequentially different by one third period.
  • the threshold voltage Vth of the TFT will be biased overall, Q The waveform of the point is improved.
  • the threshold voltage Vth of the TFT is more positive overall, and the waveform of the Q point is normal. Therefore, the bottom gate voltage can be set to -8V before leaving the factory. .
  • each level of GOA unit has only six TFTs, which not only greatly reduces the space occupied by the GOA circuit layout, but also facilitates the narrowing of the display screen, and can also compensate the threshold voltage Vth of the TFT in the GOA circuit Unevenness and variation improve the reliability of GOA circuits.
  • FIG. 7 it is a schematic diagram of the output effect of the simulation simulation of a preferred embodiment of the GOA circuit of the present invention.
  • the simulation circuit simulator (spice) simulation simulation of the GOA circuit of the preferred embodiment is very good.
  • the signal output Take the single-stage GOA circuit as an example, the factory voltage of the bottom gate of T1, T41 and T42 is set to -8V to illustrate the working process of the circuit.
  • S1 stage CK1 and G(n-1) rise to high potential, T1 opens, Q point rises to high potential, the high potential is stored in the storage capacitor Cbt, T2 and T32 are opened, because the TFT aspect ratio of T32 is much higher than that of T31 Large, QB outputs a low potential, and the output signal G(n) outputs a low potential.
  • S2 stage CK1 and G(n-1) fall to low potential, T1 is closed, CK2 rises from low potential to high potential, and the output signal G(n) rises to high potential. Due to the existence of the storage capacitor, the potential of point Q is coupled To a higher potential.
  • S3 stage CK1 and G(n-1) are at low potential, T1 remains closed, CK2 is reduced from high to low, T2 is turned on, output signal G(n) is pulled low to low, and Q point potential is coupled to high Potential.
  • the GOA circuit of the present invention can reduce the space occupied by the GOA circuit layout, is beneficial to narrow the frame of the display screen, and can compensate for the unevenness and variation of the threshold voltage Vth of the TFT in the GOA circuit, so that the reliability of the GOA circuit is improved; Realize that the threshold voltage Vth of the TFT in the GOA circuit can be adjusted; realize the independent control of the threshold voltage Vth of each TFT; ensure that the threshold voltage Vth of the TFT in the GOA circuit can be compensated in real time, and ensure that the output of the GOA circuit is good.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

本发明涉及一种GOA电路。该GOA电路包括多个级联的GOA单元，第n级GOA单元包括：第一薄膜晶体管（T1），第二薄膜晶体管（T2），第三薄膜晶体管（T31），第四薄膜晶体管（T32），第五薄膜晶体管（T41），第六薄膜晶体管（T42），以及存储电容（Cbt）；所述第一薄膜晶体管（T1）、第二薄膜晶体管（T2）、第四薄膜晶体管（T32）、第五薄膜晶体管（T41）以及第六薄膜晶体管（T42）中至少其中之一为双栅极薄膜晶体管，所述双栅极薄膜晶体管的顶栅分别作为所述栅极连接于所述GOA单元中，所述双栅极薄膜晶体管的底栅分别连接对应的电位可调的底栅电压。本发明的GOA电路能够实现GOA电路中TFT的阈值电压Vth可调节；实现每颗TFT的阈值电压Vth的独立控制。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
 背景技术
目前，AMOLED（有源矩阵型有机发光二极管）显示面板水平扫描线的驱动是由外接集成电路来实现的，外接集成电路可以控制各级行扫描线的逐级开启，而采用阵列基板行驱动 (GOA，Gate Driver on Array)方法，可以将行扫描驱动电路集成在显示面板基板上，能够减少外接芯片（IC）的数量，从而降低了显示面板的生产成本，并且能够实现显示装置的窄边框化。铟镓锌氧化物（IGZO）具有高的迁移率，和良好的器件稳定性，目前广泛的应用于铟镓锌氧化物GOA（IGZO-GOA）电路中。IGZO-GOA电路可运用于LCD显示面板和OLED显示面板的设计中。
在IGZO-TFT（铟镓锌氧化物薄膜晶体管）制程中，工艺波动会影响整体面板阈值电压Vth的均匀性，此外，IGZO-TFT受到电学压力（stress），光照及温度变异等外界条件干扰，器件阈值电压Vth较易发生偏移。综合以上因素，为保证GOA电路在阈值电压Vth不均匀或变异前提下能够正常工作，IGZO-GOA电路中需要设置很多的子电路，因而每级IGZO-GOA电路的设计较为复杂，TFT（薄膜晶体管）的数量众多（通常20个以上），这不利于显示面板的窄边框化，与GOA电路的设计初衷不符。
如图1所示，其为现有的设计中最简化的一种GOA电路的单级GOA单元结构示意图，该单级GOA单元由T1、T2、T31、T32、T41及T42共六颗TFT以及存储电容Cbt组成，具有节点Q和节点QB，输出第n级水平扫描信号G（n）；时钟信号CK1、时钟信号CK2、直流高电压VGH、直流低电压VGL以及作为级传信号的第n－1级水平扫描信号G（n－1）输入该GOA单元。尽管该GOA电路原理性正确，但是该电路不具备防止阈值电压Vth变异的功能，如果TFT的阈值电压Vth发生偏移或者TFT的阈值电压Vth均匀性较差，该电路就会失效。GOA电路中Q点是控制输出信号高电平的TFT栅极点，当Q点处于高电位时，TFT处于开启状态，输出信号保持高电位。因此，在实际工作过程中，Q点电位的维持能力是保证GOA电路稳定输出的关键所在。
图2为图1所示电路的时序图，显示了该电路的输出情况，从图中可以看出由于该电路未设置防止阈值电压Vth负偏的子电路，在Q点电位被耦合（couple）阶段，Q点的电位难以维持住，逐渐降低，尽管输出信号G(n)仍有效，但是如果GOA电路工作过程中，TFT 的阈值电压Vth发生负偏，GOA电路易失效。此外，图1中GOA电路的工作脉宽为15微秒（us），目前AMOLED 显示面板的像素电路主要采用外部补偿方式，外部补偿需要毫秒（ms）级超宽脉冲，由于Q点电位无法维持，最简化的GOA电路无法满足GOA电路的宽脉冲需求。因此，该电路不具备可行性 。
 技术问题
因此，本发明的目的在于提供一种GOA电路，减少GOA电路版图所占空间，补偿GOA电路中TFT的阈值电压Vth不均及变异。
 技术解决方案
为实现上述目的，本发明提供了一种GOA电路，包括多个级联的GOA单元，设n为自然数，负责输出第n级水平扫描信号的第n级GOA单元包括：
第一薄膜晶体管，其栅极连接第一时钟信号，源极和漏极分别连接来自前一级GOA单元的级传信号和第一节点；
第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二时钟信号和第n级水平扫描信号输出端；
第三薄膜晶体管，其栅极连接电源高电压，源极和漏极分别连接电源高电压和第二节点；
第四薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电压；
第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第n级水平扫描信号输出端和直流低电压；
第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电压；
存储电容，其两端分别连接第一节点和第n级水平扫描信号输出端；
所述第一薄膜晶体管、第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管中至少其中之一为双栅极薄膜晶体管，所述双栅极薄膜晶体管的顶栅分别作为所述栅极连接于所述GOA单元中，所述双栅极薄膜晶体管的底栅分别连接对应的电位可调的底栅电压。
其中，所述第五薄膜晶体管以及第六薄膜晶体管为双栅极薄膜晶体管，其底栅连接第一底栅电压。
其中，所述第一薄膜晶体管为双栅极薄膜晶体管，其底栅连接第二底栅电压。
其中，所述第四薄膜晶体管为双栅极薄膜晶体管，其底栅连接第三底栅电压。
其中，所述第二薄膜晶体管为双栅极薄膜晶体管，其底栅连接第四底栅电压。
其中，所述第n级水平扫描信号作为级传信号输入下一级GOA单元。
其中，对于第1级GOA单元，启动信号作为来自前一级GOA单元的级传信号。
其中，所述GOA电路为铟镓锌氧化物GOA电路。
其中，所述第一时钟信号和第二时钟信号波形相同，占空比为三分之一，并且相位相差三分之一周期。
其中，每当所述GOA电路工作一段时间后，智能调节一次所述底栅电压。
 有益效果
综上，本发明的GOA电路能够减少GOA电路版图所占空间，有利于显示屏窄边框化，同时能够补偿GOA电路中TFT的阈值电压Vth不均及变异，使GOA电路的可靠性得到提高；实现GOA电路中TFT的阈值电压Vth可调节；实现每颗TFT的阈值电压Vth的独立控制；保证GOA电路中TFT的阈值电压Vth能够得到实时补偿，并保证GOA电路的输出良好。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的一种GOA电路的单级GOA单元结构示意图；
图2为图1所示电路的时序图；
图3为本发明GOA电路一较佳实施例的单级GOA单元结构示意图；
图4为通过底栅电压调节阈值电压的示意图；
图5为本发明的GOA电路一较佳实施例的时序图；
图6为本发明的GOA电路一较佳实施例的输出效果示意图；
图7为本发明的GOA电路一较佳实施例的模拟仿真的输出效果示意图。
 本发明的实施方式
参见图3，其为本发明GOA电路一较佳实施例的单级GOA单元结构示意图，该GOA单元中TFT数量为六颗，TFT可以采用双栅型TFT设计，其中TFT顶栅可以用于连接GOA电路中节点，底栅可以用于连接外接电压源。本发明采用一组CK时钟信号（共三个时钟信号，CK1，CK2，CK3）进行驱动，第一时钟信号CK1、第二时钟信号CK2和第三时钟信号CK3波形相同，占空比为三分之一，并且相位依次相差三分之一周期，各级GOA单元按照驱动时序输入对应的两个时钟信号，图3所示的单级GOA单元以第一时钟信号CK1、第二时钟信号CK2为例进行绘示，实际上， GOA电路的各级GOA单元分别对应输入第一时钟信号CK1、第二时钟信号CK2和第三时钟信号CK3其中两个以实现顺序驱动各级GOA单元，并且前一级即第n－1级GOA单元输出的扫描信号G(n－1)作为级传信号连接当前级级即第n级GOA单元，当前级即第n级GOA单元输出的扫描信号G（n）作为级传信号连接第n＋1级GOA单元，值得注意的是，启动信号STV作为级传信号与GOA电路第一级的第一薄膜晶体管T1相连，同时每个GOA单元使用了2个直流（DC）信号直流高电压VGH与直流低电压VGL。
负责输出第n级水平扫描信号G(n)的第n级GOA单元包括：
第一薄膜晶体管T1，其栅极连接第一时钟信号CK1，源极和漏极分别连接来自前一级GOA单元的级传信号G(n－1)和第一节点Q；第n级水平扫描信号G(n)作为级传信号输入下一级GOA单元；
第二薄膜晶体管T2，其栅极连接第一节点Q，源极和漏极分别连接第二时钟信号CK2和第n级水平扫描信号G(n)输出端；
第三薄膜晶体管T31，其栅极连接电源高电压VGH，源极和漏极分别连接电源高电压VGH和第二节点QB；
第四薄膜晶体管T32，其栅极连接第一节点Q，源极和漏极分别连接第二节点QB和直流低电压VGL；
第五薄膜晶体管T41，其栅极连接第二节点QB，源极和漏极分别连接第n级水平扫描信号G(n)输出端和直流低电压VGL；
第六薄膜晶体管T42，其栅极连接第二节点QB，源极和漏极分别连接第一节点Q和直流低电压VGL；
存储电容Cbt，其两端分别连接第一节点Q和第n级水平扫描信号G(n)输出端；
所述第一薄膜晶体管T1、第二薄膜晶体管T2、第四薄膜晶体管T32、第五薄膜晶体管T41以及第六薄膜晶体管T42中至少其中之一为双栅极薄膜晶体管，在此实施例中，前述薄膜晶体管均为双栅极薄膜晶体管，所述双栅极薄膜晶体管的顶栅分别作为所述栅极连接于所述GOA单元中，所述双栅极薄膜晶体管的底栅分别连接对应的电位可调的底栅电压；
在此实施例中，第五薄膜晶体管T41以及第六薄膜晶体管T42的底栅连接第一底栅电压V1；第一薄膜晶体管T1的底栅连接第二底栅电压V2；第四薄膜晶体管T32的底栅连接第三底栅电压V3；第二薄膜晶体管T2的底栅连接第四底栅电压V4。前述GOA电路可以为铟镓锌氧化物GOA电路。
本发明的设计优点如下：
1、TFT的阈值电压Vth不仅受顶栅控制（顶栅连接GOA电路中节点），同时受底栅控制（可调电位控制）。在GOA电路工作过程中，利用该设计能够使底栅实现TFT的阈值电压Vth可控，实现GOA电路中TFT的阈值电压Vth可调节。
图4为通过底栅电压调节阈值电压的示意图，横轴表示底栅电压V BG（单位V），纵轴为Log漏极电流（单位A），TFT的底栅电压V BG对TFT的阈值电压Vth可控，图4中，在漏极电压V D=0.1V的条件下，各曲线分别表示顶栅电压V TG为0V，2V，4V，6V，8V，10V时的曲线，以及通过底栅电压调节阈值电压得到的校正后的曲线。如果面板产出后，经过量测，TFT的阈值电压Vth整体偏负，可将底栅电压调负。如果TFT的阈值电压Vth正偏，可以将底栅电压调正，利用该方案可实现TFT的电性可控。
2、该GOA电路中T31基本不受电压压力作用，可近似认为T31的阈值电压Vth不会发生偏移，因此无需加底栅，其余5颗TFT均添加底栅实现阈值电压Vth可控；由于不同TFT受到的压力不同，T1受50%占空比的Vgs 交流（AC）压力作用，T2受Vds 交流作用，T32受Vgs 交流压力作用；T41及T42受到Vgs 交流压力条件相似，可认为工作过程中，阈值电压Vth的偏移量相同；该设计可以针对不同TFT添加不同的底栅电压V1~V4，实现每颗TFT的阈值电压Vth的独立控制。
3、该架构能够在面板出厂前探测GOA电路的输出信号，根据输出信号的波形，判断整体TFT的电性偏移情况以及底栅电压是否需要调节。
4、面板出厂前可对GOA电路进行编程（预先设定），每当GOA电路工作一段时间后，智能调节一次底栅电压，保证GOA电路中TFT的阈值电压Vth能够得到实时补偿，并保证GOA电路的输出良好。
图5为本发明的GOA电路一较佳实施例的时序图，如下表一为该较佳实施例的信号幅值，图6为本发明的GOA电路一较佳实施例的输出效果示意图；在此实施例中，第一时钟信号CK1、第二时钟信号CK2和第三时钟信号CK3波形相同，占空比为三分之一，并且相位依次相差三分之一周期。面板出厂时，底栅电压整体设置为0V时，Q点波形失真，GOA电路输出失效，如果将T1，T41与T42的底栅电压设置为-3V时，TFT的阈值电压Vth整体正偏，Q点的波形得到改善，T1，T41与T42的底栅电压设置为-8V时，TFT的阈值电压Vth整体正偏更多，Q点波形正常，因此，出厂时可将底栅电压设置为-8V。
表一、信号幅值
Figure 586773dest_path_image002
本发明所提供的GOA电路及架构，每级GOA单元只有六颗TFT，不仅能够极大减少GOA电路版图所占空间，有利于显示屏窄边框化，同时能够补偿GOA电路中TFT的阈值电压Vth不均及变异，使GOA电路的可靠性得到提高。
如图7所示，其为本发明的GOA电路一较佳实施例的模拟仿真的输出效果示意图，对该较佳实施例的GOA电路进行仿真电路模拟器（spice）模拟仿真，得到了非常好的信号输出。下面以单级GOA电路为例，T1，T41与T42的底栅出厂电压设置为-8V，说明电路的工作过程。
S1阶段：CK1与G(n-1)升为高电位，T1打开，Q点升为高电位，高电位存储于存储电容Cbt中， T2与T32打开，由于T32的TFT宽长比远比T31大，QB输出低电位，输出信号G(n)输出低电位。
S2阶段：CK1与G(n-1)降为低电位，T1关闭，CK2由低电位升为高电位，输出信号G(n)升为高电位，由于存储电容的存在，Q点电位被耦合至更高电位。
S3阶段：CK1与G(n-1)为低电位，T1维持关闭，CK2由高电位降为低电位，T2打开，输出信号G(n)被拉低为低电位，Q点电位被耦合至高电位。
综上，本发明的GOA电路能够减少GOA电路版图所占空间，有利于显示屏窄边框化，同时能够补偿GOA电路中TFT的阈值电压Vth不均及变异，使GOA电路的可靠性得到提高；实现GOA电路中TFT的阈值电压Vth可调节；实现每颗TFT的阈值电压Vth的独立控制；保证GOA电路中TFT的阈值电压Vth能够得到实时补偿，并保证GOA电路的输出良好。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种GOA电路，包括多个级联的GOA单元，设n为自然数，负责输出第n级水平扫描信号的第n级GOA单元包括：
    第一薄膜晶体管，其栅极连接第一时钟信号，源极和漏极分别连接来自前一级GOA单元的级传信号和第一节点；
    第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二时钟信号和第n级水平扫描信号输出端；
    第三薄膜晶体管，其栅极连接电源高电压，源极和漏极分别连接电源高电压和第二节点；
    第四薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电压；
    第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第n级水平扫描信号输出端和直流低电压；
    第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电压；
    存储电容，其两端分别连接第一节点和第n级水平扫描信号输出端；
    所述第一薄膜晶体管、第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管中至少其中之一为双栅极薄膜晶体管，所述双栅极薄膜晶体管的顶栅分别作为所述栅极连接于所述GOA单元中，所述双栅极薄膜晶体管的底栅分别连接对应的电位可调的底栅电压。
  2. 如权利要求1所述的GOA电路，其中，所述第五薄膜晶体管以及第六薄膜晶体管为双栅极薄膜晶体管，其底栅连接第一底栅电压。
  3. 如权利要求1所述的GOA电路，其中，所述第一薄膜晶体管为双栅极薄膜晶体管，其底栅连接第二底栅电压。
  4. 如权利要求1所述的GOA电路，其中，所述第四薄膜晶体管为双栅极薄膜晶体管，其底栅连接第三底栅电压。
  5. 如权利要求1所述的GOA电路，其中，所述第二薄膜晶体管为双栅极薄膜晶体管，其底栅连接第四底栅电压。
  6. 如权利要求1所述的GOA电路，其中，所述第n级水平扫描信号作为级传信号输入下一级GOA单元。
  7. 如权利要求1所述的GOA电路，其中，对于第1级GOA单元，启动信号作为来自前一级GOA单元的级传信号。
  8. 如权利要求1所述的GOA电路，其中，所述GOA电路为铟镓锌氧化物GOA电路。
  9. 如权利要求1所述的GOA电路，其中，所述第一时钟信号和第二时钟信号波形相同，占空比为三分之一，并且相位相差三分之一周期。
  10. 如权利要求1所述的GOA电路，其中，每当所述GOA电路工作一段时间后，智能调节一次所述底栅电压。
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