WO2021000375A1 - 一种显示面板及其制备方法 - Google Patents

一种显示面板及其制备方法 Download PDF

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WO2021000375A1
WO2021000375A1 PCT/CN2019/099560 CN2019099560W WO2021000375A1 WO 2021000375 A1 WO2021000375 A1 WO 2021000375A1 CN 2019099560 W CN2019099560 W CN 2019099560W WO 2021000375 A1 WO2021000375 A1 WO 2021000375A1
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layer
display area
display panel
groove
array substrate
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PCT/CN2019/099560
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English (en)
French (fr)
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刘晓伟
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/618,367 priority Critical patent/US11316129B2/en
Publication of WO2021000375A1 publication Critical patent/WO2021000375A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations

Definitions

  • the invention relates to the field of display, in particular to a display panel and a preparation method thereof.
  • Oxide TFT Thin Film Transistor (Thin Film Transistor) panels have an increasing market share due to their advantages in low power consumption and narrow bezels.
  • oxide TFTs are very sensitive to water vapor and hydrogen ions in the air, and water vapor and free hydrogen ions will deprive the oxide semiconductor of oxygen, making the semiconductor conductive, and the TFT loses its switching function. This results in poor display.
  • SiNx has good insulating properties, dense film quality, and excellent ability to block water vapor and free Na, K plasma.
  • SiNx has good insulating properties, dense film quality, and excellent ability to block water vapor and free Na, K plasma.
  • there is a lot of free H+ in SiNx which is easy to diffuse to the TFT device, causing the TFT device to fail, resulting in a decrease in yield.
  • SiNx and SiOx are etched at the same time. Because the etching characteristics of SiNx and SiOx are quite different, it is very easy to produce UnderCut, etching by-products and other problems, and the process window is small.
  • the second solution is to use SiNO or SiOx as the insulating layer of the TFT device.
  • SiNO and SiOx films are loose and have hydrophilic characteristics, and their ability to block water vapor and free Na and K plasma is very weak. Especially for the peripheral position of the panel, water vapor is very easy to enter, resulting in poor display around the panel.
  • the present invention provides a display panel and a manufacturing method thereof to solve the problem that in the prior art, there are many free hydrogen ions in silicon nitride, which are easily diffused to electrical components, causing device failure. There is a problem that it cannot effectively isolate water and oxygen.
  • the present invention provides a display panel including a display area and a non-display area surrounding the display area, and an array substrate disposed in the display area and the non-display area; the array substrate includes A groove is provided in the array substrate and is located in the non-display area and forms a circle around the display area; an encapsulation filling layer is filled in the groove, and the encapsulation filling layer is made of nitride silicon.
  • the array substrate further includes a substrate; a gate layer is provided on the substrate; a first insulating layer is provided on the substrate and covers the gate layer; a second insulating layer is provided on the On the first insulating layer; a first metal layer, arranged on the second insulating layer; source and drain electrodes, arranged on the second insulating layer and electrically connected to the first metal layer; first encapsulation layer , Disposed on the second insulating layer and covering the source and drain electrodes and the first metal layer; a second encapsulation layer, disposed on the first encapsulation layer; light emitting layer, disposed on the second encapsulation The layer passes through the first encapsulation layer and the second encapsulation layer and is electrically connected to the source and drain electrodes; wherein, the groove to the second encapsulation layer penetrates to the first insulating layer.
  • the array substrate further includes a second metal layer disposed on the substrate and having the same height as the gate layer; wherein, the second metal layer corresponds to the groove.
  • the material of the first insulating layer is silicon nitride; the material of the second insulating layer is silicon oxide.
  • the material of the first packaging layer is silicon oxide; the material of the second packaging layer is silicon oxynitride.
  • it further includes a color filter substrate, which is arranged opposite to the array substrate; and a sealing structure, which is sealed between the color filter substrate and the array substrate and corresponds to the groove.
  • the present invention also provides a method for manufacturing a display panel, including a display area and a non-display area surrounding the display area, including providing an array substrate, the array substrate including a display area and a non-display area; A groove is provided on the non-display area, and the groove forms a circle around the display area; a photoresist is coated on one side of the groove opening of the array substrate to form a photoresist layer; Coating a layer of silicon nitride on the photoresist layer, the silicon nitride filling the groove; developing to remove the photoresist layer and the silicon nitride on the photoresist layer; The silicon nitride in the groove forms a packaging filling layer.
  • the preparation step of the array substrate includes:
  • a gate layer is formed on the substrate, the gate layer is disposed in the display area, a second metal layer is formed in the non-display area of the substrate, and the second metal layer is in contact with the gate.
  • the poles are the same height;
  • a second packaging layer is formed on the first packaging layer.
  • the temperature is less than 200°C.
  • the manufacturing method of the display panel further includes providing a color filter substrate; forming a sealing structure corresponding to the groove, and the sealing structure connects the color filter substrate and the array substrate.
  • the display panel and the preparation method of the present invention provide grooves in the corresponding sealing structure of the array substrate and fill silicon nitride to effectively isolate the water and oxygen intrusion at the edge of the display panel.
  • the grooves are arranged in the non-display area of the display panel. The free hydrogen ions in the silicon dioxide cannot diffuse to the source and drain electrodes, which will not cause the display panel to fail, and effectively prevent the display panel from displaying poorly.
  • Fig. 1 is a schematic diagram of a display panel in an embodiment.
  • Fig. 2 is a partial schematic diagram of the display panel in the embodiment.
  • Fig. 3 is a step diagram of a method for manufacturing a display panel in an embodiment.
  • Fig. 4 is a schematic diagram of the array substrate in the embodiment.
  • the first packaging layer 180 second encapsulation layer;
  • the display panel 10 of the present invention includes an array substrate 100 and a color filter substrate 200 arranged oppositely.
  • the display panel 10 is provided with a display area 11 and a non-display area 12 surrounding the display area 11.
  • the array substrate 100 includes a substrate 110, a gate layer 120, a first insulating layer 130, a second insulating layer 140, a first metal layer 150, source and drain electrodes 160, a first encapsulation layer 170, and a second encapsulation layer 180 And luminescent layer 190.
  • the substrate 110 is a hard glass substrate.
  • the gate layer 120 is disposed on the substrate 110.
  • the first insulating layer 130 is disposed on the substrate 110 and covers the gate layer 120 for insulating the gate layer 120.
  • the material of the first insulating layer 130 is silicon nitride, silicon nitride The insulation performance is good, the film quality is dense, and it has a very excellent ability to block water vapor and free Na, K plasma.
  • the first insulating layer 130 The second insulating layer 140 is provided thereon, and the second insulating layer 140 is silicon oxide to prevent moisture intrusion.
  • the first metal layer 150 is disposed on the second insulating layer 140, wherein the first metal layer 150 is located in the display area 11 of the display panel 10.
  • the source and drain electrodes 160 are disposed on both sides of the first metal layer 150 and are electrically connected to the first metal layer 150.
  • the first encapsulation layer 170 is disposed on the second insulating layer 140 and covers the first metal layer 150 and the source and drain electrodes 160.
  • the material of the first encapsulation layer 170 is silicon oxide, It is used to prevent the intrusion of water vapor and make the display panel 10 invalid.
  • the second encapsulation layer 180 is disposed on the first encapsulation layer 170.
  • the material of the second encapsulation layer 180 is silicon oxynitride, which further prevents water and oxygen intrusion, and protects the first metal layer 150 and the Source and drain electrodes 160.
  • the light emitting layer 190 is disposed on the second encapsulation layer 180, penetrates the first encapsulation layer 170 and the second encapsulation layer 180, and is electrically connected to the source and drain electrodes 160.
  • the films of silicon oxide and silicon oxynitride are loose and hydrophilic, they have weak blocking ability against water vapor and free Na and K plasma, especially at the edge of the display panel 10, where water vapor can easily enter. As a result, the display around the display panel 10 is poor.
  • the present invention is provided with a groove 101 in the non-display area 12 of the display panel 10.
  • the groove 101 is provided in the array.
  • the groove 101 is located in the non-display area 12 and forms a circle around the display area 11.
  • the groove 101 is an inverted trapezoid with a wide top and a narrow bottom for filling the packaging filling layer 102.
  • One end of the packaging filling layer 102 is connected to the first insulating layer 130, and one end is away from the second packaging layer 180
  • One side of the first encapsulation layer 170 is flush, and the material of the encapsulation filling layer 102 is the same as the material of the first insulating layer 130, both of which are silicon nitride. Silicon nitride has good insulating properties and the film quality It is compact and has excellent ability to block water vapor and free Na, K plasma.
  • the packaging filling layer 102 is only provided in the groove 101, it can avoid the use of silicon oxide and nitrogen around the display panel 10
  • the intrusion of water vapor caused by the first encapsulation layer 170 and the second encapsulation layer 180 made of oxides such as silicon oxide can also avoid the use of free hydrogen ions caused by silicon nitride to affect the first metal layer 150 and the Damage to the source and drain electrodes 160.
  • a second metal layer 121 is provided on the substrate 110, and the second metal layer 121 is The material and height of the gate layer 120 are the same. The difference is that the second metal layer 121 is disposed in the non-display area of the array substrate 100 corresponding to the position of the groove 101.
  • the display panel 10 further includes a sealing structure 300 that connects the array substrate 100 and the color filter substrate 200.
  • the sealing structure 300 is located on the display panel 10. In the non-display area 12 of the array substrate 100 and corresponding to the position of the groove 101, the display panel is sealed.
  • the present embodiment provides a method for preparing the display panel 10, wherein the steps of preparing the array substrate include S1) to S7).
  • a gate layer 120 is formed on the substrate 110, the gate layer 120 is disposed in the display area 11, and a second metal layer 121 is formed in the non-display area 12 of the substrate 110.
  • the two metal layers 121 are at the same height as the gate layer 120;
  • source and drain electrodes 160 are dispersed on both sides of the first metal layer 150 and are electrically connected to the first metal layer 150;
  • a first packaging layer 170 is formed on the second insulating layer 140, and the first packaging layer 170 covers the source and drain electrodes 160 and the first metal layer 150;
  • a groove 101 is opened on the second packaging layer 180 in the non-display area of the array substrate, and the groove 101 penetrates from the second packaging layer 180 to the first insulating layer 130.
  • the photoresist layer 181 and the silicon nitride layer 182 on the photoresist layer 181 are removed by developing, because the silicon nitride layer on the photoresist layer 181 will follow
  • the photoresist 181 is developed and dissolved and falls off automatically, which prevents the silicon nitride layer 182 from being removed by etching, which may cause damage to the second encapsulation layer 180.
  • the silicon nitride remaining in the groove 101 forms an encapsulation filling layer 102.

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Abstract

本发明公开了一种显示面板及其制备方法，显示面板包括显示区和围绕所述显示区的非显示区，以及阵列基板，设置在显示区和非显示区中；所述阵列基板包括凹槽，设于所述阵列基板中，且位于所述非显示区并围绕所述显示区形成一圈；封装填充层，填充于所述凹槽中，所述封装填充层所用材料为氮化硅。本发明的有益效果在于本发明的显示面板及其制备方法通过在阵列基板对应密封结构处开设凹槽并填充氮化硅从而有效隔绝显示面板边缘处的水氧入侵，同时凹槽设于显示面板的非显示区，氮化硅中的游离态氢离子无法扩散到源漏电极上，不会导致显示面板失效，有效防治显示面板显示不良。

Description

一种显示面板及其制备方法 技术领域
本发明涉及显示领域，特别涉及一种显示面板及其制备方法。
 背景技术
氧化物TFT（Thin Film Transistor 薄膜晶体管）面板因其在低功耗，窄边框方面的优势，市场占有率越来越高。但氧化物TFT对空气中的水汽，氢离子非常敏感，水汽和游离态的氢离子会剥夺氧化物半导体中的氧，使得半导体导体化，TFT失去开关作用。从而造成显示不良。
目前采用的方案主要有两种，一种是用SiNx作为TFT的绝缘层，SiNx绝缘特性较好，膜质致密，有非常优异的阻挡水汽和游离态的Na，K等离子的能力。但SiNx中游离态的H+很多，很容易扩散到TFT器件上，导致TFT器件失效，导致良率下降，另外，采用SiNx作为钝化层，进行过孔刻蚀的时候，SiNx与SiOx同时刻蚀，因为SiNx和SiOx的刻蚀特性差异较大，非常容易产生UnderCut，刻蚀副产物等问题，工艺窗口很小，为此常常需要增加一道绝缘层工艺，严重影响产能和良率。第二种方案是用SiNO或SiOx来作为TFT器件的绝缘层，但SiNO和SiOx膜质疏松，且呈亲水特性，对水汽和游离态的Na，K等离子的阻挡能力很弱。特别对于面板的周边位置，水汽非常容易进入，从而形成面板周边显示不良。
 技术问题
为了解决上述问题，本发明提供了一种显示面板及其制备方法，用以解决现有技术中由于氮化硅中游离态的氢离子很多，容易扩散到电元件上，造成器件失效，而氧化硅有无法有效隔绝水氧的问题。
 技术解决方案
解决上述问题的技术方案是：本发明提供了一种显示面板，包括显示区和围绕所述显示区的非显示区，以及阵列基板，设置在显示区和非显示区中；所述阵列基板包括凹槽，设于所述阵列基板中，且位于所述非显示区并围绕所述显示区形成一圈；封装填充层，填充于所述凹槽中，所述封装填充层所用材料为氮化硅。
进一步的，所述阵列基板还包括基板；栅极层，设于所述基板上；第一绝缘层，设于所述基板上且覆盖所述栅极层；第二绝缘层，设于所述第一绝缘层上；第一金属层，设于所述第二绝缘层上；源漏电极，设于所述第二绝缘层上且与所述第一金属层电性连接；第一封装层，设于所述第二绝缘层上且覆盖所述源漏电极和所述第一金属层；第二封装层，设于所述第一封装层上；发光层，设于所述第二封装层且穿过所述第一封装层、第二封装层电性连接于所述源漏电极上；其中，所述凹槽至所述第二封装层贯穿至所述第一绝缘层。
进一步的，所述阵列基板还包括第二金属层，设于所述基板上且与所述栅极层高度相同；其中，所述第二金属层对应所述凹槽。
进一步的，所述第一绝缘层的材质为氮化硅；所述第二绝缘层的材质为氧化硅。
进一步的，所述第一封装层的材料为氧化硅；所述第二封装层的材料为氮氧化硅。
进一步的，还包括彩膜基板，与所述阵列基板相对设置；密封结构，密封的设于所述彩膜基板和所述阵列基板之间，且对应于所述凹槽。
本发明还提供了一种显示面板的制备方法，包括显示区和围绕所述显示区的非显示区，包括提供阵列基板，所述阵列基板包括显示区和非显示区；在所述阵列基板的所述非显示区上开设凹槽，所述凹槽围绕所述显示区形成一圈；在所述阵列基板的所述凹槽开口处一侧涂布光刻胶形成光刻胶层；在所述光刻胶层上涂布一层氮化硅，所述氮化硅填充所述凹槽；显影去除所述光刻胶层及所述光刻胶层上的氮化硅；残留于所述凹槽内的所述氮化硅形成封装填充层。
进一步的，所述阵列基板制备步骤包括：
S1) 提供一基板；
S2) 在所述基板上形成栅极层，所述栅极层设于所述显示区中，在所述基板的非显示区中形成第二金属层，所述第二金属层与所述栅极层同高；
S3) 在所述栅极层上沉积第一绝缘层，其中，所述第一绝缘层覆盖所述栅极层和所述第二金属层；
S4) 在所述第一绝缘层上形成第一金属层，所述第一金属层对应所述栅极层；
S5) 在所述第二绝缘层上形成源漏电极，所述源漏电极分散于所述第一金属层两侧且与所述第一金属层电性连接；
S6) 在所述第二绝缘层上形成第一封装层，所述第一封装层覆盖所述源漏电极和所述第一金属层；
S7) 在所述第一封装层形成第二封装层。
进一步的，在涂布所述氮化硅的过程中，温度小于200℃。
进一步的，所述显示面板的制备方法还包括提供一彩膜基板；在对应所述凹槽处形成一密封结构，所述密封结构连接所述彩膜基板和所述阵列基板。
 有益效果
本发明的显示面板及其制备方法通过在阵列基板对应密封结构处开设凹槽并填充氮化硅从而有效隔绝显示面板边缘处的水氧入侵，同时凹槽设于显示面板的非显示区，氮化硅中的游离态氢离子无法扩散到源漏电极上，不会导致显示面板失效，有效防治显示面板显示不良。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是实施例中显示面板示意图。
图2是实施例中显示面板局部示意图。
图3是实施例中显示面板制备方法步骤图。
图4是实施例中阵列基板示意图。
10 显示面板；                          100阵列基板；
200 彩膜基板；                         300 密封结构；
11 显示区；                            12 非显示区；
110 基板；                             120 栅极层；
130 第一绝缘层；                       140 第二绝缘层；
150 第一金属层；                       160 源漏电极；
170 第一封装层；                       180 第二封装层；
190 发光层；                           101 凹槽；
102 封装填充层；                       121 第二金属层；
181 光刻胶层；                         182 氮化硅层；
 本发明的实施方式
以下实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「顶」、「底」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
实施例
如图1所示，本发明的显示面板10包括相对设置的阵列基板100和彩膜基板200。
所述显示面板10上设有显示区11和围绕所述显示区11的非显示区12。其中，所述阵列基板100包括基板110、栅极层120、第一绝缘层130、第二绝缘层140、第一金属层150、源漏电极160、第一封装层170、第二封装层180和发光层190。
所述基板110为硬质玻璃基板。所述栅极层120设于所述基板110上。
所述第一绝缘层130设于所述基板110上并覆盖所述栅极层120，用于绝缘所述栅极层120，所述第一绝缘层130所用材质为氮化硅，氮化硅的绝缘性能较好，膜质致密，有非常优异的阻挡水汽和游离态的Na，K等离子的能力。
然而，由于氮化硅中游离态的H+很多，很容易扩散到所述显示面板10上，使所述显示面板10失效，导致良率下降，故本实施例中，在所述第一绝缘层130上设置所述第二绝缘层140，所述第二绝缘层140为氧化硅，避免水汽入侵。
所述第一金属层150设于所述第二绝缘层140上，其中，所述第一金属层150位于所述显示面板10的显示区11中。
所述源漏电极160设于所述第一金属层150两侧且与所述第一金属层150电性连接。
所述第一封装层170设于所述第二绝缘层140上，且覆盖所述第一金属层150和所述源漏电极160，其中，所述第一封装层170的材料为氧化硅，用以防止水汽入侵，使所述显示面板10显示失效。
所述第二封装层180设于所述第一封装层170上，所述第二封装层180的所用材料为氮氧化硅，进一步隔绝水氧入侵，保护所述第一金属层150和所述源漏电极160。
所述发光层190设于所述第二封装层180上，其贯穿所述第一封装层170和第二封装层180，电性连接于所述源漏电极160上。
由于氧化硅和氮氧化硅的膜质疏松，且呈亲水性，所以对水汽和游离态的Na，K等离子的阻挡能力很弱，特别是所述显示面板10的边缘处，水汽非常容易进入，从而使所述显示面板10周边显示不良。
如图2所示，为了避免这一现象，本实施例中，本发明在所述显示面板10的非显示区12中设有一凹槽101，具体的，所述凹槽101设于所述阵列基板100上，自所述第二封装层180贯穿至所述第一绝缘层130，所述凹槽101位于所述非显示区12中并围绕所述显示区11形成一圈。
所述凹槽101为上宽下窄的类倒梯形，用于填充封装填充层102，所述封装填充层102一端与所述第一绝缘层130相连，一端与所述第二封装层180远离所述第一封装层170的一侧平齐，所述封装填充层102的材料与所述第一绝缘层130的材料相同，均为氮化硅，氮化硅的绝缘性能较好，膜质致密，有非常优异的阻挡水汽和游离态的Na，K等离子的能力，由于所述封装填充层102只设于所述凹槽101内，既可以避免所述显示面板10周围因为采用氧化硅和氮氧化硅等氧化物的所述第一封装层170和所述第二封装层180而导致的水汽入侵，又可以避免采用氮化硅导致的游离态氢离子对所述第一金属层150和所述源漏电极160的损害。
为了减少所述封装填充层102在所述凹槽101内的深度，提高均一性，本实施例中，在所述基板110上设置一第二金属层121，所述第二金属层121与所述栅极层120的材料及高度一致，不同点在于，所述第二金属层121设于所述阵列基板100的非显示区中，对应所述凹槽101的位置。
本实施例中，所述显示面板10还包括一密封结构300，所述密封结构300连接所述阵列基板100和所述彩膜基板200，具体的，所述密封结构300位于所述显示面板10的非显示区12中，且在所述阵列基板100上对应所述凹槽101所在位置，用以对所述显示面板进行密封。
为了更好的解释本发明，本实施提供了一种所述显示面板10的制备方法，其中阵列基板的制备步骤包括S1)～S7)。
S1) 提供一基板；
S2) 在所述基板110上形成栅极层120，所述栅极层120设于所述显示区11中，在所述基板110的非显示区12中形成第二金属层121，所述第二金属层121与所述栅极层120同高；
S3) 在所述栅极层120上沉积第一绝缘层130，其中，所述第一绝缘层130覆盖所述栅极层120和所述第二金属层121；
S4) 在所述第一绝缘层130上形成第二绝缘层140；
S5) 在所述第二绝缘层140形成第一金属层150，所述第一金属层150对应所述栅极层120；
S6) 在所述第二绝缘层140上形成源漏电极160，所述源漏电极160分散于所述第一金属层150两侧且与所述第一金属层150电性连接；
S7) 在所述第二绝缘层140上形成第一封装层170，所述第一封装层170覆盖所述源漏电极160和所述第一金属层150；
S8) 在所述第一封装层170形成第二封装层180；
S9) 在所述阵列基板的所述非显示区即所述第二封装层180上开设凹槽101，所述凹槽101自所述第二封装层180贯穿至所述第一绝缘层130。
S10) 如图3所示，在所述阵列基板100的所述第二封装层180上涂布光刻胶；
对所述凹槽101上方的所述光刻胶进行曝光显影，其余部分的光刻胶保留形成光刻胶层181；
S11) 在所述光刻胶层181上涂布氮化硅形成氮化硅层182，由于所述凹槽101上方的所述光刻胶被去除，所以所述氮化硅经由所述凹槽101上方开口进入所述凹槽101内部并填充满所述凹槽101，为了避免所述光刻胶在涂布所述氮化硅的过程中被挥发，需要保持温度在200℃以下；
如图4所示，显影去除所述光刻胶层181及所述光刻胶层181上的氮化硅层182，由于所述光刻胶层181上的所述氮化硅会随着下方的所述光刻胶181的显影溶解而自动脱落，避免了通过刻蚀来去除所述氮化硅层182从而导致所述第二封装层180损伤。残留于所述凹槽101内的所述氮化硅形成封装填充层102。
以上仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种显示面板，其中，包括显示区和围绕所述显示区的非显示区，以及
    阵列基板，设置在显示区和非显示区中；所述阵列基板包括
    凹槽，设于所述阵列基板中，且位于所述非显示区并围绕所述显示区形成一圈；
    封装填充层，填充于所述凹槽中，所述封装填充层所用材料为氮化硅。
  2. 根据权利要求1所述的显示面板，其中，
    所述阵列基板还包括
    基板；
    栅极层，设于所述基板上；
    第一绝缘层，设于所述基板上且覆盖所述栅极层；
    第二绝缘层，设于所述第一绝缘层上；
    第一金属层，设于所述第二绝缘层上；
    源漏电极，设于所述第二绝缘层上且与所述第一金属层电性连接；
    第一封装层，设于所述第二绝缘层上且覆盖所述源漏电极和所述第一金属层；
    第二封装层，设于所述第一封装层上；
    发光层，设于所述第二封装层且穿过所述第一封装层、第二封装层电性连接于所述源漏电极上；其中，所述凹槽至所述第二封装层贯穿至所述第一绝缘层。
  3. 根据权利要求2所述的显示面板，其中，还包括
    第二金属层，设于所述基板上且与所述栅极层高度相同；其中，所述第二金属层对应所述凹槽。
  4. 根据权利要求2所述的显示面板，其中，
    所述第一绝缘层的材质为氮化硅；
    所述第二绝缘层的材质为氧化硅。
  5. 根据权利要求2所述的显示面板，其中，
    所述第一封装层的材料为氧化硅；
    所述第二封装层的材料为氮氧化硅。
  6. 根据权利要求1所述的显示面板，其中，还包括
    彩膜基板，与所述阵列基板相对设置；
    密封结构，密封的设于所述彩膜基板和所述阵列基板之间，且对应于所述凹槽。
  7. 一种显示面板的制备方法，包括显示区和围绕所述显示区的非显示区，其中，包括
    提供阵列基板，所述阵列基板包括显示区和非显示区；
    在所述阵列基板的所述非显示区上开设凹槽，所述凹槽围绕所述显示区形成一圈；
    在所述阵列基板的所述凹槽开口处一侧涂布光刻胶形成光刻胶层；
    在所述光刻胶层上涂布一层氮化硅，所述氮化硅填充所述凹槽；
    显影去除所述光刻胶层及所述光刻胶层上的氮化硅；残留于所述凹槽内的所述氮化硅形成封装填充层。
  8. 根据权利要求7所述的显示面板的制备方法，其中，所述阵列基板制备步骤包括
    S1) 提供一基板；
    S2) 在所述基板上形成栅极层，所述栅极层设于所述显示区中，在所述基板的非显示区中形成第二金属层，所述第二金属层与所述栅极层同高；
    S3) 在所述栅极层上沉积第一绝缘层，其中，所述第一绝缘层覆盖所述栅极层和所述第二金属层；
    S4) 在所述第一绝缘层上形成第一金属层，所述第一金属层对应所述栅极层；
    S5) 在所述第二绝缘层上形成源漏电极，所述源漏电极分散于所述第一金属层两侧且与所述第一金属层电性连接；
    S6) 在所述第二绝缘层上形成第一封装层，所述第一封装层覆盖所述源漏电极和所述第一金属层；
    S7) 在所述第一封装层形成第二封装层。
  9. 根据权利要求7所述的显示面板的制备方法，其中，
    在涂布所述氮化硅的过程中，温度小于200℃。
  10. 根据权利要求7所述的显示面板的制备方法，其中，还包括
    提供一彩膜基板；
    在对应所述凹槽处形成一密封结构，所述密封结构密封地连接所述彩膜基板和所述阵列基板。
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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950277A (zh) * 2017-12-08 2019-06-28 乐金显示有限公司 有机发光显示装置及其制造方法
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