WO2020259012A1 - 静电释放电路、显示面板、显示装置以及静电释放电路的驱动方法 - Google Patents

静电释放电路、显示面板、显示装置以及静电释放电路的驱动方法 Download PDF

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WO2020259012A1
WO2020259012A1 PCT/CN2020/084882 CN2020084882W WO2020259012A1 WO 2020259012 A1 WO2020259012 A1 WO 2020259012A1 CN 2020084882 W CN2020084882 W CN 2020084882W WO 2020259012 A1 WO2020259012 A1 WO 2020259012A1
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circuit
area
charge
sub
discharge
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PCT/CN2020/084882
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English (en)
French (fr)
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曹丹
刘庭良
郭永林
张锴
李�根
李依然
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2020259012A1 publication Critical patent/WO2020259012A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, in particular to an electrostatic discharge circuit, a display panel, a display device, and a driving method of the electrostatic discharge circuit.
  • the ESD (electrostatic discharge) unit is used to discharge static electricity and play a role in protecting the circuit.
  • the embodiment of the present disclosure provides an electrostatic discharge circuit, which is applied to a display panel, the display panel includes a display area and a non-display area; the electrostatic discharge circuit is disposed in the non-display area, and the electrostatic discharge circuit includes a first A charge release sub-circuit and a second charge release sub-circuit;
  • the first charge discharge sub-circuit is arranged in the first sub-area of the non-display area, the first end of the first charge discharge sub-circuit and the first signal input of the data signal line are arranged in the first sub-area Terminal coupled, the second terminal of the first charge discharge sub-circuit is coupled to the first voltage input terminal, and the first charge discharge sub-circuit is configured to discharge the first charge accumulated on the data signal line;
  • the second charge discharge sub-circuit is arranged in the second sub-area of the non-display area, and the first end of the second charge discharge sub-circuit and the second end of the data signal line are arranged in the second sub-area.
  • the signal input terminal is coupled, the second terminal of the second charge discharge sub-circuit is coupled to the second voltage input terminal, and the second charge discharge sub-circuit is configured to discharge the second charge accumulated on the data signal line.
  • the first charge discharge sub-circuit includes a first transistor.
  • the control electrode and the first electrode of the first transistor are both coupled to the first voltage input terminal, the second electrode of the first transistor is coupled to the first signal input terminal, and the first charge is A positive charge, and the first voltage input terminal is a positive power supply voltage input terminal.
  • the second charge discharge sub-circuit includes a second transistor
  • the control electrode and the first electrode of the second transistor are both coupled to the second signal input terminal, the second electrode of the second transistor is coupled to the second voltage input terminal, and the second charge is Negative charge, the second voltage input terminal is a negative power supply voltage input terminal.
  • the display panel of the non-display area includes a stacked unit test area, a fan-out area, and a multiplex switch area;
  • the first charge discharge sub-circuit is disposed between the fan-out area and the unit test area, and the second charge discharge sub-circuit is disposed in the multiplex switch area away from the fan-out area.
  • the first charge discharge sub-circuit is disposed between the fan-out area and the unit test area, and the second charge discharge sub-circuit is disposed in the multiplex switch area away from the fan-out area.
  • the display panel of the non-display area includes a stacked unit test area, a fan-out area, and a multiplex switch area;
  • the first charge discharge sub-circuit is arranged between the fan-out area and the unit test area
  • the second charge discharge sub-circuit is arranged between the multiplex switch area and the fan-out area.
  • the display panel of the non-display area includes a stacked unit test area, a fan-out area, and a multiplex switch area;
  • the first charge discharge sub-circuit is arranged between the fan-out area and the unit test area, and the second charge discharge sub-circuit is arranged on the side of the unit test area away from the fan-out area .
  • the display panel of the non-display area includes a stacking unit test area, a fan-out area, and a multiple selection switch area;
  • the first charge discharge sub-circuit is arranged on a side of the unit test area away from the fan-out area, and the second charge discharge sub-circuit is arranged between the fan-out area and the multiplex switch area.
  • An embodiment of the present disclosure also provides a display panel, including an electrostatic discharge circuit according to an embodiment of the present disclosure; each of the electrostatic discharge circuits is respectively coupled to one of a plurality of data signal lines.
  • the embodiment of the present disclosure further provides a display device, which includes the display panel according to the embodiment of the present disclosure.
  • the embodiments of the present disclosure also provide a driving method of an electrostatic discharge circuit, the method including:
  • a second voltage signal is input to the second input terminal to perform electrostatic discharge on the second charge accumulated on the data signal line.
  • Figure 1 is a schematic diagram of an electrostatic discharge circuit
  • Figure 2 is a layout diagram of a plurality of electrostatic discharge circuits
  • FIG. 3 is a structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure.
  • Fig. 5 is a circuit diagram of a first charge discharge sub-circuit according to an embodiment of the present disclosure
  • Fig. 6 is a circuit diagram of a second charge discharge sub-circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a non-display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of another non-display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a structural diagram of another non-display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a structural diagram of another non-display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a layout structure diagram of multiple electrostatic discharge circuits according to another embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a display device according to another embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a driving method of an electrostatic discharge circuit according to another embodiment of the present disclosure.
  • FIG. 1 shows a schematic diagram of an electrostatic discharge circuit.
  • the electrostatic discharge circuit may include two TFTs (Thin Film Transistors).
  • the gate of one TFT is connected to the first voltage signal terminal VGH, and is mainly used to release, for example, positive charges (defined as Part 1) accumulated on the data signal line Dada.
  • the gate of the other TFT is connected to the data signal line Dada, and is mainly used to discharge the negative charge accumulated on the data signal line Dada (defined as Part 2).
  • an electrostatic discharge circuit according to an embodiment of the present disclosure is shown. It can be applied to a display panel, and the display panel includes an AA display area 100 and a non-display area 200.
  • the electrostatic discharge circuit is provided in the non-display area 200.
  • Fig. 4 is a structural diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure.
  • the electrostatic discharge circuit may include a first charge discharge sub-circuit 201 and a second charge discharge sub-circuit 202.
  • the first charge discharge sub-circuit 201 is arranged in the first sub-area of the non-display area.
  • the first terminal of the first charge discharge sub-circuit 201 is coupled to the first signal input terminal 2011 of the data signal line arranged in the first sub-region, and the second terminal of the first charge discharge sub-circuit 201 is connected to the first voltage The input terminal is coupled.
  • the first charge discharge sub-circuit 201 is configured to discharge the first charge accumulated on the data signal line.
  • the second charge discharge sub-circuit 202 is arranged in the second sub-region of the non-display area.
  • the first terminal of the second charge discharge sub-circuit 202 is coupled to the second signal input terminal 2021 of the data signal line arranged in the second sub-region, and the second terminal of the second charge discharge sub-circuit 202 is connected to a second voltage The input terminal is coupled.
  • the second charge discharge sub-circuit 202 is configured to discharge the second charge accumulated on the data signal line.
  • the electrostatic discharge circuit in view of the severe burns of the electrostatic discharge circuit when it discharges static electricity, is configured as the first charge discharge sub-circuit and the second charge discharge sub-circuit.
  • the first charge discharge sub-circuit is used to discharge the first charge accumulated on the data signal line, for example, the first charge is a positive charge.
  • the second charge discharge sub-circuit is used to discharge the second charge accumulated on the data signal line, for example, the second charge is a negative charge.
  • the first charge discharge sub-circuit is coupled to the first signal input terminal, and the second charge discharge sub-circuit is coupled to the second signal input terminal. Wherein, the first signal input terminal and the second signal input terminal are both coupled to the data signal line, so as to release the charge accumulated on the data signal line.
  • the first charge discharge sub-circuit and the second charge discharge sub-circuit are respectively disposed in the first sub-region and the second sub-region of the non-display area. According to the embodiment of the present disclosure, the first charge discharge sub-circuit and the second charge discharge sub-circuit are arranged separately, which not only ensures the proper function of the electrostatic circuit, but also realizes the reasonable utilization of the circuit space.
  • Fig. 5 is a circuit diagram of a first charge discharge sub-circuit according to an embodiment of the present disclosure.
  • the first charge discharge sub-circuit includes a first transistor T1.
  • the control electrode and the first electrode of the first transistor T1 are both coupled to the first voltage input terminal VGH, and the second electrode of the first transistor T1 is coupled to the first signal input terminal 2011.
  • the first charge may be a positive charge
  • the first voltage input terminal may be a positive power supply voltage input terminal.
  • Fig. 6 is a circuit diagram of a second charge discharge sub-circuit according to an embodiment of the present disclosure.
  • the second charge discharge sub-circuit includes a second transistor T2.
  • the control electrode and the first electrode of the second transistor T2 are both coupled to the second signal input terminal 2021, and the second electrode of the second transistor is coupled to the second voltage input terminal VGL.
  • the second charge may be a negative charge
  • the second voltage input terminal may be a negative power supply voltage input terminal.
  • the second stage of the first transistor T2 is coupled to the first signal input terminal 2011, and the first signal input terminal 2011 is coupled to the data signal line.
  • the first voltage input terminal is a positive power supply voltage input terminal, and the first transistor is coupled with the first voltage input terminal to release positive charges accumulated on the data signal line.
  • the first stage of the second transistor is coupled to the second signal input terminal 2021, and the second signal input terminal 2021 is coupled to the data signal line.
  • the second voltage input terminal is a negative power supply voltage input terminal, and the second transistor is coupled to the second voltage input terminal to release the negative charge accumulated on the data signal line.
  • FIG. 7 is a structural diagram of a non-display area of a display panel according to an embodiment of the present disclosure.
  • the display panel in the non-display area includes a unit test area 701, a fan-out area 702 and a multiplex switch area 703 which are stacked in layers.
  • the first charge discharge sub-circuit 201 is disposed between the fan-out area 702 and the unit test area 701
  • the second charge discharge sub-circuit 202 is disposed on the side of the multiplex switch area 703 away from the fan-out area 702. .
  • the first charge discharge sub-circuit 201 is disposed between the fan-out area 702 and the unit test area 701.
  • the first charge discharge sub-circuit is used to discharge the positive charge on the data signal line, thereby ensuring that the data signal line is not affected by the positive charge.
  • the second charge discharge sub-circuit is arranged on the side of the multiplex switch area 703 away from the fan-out area 702.
  • the second charge release sub-circuit is used to release the negative charge on the data signal line, thereby ensuring that the data signal line is not affected by the negative charge.
  • the electrostatic discharge circuit is arranged in two relatively independent parts, which are respectively arranged in different areas of the non-display area, which can effectively avoid the burning of the second charge discharge sub-circuit that discharges negative charges and affect the entire electrostatic discharge circuit.
  • Performance so as to reduce the probability of burning of the electrostatic discharge circuit under the premise of ensuring the protection function of the electrostatic discharge circuit, improve the yield of the product, and improve the display effect of the product.
  • the space occupied by the first charge discharge sub-circuit and the second charge discharge sub-circuit is half of the space occupied by the original electrostatic discharge circuit. In the case of limited space, this separate arrangement can not only effectively reduce the probability of burns of the electrostatic discharge circuit, but also realize a reasonable use of space.
  • FIG. 8 is a structural diagram of another non-display area of a display panel according to an embodiment of the present disclosure.
  • the display panel of the non-display area may include a unit test area 701, a fan-out area 702, and a multiplex switch area 703 that are stacked.
  • the first charge discharge sub-circuit 201 is arranged between the fan-out area 702 and the unit test area 701
  • the second charge discharge sub-circuit 202 is arranged between the multiplex switch area 703 and the fan-out area 702.
  • FIG. 9 is a structural diagram of another non-display area of a display panel according to an embodiment of the present disclosure.
  • the display panel in the non-display area includes a unit test area 701, a fan-out area 702, and a multiplex switch area 703 that are stacked.
  • the first charge discharge sub-circuit 201 is disposed between the fan-out area 702 and the unit test area 701, and the second charge discharge sub-circuit 202 is disposed on the side of the unit test area 701 away from the fan-out area 702.
  • FIG. 10 is a structural diagram of another non-display area of a display panel according to an embodiment of the present disclosure.
  • the display panel of the non-display area includes a stacked unit test area 701, a fan-out area 702 and a multiplexer area 703.
  • the first charge discharge sub-circuit 201 is arranged on a side of the unit test area 701 away from the fan-out area 702, and the second charge discharge sub-circuit 202 is arranged between the fan-out area 702 and the multiplex switch area 703.
  • the first charge discharge sub-circuit 201 and the second charge discharge sub-circuit 202 can be arbitrarily placed between or on one side of the unit test area 701, the fan-out area 702, and the multiplexer area 703. It can be understood that the embodiment of the present disclosure only restricts the first charge discharge sub-circuit 201 and the second charge discharge sub-circuit 202 not to be arranged in the same area, and does not restrict which two areas are specifically placed.
  • FIG. 11 is a layout structure diagram of multiple electrostatic discharge circuits according to another embodiment of the present disclosure.
  • the display panel 110 may include a plurality of electrostatic discharge circuits; each electrostatic discharge circuit is respectively coupled to one of the plurality of data signal lines Data1, Data2,... DataN.
  • each electrostatic discharge circuit includes a first electrostatic discharge sub-circuit for discharging positive charges and a second electrostatic discharge sub-circuit for discharging negative charges.
  • the first charge discharge sub-circuit and the second charge discharge sub-circuit in the electrostatic discharge circuit are separately arranged, and are respectively arranged in the first sub-region and the second sub-region of the non-display area.
  • the separate placement of the first charge release sub-circuit and the second charge release sub-circuit can not only ensure the proper function of the electrostatic circuit and improve the yield, but also realize the reasonable utilization of the circuit space.
  • FIG. 12 is a schematic diagram of the display device of the embodiment of the present disclosure.
  • the display device 120 includes a display panel 121 according to an embodiment of the present disclosure.
  • the disclosed embodiment since the display device includes the display panel according to the embodiment of the present disclosure, and the display panel includes the electrostatic discharge circuit according to the embodiment of the present disclosure, the disclosed embodiment also has the function of ensuring the electrostatic circuit. Improve the yield rate and realize the rational use of BP circuit space.
  • FIG. 13 is a flowchart of a driving method of an electrostatic discharge circuit according to an embodiment of the present disclosure. As shown in Fig. 13, the method for driving an electrostatic discharge circuit according to an embodiment of the present disclosure may include the following steps.
  • step S1301 when the first charge accumulated on the data signal line satisfies the first condition, a first voltage signal is input to the first voltage input terminal to electrostatically discharge the first charge accumulated on the data signal line.
  • step S1302 when the second charge accumulated on the data signal line satisfies the second condition, a second voltage signal is input to the second voltage input terminal to electrostatically discharge the second charge accumulated on the data signal line.
  • the first voltage signal is input to the first voltage input terminal of the first charge release sub-circuit.
  • the first condition may be: the amount of positive charge accumulated on the data signal line is greater than a first threshold.
  • the first threshold can be determined according to specific conditions. For example, the first threshold is the lowest amount of positive charge that can cause the electrostatic discharge circuit to burn.
  • the first voltage signal input by the first voltage input terminal is used to discharge the first electric charge accumulated on the data signal line.
  • a second voltage signal is input to the second voltage input terminal of the second charge release sub-circuit.
  • the second condition may be: the amount of negative charge accumulated on the data signal line is greater than the second threshold.
  • the second threshold can be determined according to specific conditions. For example, the second threshold is the amount of the lowest negative charge that can cause the electrostatic discharge circuit to burn.
  • the second voltage signal input from the second voltage input terminal is used to discharge the second electric charge accumulated on the data signal line.
  • the first charge discharge sub-circuit and the second charge discharge sub-circuit in the electrostatic discharge circuit are separately arranged, and are respectively arranged in the first sub-region and the second sub-region of the non-display area.
  • the separation of the first charge discharge sub-circuit and the second charge discharge sub-circuit can not only ensure the proper function of the electrostatic circuit and improve the yield, but also realize the rational use of the BP circuit space.

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Abstract

本公开实施例提供了一种静电释放电路、显示面板、显示装置和一种静电释放电路的驱动方法。显示面板包括显示区和非显示区；静电释放电路设置在所述非显示区，静电释放电路包括第一电荷释放子电路和第二电荷释放子电路。第一电荷释放子电路设置在所述非显示区的第一子区域，被配置为释放所述数据信号线上积聚的第一电荷。第二电荷释放子电路设置在所述非显示区的第二子区域，被配置为释放数据信号线上积聚的第二电荷。

Description

静电释放电路、显示面板、显示装置以及静电释放电路的驱动方法
本申请要求于2019年6月24日提交的、申请号为201910549749.4的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及显示技术领域，特别是涉及一种静电释放电路、显示面板、显示装置以及静电释放电路的驱动方法。
背景技术
ESD(静电释放)单元用于释放静电，起到保护电路的作用。
发明内容
本公开实施例提供了一种静电释放电路，应用于显示面板，所述显示面板包括显示区和非显示区；所述静电释放电路设置在所述非显示区，所述静电释放电路包括第一电荷释放子电路和第二电荷释放子电路；
所述第一电荷释放子电路设置在所述非显示区的第一子区域，第一电荷释放子电路的第一端与数据信号线的布设于所述第一子区域中的第一信号输入端耦接，第一电荷释放子电路的第二端与第一电压输入端耦接，第一电荷释放子电路被配置为释放所述数据信号线上积聚的第一电荷；
所述第二电荷释放子电路设置在所述非显示区的第二子区域，第二电荷释放子电路的第一端与所述数据信号线的布设于所述第二子区域中的第二信号输入端耦接，第二电荷释放子电路的第二端与第二电压输入端耦接，第二电荷释放子电路被配置为释放数据信号线上积聚的第二电荷。
例如，所述第一电荷释放子电路包括第一晶体管。所述第一晶体管的控制极及第一极均与所述第一电压输入端耦接，所述第一晶体管的第二极与所述第一信号输入端耦接，所述第一电荷为正电荷，所述第一电压输入端为正电源电压输入端。
例如，所述第二电荷释放子电路包括第二晶体管，
所述第二晶体管的控制极及第一极均与所述第二信号输入端耦接，所述第二晶体管 的第二极与所述第二电压输入端耦接，所述第二电荷为负电荷，所述第二电压输入端为负电源电压输入端。
例如，所述非显示区的所述显示面板包括层叠设置的单元测试区、扇出区和多路选择开关区；
其中，所述第一电荷释放子电路设置在所述扇出区与所述单元测试区之间，所述第二电荷释放子电路设置在所述多路选择开关区背离所述扇出区的一侧。
例如，所述非显示区的所述显示面板包括层叠设置的单元测试区、扇出区和多路选择开关区；
其中，所述第一电荷释放子电路设置在所述扇出区与所述单元测试区之间，所述第二电荷释放子电路设置在所述多路选择开关区与扇出区之间。
例如，所述非显示区的所述显示面板包括层叠设置的单元测试区、扇出区和多路选择开关区；
其中，所述第一电荷释放子电路设置在所述扇出区与所述单元测试区之间，所述第二电荷释放子电路设置在所述单元测试区背离所述扇出区的一侧。
例如，所述非显示区的所述显示面板包括层叠设置单元测试区、扇出区和多路选择开关区；
其中，所述第一电荷释放子电路设置在所述单元测试区远离扇出区的一侧，所述第二电荷释放子电路设置在所述扇出区与多路选择开关区之间。
本公开实施例还提供了一种显示面板，包括根据本公开实施例的静电释放电路；各所述静电释放电路分别与多个数据信号线之一耦接。
本公开实施例还提供了一种显示装置，所述显示装置包括根据本公开实施例的显示面板。
本公开实施例还提供了一种静电释放电路的驱动方法，所述方法包括：
在所述数据信号线上积聚的第一电荷满足第一条件时，向第一电压输入端输入第一电压信号，对数据信号线上积聚的第一电荷进行静电释放；以及
在所述数据信号线上积聚的第二电荷满足第二条件时，向第二输入端输入第二电压信号，对数据信号线上积聚的第二电荷进行静电释放。
附图说明
图1是一种静电释放电路原理图；
图2是一种多个静电释放电路的布局结构图；
图3是本公开一个实施例的一种显示面板的结构图；
图4是本公开一个实施例的一种静电释放电路的结构图；
图5是本公开一个实施例的第一电荷释放子电路的电路图；
图6是本公开一个实施例的第二电荷释放子电路的电路图；
图7是本公开一个实施例的一种显示面板非显示区域的结构图；
图8是本公开一个实施例的另一种显示面板非显示区域的结构图；
图9是本公开一个实施例的另一种显示面板非显示区域的结构图；
图10是本公开一个实施例的另一种显示面板非显示区域的结构图；
图11是本公开另一实施例的多个静电释放电路的布局结构图；
图12是本公开另一实施例的显示装置的示意图；以及
图13是本公开另一实施例的一种静电释放电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开实施例作进一步详细的说明。
图1示出了一种静电释放电路的原理图。如图1所示，静电释放电路可以包括两个TFT(薄膜晶体管)。其中，一个TFT的栅极连接至第一电压信号端VGH，主要用于释放数据信号线Dada上积聚的例如正电荷(定义为Part1)。另一个TFT的栅极连接数据信号线Dada，主要用于释放数据信号线Dada上积聚的负电荷(定义为Part2)。在例如6.47英寸全高清FHD显示面板中，在剥离上层保护膜(Top Protect Film，TPF)时，激光能量使单元测试区(Cell Test，CT)上方的ESD电路发生灼烧，从而引起AA区(显示区)出现亮线。通过对ESD电路灼烧情况的研究，发明人认为ESD电路中用于释放负电荷的电路连接部分灼烧严重，这是造成整个ESD灼烧的重要因素。发生灼烧的ESD电路部分位于CT单元上方，其在Panel上的位置分布如图2所示，其中Part2部分灼烧严重。此外，由图2可见，这种layout方案占据了panel下部分的空间，不利于空间的合理利用。
参照图3，示出了本公开一个实施例的一种静电释放电路。可以应用于显示面板， 所述显示面板包括AA显示区100和非显示区200。静电释放电路设置在非显示区200中。
图4是本公开一个实施例的一种静电释放电路的结构图。参考图4，静电释放电路可以包括第一电荷释放子电路201和第二电荷释放子电路202。
第一电荷释放子电路201设置在所述非显示区的第一子区域。第一电荷释放子电路201的第一端与数据信号线的布设于所述第一子区域中的第一信号输入端2011耦接，第一电荷释放子电路201的第二端与第一电压输入端耦接。第一电荷释放子电路201被配置为释放所述数据信号线上积聚的第一电荷。
第二电荷释放子电路202设置在所述非显示区的第二子区域。第二电荷释放子电路202的第一端与所述数据信号线的布设于第二子区域中的第二信号输入端2021耦接，第二电荷释放子电路202的第二端与第二电压输入端耦接。第二电荷释放子电路202被配置为释放数据信号线上积聚的第二电荷。
本公开实施例中，针对静电释放电路在释放静电时灼伤严重的情况，将静电释放电路设置为第一电荷释放子电路和第二电荷释放子电路。第一电荷释放子电路用于释放数据信号线上积聚的第一电荷，例如，第一电荷为正电荷。第二电荷释放子电路用于释放数据信号线上积聚的第二电荷，例如，第二电荷为负电荷。第一电荷释放子电路与第一信号输入端耦接，所述第二电荷释放子电路与第二信号输入端耦接。其中，所述第一信号输入端和第二信号输入端都与数据信号线耦接，以便释放数据信号线上积聚的电荷。
本公开实施例将第一电荷释放子电路和第二电荷释放子电路分别设置在所述非显示区的第一子区域中和第二子区域中。通过本公开实施例将所述第一电荷释放子电路和第二电荷释放子电路分开设置，不仅能保证静电电路的应有功能，同时能够实现电路空间的合理利用。
图5是本公开一个实施例的第一电荷释放子电路的电路图。参考图5，第一电荷释放子电路包括第一晶体管T1。第一晶体管T1的控制极及第一极均与第一电压输入端VGH耦接，第一晶体管T1的第二极与第一信号输入端2011耦接。第一电荷可以为正电荷，第一电压输入端可以为正电源电压输入端。
图6是本公开一个实施例的第二电荷释放子电路的电路图。参考图6，第二电荷释放子电路包括第二晶体管T2。第二晶体管T2的控制极及第一极均与第二信号输入端2021耦接，第二晶体管的第二极与第二电压输入端VGL耦接。第二电荷可以为负电荷， 第二电压输入端可以为负电源电压输入端。
第一晶体管T2的第二级与第一信号输入端2011耦接，第一信号输入端2011与数据信号线耦接。第一电压输入端为正电源电压输入端，第一晶体管通过与第一电压输入端耦接，释放数据信号线上积聚的正电荷。第二晶体管的第一级与第二信号输入端2021耦接，第二信号输入端2021与数据信号线耦接。第二电压输入端为负电源电压输入端，第二晶体管通过与第二电压输入端耦接，释放数据信号线上积聚的负电荷。
图7是本公开一个实施例的一种显示面板非显示区域的结构图。参考图7，非显示区的显示面板包括层叠设置的单元测试区701、扇出区702和多路选择开关区703。其中，第一电荷释放子电路201设置在扇出区702与单元测试区701之间，第二电荷释放子电路202设置在所述多路选择开关区703远离所述扇出区702的一侧。
本公开实施例，将第一电荷释放子电路201设置在扇出区702与单元测试区701之间。第一电荷释放子电路用于释放数据信号线上的正电荷，从而保证数据信号线不受正电荷的影响。将第二电荷释放子电路设置在多路选择开关区703背离扇出区702的一侧。第二电荷释放子电路用于释放数据信号线上的负电荷，从而保证数据信号线不受负电荷的影响。本公开实施例将静电释放电路设置为两个相对独立的部分，分别设置在非显示区的不同区域，能够有效避免因释放负电荷的第二电荷释放子电路发生灼烧而影响整个静电释放电路性能，从而在保证静电释放电路防护功能的前提下降低静电释放电路发生灼烧的概率，提高产品的良率，提高产品的显示效果。并且，基于此，第一电荷释放子电路和第二电荷释放子电路所占用的空间为原来静电释放电路占用空间的一半。在空间有限的情况下，这种分开设置的方式可以不仅可以有效降低静电释放电路发生灼伤的概率，还可以同时实现合理利用空间。
作为一种示例，图8是本公开一个实施例的另一种显示面板非显示区域的结构图。参考图8，非显示区的显示面板可以包括层叠设置的单元测试区701、扇出区702和多路选择开关区703。其中，第一电荷释放子电路201设置在扇出区702与单元测试区701之间，第二电荷释放202子电路设置在多路选择开关区703与扇出区702之间。
作为另一种示例，图9是本公开一个实施例的另一种显示面板非显示区域的结构图。
参考图9，非显示区的显示面板包括层叠设置的单元测试区701、扇出区702和多路选择开关区703。其中，第一电荷释放子电路201设置在扇出区702与单元测试区701之间，第二电荷释放子电路202设置在所述单元测试区701背离所述扇出区702的一侧。
作为另一种示例，图10是本公开一个实施例的另一种显示面板非显示区域的结构图。参考图10，所述非显示区的所述显示面板包括层叠设置单元测试区701、扇出区702和多路选择开关区703。
其中，第一电荷释放子电路201设置在单元测试区701远离扇出区702的一侧，第二电荷释放子电路202设置在扇出区702与多路选择开关区703之间。
在本公开实施例中，第一电荷释放子电路201和第二电荷释放子电路202可以任意放置在单元测试区701、扇出区702、多路选择开关区703之间或者一侧。可以理解，本公开实施例只对第一电荷释放子电路201和第二电荷释放子电路202不设置在同一区域作限制，而不对具体放置在哪两个区域进行限制。
本公开实施例还提供了一种显示面板。图11是本公开另一实施例的多个静电释放电路的布局结构图。参考图11，显示面板110可以包括多个的静电释放电路；各静电释放电路分别与多个数据信号线Data1、Data2、…DataN之一耦接。
本公开实施例中，各静电释放电路都包括用于释放正电荷的第一静电释放子电路和用于释放负电荷的第二静电释放子电路。
本公开实施例将静电释放电路中的第一电荷释放子电路和第二电荷释放子电路分开设置，分别设置在非显示区的第一子区域中和第二子区域中。本公开实施例将所述第一电荷释放子电路和第二电荷释放子电路分开放置不仅能保证静电电路的应有功能，提高良品率，而且还能够实现电路空间的合理利用。
本公开实施例提供了一种显示装置，图12是本公开实施例的显示装置的示意图。如图12所示，显示装置120包括根据本公开实施例的显示面板121。
本公开实施例中，由于显示装置包括了根据本公开实施例的显示面板，而显示面板包括了根据本公开实施例的静电释放电路，故公开实施例同样具有能保证静电电路的应有功能，提高良品率，而且能够实现BP电路空间的合理利用。
本公开实施例提供了一种静电释放电路的驱动方法。图13是本公开实施例的静电释放电路的驱动方法的流程图。如图13所示，根据本公开实施例的静电释放电路的驱 动方法可以包括以下步骤。
在步骤S1301，在数据信号线上积聚的第一电荷满足第一条件时，向第一电压输入端输入第一电压信号，以便对数据信号线上积聚的第一电荷进行静电释放。
在步骤S1302，在数据信号线上积聚的第二电荷满足第二条件时，向第二电压输入端输入第二电压信号，以便对数据信号线上积聚的第二电荷进行静电释放。
本公开实施例中，当数据信号线上积聚的第一电荷满足第一条件时，向第一电荷释放子电路的第一电压输入端输入第一电压信号。例如，第一条件可以为：所述数据信号线上积聚正电荷的量大于第一阈值。其中第一阈值可根据具体的情况而定。例如：第一阈值为能够使静电释放电路产生灼烧的最低正电荷量。利用所述第一电压输入端输入的第一电压信号，对数据信号线上积聚的第一电荷进行静电释放。
当数据信号线上积聚的负电荷满足第二条件时，向所述第二电荷释放子电路的第二电压输入端输入第二电压信号。例如，第二条件可以为：数据信号线上积聚负电荷的量大于第二阈值。其中第二阈值可根据具体的情况而定。例如，所述第二阈值为能够使静电释放电路产生灼烧的最低负电荷的量。利用第二电压输入端输入的第二电压信号，对数据信号线上积聚的第二电荷进行静电释放。
本公开实施例将所述静电释放电路中的第一电荷释放子电路和第二电荷释放子电路分开设置，分别设置在所述非显示区的第一子区域中和第二子区域中。本公开实施例将所述第一电荷释放子电路和第二电荷释放子电路分开放置不仅能保证静电电路的应有功能，提高良品率，而且还能够实现BP电路空间的合理利用。
对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合。但是本领域技术人员应该知悉，本公开实施例并不受所描述的动作顺序的限制，因为依据本公开实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和子电路并不一定是本公开实施例所必须的。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操 作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开实施例所提供的一种静电释放电路、显示面板、显示装置以及静电释放方法，进行了详细介绍。本文中应用了具体个例对本公开实施例的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开实施例的方法及其核心思想。同时，对于本领域的一般技术人员，依据本公开实施例的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开实施例的限制。

Claims (10)

  1. 一种静电释放电路，应用于显示面板，所述显示面板包括显示区和非显示区；所述静电释放电路设置在所述非显示区，所述静电释放电路：
    第一电荷释放子电路，设置在所述非显示区的第一子区域，第一电荷释放子电路的第一端与数据信号线的布设于所述第一子区域中的第一信号输入端耦接，第一电荷释放子电路的第二端与第一电压输入端耦接，第一电荷释放子电路被配置为释放所述数据信号线上积聚的第一电荷；以及
    第二电荷释放子电路，设置在所述非显示区的第二子区域，第二电荷释放子电路的第一端与所述数据信号线的布设于所述第二子区域中的第二信号输入端耦接，第二电荷释放子电路的第二端与第二电压输入端耦接，第二电荷释放子电路被配置为释放所述数据信号线上积聚的第二电荷。
  2. 根据权利要求1所述的释放电路，其中，所述第一电荷释放子电路包括第一晶体管，
    所述第一晶体管的控制极及第一极均与所述第一电压输入端耦接，所述第一晶体管的第二极与所述第一信号输入端耦接，所述第一电荷为正电荷，所述第一电压输入端为正电源电压输入端。
  3. 根据权利要求1所述的释放电路，其中，所述第二电荷释放子电路包括第二晶体管，
    所述第二晶体管的控制极及第一极均与所述第二信号输入端耦接，所述第二晶体管的第二极与所述第二电压输入端耦接，所述第二电荷为负电荷，所述第二电压输入端为负电源电压输入端。
  4. 根据权利要求1所述的释放电路，其中，所述非显示区的所述显示面板包括层叠设置的单元测试区、扇出区和多路选择开关区；
    其中，所述第一电荷释放子电路设置在所述扇出区与所述单元测试区之间，所述第二电荷释放子电路设置在所述多路选择开关区远离所述扇出区的一侧。
  5. 根据权利要求1所述的释放电路，其特征在于，所述非显示区的所述显示面板包括层叠设置的单元测试区、扇出区、多路选择开关区；
    其中，所述第一电荷释放子电路设置在所述扇出区与所述单元测试区之间，所 述第二电荷释放子电路设置在所述多路选择开关区与扇出区之间。
  6. 根据权利要求1所述的释放电路，其中，所述非显示区的所述显示面板包括层叠设置的单元测试区、扇出区、多路选择开关区；
    其中，所述第一电荷释放子电路设置在所述扇出区与所述单元测试区之间，所述第二电荷释放子电路设置在所述单元测试区背离所述扇出区的一侧。
  7. 根据权利要求1所述的释放电路，其特征在于，所述非显示区的所述显示面板包括层叠设置单元测试区、扇出区、多路选择开关区；
    其中，所述第一电荷释放子电路设置在所述单元测试区远离扇出区的一侧，所述第二电荷释放子电路设置在所述扇出区与多路选择开关区之间。
  8. 一种显示面板，包括多个如权利要求1-7任一所述的静电释放电路，其中，各所述静电释放电路分别与多个数据信号线之一耦接。
  9. 一种显示装置，包括权利要求8所述的显示面板。
  10. 一种如权利要求1所述的静电释放电路的驱动方法，包括：
    响应于所述数据信号线上积聚的第一电荷满足第一条件，向所述第一电压输入端输入第一电压信号，以便对数据信号线上积聚的第一电荷进行静电释放；
    响应于所述数据信号线上积聚的第二电荷满足第二条件，向第二输入端输入第二电压信号，以便对数据信号线上积聚的第二电荷进行静电释放。
PCT/CN2020/084882 2019-06-24 2020-04-15 静电释放电路、显示面板、显示装置以及静电释放电路的驱动方法 WO2020259012A1 (zh)

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