WO2020258428A1 - 一种显示装置 - Google Patents

一种显示装置 Download PDF

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Publication number
WO2020258428A1
WO2020258428A1 PCT/CN2019/097161 CN2019097161W WO2020258428A1 WO 2020258428 A1 WO2020258428 A1 WO 2020258428A1 CN 2019097161 W CN2019097161 W CN 2019097161W WO 2020258428 A1 WO2020258428 A1 WO 2020258428A1
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WO
WIPO (PCT)
Prior art keywords
circuit
connector
conversion circuit
core
signal
Prior art date
Application number
PCT/CN2019/097161
Other languages
English (en)
French (fr)
Inventor
吴永良
陈宥烨
孙磊
刘子涵
师俊
Original Assignee
咸阳彩虹光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/CN2019/095757 external-priority patent/WO2020258392A1/zh
Application filed by 咸阳彩虹光电科技有限公司 filed Critical 咸阳彩虹光电科技有限公司
Priority to EP19934878.0A priority Critical patent/EP3985657A4/en
Publication of WO2020258428A1 publication Critical patent/WO2020258428A1/zh
Priority to US17/553,177 priority patent/US11620930B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the invention belongs to the field of displays, and specifically relates to a display device.
  • the display mainly includes System On Chip (SOC), Timing Control (TCON), horizontal direction circuit panel (X-board, XB), source
  • SOC System On Chip
  • TCON Timing Control
  • X-board XB
  • source The driving circuit and the gate driving circuit, wherein the system-on-chip receives the image data signal to be transmitted, and outputs the image data signal to be transmitted, and then the input signal is processed by the row expansion module and the column expansion module, and the processed data It is transmitted to the timing control board, and the timing control board transmits the received data to the source drive circuit and the gate drive circuit through the horizontal direction circuit panel, thereby driving the thin film transistor liquid crystal display to display.
  • the circuit main board and the horizontal direction circuit panel are usually connected through a flexible flat cable (Flexible Flat Cable, FFC) for signal transmission between the two.
  • FFC Flexible Flat Cable
  • the present invention provides a display device.
  • the technical problem to be solved by the present invention is realized through the following technical solutions:
  • a display device includes:
  • a display panel with a gate drive circuit and a source drive circuit thereon;
  • the XB board has a drive circuit board assembly thereon.
  • the drive circuit board assembly includes a display control circuit and a first connector.
  • the display control circuit is electrically connected to the gate drive circuit, the source drive circuit, and the first connector. Connector;
  • a system board provided with a second connector and a system-on-chip electrically connected to the second connector, and the system-on-chip has a built-in optical taste adjustment IP core;
  • the connector is connected between the first connector and the second connector.
  • the XB board includes at least two circuit sub-boards arranged in parallel, the drive circuit board assembly is disposed on any one of the circuit sub-boards, and each of the plurality of circuit sub-boards is adjacent to each other. An electrical connection is formed between the two circuit sub-boards through the connector and the respective connector.
  • the XB board is also provided with several Mini-LVDS interfaces
  • the first connector includes a P2P interface
  • the display control circuit includes a signal conversion circuit
  • the signal conversion circuit is electrically connected to the A first connector and the Mini-LVDS interface are configured to receive a P2P interface signal including image data via the first connector, and generate a source control signal and a second interface type image according to the P2P interface signal
  • the data signal is output to the source driving circuit through the Mini-LVDS interface, wherein the second interface type image data signal is a Mini-LVDS interface signal.
  • the display control circuit further includes a level conversion circuit and a DC voltage conversion circuit; wherein,
  • the DC voltage conversion circuit is electrically connected to the first connector and is configured to receive an input DC voltage via the first connector and generate a gate switching voltage and a reference voltage to the level respectively according to the input DC voltage Conversion circuit;
  • the level conversion circuit is electrically connected to the first connector, and is configured to receive a reference timing signal via the first connector to generate a gate according to the reference timing signal and the gate switch voltage Control signals to the gate drive circuit.
  • the DC voltage conversion circuit, the level conversion circuit, and the signal conversion circuit are integrated in the same chip; or the DC voltage conversion circuit and the level conversion circuit are integrated in the same chip Chip and the signal conversion circuit is integrated in another chip; or the DC voltage conversion circuit and the signal conversion circuit are integrated in the same chip and the level conversion circuit is integrated in another chip; or the level conversion The circuit and the signal conversion circuit are integrated in the same chip and the DC voltage conversion circuit is integrated in another chip; or the DC voltage conversion circuit, the level conversion circuit and the signal conversion circuit are integrated in the same chip.
  • the display control circuit includes a level conversion circuit, a DC voltage conversion circuit, and a Gamma correction circuit; wherein,
  • the DC voltage conversion circuit is electrically connected to the first connector and is configured to receive an input DC voltage via the first connector and generate a gate switching voltage and a reference voltage to the level respectively according to the input DC voltage
  • the conversion circuit and the Gamma correction circuit ;
  • the level conversion circuit is electrically connected to the first connector, and is configured to receive a reference timing signal via the first connector to respond to the reference timing signal and the gate
  • the pole switch voltage generates a gate control signal to the gate drive circuit;
  • the Gamma correction circuit is configured to generate a plurality of Gamma voltages to the source drive circuit according to the reference voltage.
  • the XB board further includes a non-volatile memory, the non-volatile memory is electrically connected to the first connector, and the non-volatile memory stores optical taste adjustments.
  • a parameter table wherein the system-on-chip is configured to read the optical taste adjustment parameter stored in the non-volatile memory via the second connector, the connector, and the first connector Table and load to the optical taste adjustment IP core.
  • the optical taste adjustment IP core includes one or more of Mura elimination IP core, white balance adjustment IP core, low color shift compensation IP core, overvoltage drive IP core, and jitter processing IP core
  • the optical taste adjustment parameter table includes corresponding ones of the Mura elimination parameter table, the white balance adjustment parameter table, the low color shift compensation parameter table, the overvoltage drive parameter table, and the dither processing parameter table.
  • the system-on-chip Is configured to sequentially control the Mura elimination IP core, the white balance adjustment IP core, the low color shift compensation IP core, the overvoltage drive IP core, and the jitter processing IP core respectively according to the Mura elimination parameter Table, the white balance adjustment parameter table, the low color shift compensation parameter table, the overvoltage drive parameter table, and the jitter processing parameter table perform mura elimination operation, white balance adjustment, low color shift compensation operation, and overvoltage Drive operation and dither processing operation.
  • the display device of this embodiment is equipped with the drive circuit board assembly on the XB board, so that the XB board has part of the TCON function.
  • the XB board has part of the TCON function.
  • debugging and changing the Panel Timming it is completely independent of SOC and can be developed independently.
  • the structure adjustment of the circuit board MB and the horizontal direction circuit panel XB can be manufactured and sold separately, and the panel manufacturer can independently complete the panel debugging and changes without relying on changes to the SOC.
  • the display device of this embodiment adds a signal conversion circuit (for example in the form of a chip) to the display control circuit of the drive circuit board assembly, which converts the P2P interface signal into a mini-LVDS interface signal on the one hand, so that the source drive circuit
  • the interface between the COF type source driver and the drive circuit board components is changed to a mini-LVDS interface, which greatly reduces the cost;
  • the signal conversion circuit can generate the timing control signals required by the display panel, and panel debugging and revision can be all Completed by the panel manufacturer, the complete machine manufacturer can reduce the development cost without making any changes; on the other hand, the new panel technology can be completed by the signal conversion circuit, and the system board can be completed without any changes.
  • the display device of this embodiment stores the optical taste adjustment parameters in the non-volatile memory on the XB board in the form of a parameter table, and the debugging of each parameter in the optical taste adjustment parameter table is changed from the complete machine manufacturer to the panel manufacturer; Because the optical taste adjustment parameters are strongly related to the panel, the optical taste adjustment parameter tables required by different panels are different, and the panel manufacturers know the optical characteristics of their own panels better, so they can flexibly adjust the optical characteristics of the panel according to their own panel characteristics, so that The whole machine manufacturer is freed from the tedious work of adjusting the optical characteristics to accelerate the development speed of the whole machine.
  • FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the application.
  • FIG. 2 illustrates a specific structure of a display control circuit in the display device shown in FIG. 1;
  • FIG. 3 illustrates another specific structure of the display control circuit in the display device shown in FIG. 1;
  • FIG. 4 is a schematic diagram of internal modules of the system-on-chip and non-volatile memory on the XB board in the display device shown in FIG. 1;
  • FIG. 5 illustrates a specific composition of the optical taste adjustment parameter table and the optical taste adjustment IP core in FIG. 4.
  • a display device 10 provided by an embodiment of the present application includes: a display panel 111 having a gate driving circuit and a source driving circuit thereon; an XB board 113 having a driving circuit board assembly 1130 thereon, and a system Board 13 and connector CL1.
  • the active matrix display device 10 of this embodiment is, for example, a TCONLESS LCD TV.
  • the system-on-chip on the system board integrates at least part of the functions of the traditional TCON chip, and the XB board integrates at least part of the functions of the traditional TCON chip.
  • the embodiments of the present application are not limited thereto.
  • the display panel 111 includes a display area 1111 and a gate drive circuit and a source drive circuit electrically connected to the display area 1111.
  • a plurality of data lines DL, a plurality of gate lines GL, and a plurality of pixels P electrically connecting each data line DL and each gate line GL are provided in the display area 1111; each pixel P is located on the corresponding gate line GL Intersection with data line DL.
  • the gate drive circuit includes, for example, two GOA (Gate-On Array, gate drive circuits integrated on an array substrate) circuits 1113, and the two GOA circuits 1113 are located in the peripheral area of the display area 1111 and are separately provided on two opposite sides of the display area 1111.
  • the gate drive circuit of the display panel 111 is a double-sided GOA circuit.
  • Each GOA circuit 1113 is electrically connected to the gate line GL in the display area 1111, and is used to provide a gate driving signal to each gate line GL in the display area 1111.
  • the source driving circuit includes a plurality of COF type source drivers 1115, such as the twelve COF (Chip-On-Flex, chip-on-film) type source drivers 1115 shown in FIG. 1; each COF type source driver 1115 is electrically connected
  • the data lines DL in the display area 1111 are used for each data line DL to provide image data signals.
  • a single COF-type source driver 1115 includes, for example, a flexible circuit board and a source driver IC (source driver IC) provided on the flexible circuit board.
  • the XB board 113 can be a whole independent circuit board, or multiple circuit daughter boards arranged in parallel. If there are multiple circuit daughter boards arranged in parallel, the driving circuit board assembly 1130 can be arranged on On any one of the circuit sub-boards, each two adjacent circuit sub-boards of the plurality of circuit sub-boards form an electrical connection through a connector and a respective connector.
  • the XB board 113 includes two circuit daughter boards 113a, 113b.
  • the two circuit daughter boards 113a, 113b are arranged on one side of the display panel 111 along the horizontal direction in FIG. That is, as a row-direction drive circuit board; each circuit daughter board 113a, 113b is provided with a COF-type source driver 1115 connection interface such as a mini-LVDS interface on one side adjacent to the display area 1111.
  • the driving circuit board assembly 1130 is arranged on the circuit sub-board 113a.
  • the circuit sub-board 113a is provided with the display control circuit 1131, the connector CN1, the nonvolatile memory 1133, and the connector CN3.
  • the circuit daughter board 113a is electrically connected to the display area 1111 through a plurality of, for example, seven COF-type source drivers 1115, and is electrically connected to the GOA circuit 1113 on the right side of the display panel 111 through the rightmost COF-type source driver 1115.
  • the circuit daughter board 113b is provided with a connector CN4.
  • the circuit daughter board 113b is electrically connected to the display area 1111 through a plurality of, for example, five COF type source drivers 1115, and is electrically connected to the GOA circuit 1113 on the left side of the display panel 111 through the leftmost COF type source driver 1115.
  • the connector CN3 of the circuit daughter board 113a and the connector CN4 of the circuit daughter board 113b form an electrical connection through a connector CL2, where the connector CL2 is, for example, a flexible circuit board or a flexible flat cable (FFC),
  • the connector CL2 is, for example, a flexible circuit board or a flexible flat cable (FFC)
  • the display control circuit 1131 is electrically connected to the first connector CN1, the connector CN3, and a plurality of, for example, seven COF-type source drivers 1115; in this way, the display control circuit 1131 except for the printed circuit board on the circuit sub-board 113a Board, printed circuit board)
  • the wiring is electrically connected to the seven COF source drivers 1115 on the right side, and also connected to the left side through the connector CN3, the connector CL2, the connector CN4, and the PCB trace on the circuit daughter board 113b.
  • a number of Mini-LVDS interfaces are also provided on the XB board 113.
  • the Mini-LVDS interfaces are provided between the COF source driver 1115 and the display control circuit 1131.
  • the first connector includes a P2P interface; see FIG. 2, the display
  • the control circuit 1131 includes a signal conversion circuit 11312 that is electrically connected to the first connector CN1 and the Mini-LVDS interface, and is configured to receive P2P including image data via the first connector CN1 Interface signal, and generate a source control signal and a second interface type image data signal according to the P2P interface signal, and output to the source driving circuit through the Mini-LVDS interface, wherein the second interface type image data
  • the signal is a Mini-LVDS interface signal.
  • the interface of the source driver needs to be adjusted accordingly. For example, if the signal sent by the SOC is transmitted through the P2P interface interface, the corresponding source driver interface Only P2Pinterface can be used, which leads to an increase in overall manufacturing costs and testing costs.
  • the connector CL1 transmits the signal from the SOC to the signal conversion circuit 11312 in the display control circuit 1131 through the P2P interface interface, the signal conversion circuit 11312 can convert the P2P interface signal into a source driver corresponding to the panel.
  • the COF-type source driver interface 1115 is a Mini-LVDS interface
  • the P2P interface signal is converted into a Mini-LVDS signal
  • the converted Mini-LVDS signal is sent to the panel COF-type source driver interface 1115, namely It is equivalent to completing the conversion of the interface signal through the signal conversion circuit 11312, thus completing the data transmission without changing the original Mini-LVDS interface on the panel.
  • a signal conversion circuit 11312 (for example in the form of a chip) to the display control circuit 1131 of the XB board 113a, it converts the P2P interface signal into a mini-LVDS interface signal on the one hand, so that the COF source driver 1115 and the The interface between the XB board 113 is changed to a mini-LVDS interface, which greatly reduces the cost; on the other hand, the signal conversion circuit 11312 can generate the timing control signals required by the display panel 111, and panel debugging and revision can all be completed by the panel manufacturer. The whole machine manufacturer does not need to make any changes, which reduces the development cost; on the other hand, the new panel technology can be completed by the signal conversion circuit 11312, and the system board 13 does not need to make any changes.
  • the display control circuit 1131 may also include a DC voltage conversion circuit 11314, a level conversion circuit 11316, and a Gamma correction (gamma correction) circuit 11318.
  • the signal conversion circuit 11312 is electrically connected to the connector CN1, the level conversion circuit 11316, and the source drive circuit, and is configured to receive reference timing signals such as STV, CKV, and a P2P interface containing image data (such as RGB data) via the connector CN1 Signal, generate source control signals such as TP, POL and a second interface type image data signal such as Mini-LVDS to the source drive circuit according to the P2P interface signal, and generate an initial gate according to the reference timing signals STV and CKV Control signals such as ST_in, CKx_in, LC_in, Reset_in to the level conversion circuit 11316.
  • the DC voltage conversion circuit 11314 is electrically connected to the connector CN1 and is configured to receive the input DC voltage Vin via the connector CN1 and generate gate switching voltages such as VGH, VGL and reference voltages such as VAA to the level conversion circuit 11316 according to the input DC voltage Vin. And Gamma correction circuit 11318.
  • the level conversion circuit 11316 is configured to generate gate control signals such as ST, CKx, LCx, Reset to the gate according to the gate switching voltages VGH, VGL and the initial gate control signals ST_in, CKx_in, LC_in, and Reset_in. Drive circuit.
  • the Gamma correction circuit 11318 is configured to generate a plurality of Gamma voltages such as GMAx to the source driving circuit according to the reference voltage VAA.
  • CKx_in is for example four high frequency clock signals CK1 to CK4
  • CKx is for example eight high frequency clock signals CK1 to CK8
  • LCx is two low frequency clock signals LC1 to LC2 relative to CKx
  • GMAx is, for example, fourteen Gamma voltages such as GMA1 to GMA14
  • VGH is used as the gate turn-on voltage, for example, +20V to +30V
  • VGL is used as the gate turn-off voltage, for example, about -5V, but the application is not limited thereto.
  • the P2P interface signal includes multiple pairs of differential signals, which is another interface type different from the mini LVDS (mini Low Voltage Differential Signaling) interface, and is very suitable for
  • the short-distance signal transmission from the system board 13 to the circuit daughter board 113a may be a well-known and mature USI-T, EPI, CMPI, iSP interface, etc.
  • the DC voltage conversion circuit 11314 is not limited to generating the aforementioned VGH, VGL, and VAA. It is also used to generate the signal conversion circuit 11312, the level conversion circuit 11316, the Gamma correction circuit 11318, and the gate drive circuit.
  • the source driving circuit provides power supply voltages such as digital voltage VDD and analog voltage HVAA (not shown in the figure).
  • the signal conversion circuit 11312, the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the Gamma correction circuit 11318 in the embodiment shown in FIG. 2 are respectively integrated into four different chips; for example, the DC voltage conversion circuit 11314 uses a known For a PMIC chip with mature technology, the level conversion circuit 11316 uses a level shift (Level Shift) chip in a known mature technology, and the Gamma correction circuit 11318 uses a P-Gamma chip in a known mature technology.
  • the DC voltage conversion circuit 11314 uses a known For a PMIC chip with mature technology
  • the level conversion circuit 11316 uses a level shift (Level Shift) chip in a known mature technology
  • the Gamma correction circuit 11318 uses a P-Gamma chip in a known mature technology.
  • the DC voltage conversion circuit 11314 and the level conversion circuit 11316 can be integrated on the same chip and the Gamma correction circuit 11318 can be integrated on another chip, or the DC voltage can be converted
  • the circuit 11314 and the Gamma correction circuit 11318 are integrated in the same chip and the level conversion circuit 11316 is integrated in another chip, or the level conversion circuit 11316 and the Gamma correction circuit 11318 are integrated in the same chip and the DC voltage conversion circuit 11314 is integrated in the same chip, It is even possible to integrate the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the Gamma correction circuit 11318 into the same chip.
  • the SOC needs to be coordinated when debugging and changing the Panel Timming.
  • some functions of the TCON IC in this implementation are set on the XB board. Timming does not depend on SOC at all when debugging and changing, and can develop independently.
  • the circuit main board MB and the horizontal direction circuit panel XB can be manufactured and sold separately, and the panel manufacturer can independently complete panel debugging and changes without relying on changes to the SOC.
  • the display control circuit 1131 includes the Gamma correction circuit 11318
  • the Gamma correction circuit 11318 is arranged on the horizontal direction circuit panel XB
  • the power management circuit 135 can also be arranged on the horizontal direction circuit panel XB.
  • the power management circuit 135 is connected to the display control circuit 1131, so that the panel manufacturer can adjust and revise the power supply part when the panel is manufactured.
  • the display control circuit 1131 may not include one or more of the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the Gamma correction circuit 11318.
  • the DC voltage conversion circuit 11314 when the Gamma correction circuit 11318 is not included, the DC voltage conversion circuit 11314 , The level conversion circuit 11316 and the signal conversion circuit 11312 can be integrated in the same chip; or the DC voltage conversion circuit 11314 and the level conversion circuit 11316 are integrated in the same chip and the signal conversion circuit 11312 is integrated in another chip; or the DC voltage conversion The circuit 11314 and the signal conversion circuit 11312 are integrated in the same chip and the level conversion circuit 11316 is integrated in another chip; or the level conversion circuit 11316 and the signal conversion circuit 11312 are integrated in the same chip and the DC voltage conversion circuit 11314 is integrated in another chip Chip; or the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the signal conversion circuit 11312 are integrated in the same chip.
  • the display control circuit 1131 includes a signal conversion circuit 11312, a DC voltage conversion circuit 11314, a level conversion circuit 11316 and a Gamma correction circuit 11318.
  • the signal conversion circuit 11312 is electrically connected to the connector CN1 and the source drive circuit, and is configured to receive a P2P interface signal containing image data via the connector CN1, and generate source control signals TP, POL, and the first source control signal according to the P2P interface signal.
  • Two-interface type image data signal such as Mini-LVDS to the source driving circuit.
  • the DC voltage conversion circuit 11314 is electrically connected to the connector CN1 and is configured to receive the input DC voltage Vin via the connector CN1 and generate gate switching voltages such as VGH, VGL and reference voltages such as VAA to level conversion according to the input DC voltage Vin.
  • the level conversion circuit 11316 is electrically connected to the connector CN1, and is configured to receive reference timing signals such as STV and CKV via the connector CN1 to generate a gate according to the reference timing signals STV, CKV and the gate switching voltages VGH, VGL. Control signals such as ST, CKx, LCx, Reset to the gate drive circuit.
  • the Gamma correction circuit 11318 is configured to generate a plurality of Gamma voltages GMAx to the source driving circuit according to the reference voltage VAA.
  • the reference timing signals STV and CKV in the embodiment shown in FIG. 3 are directly sent to the level conversion circuit 11316 instead of As shown in FIG. 2, preliminary conversion is performed by the signal conversion circuit 11312 and then sent to the level conversion circuit 11316.
  • the reference timing signals STV and CKV may also be generated locally by the signal conversion circuit 11312 instead of being directly provided by the system board 13.
  • the display control circuit 1131 can be further electrically connected (not shown in FIG. 1) to the non-volatile memory 1133, for example, connected to the non-volatile memory on the same serial bus such as SPI (Serial Peripheral Interface, serial external interface). Set interface) bus; SPI bus has the advantage of fast data read and write speed.
  • SPI Serial Peripheral Interface, serial external interface. Set interface
  • the nonvolatile memory 1133 is electrically connected to the connector CN1. As shown in FIG. 4, the non-volatile memory 1133 stores an optical taste adjustment parameter table 11330, where the optical taste adjustment parameter table 11330 contains parameters that are stronger than the optical taste (or optical characteristics) of the display panel 111 Related parameters.
  • the non-volatile memory 1133 is an SPI interface flash memory (Flash), and correspondingly, the connector CN1 includes an SPI bus interface.
  • the system board 13 is provided with a connector CN2, a system-on-chip 133 and a power management circuit 135.
  • the connector CN2 of the system board 13 is connected to the connector CN1 of the circuit daughter board 113a through the connector CL1.
  • the system-on-chip 133 is electrically connected to the connector CN2 and has a built-in optical taste adjustment IP core 1330 (see Figure 4). In this way, the system-on-chip 133 can be connected in series via the connector CN2, the connector CL1, and the connector CN1.
  • the line communication method reads the optical taste adjustment parameter 11330 stored in the non-volatile memory of the circuit sub-board 113a and loads it to the optical taste adjustment IP core 1330 to adjust the optical taste of the display panel 111.
  • the connector CL1 is, for example, a single flexible cable (FFC).
  • the system board 13 of this embodiment is typically also provided with multiple audio and video input interfaces such as CVBS interface, HDMI interface, etc.; the system board 13 is also called the main board (Main Board), which is used to The video and audio signals input by the audio and video input interface are decoded, and then the video signals are output to the XB board in digital signal format.
  • the optical taste adjustment IP core 1330 includes Mura elimination (Demura) IP core 1331, white balance (white tracking) adjustment IP core 1332, low color shift compensation IP core 1333, overvoltage drive (OverDrive, OD) IP core 1334 and jitter processing IP core 1335, corresponding optical taste adjustment parameter table 11330 includes Mura elimination parameter table 11331, white balance adjustment parameter table 11332, low color shift compensation parameter table 11333, overvoltage drive parameter table 11334 and jitter Processing parameter table 11335.
  • the Mura elimination IP core 1331 is used to perform Mura elimination (that is, a phenomenon that causes various traces due to uneven display brightness) according to the Mura elimination parameter table 11331, and the white balance adjustment IP core 1332 is used to eliminate The balance adjustment parameter table 11332 performs the white balance adjustment operation.
  • the low color shift compensation IP core 1333 is used to perform the low color shift compensation operation according to the low color shift compensation parameter table 11333 to make the display panel 111 achieve low color shift display quality, and the overvoltage drive IP
  • the core 1334 is used to perform overvoltage driving operations according to the overvoltage driving parameter table 11334
  • the jitter processing IP core 1335 is used to perform dither processing operations such as temporal dithering and/or spatial dithering according to the dither processing parameter table 11335 ( spatial dithering).
  • the parameters required for the mura elimination operation the white balance adjustment operation, the low color shift compensation operation, the overvoltage driving operation, and the jitter processing operation, they are known and mature technologies, so they will not be repeated here.
  • the power management circuit 135 it is electrically connected to the connector CN2 to provide an input DC voltage such as 12V to the circuit daughter board 113a; in addition, the power management circuit 135 uses, for example, a mature PMIC chip.
  • the Mura elimination IP core 1331, the white balance adjustment IP core 1332, the low color shift compensation IP core 1333, the overvoltage driving IP core 1334, and the IP core 1334 The jitter processing IP core 1335 performs Mura elimination operation, white balance adjustment, low color shift compensation parameter table 11333, overvoltage drive parameter table 11334, and jitter processing parameter table 11335 according to Mura elimination parameter table 11331, white balance adjustment parameter table 11332, low color shift compensation parameter table 11333, and jitter processing parameter table 11335.
  • the color shift compensation operation, the overvoltage driving operation, and the dithering processing operation, such a specific optical taste adjustment sequence, are relatively easy to make the display panel 111 achieve better display quality and optical taste.
  • the optical taste adjustment IP core 1330 may also only include the Mura elimination IP core 1331, the white balance adjustment IP core 1332, the low color shift compensation IP core 1333, and the overvoltage driving IP core 1334. Similar to some of the IP cores in the jitter processing IP core 1335; similarly, the optical taste adjustment parameter table 11330 can also only include the Mura elimination parameter table 11331, the white balance adjustment parameter table 11332, the low color shift compensation parameter table 11333, and the overvoltage drive parameter Table 11334 and part of the parameter table in the jitter processing parameter table 11335.
  • the optical taste adjustment parameter (or optical code) is stored in the nonvolatile memory 1133 on the circuit daughter board 113a in the form of a parameter table, and the value of each parameter in the optical taste adjustment parameter table 11330 is The debugging is changed from the complete machine manufacturer to the panel manufacturer; because the optical taste adjustment parameters are strongly related to the panel, the optical taste adjustment parameter table required for different panels is different, and the panel manufacturer knows the optical characteristics of their own panels better, so they can follow their own panels.
  • Flexible adjustment of the optical characteristics of the panel can free the complete machine manufacturer from the tedious work of adjusting the optical characteristics to accelerate the development of the complete machine.
  • the foregoing embodiments are only exemplary descriptions of the present application, and the technical solutions of the various embodiments can be combined arbitrarily, provided that the technical features do not conflict, the structure does not contradict, and does not violate the purpose of the invention of the present application.
  • the signal conversion circuit 11312, DC voltage conversion circuit 11314, level conversion circuit 11316, and Gamma correction circuit 11318 of the display control circuit 1131 in the foregoing embodiments are not limited to being distributed on a single circuit sub-board 113a. It can also be distributed on multiple driving circuit boards, such as the circuit sub-boards 113a and 113b in FIG.
  • the above-mentioned display device can be: LTPO display device, Micro LED display device, liquid crystal panel, electronic paper, OLED panel, AMOLED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame and other products with display function or part.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units.
  • the above-mentioned integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium.
  • the above-mentioned software function unit is stored in a storage medium, and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to execute part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disks or optical disks, etc., which can store program codes Medium.

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Abstract

一种显示装置（10），包括：显示面板（111），其上具有栅驱动电路、源驱动电路；XB板（113），其上具有驱动电路板组件（1130），驱动电路板组件（1130）包括显示控制电路（1131）、第一连接器（CN1），显示控制电路（1131）电连接栅驱动电路、源驱动电路和第一连接器（CN1）；系统板（13），其上设置有第二连接器（CN2）和电连接第二连接器（CN2）的系统级芯片（133），系统级芯片（133）内置有光学品味调整IP核（1330）；以及连接件（CL1），连接在第一连接器（CN1）和第二连接器（CN2）之间。通过将驱动电路板组件（1130）设置在XB板（113）上，使得XB板（113）具有部分TCON功能在对Panel Timming进行调试和改变时完全不依赖于SOC，能够独立进行开发，面板厂商能够独立完成面板调试和改变，而无需依赖于对SOC做更改。

Description

一种显示装置 技术领域
本发明属于显示器领域，具体涉及一种显示装置。
背景技术
显示器主要包括设置在电路主板(MB板)上的系统级芯片(System On Chip，简称SOC)、时序控制板(Timing Control，简称TCON)、水平方向电路面板(X-board，简称XB)、源驱动电路和栅驱动电路，其中，系统级芯片接收待传输图像数据信号，并将所述待传输图像数据信号输出，随后将输入信号经过行扩展模块和列扩展模块进行处理，将处理后的数据传送给时序控制板，时序控制板将接收到的数据通过水平方向电路面板传输至源驱动电路和栅驱动电路，从而驱动薄膜晶体管液晶显示器显示。
目前，通常通过柔性扁平电缆(Flexible Flat Cable，简称FFC)来连接电路主板和水平方向电路面板，以进行二者之间的信号传输，然而，由于TCON IC的功能集成在电路主板的SOC上，使得在对面板(Panel)进行调试和改变时，需要SOC配合，由于对TCON的操作均需要依赖于SOC，无法独立对TCON进行开发。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种显示装置。本发明要解决的技术问题通过以下技术方案实现：
一种显示装置，包括：
显示面板，其上具有栅驱动电路、源驱动电路；
XB板，其上具有驱动电路板组件，所述驱动电路板组件包括显示控制电路、第一连接器，所述显示控制电路电连接所述栅驱动电路、所述源驱 动电路和所述第一连接器；
系统板，其上设置有第二连接器和电连接所述第二连接器的系统级芯片，所述系统级芯片内置有光学品味调整IP核；以及
连接件，连接在所述第一连接器和所述第二连接器之间。
在一个具体实施方式中，所述XB板包括并列设置的至少两个电路子板，所述驱动电路板组件设置在任一个所述电路子板上，且所述多个电路子板中每相邻两个电路子板之间通过连接件和各自设置的连接器形成电连接。
在一个具体实施方式中，所述XB板上还设置有若干Mini-LVDS接口，所述第一连接器包括P2P接口；所述显示控制电路包括信号转换电路，所述信号转换电路电连接所述第一连接器和所述Mini-LVDS接口，且被配置成经由所述第一连接器接收包含图像数据的P2P接口信号，并根据所述P2P接口信号生成源极控制信号及第二接口类型图像数据信号，并通过所述Mini-LVDS接口输出至所述源驱动电路，其中，所述第二接口类型图像数据信号为Mini-LVDS接口信号。
在一个具体实施方式中，所述显示控制电路还包括电平转换电路、直流电压转换电路；其中，
所述直流电压转换电路电连接所述第一连接器且被配置成经由所述第一连接器接收输入直流电压并根据所述输入直流电压产生栅极开关电压和基准电压分别至所述电平转换电路；所述电平转换电路电连接所述第一连接器，且被配置成经由所述第一连接器接收基准时序信号以根据所述基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路。
在一个具体实施方式中，所述直流电压转换电路、所述电平转换电路和所述信号转换电路整合于同一个芯片；或者所述直流电压转换电路和所 述电平转换电路整合于同一个芯片且所述信号转换电路整合于另一个芯片；或者所述直流电压转换电路和所述信号转换电路整合于同一个芯片且所述电平转换电路整合于另一个芯片；或者所述电平转换电路和所述信号转换电路整合于同一个芯片且所述直流电压转换电路整合于另一个芯片；或者所述直流电压转换电路、所述电平转换电路和所述信号转换电路整合于同一芯片。
在一个具体实施方式中，所述显示控制电路包括电平转换电路、直流电压转换电路、Gamma校正电路；其中，
所述直流电压转换电路电连接所述第一连接器且被配置成经由所述第一连接器接收输入直流电压并根据所述输入直流电压产生栅极开关电压和基准电压分别至所述电平转换电路和所述Gamma校正电路；所述电平转换电路电连接所述第一连接器，且被配置成经由所述第一连接器接收基准时序信号以根据所述基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；所述Gamma校正电路被配置成根据所述基准电压产生多个Gamma电压至所述源驱动电路。
在一个具体实施方式中，所述XB板上还包括非易失性存储器，所述非易失性存储器电连接所述第一连接器，且所述非易失性存储器内存储有光学品味调整参数表，其中，所述系统级芯片被配置成经由所述第二连接器、所述连接件和所述第一连接器读取所述非易失性存储器内存储的所述光学品味调整参数表并加载至所述光学品味调整IP核。
在一个具体实施方式中，所述光学品味调整IP核包括Mura消除IP核、白平衡调整IP核、低色偏补偿IP核、过压驱动IP核和抖动处理IP核中的一个或多个，所述光学品味调整参数表包括Mura消除参数表、白平衡调整 参数表、低色偏补偿参数表、过压驱动参数表和抖动处理参数表中的相应者。
在一个具体实施方式中，当所述光学品味调整IP核包括Mura消除IP核、白平衡调整IP核、低色偏补偿IP核、过压驱动IP核和抖动处理IP核，所述系统级芯片被配置成依次控制所述Mura消除IP核、所述白平衡调整IP核、所述低色偏补偿IP核、所述过压驱动IP核和所述抖动处理IP核分别根据所述Mura消除参数表、所述白平衡调整参数表、所述低色偏补偿参数表、所述过压驱动参数表和所述抖动处理参数表进行Mura消除操作、白平衡调整、低色偏补偿操作、过压驱动操作和抖动处理操作。
相比现有技术，上述一个或多个技术方案具有如下一个或多个优点或
有益效果：
1、本实施的显示装置通过将驱动电路板组件设置在XB板上，使得XB板具有部分TCON功能在对Panel Timming进行调试和改变时完全不依赖于SOC，能够独立进行开发，通过本实施例的架构调整，使得电路主板MB和水平方向电路面板XB能够分开制造与销售，面板厂商能够独立完成面板调试和改变，而无需依赖于对SOC做更改。
2、本实施例的显示装置通过在驱动电路板组件的显示控制电路中增设信号转换电路(例如以芯片形式呈现)，其一方面将P2P接口信号转为mini-LVDS接口信号，使得源驱动电路中COF型源驱动器与驱动电路板组件之间的接口被改为mini-LVDS接口，成本大大降低；另一方面，信号转换电路可产生显示面板所需的时序控制信号，面板调试、改版可以全部由面板厂商完成，整机厂商可以无需做任何变更，降低了开发成本；又一方面，面板新技术可由信号转换电路完成，系统板可以无需做任何变更。
3、本实施例的显示装置通过将光学品味调整参数以参数表形式存储在XB板上的非易失性存储器中，光学品味调整参数表中各个参数的调试由整机厂商改为面板厂商；因为光学品味调整参数跟面板强相关，不同的面板所需的光学品味调整参数表不同，而面板厂商更了解自己面板的光学特性，因此可以根据自己的面板特性灵活调整面板光学特性，从而可以将整机厂商从繁琐的调整光学特性工作中解放出来，以加速整机的开发速度。
以下将结合附图及实施例对本发明做进一步详细说明。
附图说明
图1为本申请一个实施例的一种显示装置的结构示意图；
图2示意出图1所示显示装置中的显示控制电路的一种具体结构；
图3示意出图1所示显示装置中的显示控制电路的另一种具体结构；
图4为图1所示显示装置中的系统级芯片和XB板上非易失性存储器的内部模块示意图；
图5示意出图4中光学品味调整参数表和光学品味调整IP核的一种具体构成。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。
实施例一
如图1所示，本申请一个实施例提供的一种显示装置10，包括：显示面板111，其上具有栅驱动电路、源驱动电路；XB板113，其上具有驱动电路板组件1130，系统板13以及连接件CL1。本实施例的主动式矩阵显示装置10例如是TCONLESS型液晶电视，其系统板上的系统级芯片整合有 传统TCON芯片的至少部分功能，且其XB板上整合有传统TCON芯片的至少部分功能，但本申请实施例并不以此为限。
其中，显示面板111包括显示区域1111和电连接显示区域1111的栅驱动电路及源驱动电路。显示区域1111内设置有多条数据线DL、多条栅极线GL和电连接各条数据线DL与各条栅极线GL的多个像素P；各个像素P位于相对应的栅极线GL与数据线DL的交叉处。所述栅驱动电路例如包括两个GOA(Gate-On Array，栅驱动电路集成在阵列基板上)电路1113，这两个GOA电路1113位于显示区域1111的周边区域且分设于显示区域1111的相对两侧，也即显示面板111的栅驱动电路为双侧GOA电路。各个GOA电路1113电连接显示区域1111内的栅极线GL，用于向显示区域1111的各条栅极线GL提供栅极驱动信号。所述源驱动电路例如包括多个COF型源驱动器1115，比如图1中所示的十二个COF(Chip-On-Flex，覆晶薄膜)型源驱动器1115；各个COF型源驱动器1115电连接显示区域1111内的数据线DL，用于各个数据线DL提供图像数据信号。更具体地，单个COF型源驱动器1115例如包括柔性电路板和设置在柔性电路板上的源驱动器芯片(source driver IC)。
其中，XB板113可以为整块独立的电路板，也可以是多个并列设置的多块电路子板，若为多个并列设置的多块电路子板，则驱动电路板组件1130可以设置在其中任一个电路子板上，且所述多个电路子板中每相邻两个电路子板之间通过连接件和各自设置的连接器形成电连接。
本实施例以两块电路子板进行说明，XB板113包括两个电路子板113a、113b，这两个电路子板113a、113b沿着图1水平方向排列于显示面板111的一侧，也即作为行方向驱动电路板；各个电路子板113a、113b邻近显示 区域1111的一侧设置有COF型源驱动器1115的连接介面例如mini-LVDS接口。如上所述，驱动电路板组件1130设置于电路子板113a上，具体为，电路子板113a设置有显示控制电路1131、连接器CN1、非易失性存储器1133和连接器CN3。电路子板113a通过多个例如七个COF型源驱动器1115电连接显示区域1111，并利用最右侧COF型源驱动器1115电连接显示面板111右侧的GOA电路1113。电路子板113b设置有连接器CN4。电路子板113b通过多个例如五个COF型源驱动器1115电连接显示区域1111，并利用最左侧COF型源驱动器1115电连接显示面板111左侧的GOA电路1113。电路子板113a的连接器CN3和电路子板113b的连接器CN4之间通过连接件CL2形成电连接，此处的连接件CL2例如是柔性电路板或软排线(Flexible Flat Cable，FFC)，从而使得产生于电路子板113a上的信号通过该连接件CL2传输到电路子板113b上。
再者，显示控制电路1131电连接第一连接器CN1、连接器CN3以及多个例如七个COF型源驱动器1115；如此一来，显示控制电路1131除了通过电路子板113a上的PCB(Printed Circuit Board，印刷电路板)走线电连接右侧的七个COF型源驱动器1115之外，还通过连接器CN3、连接件CL2和连接器CN4以及电路子板113b上的PCB走线连接左侧的五个COF型源驱动器1115。XB板113上还设置有若干Mini-LVDS接口，该Mini-LVDS接口设置于COF型源驱动器1115与显示控制电路1131之间，所述第一连接器包括P2P接口；参见图2，所述显示控制电路1131包括信号转换电路11312，所述信号转换电路11312电连接所述第一连接器CN1和所述Mini-LVDS接口，且被配置成经由所述第一连接器CN1接收包含图像数据的P2P接口信号，并根据所述P2P接口信号生成源极控制信号及第二接口 类型图像数据信号，并通过所述Mini-LVDS接口输出至所述源驱动电路，其中，所述第二接口类型图像数据信号为Mini-LVDS接口信号。
需要说明的是，在现有技术中，为了匹配SOC发送的信号，源极驱动器的接口需要对应进行调整，例如，若SOC发送的信号是通过P2Pinterface接口进行传输的，则对应的源极驱动器接口也只能使用P2Pinterface接口，从而导致整体制造成本和测试成本增加。而在本实施例中，若连接件CL1通过P2P interface接口将信号从SOC传输到显示控制电路1131中的信号转换电路11312，信号转换电路11312能够将P2P interface信号转换成对应于该面板源极驱动器的接口信号，例如COF型源驱动器接口1115为Mini-LVDS接口，则对应将P2P interface信号转换成Mini-LVDS信号，将转换后的Mini-LVDS信号发送至该面板COF型源驱动器接口1115，即相当于通过信号转换电路11312完成了接口信号的转换，从而在不改变面板上原来Mini-LVDS接口的情况下完成数据传输。通过在XB板113a的显示控制电路1131中增设信号转换电路11312(例如以芯片形式呈现)，其一方面将P2P接口信号转为mini-LVDS接口信号，使得源驱动电路中COF型源驱动器1115与XB板113之间的接口被改为mini-LVDS接口，成本大大降低；另一方面，信号转换电路11312可产生显示面板111所需的时序控制信号，面板调试、改版可以全部由面板厂商完成，整机厂商可以无需做任何变更，降低了开发成本；又一方面，面板新技术可由信号转换电路11312完成，系统板13可以无需做任何变更。
另一方面，显示控制电路1131还可以包括直流电压转换电路11314、电平转换电路11316和Gamma校正(伽马校正)电路11318。信号转换电路11312电连接连接器CN1、电平转换电路11316和所述源驱动电路，且被配 置成经由连接器CN1接收基准时序信号例如STV、CKV和包含图像数据(比如RGB数据)的P2P接口信号，根据所述P2P接口信号生成源极控制信号例如TP、POL及第二接口类型图像数据信号例如Mini-LVDS至所述源驱动电路，以及根据所述基准时序信号STV、CKV生成初始栅极控制信号例如ST_in、CKx_in、LC_in、Reset_in至电平转换电路11316。直流电压转换电路11314电连接连接器CN1且被配置成经由连接器CN1接收输入直流电压Vin并根据输入直流电压Vin产生栅极开关电压例如VGH、VGL和基准电压例如VAA分别至电平转换电路11316和Gamma校正电路11318。电平转换电路11316被配置成根据所述栅极开关电压VGH、VGL和所述初始栅极控制信号ST_in、CKx_in、LC_in、Reset_in产生栅极控制信号例如ST、CKx、LCx、Reset至所述栅驱动电路。Gamma校正电路11318被配置成根据所述基准电压VAA产生多个Gamma电压例如GMAx至所述源驱动电路。在一个具体例子中，CKx_in例如为四个高频时钟信号CK1～CK4，CKx例如是八个高频时钟信号CK1～CK8、且LCx为相对于CKx而言的两个低频时钟信号LC1～LC2，GMAx例如为GMA1～GMA14等十四路Gamma电压，VGH作为栅极开启电压例如是+20V～+30V，VGL作为栅极关闭电压例如选取-5V左右，但本申请并不以此为限。此外，值得说明的是，所述P2P接口信号包含多对差分信号，其为一种不同于mini LVDS(mini Low Voltage Differential Signaling，微型低压差分信号)接口的另一种接口类型，而且非常适用于系统板13到电路子板113a这种短距离的信号传输，其可以是已知成熟的USI-T、EPI、CMPI、iSP接口等。另外，需要说明的是，直流电压转换电路11314并不限于产生前述的VGH、VGL及VAA，其还用于向信号转换电路11312、电平转换电路11316、Gamma 校正电路11318、所述栅驱动电路和所述源驱动电路提供电源电压比如数字电压VDD和模拟电压HVAA(图未绘出)。
承上述，图2所示实施例中的信号转换电路11312、直流电压转换电路11314、电平转换电路11316和Gamma校正电路11318例如分别整合于四个不同芯片；例如直流电压转换电路11314采用已知成熟技术的PMIC芯片，电平转换电路11316采用已知成熟技术中的电平转换(Level Shift)芯片，以及Gamma校正电路11318采用已知成熟技术中的P-Gamma芯片。此外，为了进一步提升电路的集成度，在其他实施例中，还可以将直流电压转换电路11314和电平转换电路11316整合于同一芯片且Gamma校正电路11318整合于另一芯片，或者将直流电压转换电路11314和Gamma校正电路11318整合于同一芯片且电平转换电路11316整合于另一芯片，或者将电平转换电路11316和Gamma校正电路11318整合于同一芯片且直流电压转换电路11314整合于同一芯片，甚至还可以将直流电压转换电路11314、电平转换电路11316和Gamma校正电路11318三者整合于同一芯片。
在现有技术中，由于TCON IC的功能集成在电路主板的SOC上，在对Panel Timming进行调试和改变时，需要SOC配合，而本实施的TCON IC部分功能设置于XB板上，在对Panel Timming进行调试和改变时完全不依赖于SOC，能够独立进行开发。通过本实施例的架构调整，使得电路主板MB和水平方向电路面板XB能够分开制造与销售，面板厂商能够独立完成面板调试和改变，而无需依赖于对SOC做更改。
当显示控制电路1131包括Gamma校正电路11318时，由于Gamma校正电路11318设置在水平方向电路面板XB上，使得能够片片调整gamma曲线，此外，电源管理电路135也可以设置在水平方向电路面板XB上，电 源管理电路135连接显示控制电路1131，使面板厂商能够在面板制造时自行调整和改版电源部分。
当然，显示控制电路1131也可以不包括上述直流电压转换电路11314、电平转换电路11316和Gamma校正电路11318中的一个或多个电路，例如不包括Gamma校正电路11318时，则直流电压转换电路11314、电平转换电路11316和信号转换电路11312可以整合于同一个芯片；或者直流电压转换电路11314和电平转换电路11316整合于同一个芯片且信号转换电路11312整合于另一个芯片；或者直流电压转换电路11314和信号转换电路11312整合于同一个芯片且电平转换电路11316整合于另一个芯片；或者电平转换电路11316和信号转换电路11312整合于同一个芯片且直流电压转换电路11314整合于另一个芯片；或者直流电压转换电路11314、电平转换电路11316和信号转换电路11312整合于同一芯片。
参见图3，在另一个实施例中，显示控制电路1131包括信号转换电路11312、直流电压转换电路11314、电平转换电路11316和Gamma校正电路11318。信号转换电路11312电连接连接器CN1和所述源驱动电路，且被配置成经由连接器CN1接收包含图像数据的P2P接口信号，并根据所述P2P接口信号生成源极控制信号TP,POL及第二接口类型图像数据信号例如Mini-LVDS至所述源驱动电路。直流电压转换电路11314电连接连接器CN1且被配置成经由连接器CN1接收输入直流电压Vin并根据所述输入直流电压Vin产生栅极开关电压例如VGH、VGL和基准电压例如VAA分别至电平转换电路11316和Gamma校正电路11318。电平转换电路11316电连接连接器CN1，且被配置成经由连接器CN1接收基准时序信号例如STV、CKV以根据所述基准时序信号STV、CKV和所述栅极开关电压VGH、VGL产 生栅极控制信号例如ST、CKx、LCx、Reset至所述栅驱动电路。Gamma校正电路11318被配置成根据所述基准电压VAA产生多个Gamma电压GMAx至所述源驱动电路。简而言之，图3所示实施例与图2所示实施例的主要不同之处在于：图3所示实施例中的基准时序信号STV、CKV直接送至电平转换电路11316，而非如图2所示先经由信号转换电路11312进行初步转换再送至电平转换电路11316。又或者，在其他实施例中，基准时序信号STV、CKV也可以由信号转换电路11312本地产生而非由系统板13直接提供。
此外，显示控制电路1131还可以进一步电连接(图1中未绘出)非易失性存储器1133，例如与非易失性存储器挂接在同一串行总线比如SPI(Serial Peripheral Interface，串行外设接口)总线；SPI总线具有数据读写速度快的优点。
另外，非易失性存储器1133电连接连接器CN1。如图4所示，非易失性存储器1133内存储有光学品味调整参数表11330，此处的光学品味调整参数表11330中包含的参数为与显示面板111的光学品味(或称光学特性)强相关的参数。在本实施例中，非易失性存储器1133为SPI接口闪存(Flash)，相应地连接器CN1包含SPI总线接口。
系统板13设置有连接器CN2、系统级芯片133和电源管理电路135。系统板13的连接器CN2通过连接件CL1连接电路子板113a的连接器CN1。再者，系统级芯片133电连接连接器CN2且内置有光学品味调整IP核1330(参见图4)，如此一来，系统级芯片133可以经由连接器CN2、连接件CL1和连接器CN1以串行通信方式读取电路子板113a的非易失性存储器中存储的光学品味调整参数11330并加载至光学品味调整IP核1330以对显示 面板111的光学品味进行调整。另外，连接件CL1例如是单条软排线(FFC)。此外，值得一提的是，本实施例的系统板13典型地还设置有多个音视频输入接口例如CVBS接口、HDMI接口等；系统板13又称主板(Main Board)，其用于对经由音视频输入接口输入的视频和音频信号进行解码处理，再将视频信号以数字信号格式输出至XB板。
参见图5，光学品味调整IP核1330包括Mura消除(Demura)IP核1331、白平衡(white tracking)调整IP核1332、低色偏(low color shift)补偿IP核1333、过压驱动(OverDrive,OD)IP核1334和抖动处理IP核1335，相应地光学品味调整参数表11330包括Mura消除参数表11331、白平衡调整参数表11332、低色偏补偿参数表11333、过压驱动参数表11334和抖动处理参数表11335。更具体地，Mura消除IP核1331用于根据Mura消除参数表11331进行Mura(也即一种因显示亮度不均匀而造成各种痕迹的现象)消除操作，白平衡调整IP核1332用于根据白平衡调整参数表11332进行白平衡调整操作，低色偏补偿IP核1333用于根据低色偏补偿参数表11333进行低色偏补偿操作以使得显示面板111达到低色偏显示品质，过压驱动IP核1334用于根据过压驱动参数表11334进行过压驱动操作，以及抖动处理IP核1335用于根据抖动处理参数表11335进行抖动处理操作比如时间抖动处理(temporal dithering)和/或空间抖动处理(spatial dithering)。至于Mura消除操作、白平衡调整操作、低色偏补偿操作、过压驱动操作和抖动处理操作各自所需的参数为已知成熟技术，故在此不再赘述。至于电源管理电路135，其电连接连接器CN2以向电路子板113a提供输入直流电压比如12V；再者，电源管理电路135例如采用成熟的PMIC芯片。
值得一提的是，根据发明人的试验验证得知，通过系统级芯片133依 次控制Mura消除IP核1331、白平衡调整IP核1332、低色偏补偿IP核1333、过压驱动IP核1334和抖动处理IP核1335分别根据Mura消除参数表11331、白平衡调整参数表11332、低色偏补偿参数表11333、过压驱动参数表11334和抖动处理参数表11335进行Mura消除操作、白平衡调整、低色偏补偿操作、过压驱动操作和抖动处理操作，这种特定的光学品味调整顺序，比较容易使得显示面板111达到较佳的显示品质和光学品味。
此外，值得说明的是，在其他实施例中，光学品味调整IP核1330也可以只包括Mura消除IP核1331、白平衡调整IP核1332、低色偏补偿IP核1333、过压驱动IP核1334和抖动处理IP核1335中的部分IP核；类似地，光学品味调整参数表11330也可以只包括Mura消除参数表11331、白平衡调整参数表11332、低色偏补偿参数表11333、过压驱动参数表11334和抖动处理参数表11335中的部分参数表。
综上所述，本申请实施例将光学品味调整参数(或称光学code)以参数表形式存储在电路子板113a上的非易失性存储器1133中，光学品味调整参数表11330中各个参数的调试由整机厂商改为面板厂商；因为光学品味调整参数跟面板强相关，不同的面板所需的光学品味调整参数表不同，而面板厂商更了解自己面板的光学特性，因此可以根据自己的面板特性灵活调整面板光学特性，从而可以将整机厂商从繁琐的调整光学特性工作中解放出来，以加速整机的开发速度。
此外，可以理解的是，前述各个实施例仅为本申请的示例性说明，在技术特征不冲突、结构不矛盾、不违背本申请的发明目的前提下，各个实施例的技术方案可以任意组合、搭配使用。再者，可以理解的是，前述各个实施例中显示控制电路1131的信号转换电路11312、直流电压转换电路 11314、电平转换电路11316和Gamma校正电路11318并不限于分布在单个电路子板113a上，其也可以分布在多个驱动电路板上例如图1中的电路子板113a和113b上。
上述显示装置可以为：LTPO显示装置、Micro LED显示装置、液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框等任何具有显示功能的产品或部件。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多路单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多路网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能单元的形式实现的集成的单元，可以存储在一个计算机可读取存储介质中。上述软件功能单元存储在一个存储介质中，包括若 干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (9)

  1. 一种显示装置，其特征在于，包括：
    显示面板，其上具有栅驱动电路、源驱动电路；
    XB板，其上具有驱动电路板组件，所述驱动电路板组件包括显示控制电路、第一连接器，所述显示控制电路电连接所述栅驱动电路、所述源驱动电路和所述第一连接器；
    系统板，其上设置有第二连接器和电连接所述第二连接器的系统级芯片，所述系统级芯片内置有光学品味调整IP核；以及
    连接件，连接在所述第一连接器和所述第二连接器之间。
  2. 根据权利要求1所述的显示装置，其特征在于，所述XB板包括并列设置的至少两个电路子板，所述驱动电路板组件设置在任一个所述电路子板上，且所述多个电路子板中每相邻两个电路子板之间通过连接件和各自设置的连接器形成电连接。
  3. 根据权利要求1所述的显示装置，其特征在于，所述XB板上还设置有若干Mini-LVDS接口，所述第一连接器包括P2P接口；所述显示控制电路包括信号转换电路，所述信号转换电路电连接所述第一连接器和所述Mini-LVDS接口，且被配置成经由所述第一连接器接收包含图像数据的P2P接口信号，并根据所述P2P接口信号生成源极控制信号及第二接口类型图像数据信号，并通过所述Mini-LVDS接口输出至所述源驱动电路，其中，所述第二接口类型图像数据信号为Mini-LVDS接口信号。
  4. 根据权利要求3所述的显示装置，其特征在于，所述显示控制电路还包括电平转换电路、直流电压转换电路；其中，
    所述直流电压转换电路电连接所述第一连接器且被配置成经由所述第一连接器接收输入直流电压并根据所述输入直流电压产生栅极开关电压和 基准电压分别至所述电平转换电路；所述电平转换电路电连接所述第一连接器，且被配置成经由所述第一连接器接收基准时序信号以根据所述基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路。
  5. 根据权利要求4所述的显示装置，其特征在于，所述直流电压转换电路、所述电平转换电路和所述信号转换电路整合于同一个芯片；或者所述直流电压转换电路和所述电平转换电路整合于同一个芯片且所述信号转换电路整合于另一个芯片；或者所述直流电压转换电路和所述信号转换电路整合于同一个芯片且所述电平转换电路整合于另一个芯片；或者所述电平转换电路和所述信号转换电路整合于同一个芯片且所述直流电压转换电路整合于另一个芯片；或者所述直流电压转换电路、所述电平转换电路和所述信号转换电路整合于同一芯片。
  6. 根据权利要求3所述的显示装置，其特征在于，所述显示控制电路包括电平转换电路、直流电压转换电路、Gamma校正电路；其中，
    所述直流电压转换电路电连接所述第一连接器且被配置成经由所述第一连接器接收输入直流电压并根据所述输入直流电压产生栅极开关电压和基准电压分别至所述电平转换电路和所述Gamma校正电路；所述电平转换电路电连接所述第一连接器，且被配置成经由所述第一连接器接收基准时序信号以根据所述基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；所述Gamma校正电路被配置成根据所述基准电压产生多个Gamma电压至所述源驱动电路。
  7. 根据权利要求1所述的显示装置，其特征在于，所述XB板上还包括非易失性存储器，所述非易失性存储器电连接所述第一连接器，且所述非易失性存储器内存储有光学品味调整参数表，其中，所述系统级芯片被 配置成经由所述第二连接器、所述连接件和所述第一连接器读取所述非易失性存储器内存储的所述光学品味调整参数表并加载至所述光学品味调整IP核。
  8. 根据权利要求1所述的显示装置，其特征在于，所述光学品味调整IP核包括Mura消除IP核、白平衡调整IP核、低色偏补偿IP核、过压驱动IP核和抖动处理IP核中的一个或多个，所述光学品味调整参数表包括Mura消除参数表、白平衡调整参数表、低色偏补偿参数表、过压驱动参数表和抖动处理参数表中的相应者。
  9. 根据权利要求8所述的显示装置，其特征在于，当所述光学品味调整IP核包括Mura消除IP核、白平衡调整IP核、低色偏补偿IP核、过压驱动IP核和抖动处理IP核，所述系统级芯片被配置成依次控制所述Mura消除IP核、所述白平衡调整IP核、所述低色偏补偿IP核、所述过压驱动IP核和所述抖动处理IP核分别根据所述Mura消除参数表、所述白平衡调整参数表、所述低色偏补偿参数表、所述过压驱动参数表和所述抖动处理参数表进行Mura消除操作、白平衡调整、低色偏补偿操作、过压驱动操作和抖动处理操作。
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