WO2020258428A1

WO2020258428A1 - Display device

Info

Publication number: WO2020258428A1
Application number: PCT/CN2019/097161
Authority: WO
Inventors: 吴永良; 陈宥烨; 孙磊; 刘子涵; 师俊
Original assignee: 咸阳彩虹光电科技有限公司
Priority date: 2019-06-25
Filing date: 2019-07-22
Publication date: 2020-12-30
Also published as: EP3985657A4; CN112133256A; EP3985657A1

Abstract

A display device (10), comprising: a display panel (111) having a gate drive circuit and a source drive circuit thereon; an X-board (113) having a drive circuit board assembly (1130) thereon, wherein the drive circuit board assembly (1130) comprises a display control circuit (1131) and a first connector (CN1), and the display control circuit (1131) is electrically connected to the gate drive circuit, the source drive circuit, and the first connector (CN1); a system board (13) provided with a second connector (CN2) and a system on a chip (133) electrically connected to the second connector (CN2), wherein the system on a chip (133) is provided with a built-in optical level adjustment IP core (1330); and a connection member (CL1) connected between the first connector (CN1) and the second connector (CN2). The drive circuit board assembly (1130) is disposed on the X-board (113), such that the X-board (113) has part of TCON functions, and does not rely on the SOC when performing debugging and adjustment during panel trimming, thereby facilitating independent development, and enabling panel manufacturers to independently perform panel debugging and adjustment without the need to modify the SOC.

Description

A display device

Technical field

The invention belongs to the field of displays, and specifically relates to a display device.

Background technique

The display mainly includes System On Chip (SOC), Timing Control (TCON), horizontal direction circuit panel (X-board, XB), source The driving circuit and the gate driving circuit, wherein the system-on-chip receives the image data signal to be transmitted, and outputs the image data signal to be transmitted, and then the input signal is processed by the row expansion module and the column expansion module, and the processed data It is transmitted to the timing control board, and the timing control board transmits the received data to the source drive circuit and the gate drive circuit through the horizontal direction circuit panel, thereby driving the thin film transistor liquid crystal display to display.

At present, the circuit main board and the horizontal direction circuit panel are usually connected through a flexible flat cable (Flexible Flat Cable, FFC) for signal transmission between the two. However, because the function of TCON IC is integrated on the SOC of the circuit main board, So that when debugging and changing the panel (Panel), the cooperation of SOC is required. Because the operation of TCON needs to rely on SOC, it is impossible to develop TCON independently.

Summary of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a display device. The technical problem to be solved by the present invention is realized through the following technical solutions:

A display device includes:

A display panel with a gate drive circuit and a source drive circuit thereon;

The XB board has a drive circuit board assembly thereon. The drive circuit board assembly includes a display control circuit and a first connector. The display control circuit is electrically connected to the gate drive circuit, the source drive circuit, and the first connector. Connector;

A system board provided with a second connector and a system-on-chip electrically connected to the second connector, and the system-on-chip has a built-in optical taste adjustment IP core; and

The connector is connected between the first connector and the second connector.

In a specific embodiment, the XB board includes at least two circuit sub-boards arranged in parallel, the drive circuit board assembly is disposed on any one of the circuit sub-boards, and each of the plurality of circuit sub-boards is adjacent to each other. An electrical connection is formed between the two circuit sub-boards through the connector and the respective connector.

In a specific embodiment, the XB board is also provided with several Mini-LVDS interfaces, the first connector includes a P2P interface; the display control circuit includes a signal conversion circuit, and the signal conversion circuit is electrically connected to the A first connector and the Mini-LVDS interface are configured to receive a P2P interface signal including image data via the first connector, and generate a source control signal and a second interface type image according to the P2P interface signal The data signal is output to the source driving circuit through the Mini-LVDS interface, wherein the second interface type image data signal is a Mini-LVDS interface signal.

In a specific embodiment, the display control circuit further includes a level conversion circuit and a DC voltage conversion circuit; wherein,

The DC voltage conversion circuit is electrically connected to the first connector and is configured to receive an input DC voltage via the first connector and generate a gate switching voltage and a reference voltage to the level respectively according to the input DC voltage Conversion circuit; the level conversion circuit is electrically connected to the first connector, and is configured to receive a reference timing signal via the first connector to generate a gate according to the reference timing signal and the gate switch voltage Control signals to the gate drive circuit.

In a specific embodiment, the DC voltage conversion circuit, the level conversion circuit, and the signal conversion circuit are integrated in the same chip; or the DC voltage conversion circuit and the level conversion circuit are integrated in the same chip Chip and the signal conversion circuit is integrated in another chip; or the DC voltage conversion circuit and the signal conversion circuit are integrated in the same chip and the level conversion circuit is integrated in another chip; or the level conversion The circuit and the signal conversion circuit are integrated in the same chip and the DC voltage conversion circuit is integrated in another chip; or the DC voltage conversion circuit, the level conversion circuit and the signal conversion circuit are integrated in the same chip.

In a specific embodiment, the display control circuit includes a level conversion circuit, a DC voltage conversion circuit, and a Gamma correction circuit; wherein,

The DC voltage conversion circuit is electrically connected to the first connector and is configured to receive an input DC voltage via the first connector and generate a gate switching voltage and a reference voltage to the level respectively according to the input DC voltage The conversion circuit and the Gamma correction circuit; the level conversion circuit is electrically connected to the first connector, and is configured to receive a reference timing signal via the first connector to respond to the reference timing signal and the gate The pole switch voltage generates a gate control signal to the gate drive circuit; the Gamma correction circuit is configured to generate a plurality of Gamma voltages to the source drive circuit according to the reference voltage.

In a specific embodiment, the XB board further includes a non-volatile memory, the non-volatile memory is electrically connected to the first connector, and the non-volatile memory stores optical taste adjustments. A parameter table, wherein the system-on-chip is configured to read the optical taste adjustment parameter stored in the non-volatile memory via the second connector, the connector, and the first connector Table and load to the optical taste adjustment IP core.

In a specific embodiment, the optical taste adjustment IP core includes one or more of Mura elimination IP core, white balance adjustment IP core, low color shift compensation IP core, overvoltage drive IP core, and jitter processing IP core, The optical taste adjustment parameter table includes corresponding ones of the Mura elimination parameter table, the white balance adjustment parameter table, the low color shift compensation parameter table, the overvoltage drive parameter table, and the dither processing parameter table.

In a specific embodiment, when the optical taste adjustment IP core includes Mura elimination IP core, white balance adjustment IP core, low color shift compensation IP core, overvoltage drive IP core, and jitter processing IP core, the system-on-chip Is configured to sequentially control the Mura elimination IP core, the white balance adjustment IP core, the low color shift compensation IP core, the overvoltage drive IP core, and the jitter processing IP core respectively according to the Mura elimination parameter Table, the white balance adjustment parameter table, the low color shift compensation parameter table, the overvoltage drive parameter table, and the jitter processing parameter table perform mura elimination operation, white balance adjustment, low color shift compensation operation, and overvoltage Drive operation and dither processing operation.

Compared with the prior art, one or more of the above technical solutions have one or more of the following advantages or

Benefits:

1. The display device of this embodiment is equipped with the drive circuit board assembly on the XB board, so that the XB board has part of the TCON function. When debugging and changing the Panel Timming, it is completely independent of SOC and can be developed independently. Through this embodiment The structure adjustment of the circuit board MB and the horizontal direction circuit panel XB can be manufactured and sold separately, and the panel manufacturer can independently complete the panel debugging and changes without relying on changes to the SOC.

2. The display device of this embodiment adds a signal conversion circuit (for example in the form of a chip) to the display control circuit of the drive circuit board assembly, which converts the P2P interface signal into a mini-LVDS interface signal on the one hand, so that the source drive circuit The interface between the COF type source driver and the drive circuit board components is changed to a mini-LVDS interface, which greatly reduces the cost; on the other hand, the signal conversion circuit can generate the timing control signals required by the display panel, and panel debugging and revision can be all Completed by the panel manufacturer, the complete machine manufacturer can reduce the development cost without making any changes; on the other hand, the new panel technology can be completed by the signal conversion circuit, and the system board can be completed without any changes.

3. The display device of this embodiment stores the optical taste adjustment parameters in the non-volatile memory on the XB board in the form of a parameter table, and the debugging of each parameter in the optical taste adjustment parameter table is changed from the complete machine manufacturer to the panel manufacturer; Because the optical taste adjustment parameters are strongly related to the panel, the optical taste adjustment parameter tables required by different panels are different, and the panel manufacturers know the optical characteristics of their own panels better, so they can flexibly adjust the optical characteristics of the panel according to their own panel characteristics, so that The whole machine manufacturer is freed from the tedious work of adjusting the optical characteristics to accelerate the development speed of the whole machine.

The present invention will be further described in detail below in conjunction with the drawings and embodiments.

Description of the drawings

FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the application;

FIG. 2 illustrates a specific structure of a display control circuit in the display device shown in FIG. 1;

FIG. 3 illustrates another specific structure of the display control circuit in the display device shown in FIG. 1;

4 is a schematic diagram of internal modules of the system-on-chip and non-volatile memory on the XB board in the display device shown in FIG. 1;

FIG. 5 illustrates a specific composition of the optical taste adjustment parameter table and the optical taste adjustment IP core in FIG. 4.

Detailed ways

The present invention will be further described in detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.

Example one

As shown in FIG. 1, a display device 10 provided by an embodiment of the present application includes: a display panel 111 having a gate driving circuit and a source driving circuit thereon; an XB board 113 having a driving circuit board assembly 1130 thereon, and a system Board 13 and connector CL1. The active matrix display device 10 of this embodiment is, for example, a TCONLESS LCD TV. The system-on-chip on the system board integrates at least part of the functions of the traditional TCON chip, and the XB board integrates at least part of the functions of the traditional TCON chip. However, the embodiments of the present application are not limited thereto.

The display panel 111 includes a display area 1111 and a gate drive circuit and a source drive circuit electrically connected to the display area 1111. A plurality of data lines DL, a plurality of gate lines GL, and a plurality of pixels P electrically connecting each data line DL and each gate line GL are provided in the display area 1111; each pixel P is located on the corresponding gate line GL Intersection with data line DL. The gate drive circuit includes, for example, two GOA (Gate-On Array, gate drive circuits integrated on an array substrate) circuits 1113, and the two GOA circuits 1113 are located in the peripheral area of the display area 1111 and are separately provided on two opposite sides of the display area 1111. On the other hand, that is, the gate drive circuit of the display panel 111 is a double-sided GOA circuit. Each GOA circuit 1113 is electrically connected to the gate line GL in the display area 1111, and is used to provide a gate driving signal to each gate line GL in the display area 1111. The source driving circuit, for example, includes a plurality of COF type source drivers 1115, such as the twelve COF (Chip-On-Flex, chip-on-film) type source drivers 1115 shown in FIG. 1; each COF type source driver 1115 is electrically connected The data lines DL in the display area 1111 are used for each data line DL to provide image data signals. More specifically, a single COF-type source driver 1115 includes, for example, a flexible circuit board and a source driver IC (source driver IC) provided on the flexible circuit board.

Among them, the XB board 113 can be a whole independent circuit board, or multiple circuit daughter boards arranged in parallel. If there are multiple circuit daughter boards arranged in parallel, the driving circuit board assembly 1130 can be arranged on On any one of the circuit sub-boards, each two adjacent circuit sub-boards of the plurality of circuit sub-boards form an electrical connection through a connector and a respective connector.

This embodiment is described with two circuit daughter boards. The XB board 113 includes two

circuit daughter boards

113a, 113b. The two

circuit daughter boards

113a, 113b are arranged on one side of the display panel 111 along the horizontal direction in FIG. That is, as a row-direction drive circuit board; each

circuit daughter board

113a, 113b is provided with a COF-type source driver 1115 connection interface such as a mini-LVDS interface on one side adjacent to the display area 1111. As described above, the driving circuit board assembly 1130 is arranged on the circuit sub-board 113a. Specifically, the circuit sub-board 113a is provided with the display control circuit 1131, the connector CN1, the nonvolatile memory 1133, and the connector CN3. The circuit daughter board 113a is electrically connected to the display area 1111 through a plurality of, for example, seven COF-type source drivers 1115, and is electrically connected to the GOA circuit 1113 on the right side of the display panel 111 through the rightmost COF-type source driver 1115. The circuit daughter board 113b is provided with a connector CN4. The circuit daughter board 113b is electrically connected to the display area 1111 through a plurality of, for example, five COF type source drivers 1115, and is electrically connected to the GOA circuit 1113 on the left side of the display panel 111 through the leftmost COF type source driver 1115. The connector CN3 of the circuit daughter board 113a and the connector CN4 of the circuit daughter board 113b form an electrical connection through a connector CL2, where the connector CL2 is, for example, a flexible circuit board or a flexible flat cable (FFC), Thus, the signal generated on the circuit sub-board 113a is transmitted to the circuit sub-board 113b through the connector CL2.

Furthermore, the display control circuit 1131 is electrically connected to the first connector CN1, the connector CN3, and a plurality of, for example, seven COF-type source drivers 1115; in this way, the display control circuit 1131 except for the printed circuit board on the circuit sub-board 113a Board, printed circuit board) The wiring is electrically connected to the seven COF source drivers 1115 on the right side, and also connected to the left side through the connector CN3, the connector CL2, the connector CN4, and the PCB trace on the circuit daughter board 113b. Five COF type source drivers 1115. A number of Mini-LVDS interfaces are also provided on the XB board 113. The Mini-LVDS interfaces are provided between the COF source driver 1115 and the display control circuit 1131. The first connector includes a P2P interface; see FIG. 2, the display The control circuit 1131 includes a signal conversion circuit 11312 that is electrically connected to the first connector CN1 and the Mini-LVDS interface, and is configured to receive P2P including image data via the first connector CN1 Interface signal, and generate a source control signal and a second interface type image data signal according to the P2P interface signal, and output to the source driving circuit through the Mini-LVDS interface, wherein the second interface type image data The signal is a Mini-LVDS interface signal.

It should be noted that in the prior art, in order to match the signal sent by the SOC, the interface of the source driver needs to be adjusted accordingly. For example, if the signal sent by the SOC is transmitted through the P2P interface interface, the corresponding source driver interface Only P2Pinterface can be used, which leads to an increase in overall manufacturing costs and testing costs. In this embodiment, if the connector CL1 transmits the signal from the SOC to the signal conversion circuit 11312 in the display control circuit 1131 through the P2P interface interface, the signal conversion circuit 11312 can convert the P2P interface signal into a source driver corresponding to the panel. For example, the COF-type source driver interface 1115 is a Mini-LVDS interface, and the P2P interface signal is converted into a Mini-LVDS signal, and the converted Mini-LVDS signal is sent to the panel COF-type source driver interface 1115, namely It is equivalent to completing the conversion of the interface signal through the signal conversion circuit 11312, thus completing the data transmission without changing the original Mini-LVDS interface on the panel. By adding a signal conversion circuit 11312 (for example in the form of a chip) to the display control circuit 1131 of the XB board 113a, it converts the P2P interface signal into a mini-LVDS interface signal on the one hand, so that the COF source driver 1115 and the The interface between the XB board 113 is changed to a mini-LVDS interface, which greatly reduces the cost; on the other hand, the signal conversion circuit 11312 can generate the timing control signals required by the display panel 111, and panel debugging and revision can all be completed by the panel manufacturer. The whole machine manufacturer does not need to make any changes, which reduces the development cost; on the other hand, the new panel technology can be completed by the signal conversion circuit 11312, and the system board 13 does not need to make any changes.

On the other hand, the display control circuit 1131 may also include a DC voltage conversion circuit 11314, a level conversion circuit 11316, and a Gamma correction (gamma correction) circuit 11318. The signal conversion circuit 11312 is electrically connected to the connector CN1, the level conversion circuit 11316, and the source drive circuit, and is configured to receive reference timing signals such as STV, CKV, and a P2P interface containing image data (such as RGB data) via the connector CN1 Signal, generate source control signals such as TP, POL and a second interface type image data signal such as Mini-LVDS to the source drive circuit according to the P2P interface signal, and generate an initial gate according to the reference timing signals STV and CKV Control signals such as ST_in, CKx_in, LC_in, Reset_in to the level conversion circuit 11316. The DC voltage conversion circuit 11314 is electrically connected to the connector CN1 and is configured to receive the input DC voltage Vin via the connector CN1 and generate gate switching voltages such as VGH, VGL and reference voltages such as VAA to the level conversion circuit 11316 according to the input DC voltage Vin. And Gamma correction circuit 11318. The level conversion circuit 11316 is configured to generate gate control signals such as ST, CKx, LCx, Reset to the gate according to the gate switching voltages VGH, VGL and the initial gate control signals ST_in, CKx_in, LC_in, and Reset_in. Drive circuit. The Gamma correction circuit 11318 is configured to generate a plurality of Gamma voltages such as GMAx to the source driving circuit according to the reference voltage VAA. In a specific example, CKx_in is for example four high frequency clock signals CK1 to CK4, CKx is for example eight high frequency clock signals CK1 to CK8, and LCx is two low frequency clock signals LC1 to LC2 relative to CKx, GMAx is, for example, fourteen Gamma voltages such as GMA1 to GMA14, VGH is used as the gate turn-on voltage, for example, +20V to +30V, and VGL is used as the gate turn-off voltage, for example, about -5V, but the application is not limited thereto. In addition, it is worth noting that the P2P interface signal includes multiple pairs of differential signals, which is another interface type different from the mini LVDS (mini Low Voltage Differential Signaling) interface, and is very suitable for The short-distance signal transmission from the system board 13 to the circuit daughter board 113a may be a well-known and mature USI-T, EPI, CMPI, iSP interface, etc. In addition, it should be noted that the DC voltage conversion circuit 11314 is not limited to generating the aforementioned VGH, VGL, and VAA. It is also used to generate the signal conversion circuit 11312, the level conversion circuit 11316, the Gamma correction circuit 11318, and the gate drive circuit. And the source driving circuit provides power supply voltages such as digital voltage VDD and analog voltage HVAA (not shown in the figure).

In view of the above, the signal conversion circuit 11312, the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the Gamma correction circuit 11318 in the embodiment shown in FIG. 2 are respectively integrated into four different chips; for example, the DC voltage conversion circuit 11314 uses a known For a PMIC chip with mature technology, the level conversion circuit 11316 uses a level shift (Level Shift) chip in a known mature technology, and the Gamma correction circuit 11318 uses a P-Gamma chip in a known mature technology. In addition, in order to further improve the integration of the circuit, in other embodiments, the DC voltage conversion circuit 11314 and the level conversion circuit 11316 can be integrated on the same chip and the Gamma correction circuit 11318 can be integrated on another chip, or the DC voltage can be converted The circuit 11314 and the Gamma correction circuit 11318 are integrated in the same chip and the level conversion circuit 11316 is integrated in another chip, or the level conversion circuit 11316 and the Gamma correction circuit 11318 are integrated in the same chip and the DC voltage conversion circuit 11314 is integrated in the same chip, It is even possible to integrate the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the Gamma correction circuit 11318 into the same chip.

In the prior art, since the functions of the TCON IC are integrated on the SOC of the circuit mainboard, the SOC needs to be coordinated when debugging and changing the Panel Timming. However, some functions of the TCON IC in this implementation are set on the XB board. Timming does not depend on SOC at all when debugging and changing, and can develop independently. Through the structural adjustment of this embodiment, the circuit main board MB and the horizontal direction circuit panel XB can be manufactured and sold separately, and the panel manufacturer can independently complete panel debugging and changes without relying on changes to the SOC.

When the display control circuit 1131 includes the Gamma correction circuit 11318, since the Gamma correction circuit 11318 is arranged on the horizontal direction circuit panel XB, the gamma curve can be adjusted piece by piece. In addition, the power management circuit 135 can also be arranged on the horizontal direction circuit panel XB. , The power management circuit 135 is connected to the display control circuit 1131, so that the panel manufacturer can adjust and revise the power supply part when the panel is manufactured.

Of course, the display control circuit 1131 may not include one or more of the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the Gamma correction circuit 11318. For example, when the Gamma correction circuit 11318 is not included, the DC voltage conversion circuit 11314 , The level conversion circuit 11316 and the signal conversion circuit 11312 can be integrated in the same chip; or the DC voltage conversion circuit 11314 and the level conversion circuit 11316 are integrated in the same chip and the signal conversion circuit 11312 is integrated in another chip; or the DC voltage conversion The circuit 11314 and the signal conversion circuit 11312 are integrated in the same chip and the level conversion circuit 11316 is integrated in another chip; or the level conversion circuit 11316 and the signal conversion circuit 11312 are integrated in the same chip and the DC voltage conversion circuit 11314 is integrated in another chip Chip; or the DC voltage conversion circuit 11314, the level conversion circuit 11316, and the signal conversion circuit 11312 are integrated in the same chip.

3, in another embodiment, the display control circuit 1131 includes a signal conversion circuit 11312, a DC voltage conversion circuit 11314, a level conversion circuit 11316 and a Gamma correction circuit 11318. The signal conversion circuit 11312 is electrically connected to the connector CN1 and the source drive circuit, and is configured to receive a P2P interface signal containing image data via the connector CN1, and generate source control signals TP, POL, and the first source control signal according to the P2P interface signal. Two-interface type image data signal such as Mini-LVDS to the source driving circuit. The DC voltage conversion circuit 11314 is electrically connected to the connector CN1 and is configured to receive the input DC voltage Vin via the connector CN1 and generate gate switching voltages such as VGH, VGL and reference voltages such as VAA to level conversion according to the input DC voltage Vin. Circuit 11316 and Gamma correction circuit 11318. The level conversion circuit 11316 is electrically connected to the connector CN1, and is configured to receive reference timing signals such as STV and CKV via the connector CN1 to generate a gate according to the reference timing signals STV, CKV and the gate switching voltages VGH, VGL. Control signals such as ST, CKx, LCx, Reset to the gate drive circuit. The Gamma correction circuit 11318 is configured to generate a plurality of Gamma voltages GMAx to the source driving circuit according to the reference voltage VAA. In short, the main difference between the embodiment shown in FIG. 3 and the embodiment shown in FIG. 2 is that the reference timing signals STV and CKV in the embodiment shown in FIG. 3 are directly sent to the level conversion circuit 11316 instead of As shown in FIG. 2, preliminary conversion is performed by the signal conversion circuit 11312 and then sent to the level conversion circuit 11316. Or, in other embodiments, the reference timing signals STV and CKV may also be generated locally by the signal conversion circuit 11312 instead of being directly provided by the system board 13.

In addition, the display control circuit 1131 can be further electrically connected (not shown in FIG. 1) to the non-volatile memory 1133, for example, connected to the non-volatile memory on the same serial bus such as SPI (Serial Peripheral Interface, serial external interface). Set interface) bus; SPI bus has the advantage of fast data read and write speed.

In addition, the nonvolatile memory 1133 is electrically connected to the connector CN1. As shown in FIG. 4, the non-volatile memory 1133 stores an optical taste adjustment parameter table 11330, where the optical taste adjustment parameter table 11330 contains parameters that are stronger than the optical taste (or optical characteristics) of the display panel 111 Related parameters. In this embodiment, the non-volatile memory 1133 is an SPI interface flash memory (Flash), and correspondingly, the connector CN1 includes an SPI bus interface.

The system board 13 is provided with a connector CN2, a system-on-chip 133 and a power management circuit 135. The connector CN2 of the system board 13 is connected to the connector CN1 of the circuit daughter board 113a through the connector CL1. Furthermore, the system-on-chip 133 is electrically connected to the connector CN2 and has a built-in optical taste adjustment IP core 1330 (see Figure 4). In this way, the system-on-chip 133 can be connected in series via the connector CN2, the connector CL1, and the connector CN1. The line communication method reads the optical taste adjustment parameter 11330 stored in the non-volatile memory of the circuit sub-board 113a and loads it to the optical taste adjustment IP core 1330 to adjust the optical taste of the display panel 111. In addition, the connector CL1 is, for example, a single flexible cable (FFC). In addition, it is worth mentioning that the system board 13 of this embodiment is typically also provided with multiple audio and video input interfaces such as CVBS interface, HDMI interface, etc.; the system board 13 is also called the main board (Main Board), which is used to The video and audio signals input by the audio and video input interface are decoded, and then the video signals are output to the XB board in digital signal format.

Referring to Figure 5, the optical taste adjustment IP core 1330 includes Mura elimination (Demura) IP core 1331, white balance (white tracking) adjustment IP core 1332, low color shift compensation IP core 1333, overvoltage drive (OverDrive, OD) IP core 1334 and jitter processing IP core 1335, corresponding optical taste adjustment parameter table 11330 includes Mura elimination parameter table 11331, white balance adjustment parameter table 11332, low color shift compensation parameter table 11333, overvoltage drive parameter table 11334 and jitter Processing parameter table 11335. More specifically, the Mura elimination IP core 1331 is used to perform Mura elimination (that is, a phenomenon that causes various traces due to uneven display brightness) according to the Mura elimination parameter table 11331, and the white balance adjustment IP core 1332 is used to eliminate The balance adjustment parameter table 11332 performs the white balance adjustment operation. The low color shift compensation IP core 1333 is used to perform the low color shift compensation operation according to the low color shift compensation parameter table 11333 to make the display panel 111 achieve low color shift display quality, and the overvoltage drive IP The core 1334 is used to perform overvoltage driving operations according to the overvoltage driving parameter table 11334, and the jitter processing IP core 1335 is used to perform dither processing operations such as temporal dithering and/or spatial dithering according to the dither processing parameter table 11335 ( spatial dithering). As for the parameters required for the mura elimination operation, the white balance adjustment operation, the low color shift compensation operation, the overvoltage driving operation, and the jitter processing operation, they are known and mature technologies, so they will not be repeated here. As for the power management circuit 135, it is electrically connected to the connector CN2 to provide an input DC voltage such as 12V to the circuit daughter board 113a; in addition, the power management circuit 135 uses, for example, a mature PMIC chip.

It is worth mentioning that according to the inventor’s experimental verification, the Mura elimination IP core 1331, the white balance adjustment IP core 1332, the low color shift compensation IP core 1333, the overvoltage driving IP core 1334, and the IP core 1334 The jitter processing IP core 1335 performs Mura elimination operation, white balance adjustment, low color shift compensation parameter table 11333, overvoltage drive parameter table 11334, and jitter processing parameter table 11335 according to Mura elimination parameter table 11331, white balance adjustment parameter table 11332, low color shift compensation parameter table 11333, and jitter processing parameter table 11335. The color shift compensation operation, the overvoltage driving operation, and the dithering processing operation, such a specific optical taste adjustment sequence, are relatively easy to make the display panel 111 achieve better display quality and optical taste.

In addition, it is worth noting that in other embodiments, the optical taste adjustment IP core 1330 may also only include the Mura elimination IP core 1331, the white balance adjustment IP core 1332, the low color shift compensation IP core 1333, and the overvoltage driving IP core 1334. Similar to some of the IP cores in the jitter processing IP core 1335; similarly, the optical taste adjustment parameter table 11330 can also only include the Mura elimination parameter table 11331, the white balance adjustment parameter table 11332, the low color shift compensation parameter table 11333, and the overvoltage drive parameter Table 11334 and part of the parameter table in the jitter processing parameter table 11335.

In summary, in the embodiment of the present application, the optical taste adjustment parameter (or optical code) is stored in the nonvolatile memory 1133 on the circuit daughter board 113a in the form of a parameter table, and the value of each parameter in the optical taste adjustment parameter table 11330 is The debugging is changed from the complete machine manufacturer to the panel manufacturer; because the optical taste adjustment parameters are strongly related to the panel, the optical taste adjustment parameter table required for different panels is different, and the panel manufacturer knows the optical characteristics of their own panels better, so they can follow their own panels. Features Flexible adjustment of the optical characteristics of the panel can free the complete machine manufacturer from the tedious work of adjusting the optical characteristics to accelerate the development of the complete machine.

In addition, it can be understood that the foregoing embodiments are only exemplary descriptions of the present application, and the technical solutions of the various embodiments can be combined arbitrarily, provided that the technical features do not conflict, the structure does not contradict, and does not violate the purpose of the invention of the present application. For use with. Furthermore, it can be understood that the signal conversion circuit 11312, DC voltage conversion circuit 11314, level conversion circuit 11316, and Gamma correction circuit 11318 of the display control circuit 1131 in the foregoing embodiments are not limited to being distributed on a single circuit sub-board 113a. It can also be distributed on multiple driving circuit boards, such as the circuit sub-boards 113a and 113b in FIG.

The above-mentioned display device can be: LTPO display device, Micro LED display device, liquid crystal panel, electronic paper, OLED panel, AMOLED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame and other products with display function or part.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units.

The above-mentioned integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The above-mentioned software function unit is stored in a storage medium, and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to execute part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disks or optical disks, etc., which can store program codes Medium.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

A display device, characterized by comprising:

A display panel with a gate drive circuit and a source drive circuit thereon;

The XB board has a drive circuit board assembly thereon. The drive circuit board assembly includes a display control circuit and a first connector. The display control circuit is electrically connected to the gate drive circuit, the source drive circuit, and the first connector. Connector;

A system board provided with a second connector and a system-on-chip electrically connected to the second connector, and the system-on-chip has a built-in optical taste adjustment IP core; and

The connector is connected between the first connector and the second connector.
The display device according to claim 1, wherein the XB board comprises at least two circuit sub-boards arranged in parallel, the driving circuit board assembly is arranged on any one of the circuit sub-boards, and the plurality of Every two adjacent circuit daughter boards in the circuit daughter board form an electrical connection through a connector and a respective connector.
The display device according to claim 1, wherein a number of Mini-LVDS interfaces are further provided on the XB board, the first connector includes a P2P interface; the display control circuit includes a signal conversion circuit, and the The signal conversion circuit is electrically connected to the first connector and the Mini-LVDS interface, and is configured to receive a P2P interface signal containing image data via the first connector, and generate a source control according to the P2P interface signal The signal and the second interface type image data signal are output to the source driving circuit through the Mini-LVDS interface, where the second interface type image data signal is a Mini-LVDS interface signal.
4. The display device of claim 3, wherein the display control circuit further comprises a level conversion circuit and a DC voltage conversion circuit; wherein,

The DC voltage conversion circuit is electrically connected to the first connector and is configured to receive an input DC voltage via the first connector and generate a gate switching voltage and a reference voltage to the level respectively according to the input DC voltage Conversion circuit; the level conversion circuit is electrically connected to the first connector, and is configured to receive a reference timing signal via the first connector to generate a gate according to the reference timing signal and the gate switch voltage Control signals to the gate drive circuit.
The display device of claim 4, wherein the DC voltage conversion circuit, the level conversion circuit, and the signal conversion circuit are integrated in the same chip; or the DC voltage conversion circuit and the electrical The level conversion circuit is integrated in the same chip and the signal conversion circuit is integrated in another chip; or the DC voltage conversion circuit and the signal conversion circuit are integrated in the same chip and the level conversion circuit is integrated in another chip Or the level conversion circuit and the signal conversion circuit are integrated in the same chip and the DC voltage conversion circuit is integrated in another chip; or the DC voltage conversion circuit, the level conversion circuit and the signal The conversion circuit is integrated in the same chip.
4. The display device of claim 3, wherein the display control circuit comprises a level conversion circuit, a DC voltage conversion circuit, and a Gamma correction circuit; wherein,

The DC voltage conversion circuit is electrically connected to the first connector and is configured to receive an input DC voltage via the first connector and generate a gate switching voltage and a reference voltage to the level respectively according to the input DC voltage The conversion circuit and the Gamma correction circuit; the level conversion circuit is electrically connected to the first connector, and is configured to receive a reference timing signal via the first connector to respond to the reference timing signal and the gate The pole switch voltage generates a gate control signal to the gate drive circuit; the Gamma correction circuit is configured to generate a plurality of Gamma voltages to the source drive circuit according to the reference voltage.
The display device of claim 1, wherein the XB board further comprises a non-volatile memory, the non-volatile memory is electrically connected to the first connector, and the non-volatile memory An optical taste adjustment parameter table is stored in the memory, wherein the system-on-chip is configured to read the storage in the non-volatile memory via the second connector, the connector, and the first connector And load the optical taste adjustment parameter table to the optical taste adjustment IP core.
The display device according to claim 1, wherein the optical taste adjustment IP core comprises Mura elimination IP core, white balance adjustment IP core, low color shift compensation IP core, overvoltage driving IP core, and jitter processing IP core In one or more of the above, the optical taste adjustment parameter table includes a corresponding one of a Mura elimination parameter table, a white balance adjustment parameter table, a low color shift compensation parameter table, an overvoltage drive parameter table, and a jitter processing parameter table.
The display device according to claim 8, wherein when the optical taste adjustment IP core includes Mura elimination IP core, white balance adjustment IP core, low color shift compensation IP core, overvoltage driving IP core, and jitter processing IP core Core, the system-level chip is configured to sequentially control the Mura elimination IP core, the white balance adjustment IP core, the low color shift compensation IP core, the overvoltage drive IP core, and the jitter processing IP core According to the Mura elimination parameter table, the white balance adjustment parameter table, the low color shift compensation parameter table, the overvoltage drive parameter table, and the jitter processing parameter table, perform Mura elimination operation, white balance adjustment, low Color shift compensation operation, over-voltage drive operation and jitter processing operation.