WO2020256028A1 - Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element - Google Patents

Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element Download PDF

Info

Publication number
WO2020256028A1
WO2020256028A1 PCT/JP2020/023827 JP2020023827W WO2020256028A1 WO 2020256028 A1 WO2020256028 A1 WO 2020256028A1 JP 2020023827 W JP2020023827 W JP 2020023827W WO 2020256028 A1 WO2020256028 A1 WO 2020256028A1
Authority
WO
WIPO (PCT)
Prior art keywords
plane
semiconductor
growth substrate
layer
growth
Prior art date
Application number
PCT/JP2020/023827
Other languages
French (fr)
Japanese (ja)
Inventor
大樹 神野
Original Assignee
株式会社小糸製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社小糸製作所 filed Critical 株式会社小糸製作所
Publication of WO2020256028A1 publication Critical patent/WO2020256028A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/38—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method, and more particularly to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting device, and a semiconductor element manufacturing method for growing an a-plane GaN crystal layer.
  • an LED that emits purple to blue light used for lighting applications an LED that forms an active layer with a GaN-based material whose main surface is a non-polar or semi-polar plane orientation has been proposed.
  • the a-plane and the m-plane are non-polar planes
  • the r-plane is a typical example of the semi-polar plane.
  • the influence of the piezo electric field in the stacking direction can be reduced and the droop characteristics can be improved.
  • Patent Document 1 a nano-sized convex portion is formed on the main surface of the r-plane sapphire substrate, and the a-plane GaN layer is grown via the buffer layer in the a-plane GaN layer that grows in the lateral direction.
  • a technique has been proposed in which dislocations are bent to reduce dislocations and defects that continue to the surface of the semiconductor layer.
  • the types of defects that occur in the GaN layer include stacking defects (BSF:) that occur in the regularity of stacking of atomic planes, in addition to through dislocations (TD: Crystals) that occur due to lattice mismatch between the sapphire substrate and GaN. Bassal plane Stacking Fault) is known.
  • stacking defects are known to be crystal defects that occur prominently in the a-plane GaN layer having a nitrogen-polar (000-1) plane in the crystal plane, and are known to occur in the lateral growth of the GaN layer. It was difficult to reduce stacking defects (BSF) even if the through-through dislocations (TD) were reduced.
  • the present invention has been made in view of the above-mentioned conventional problems, and is a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element capable of suppressing stacking defects and growing a high-quality a-plane GaN layer. It is an object of the present invention to provide a manufacturing method.
  • the semiconductor growth substrate of the present invention has the r-plane of sapphire as the main surface, and a plurality of nano-sized convex portions are formed on the main surface, and the convex portions are the sapphire.
  • the r-axis of the sapphire and the c-axis of the sapphire are projected along the a-axis direction perpendicular to the c'direction projected onto the r-plane.
  • the convex portion is formed along the r-axis of the r-plane sapphire substrate and the a-axis direction perpendicular to the c'direction, the -c-plane generated between the convex portions is aggregated along the convex portion. It is possible to suppress stacking defects and obtain a high-quality a-plane GaN layer.
  • the distance between the convex portions is in the range of 200 nm or more and 500 nm or less.
  • the convex-shaped portion has a side wall surface portion formed by rising from the main surface and a curved surface portion formed above the side wall surface portion.
  • the curved surface portion is formed with a curvature based on a diameter having a size different from the width of the convex shape portion, and the two curved surface portions intersect at the top of the convex shape portion.
  • a ridgeline portion is formed.
  • the semiconductor element of the present invention includes the semiconductor growth substrate according to any one of the above and a functional layer provided on the semiconductor growth substrate.
  • the semiconductor light emitting device of the present invention includes the semiconductor growth substrate according to any one of the above and an active layer provided on the semiconductor growth substrate.
  • the semiconductor device manufacturing method of the present invention has a c'direction in which the r-axis of the sapphire and the c-axis of the sapphire are projected onto the r-plane on a sapphire whose main surface is the r-plane.
  • the present invention includes a step of forming a plurality of convex portions along the a-axis direction perpendicular to the above, and a step of growing a nitride semiconductor layer on the main surface.
  • the present invention can provide a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method capable of suppressing stacking defects and growing a high-quality a-plane GaN layer.
  • FIG. 2A is a schematic cross-sectional view showing a state in which the a-plane GaN layer 14 is grown on the semiconductor growth substrate 10,
  • FIG. 2A shows an example in which the a-plane GaN layer 14 is directly grown, and is shown in FIG. b) shows an example in which the buffer layer 15 is formed.
  • FIG. 3A is an SEM image showing island-shaped crystals at the initial stage of growth of the a-plane GaN layer 14, and
  • FIG. 3B is a surface state after flattening the a-plane GaN layer 14 after growth. It is a TEM image showing.
  • FIG. 4A is a schematic plan view
  • FIG. 4B is a schematic cross-sectional view.
  • FIG. 5 (a) is a schematic plan view.
  • FIG. 5B is a schematic cross-sectional view.
  • FIG. 6A shows an example of a semicircular top cross section
  • FIG. 6B is a top.
  • An example in which a ridgeline portion is formed is shown.
  • FIG. 1 is a schematic perspective view showing a semiconductor growth substrate 10 according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor growth substrate 10 has a plurality of convex portions 12 formed on the r-plane sapphire substrate 11.
  • the r-plane sapphire substrate 11 is a substrate composed of a single crystal of sapphire, and has the r-plane of hexagonal crystals as the main surface.
  • the just substrate having an inclination angle of 0 degrees is shown as the r-plane sapphire substrate 11, but an off-board substrate in which the r-plane is inclined by several degrees in a predetermined plane direction may be used.
  • the convex portion 12 is a convex portion formed on the main surface of the r-plane sapphire substrate 11, and is perpendicular to both the r-axis of sapphire and the c'direction in which the c-axis of sapphire is projected onto the r-plane. It is formed along the a-axis. As shown by the arrows in FIG. 1, the upper direction in the figure is the r-axis, the right direction in the figure is the c'direction in which the c-axis is projected onto the r-plane, and the depth direction is perpendicular to the r-axis and the c'direction. A axis.
  • recesses 13 are formed between the convex portions 12, and the r-plane, which is the main surface of the r-plane sapphire substrate 11, is exposed from the recesses 13.
  • the convex portion 12 is along the a-axis is shown, but it may extend obliquely with respect to the a-axis direction by an angle of less than 45 degrees from the a-axis.
  • FIG. 2 is a schematic cross-sectional view showing a state in which the a-plane GaN layer 14 is grown on the semiconductor growth substrate 10, and FIG. 2A shows an example in which the a-plane GaN layer 14 is directly grown. FIG. 2B shows an example in which the buffer layer 15 is formed.
  • the semiconductor growth substrate 10 has an a-plane having the a-plane as the main surface from the main surface exposed by the recesses 13 between the convex portions 12 on the r-plane sapphire substrate 11.
  • the GaN layer 14 is grown.
  • a buffer layer 15 for alleviating lattice mismatch may be formed between the r-plane sapphire substrate 11 and the a-plane GaN layer 14.
  • the a-plane GaN layer 14 is a base layer grown so that the main surface is the a-plane, and is a layer for epitaxially growing a nitride semiconductor layer on the base layer.
  • a method for forming the a-plane GaN layer 14 a known method such as a MOCVD method (organic metal vapor deposition method: Metalorganic Chemical Vapor Deposition) or an HVPE method (hydride vapor phase growth method: Hydride Vapor Phase Epitaxy) is used. Although it can be done, it is preferable to use the MOCVD method.
  • the film thickness of the a-plane GaN layer 14 is not particularly limited, but it is preferably formed at 1 ⁇ m or more.
  • the buffer layer 15 is a layer formed to alleviate the lattice mismatch between the r-plane sapphire substrate 11 and the nitride semiconductor layer (a-plane GaN layer 14).
  • the material constituting the buffer layer 15 include AlN, GaN, InGaN, AlGaN, and the like, but it is preferable to use AlN.
  • a sputtering method, a MOCVD method, or the like can be used, and it is preferable to use the sputtering method.
  • the thickness of the buffer layer 15 is preferably in the range of 5 to 300 nm, more preferably in the range of 5 to 90 nm, and more preferably in the range of 5 to 30 nm because the crystal quality of the nitride semiconductor layer (a-side GaN layer 14) deteriorates if it is made too thick.
  • the range of is more preferred.
  • a method of manufacturing the semiconductor growth substrate 10 in the present embodiment will be described.
  • a method for forming the nano-sized convex portion 12 on the surface of the r-plane sapphire substrate 11 known nanoimprint and patterning can be used.
  • a resist film is applied onto the r-plane sapphire substrate 11, and a mold having a pattern corresponding to the convex portion 12 is used to transfer the pattern to the resist film using nanoimprint technology.
  • the resist film to which the nanopattern is transferred and the r-plane sapphire substrate 11 are anisotropically etched with a chlorine-based gas to form a nano-sized convex portion 12 on the r-plane sapphire substrate 11. Will be done.
  • a method of forming the buffer layer 15 and the a-plane GaN layer 14 on the semiconductor growth substrate 10 of the present embodiment will be described.
  • a buffer layer 15 having a film thickness of about 30 nm is formed by a sputtering method or the like.
  • Ar gas with AlN it is more preferable to use Ar gas with AlN as a target material.
  • the AlN as the target material may be a single crystal substrate or a powder-fired body, and its state and form are not limited.
  • ammonia (NH 3 ) is used as a group V raw material
  • TMG Trimethylgallium
  • the surface GaN layer 14 is grown.
  • a two-step growth sequence is used in which the temperature is raised to 1010 ° C., the growth temperature is kept constant, and the reactor pressure, V / III ratio, and growth time are changed.
  • V / III ratio For example, first maintain the V / III ratio at about 4000 to 5000 and the pressure at 900 to 1000 hPa for about 10 to 20 minutes, then maintain the V / III ratio at about 100 to 200 and the pressure at 100 to 150 hPa for 90 to 120 minutes. To do.
  • a plurality of nano-sized convex portions 12 are formed on the main surface of the r-plane sapphire substrate 11, and the buffer layer 15 and the a-plane GaN layer 14 are formed.
  • the formed semiconductor growth substrate 10 of the present embodiment can be obtained.
  • the penetrating dislocations generated in the recesses 13 between the convex portions 12 are aggregated by lateral growth and are aggregated near the vertices of the convex portions 12. Therefore, the density of through dislocations (TD) extending to the outermost surface of the a-plane GaN layer 14 becomes small.
  • TD through dislocations
  • FIG. 3 is a TEM image showing the crystal growth of the a-plane GaN layer 14
  • FIG. 3 (a) shows island-shaped crystals in the early stage of growth
  • FIG. 3 (b) is the a-plane GaN layer 14 after growth. Shows the surface condition after flattening.
  • the a-plane GaN layer 14 is crystal-grown on the main surface of the r-plane sapphire substrate 11, a plurality of island-shaped crystals, which are growth nuclei, are formed on the main surface in the initial stage of growth. Occurs.
  • the island-shaped crystal is a single crystal made of GaN, and it is known that the crystal size increases with the (000-1) plane, the (1-100) plane, and the (1-101) plane as facets.
  • a plurality of island-shaped crystals are bonded to obtain a large-sized single crystal.
  • the rate of crystal growth differs for each facet such as the (000-1) plane, the (1-100) plane, and the (1-101) plane, and further -c.
  • the (000-1) plane which is a plane, has a nitrogen polarity.
  • the stacking defects (b) as shown in FIG. 3 (b) are contained in the a-plane GaN layer 14. BSF) will occur innumerably.
  • FIG. 4 is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex portion 12 and the concave portion 13 formed along the a-axis
  • FIG. 4A is a schematic plan view
  • FIG. 4B is a schematic cross-sectional view
  • FIG. 5 is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex portion 12 and the concave portion 13 formed along the c'direction
  • FIG. 5 (a) is a schematic plane.
  • FIG. 5B is a schematic cross-sectional view.
  • the arrow shown in the figure indicates the position of the -c plane of the island-shaped crystal, which is a growth nucleus generated on the main plane in the initial stage of growth of the a-plane GaN layer 14.
  • each island Each of the shaped crystals has a -c plane, and crystal growth proceeds in a state where the recess 13 has a plurality of -c planes.
  • the a-plane GaN layer 14 is formed with a large number of stacking defects (BSF) due to the -c-plane remaining.
  • the convex portion 12 is perpendicular to the r-axis of the r-plane sapphire substrate 11 and the c'direction in which the c-axis of the r-plane sapphire substrate 11 is projected onto the r-plane. Since it is formed along the a-axis direction, it is possible to suppress stacking defects and obtain a high-quality a-plane GaN layer 14.
  • FIG. 6 is a partially enlarged cross-sectional view schematically showing the structure of the convex portion 12 in the present embodiment
  • FIG. 6A shows an example in which the top cross section has a semicircular shape
  • FIG. 6B shows an example. Shows an example in which a ridgeline is formed at the top.
  • the side wall surface portion 12a is formed so as to rise from the main surface of the r-plane sapphire substrate 11, and the curved surface portion 12b is formed above the side wall surface portion 12a.
  • the side wall surface portion 12a is preferably formed perpendicular to the main surface, but may be formed as a surface inclined with respect to the main surface.
  • the curved surface portion 12b is a curved surface having a semicircular cross section, and is formed with a curvature based on a diameter having a size similar to the width of the side wall surface portion 12a.
  • the uppermost portion of the curved surface portion 12b is the top portion 12c of the convex shape portion 12.
  • the side wall surface portion 12a is formed so as to rise from the main surface of the r-plane sapphire substrate 11, and the curved surface portion 12b is formed above the side wall surface portion 12a.
  • the curved surface portion 12b is a curved surface formed with a curvature based on a diameter different from the width D of the convex shape portion 12 (width of the side wall surface portion 12a), and the top portion 12c of the convex shape portion 12 has two curved surface portions 12b. It intersects to form a ridgeline portion along the a-axis.
  • the side wall surface portion 12a is substantially perpendicular to the main surface of the r-plane sapphire substrate 11, when the a-plane GaN layer 14 is crystal-grown, crystals do not grow from the surface of the side wall surface portion 12a. Further, since the curved surface portion 12b is formed above the side wall surface portion 12a and the curved surface portion 12b is formed with a predetermined curvature, a specific crystal plane orientation in the sapphire is not exposed. As a result, the a-plane GaN layer 14 is less likely to undergo crystal growth from the surface of the curved surface portion 12b. Therefore, the a-plane GaN layer 14 crystal grows from the main plane in the recess 13.
  • the r-plane of the sapphire is not exposed even around the top portion 12c, and the a-plane GaN from the top portion 12c.
  • the crystal growth of layer 14 can be effectively suppressed.
  • the interval S is preferably in the range of 200 nm or more and 500 nm or less, and more preferably in the range of 300 nm or more and 400 nm or less.
  • the height H of the convex portion 12 is preferably in the range of 500 nm or more and 1200 nm or less, and more preferably in the range of 700 nm or more and less than 1000 nm.
  • the width D of the convex portion 12 is too large, it is not preferable because the a-plane GaN layer 14 needs to be thick enough to fill the entire convex portion 12 and grow due to lateral growth, and the convex portion 12 is too small.
  • the lateral growth of the a-plane GaN layer 14 above the above is not continued, and the reduction of defects is insufficient, which is not preferable. Therefore, the width D is preferably in the range of 300 nm or more and 1200 nm or less, and more preferably in the range of 500 nm or more and less than 1000 nm.
  • the aspect ratio H / D of the convex portion 12 needs to be 1 or more in order for the a-plane GaN layer 14 to reach through dislocations and defects in the lateral growth of the a-plane GaN layer 14, but if it is too large, the a-plane GaN layer At the time of crystal growth of 14, the supply of raw materials is hindered, and it becomes difficult to carry out good crystal growth. Therefore, the aspect ratio H / D is preferably in the range of 1 or more and 4 or less, and more preferably in the range of 1 or more and 2 or less.
  • the convex portion 12 is in the a-axis direction perpendicular to the c'direction in which the r-axis of the r-plane sapphire substrate 11 and the c-axis of the r-plane sapphire substrate 11 are projected onto the r-plane. Since it is formed along the line, it is possible to suppress stacking defects and obtain a high-quality a-plane GaN layer 14.
  • FIG. 7 is a schematic cross-sectional view showing an LED which is a semiconductor device of this embodiment.
  • the LED 100 has an r-plane sapphire substrate 11, a nano-sized convex portion 12, an a-plane GaN layer 14, an active layer 16, a p-type semiconductor layer 17, an n-side electrode 18, and a p-side electrode 19. doing.
  • the r-plane sapphire substrate 11 is prepared, the nano-sized convex portion 12 is formed, and the a-plane GaN layer 14 is epitaxially grown by the MOCVD method. Subsequently, the active layer 16 and the p-type semiconductor layer 17 are sequentially grown by the MOCVD method to obtain a semiconductor substrate.
  • a part of the p-type semiconductor layer 17 and the active layer 16 is removed by photolithography and etching to expose a part of the a-plane GaN layer 14.
  • an electrode material is formed on the exposed surfaces of the a-plane GaN layer 14 and the p-type semiconductor layer 17 by vapor deposition or the like, and the LEDs are obtained by dicing and forming individual chips.
  • the active layer 16 is a semiconductor layer having the a-plane as a main surface, which is epitaxially grown on the a-plane GaN layer 14, and the LED 100 emits light when electrons and holes are luminescent and recombinated in the layer.
  • the active layer 16 is made of a material having a bandgap smaller than that of the a-plane GaN layer 14 and the p-type semiconductor layer 17, and examples thereof include InGaN and AlInGaN.
  • the active layer 16 may be intentionally non-doped containing impurities, or may be n-type containing n-type impurities or p-type containing p-type impurities.
  • the active layer 16 is a semiconductor layer having the a-plane as the main surface, spatial separation of electrons and holes due to the piezo electric field is unlikely to occur even if the film is thickened, and even if the current density is increased, the electrons and holes are efficiently positive.
  • the holes can be luminescent and recombined.
  • the p-type semiconductor layer 17 is a semiconductor layer epitaxially grown on the active layer 16 and having the a-plane as the main surface, and is a layer in which holes are injected from the p-side electrode 19 to supply holes to the active layer 16. ..
  • the a-plane GaN layer 14 and the p-type semiconductor layer 17 have been described as single layers, but they may include a plurality of layers having different materials and compositions, for example, the a-plane GaN layer 14 and the p-type semiconductor.
  • the layer 17 may include a clad layer, a contact layer, a current diffusion layer, an electron block layer, a waveguide layer, and the like.
  • the active layer 16 has been described as a single layer, it may be composed of a plurality of layers such as a multiple quantum well structure (MQW: Multi Quantum Well).
  • MQW Multi Quantum Well
  • the convex portion 12 is formed along the a-axis direction perpendicular to the r-axis of the r-plane sapphire substrate 11 and the c-axis of the r-plane sapphire substrate 11 projected onto the r-plane.
  • the active layer 16 and p are grown on the a-plane GaN layer 14 in which the stacking defects are suppressed to obtain a high-quality a-plane GaN layer 14 and the defect density is reduced.
  • the type semiconductor layer 17 also has good crystallinity and surface flatness.
  • this embodiment is an example which provided the active layer 16 as a functional layer.
  • the functional layer is a layer for exerting a predetermined electrical and chemical function in the semiconductor element.
  • the LED which is the semiconductor device of the present invention, has less droop due to the piezo electric field, has less anisotropy in the a-plane, and has good crystal quality, so that high brightness can be realized, and thus for vehicles.
  • the semiconductor device is not limited to the LED, and may be a semiconductor laser, and is used for other purposes such as a high electron mobility transistor (HEMT) having a functional layer for generating two-dimensional electron gas. You may.
  • HEMT high electron mobility transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Led Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

A substrate (10) for semiconductor growth, wherein: the r-plane of a sapphire is used as a main surface; the main surface is provided with a plurality of nanometer-sized protrusion parts (12); and the protrusion parts (12) are formed in the a-axis direction that is perpendicular to the r-axis of the sapphire and the c' direction that is the c-axis of the sapphire projected on the r-plane.

Description

半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法Semiconductor growth substrate, semiconductor element, semiconductor light emitting element and semiconductor element manufacturing method
　本発明は、半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法に関し、特にａ面ＧａＮ結晶層を成長させる半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法に関する。 The present invention relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method, and more particularly to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting device, and a semiconductor element manufacturing method for growing an a-plane GaN crystal layer.
　近年になって、照明用途に用いられる紫色から青色を発光するＬＥＤとして、非極性や半極性の面方位を主面としたＧａＮ系材料で活性層を形成するものが提案されている。ＧａＮ系半導体層では、ａ面やｍ面が非極性面であり、半極性面の代表例としてｒ面がある。非極性面や半極性面を用いたＧａＮ系半導体層では、積層方向へのピエゾ電界の影響を低減してドループ特性を改善することができる。 In recent years, as an LED that emits purple to blue light used for lighting applications, an LED that forms an active layer with a GaN-based material whose main surface is a non-polar or semi-polar plane orientation has been proposed. In the GaN-based semiconductor layer, the a-plane and the m-plane are non-polar planes, and the r-plane is a typical example of the semi-polar plane. In the GaN-based semiconductor layer using the non-polar surface or the semi-polar surface, the influence of the piezo electric field in the stacking direction can be reduced and the droop characteristics can be improved.
　特許文献１には、ｒ面サファイア基板の主面にナノサイズの凸形状部を形成し、バッファ層を介してａ面ＧａＮ層を成長させることで、横方向に成長するａ面ＧａＮ層中で転位を屈曲させ、半導体層の表面にまで継続する転位や欠陥を減少させる技術が提案されている。 In Patent Document 1, a nano-sized convex portion is formed on the main surface of the r-plane sapphire substrate, and the a-plane GaN layer is grown via the buffer layer in the a-plane GaN layer that grows in the lateral direction. A technique has been proposed in which dislocations are bent to reduce dislocations and defects that continue to the surface of the semiconductor layer.
日本国特開２０１９－０４０８９８号公報Japanese Patent Application Laid-Open No. 2019-040898
　しかし、ｒ面サファイア基板上に形成されるａ面ＧａＮ層では、成長面内に±ｃ軸方向やｍ軸方向が存在するため、面内異方性により異常成長が生じやすく、ａ面ＧａＮ層の欠陥密度の低減にも限界があった。ＧａＮ層に生じる欠陥の種類としては、サファイア基板とＧａＮの格子不整合に起因して発生する貫通転位（ＴＤ：Ｔｈｒｅａｄｉｎｇ　Ｄｉｓｌｏｃａｔｉｏｎ）に加えて、原子面の積み重ねの規則性に生じる積層欠陥（ＢＳＦ：Ｂａｓａｌ　ｐｌａｎｅ　Ｓｔａｃｋｉｎｇ　Ｆａｕｌｔ）が知られている。 However, in the a-plane GaN layer formed on the r-plane sapphire substrate, since the ± c-axis direction and the m-axis direction exist in the growth plane, abnormal growth is likely to occur due to in-plane anisotropy, and the a-plane GaN layer There was also a limit to the reduction of defect density. The types of defects that occur in the GaN layer include stacking defects (BSF:) that occur in the regularity of stacking of atomic planes, in addition to through dislocations (TD: Crystals) that occur due to lattice mismatch between the sapphire substrate and GaN. Bassal plane Stacking Fault) is known.
　特に積層欠陥（ＢＳＦ）は、結晶面内に窒素極性の（０００-１）面を有するａ面ＧａＮ層で顕著に発生する結晶欠陥であることが知られており、ＧａＮ層の横方向成長で貫通転位（ＴＤ）を低減しても積層欠陥（ＢＳＦ）を低減することが困難であった。 In particular, stacking defects (BSF) are known to be crystal defects that occur prominently in the a-plane GaN layer having a nitrogen-polar (000-1) plane in the crystal plane, and are known to occur in the lateral growth of the GaN layer. It was difficult to reduce stacking defects (BSF) even if the through-through dislocations (TD) were reduced.
　本発明は上記従来の問題点に鑑みなされたものであり、積層欠陥を抑制して高品質なａ面ＧａＮ層を成長させることが可能な半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法を提供することを目的とする。 The present invention has been made in view of the above-mentioned conventional problems, and is a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element capable of suppressing stacking defects and growing a high-quality a-plane GaN layer. It is an object of the present invention to provide a manufacturing method.
　上記課題を解決するために、本発明の半導体成長用基板は、サファイアのｒ面を主面とし、前記主面にナノサイズの凸形状部が複数形成されており、前記凸形状部は前記サファイアのｒ軸と前記サファイアのｃ軸を前記ｒ面に投影したｃ’方向とに垂直なａ軸方向に沿って形成されている。 In order to solve the above problems, the semiconductor growth substrate of the present invention has the r-plane of sapphire as the main surface, and a plurality of nano-sized convex portions are formed on the main surface, and the convex portions are the sapphire. The r-axis of the sapphire and the c-axis of the sapphire are projected along the a-axis direction perpendicular to the c'direction projected onto the r-plane.
　凸形状部がｒ面サファイア基板のｒ軸およびｃ’方向に垂直なａ軸方向に沿って形成されていることで、凸形状部の間から生じる-ｃ面を凸形状部に沿って集約することができ、積層欠陥を抑制して高品質なａ面ＧａＮ層を得ることができる。 Since the convex portion is formed along the r-axis of the r-plane sapphire substrate and the a-axis direction perpendicular to the c'direction, the -c-plane generated between the convex portions is aggregated along the convex portion. It is possible to suppress stacking defects and obtain a high-quality a-plane GaN layer.
　積層欠陥を抑制して高品質なａ面ＧａＮ層を成長させることが可能となる。 It is possible to suppress stacking defects and grow a high-quality a-plane GaN layer.
　また本発明の一態様では、前記凸形状部の間隔が２００ｎｍ以上５００ｎｍ以下の範囲である。 Further, in one aspect of the present invention, the distance between the convex portions is in the range of 200 nm or more and 500 nm or less.
　また本発明の一態様では、前記凸形状部は、前記主面から立ち上がって形成された側壁面部と、前記側壁面部より上方に形成された曲面部とを有する。 Further, in one aspect of the present invention, the convex-shaped portion has a side wall surface portion formed by rising from the main surface and a curved surface portion formed above the side wall surface portion.
　また本発明の一態様では、前記曲面部は、前記凸形状部の幅とは異なる大きさの直径に基づく曲率で形成されており、前記凸形状部の頂部には２つの前記曲面部が交わる稜線部が形成されている。 Further, in one aspect of the present invention, the curved surface portion is formed with a curvature based on a diameter having a size different from the width of the convex shape portion, and the two curved surface portions intersect at the top of the convex shape portion. A ridgeline portion is formed.
　また上記課題を解決するために本発明の半導体素子は、上記何れか一つに記載の半導体成長用基板と、前記半導体成長用基板の上に設けられた機能層と、を備える。 Further, in order to solve the above problems, the semiconductor element of the present invention includes the semiconductor growth substrate according to any one of the above and a functional layer provided on the semiconductor growth substrate.
　また上記課題を解決するために本発明の半導体発光素子は、上記何れか一つに記載の半導体成長用基板と、前記半導体成長用基板の上に設けられた活性層と、を備える。 Further, in order to solve the above problems, the semiconductor light emitting device of the present invention includes the semiconductor growth substrate according to any one of the above and an active layer provided on the semiconductor growth substrate.
　また上記課題を解決するために本発明の半導体素子製造方法は、ｒ面を主面とするサファイアの上に、前記サファイアのｒ軸と前記サファイアのｃ軸を前記ｒ面に投影したｃ’方向とに垂直なａ軸方向に沿って凸形状部を複数形成する工程と、前記主面の上に窒化物半導体層を成長させる工程と、を備える。 In order to solve the above problems, the semiconductor device manufacturing method of the present invention has a c'direction in which the r-axis of the sapphire and the c-axis of the sapphire are projected onto the r-plane on a sapphire whose main surface is the r-plane. The present invention includes a step of forming a plurality of convex portions along the a-axis direction perpendicular to the above, and a step of growing a nitride semiconductor layer on the main surface.
　本発明では、積層欠陥を抑制して高品質なａ面ＧａＮ層を成長させることが可能な半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法を提供することができる。 The present invention can provide a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method capable of suppressing stacking defects and growing a high-quality a-plane GaN layer.
第１実施形態における半導体成長用基板１０を示す模式斜視図である。It is a schematic perspective view which shows the semiconductor growth substrate 10 in 1st Embodiment. 半導体成長用基板１０上にａ面ＧａＮ層１４を成長させた状態を示す模式断面図であり、図２の（ａ）はａ面ＧａＮ層１４を直接成長させた例を示し、図２の（ｂ）はバッファ層１５を形成した例を示している。FIG. 2A is a schematic cross-sectional view showing a state in which the a-plane GaN layer 14 is grown on the semiconductor growth substrate 10, FIG. 2A shows an example in which the a-plane GaN layer 14 is directly grown, and is shown in FIG. b) shows an example in which the buffer layer 15 is formed. 図３の（ａ）はａ面ＧａＮ層１４の成長初期における島状結晶を示したＳＥＭ像であり、図３の（ｂ）は成長後のａ面ＧａＮ層１４を平坦化した後の表面状態を示したＴＥＭ像である。FIG. 3A is an SEM image showing island-shaped crystals at the initial stage of growth of the a-plane GaN layer 14, and FIG. 3B is a surface state after flattening the a-plane GaN layer 14 after growth. It is a TEM image showing. ａ軸に沿って形成した凸形状部１２と凹部１３からのａ面ＧａＮ層１４の成長初期段階の様子を模式的に示す図であり、図４の（ａ）は模式平面図であり、図４の（ｂ）は模式断面図である。It is a figure which shows typically the state of the growth initial stage of the a-plane GaN layer 14 from the convex-shaped part 12 and the concave part 13 formed along the a-axis, and FIG. 4A is a schematic plan view, and is the figure. (B) of 4 is a schematic cross-sectional view. ｃ’方向に沿って形成した凸形状部１２と凹部１３からのａ面ＧａＮ層１４の成長初期段階の様子を模式的に示す図であり、図５の（ａ）は模式平面図であり、図５の（ｂ）は模式断面図である。It is a figure which shows typically the state of the growth initial stage of the a-plane GaN layer 14 from the convex part 12 and the concave part 13 formed along the c'direction, and FIG. 5 (a) is a schematic plan view. FIG. 5B is a schematic cross-sectional view. 第２実施形態における凸形状部１２の構造を模式的に示す部分拡大断面図であり、図６の（ａ）は頂部断面が半円形状の例を示し、図６の（ｂ）は頂部に稜線部が形成された例を示している。It is a partially enlarged cross-sectional view which shows typically the structure of the convex-shaped part 12 in 2nd Embodiment, FIG. 6A shows an example of a semicircular top cross section, and FIG. 6B is a top. An example in which a ridgeline portion is formed is shown. 第３実施形態の半導体装置であるＬＥＤを示す模式断面図である。It is a schematic cross-sectional view which shows LED which is the semiconductor device of 3rd Embodiment.
　（第１実施形態）
　以下、本発明の実施の形態について、図面を参照して詳細に説明する。各図面に示される同一または同等の構成要素、部材、処理には、同一の符号を付すものとし、適宜重複した説明は省略する。図１は、本発明の第１実施形態における半導体成長用基板１０を示す模式斜視図である。図１に示すように半導体成長用基板１０は、ｒ面サファイア基板１１上に、複数の凸形状部１２が形成されている。 (First Embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. FIG. 1 is a schematic perspective view showing a semiconductor growth substrate 10 according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor growth substrate 10 has a plurality of convex portions 12 formed on the r-plane sapphire substrate 11.
　ｒ面サファイア基板１１は、サファイアの単結晶で構成された基板であり、六方晶のｒ面を主面としている。ここではｒ面サファイア基板１１として傾斜角度が０度のジャスト基板を示したが、ｒ面を所定の面方位に数度傾斜させたオフ基板としてもよい。 The r-plane sapphire substrate 11 is a substrate composed of a single crystal of sapphire, and has the r-plane of hexagonal crystals as the main surface. Here, the just substrate having an inclination angle of 0 degrees is shown as the r-plane sapphire substrate 11, but an off-board substrate in which the r-plane is inclined by several degrees in a predetermined plane direction may be used.
　凸形状部１２は、ｒ面サファイア基板１１の主面上に形成された凸部であり、サファイアのｒ軸と、サファイアのｃ軸をｒ面に投影したｃ’方向との両方に対して垂直なａ軸に沿って形成されている。図１に矢印で示したように、図中上方向はｒ軸であり、図中右方向はｃ軸をｒ面に投影したｃ’方向であり、奥行き方向がｒ軸とｃ’方向に垂直なａ軸である。後述するように、凸形状部１２同士の間には凹部１３が形成されており、凹部１３からはｒ面サファイア基板１１の主面であるｒ面が露出している。ここでは凸形状部１２がａ軸に沿っている例を示したが、ａ軸から４５度未満の角度だけａ軸方向に対して斜めに伸びていてもよい。 The convex portion 12 is a convex portion formed on the main surface of the r-plane sapphire substrate 11, and is perpendicular to both the r-axis of sapphire and the c'direction in which the c-axis of sapphire is projected onto the r-plane. It is formed along the a-axis. As shown by the arrows in FIG. 1, the upper direction in the figure is the r-axis, the right direction in the figure is the c'direction in which the c-axis is projected onto the r-plane, and the depth direction is perpendicular to the r-axis and the c'direction. A axis. As will be described later, recesses 13 are formed between the convex portions 12, and the r-plane, which is the main surface of the r-plane sapphire substrate 11, is exposed from the recesses 13. Here, an example in which the convex portion 12 is along the a-axis is shown, but it may extend obliquely with respect to the a-axis direction by an angle of less than 45 degrees from the a-axis.
　図２は、半導体成長用基板１０上にａ面ＧａＮ層１４を成長させた状態を示す模式断面図であり、図２の（ａ）はａ面ＧａＮ層１４を直接成長させた例を示し、図２の（ｂ）はバッファ層１５を形成した例を示している。 FIG. 2 is a schematic cross-sectional view showing a state in which the a-plane GaN layer 14 is grown on the semiconductor growth substrate 10, and FIG. 2A shows an example in which the a-plane GaN layer 14 is directly grown. FIG. 2B shows an example in which the buffer layer 15 is formed.
　図２の（ａ）に示すように、半導体成長用基板１０には、ｒ面サファイア基板１１上の凸形状部１２間の凹部１３で露出した主面から、ａ面を主面とするａ面ＧａＮ層１４を成長させる。図２の（ｂ）に示すように、ｒ面サファイア基板１１とａ面ＧａＮ層１４との間に格子不整合を緩和するためのバッファ層１５を形成してもよい。 As shown in FIG. 2A, the semiconductor growth substrate 10 has an a-plane having the a-plane as the main surface from the main surface exposed by the recesses 13 between the convex portions 12 on the r-plane sapphire substrate 11. The GaN layer 14 is grown. As shown in FIG. 2B, a buffer layer 15 for alleviating lattice mismatch may be formed between the r-plane sapphire substrate 11 and the a-plane GaN layer 14.
　ａ面ＧａＮ層１４は、主面がａ面となるように成長された下地層であり、その上に窒化物半導体層をエピタキシャル成長するための層である。ａ面ＧａＮ層１４の形成方法としては、ＭＯＣＶＤ法（有機金属気相成長法：ＭｅｔａｌＯｒｇａｎｉｃ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）やＨＶＰＥ法（ハイドライド気相成長法：Ｈｙｄｒｉｄｅ　Ｖａｐｏｒ　Ｐｈａｓｅ　Ｅｐｉｔａｘｙ）などの公知の方法を用いることができるが、ＭＯＣＶＤ法を用いることが好ましい。ａ面ＧａＮ層１４の膜厚は特に限定されないが、１μｍ以上形成することが好ましい。 The a-plane GaN layer 14 is a base layer grown so that the main surface is the a-plane, and is a layer for epitaxially growing a nitride semiconductor layer on the base layer. As a method for forming the a-plane GaN layer 14, a known method such as a MOCVD method (organic metal vapor deposition method: Metalorganic Chemical Vapor Deposition) or an HVPE method (hydride vapor phase growth method: Hydride Vapor Phase Epitaxy) is used. Although it can be done, it is preferable to use the MOCVD method. The film thickness of the a-plane GaN layer 14 is not particularly limited, but it is preferably formed at 1 μm or more.
　バッファ層１５は、ｒ面サファイア基板１１と窒化物半導体層（ａ面ＧａＮ層１４）との間での格子不整合を緩和するために形成された層である。バッファ層１５を構成する材料としては、ＡｌＮ，ＧａＮ，ＩｎＧａＮ，ＡｌＧａＮ等が挙げられるが、ＡｌＮを用いることが好ましい。また、バッファ層１５を形成する方法としては、スパッタ法やＭＯＣＶＤ法等を用いることができ、スパッタ法を用いることが好ましい。バッファ層１５の厚みとしては、厚くしすぎると窒化物半導体層（ａ面ＧａＮ層１４）の結晶品質が低下するため５～３００ｎｍの範囲が好ましく、５～９０ｎｍの範囲がより好ましく、５～３０ｎｍの範囲がさらに好ましい。 The buffer layer 15 is a layer formed to alleviate the lattice mismatch between the r-plane sapphire substrate 11 and the nitride semiconductor layer (a-plane GaN layer 14). Examples of the material constituting the buffer layer 15 include AlN, GaN, InGaN, AlGaN, and the like, but it is preferable to use AlN. Further, as a method for forming the buffer layer 15, a sputtering method, a MOCVD method, or the like can be used, and it is preferable to use the sputtering method. The thickness of the buffer layer 15 is preferably in the range of 5 to 300 nm, more preferably in the range of 5 to 90 nm, and more preferably in the range of 5 to 30 nm because the crystal quality of the nitride semiconductor layer (a-side GaN layer 14) deteriorates if it is made too thick. The range of is more preferred.
　（製造方法）
　次に、本実施形態における半導体成長用基板１０の製造方法について説明する。ｒ面サファイア基板１１の表面にナノサイズの凸形状部１２を形成する方法としては、公知のナノインプリントとパターニングを用いることができる。一例として、ｒ面サファイア基板１１上にレジスト膜を塗布し、凸形状部１２に対応したパターンが形成されたモールドを用い、ナノインプリント技術を用いてレジスト膜にパターンを転写する。次にナノパターンが転写されたレジスト膜とｒ面サファイア基板１１に対して、塩素系ガスを用いて異方性エッチングすることで、ナノサイズの凸形状部１２がｒ面サファイア基板１１上に形成される。 (Production method)
Next, a method of manufacturing the semiconductor growth substrate 10 in the present embodiment will be described. As a method for forming the nano-sized convex portion 12 on the surface of the r-plane sapphire substrate 11, known nanoimprint and patterning can be used. As an example, a resist film is applied onto the r-plane sapphire substrate 11, and a mold having a pattern corresponding to the convex portion 12 is used to transfer the pattern to the resist film using nanoimprint technology. Next, the resist film to which the nanopattern is transferred and the r-plane sapphire substrate 11 are anisotropically etched with a chlorine-based gas to form a nano-sized convex portion 12 on the r-plane sapphire substrate 11. Will be done.
　続いて、本実施形態の半導体成長用基板１０にバッファ層１５およびａ面ＧａＮ層１４を形成する方法を説明する。ナノサイズの凸形状部１２を複数形成したｒ面サファイア基板１１上に、例えば膜厚が３０ｎｍ程度のバッファ層１５をスパッタ法等で形成する。バッファ層１５を形成するスパッタ法としては、ＡｌＮをターゲット材としてＡｒガスを用いることがより好ましい。ターゲット材となるＡｌＮとしては単結晶基板であっても粉末焼体であってもよく、その状態や形態は限定されない。 Subsequently, a method of forming the buffer layer 15 and the a-plane GaN layer 14 on the semiconductor growth substrate 10 of the present embodiment will be described. On the r-plane sapphire substrate 11 on which a plurality of nano-sized convex portions 12 are formed, for example, a buffer layer 15 having a film thickness of about 30 nm is formed by a sputtering method or the like. As a sputtering method for forming the buffer layer 15, it is more preferable to use Ar gas with AlN as a target material. The AlN as the target material may be a single crystal substrate or a powder-fired body, and its state and form are not limited.
　次に、バッファ層１５の表面を洗浄した後に、キャリアガスとして水素、窒素を用い、Ｖ族原料としてアンモニア（ＮＨ３）を用い、ＩＩＩ族原料としてＴＭＧ（ＴｒｉｍｅｔｈｙｌＧａｌｌｉｕｍ）を用いて、ＭＯＣＶＤ法でａ面ＧａＮ層１４を成長させる。成長条件の一例としては、温度を１０１０℃まで昇温した後に成長温度を一定とし、リアクタ圧力とＶ／ＩＩＩ比および成長時間を変更する２段階の成長シーケンスを用いる。例えば、はじめにＶ／ＩＩＩ比を４０００～５０００程度、圧力を９００～１０００ｈＰａとして１０～２０分程度維持し、次にＶ／ＩＩＩ比を１００～２００程度、圧力を１００～１５０ｈＰａとして９０～１２０分維持する。ａ面ＧａＮ層１４を成長させた後に室温まで冷却して取り出すことで、ｒ面サファイア基板１１の主面にナノサイズの凸形状部１２が複数形成され、バッファ層１５およびａ面ＧａＮ層１４が形成された本実施形態の半導体成長用基板１０を得ることができる。 Next, after cleaning the surface of the buffer layer 15, hydrogen and nitrogen are used as carrier gases, ammonia (NH 3 ) is used as a group V raw material, and TMG (Trimethylgallium) is used as a group III raw material by the MOCVD method. The surface GaN layer 14 is grown. As an example of the growth conditions, a two-step growth sequence is used in which the temperature is raised to 1010 ° C., the growth temperature is kept constant, and the reactor pressure, V / III ratio, and growth time are changed. For example, first maintain the V / III ratio at about 4000 to 5000 and the pressure at 900 to 1000 hPa for about 10 to 20 minutes, then maintain the V / III ratio at about 100 to 200 and the pressure at 100 to 150 hPa for 90 to 120 minutes. To do. By growing the a-plane GaN layer 14 and then cooling it to room temperature and taking it out, a plurality of nano-sized convex portions 12 are formed on the main surface of the r-plane sapphire substrate 11, and the buffer layer 15 and the a-plane GaN layer 14 are formed. The formed semiconductor growth substrate 10 of the present embodiment can be obtained.
　ａ面ＧａＮ層１４が成長する際に、凸形状部１２の間における凹部１３で生じた貫通転位は、横方向成長によって集約されて凸形状部１２の頂点付近に集約される。したがって、ａ面ＧａＮ層１４の最表面にまで続く貫通転位（ＴＤ）の密度は小さくなる。これにより、本実施形態の半導体成長用基板１０では、結晶性が良好で表面平坦性に優れた高品質なａ面ＧａＮ層を成長させることが可能となる。 When the a-plane GaN layer 14 grows, the penetrating dislocations generated in the recesses 13 between the convex portions 12 are aggregated by lateral growth and are aggregated near the vertices of the convex portions 12. Therefore, the density of through dislocations (TD) extending to the outermost surface of the a-plane GaN layer 14 becomes small. As a result, in the semiconductor growth substrate 10 of the present embodiment, it is possible to grow a high-quality a-plane GaN layer having good crystallinity and excellent surface flatness.
　次に、ａ面ＧａＮ層１４に生じる積層欠陥（ＢＳＦ）とその低減手法について図３および図４を用いて説明する。図３は、ａ面ＧａＮ層１４の結晶成長を示すＴＥＭ像であり、図３の（ａ）は成長初期における島状結晶を示し、図３の（ｂ）は成長後のａ面ＧａＮ層１４を平坦化した後の表面状態を示している。 Next, the stacking defects (BSF) generated in the a-plane GaN layer 14 and the method for reducing them will be described with reference to FIGS. 3 and 4. FIG. 3 is a TEM image showing the crystal growth of the a-plane GaN layer 14, FIG. 3 (a) shows island-shaped crystals in the early stage of growth, and FIG. 3 (b) is the a-plane GaN layer 14 after growth. Shows the surface condition after flattening.
　図３の（ａ）に示すように、ｒ面サファイア基板１１の主面上にａ面ＧａＮ層１４を結晶成長させると、成長の初期段階において成長核である島状結晶が主面上に複数生じる。島状結晶はＧａＮからなる単結晶であり、（０００-１）面、（１-１００）面、（１-１０１）面をファセットとして結晶サイズが大きくなっていくことが知られている。ａ面ＧａＮ層１４の結晶成長を継続すると、複数の島状結晶が結合して大きなサイズの単結晶が得られる。 As shown in FIG. 3A, when the a-plane GaN layer 14 is crystal-grown on the main surface of the r-plane sapphire substrate 11, a plurality of island-shaped crystals, which are growth nuclei, are formed on the main surface in the initial stage of growth. Occurs. The island-shaped crystal is a single crystal made of GaN, and it is known that the crystal size increases with the (000-1) plane, the (1-100) plane, and the (1-101) plane as facets. When the crystal growth of the a-plane GaN layer 14 is continued, a plurality of island-shaped crystals are bonded to obtain a large-sized single crystal.
　しかし、ＧａＮの結晶成長においては、（０００-１）面、（１-１００）面、（１-１０１）面等のファセット毎に結晶成長の速度が異なることが知られており、さらに-ｃ面である（０００-１）面は、窒素極性となっている。これらによって-ｃ面でのファセット成長と、（１-１０１）面でのファセット成長とが結合する際に、ａ面ＧａＮ層１４中には図３の（ｂ）に示したような積層欠陥（ＢＳＦ）が無数に生じてしまう。 However, in the crystal growth of GaN, it is known that the rate of crystal growth differs for each facet such as the (000-1) plane, the (1-100) plane, and the (1-101) plane, and further -c. The (000-1) plane, which is a plane, has a nitrogen polarity. As a result, when the facet growth on the -c plane and the facet growth on the (1-101) plane are combined, the stacking defects (b) as shown in FIG. 3 (b) are contained in the a-plane GaN layer 14. BSF) will occur innumerably.
　図４は、ａ軸に沿って形成した凸形状部１２と凹部１３からのａ面ＧａＮ層１４の成長初期段階の様子を模式的に示す図であり、図４の（ａ）は模式平面図であり、図４の（ｂ）は模式断面図である。図５は、ｃ’方向に沿って形成した凸形状部１２と凹部１３からのａ面ＧａＮ層１４の成長初期段階の様子を模式的に示す図であり、図５の（ａ）は模式平面図であり、図５の（ｂ）は模式断面図である。図中に示した矢印は、ａ面ＧａＮ層１４の成長初期段階において主面上に生じる成長核である島状結晶の-ｃ面の位置を示している。 FIG. 4 is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex portion 12 and the concave portion 13 formed along the a-axis, and FIG. 4A is a schematic plan view. FIG. 4B is a schematic cross-sectional view. FIG. 5 is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex portion 12 and the concave portion 13 formed along the c'direction, and FIG. 5 (a) is a schematic plane. FIG. 5B is a schematic cross-sectional view. The arrow shown in the figure indicates the position of the -c plane of the island-shaped crystal, which is a growth nucleus generated on the main plane in the initial stage of growth of the a-plane GaN layer 14.
　図４の（ａ）および図４の（ｂ）に示したように、ａ軸に沿って凸形状部１２を形成すると、複数の島状結晶の-ｃ面はａ軸に沿って配向するため、凹部１３内の-ｃ面が凸形状部１２に沿って一直線に集約されて結晶成長が進行する。これにより、ａ面ＧａＮ層１４中において-ｃ面に起因する積層欠陥（ＢＳＦ）を低減することができる。 As shown in (a) of FIG. 4 and (b) of FIG. 4, when the convex portion 12 is formed along the a-axis, the -c planes of the plurality of island-shaped crystals are oriented along the a-axis. , The -c surface in the recess 13 is gathered in a straight line along the convex portion 12, and crystal growth proceeds. This makes it possible to reduce stacking defects (BSF) caused by the -c plane in the a-plane GaN layer 14.
　それに対して図５の（ａ）および図５の（ｂ）に示したように、ｃ’方向に沿って凸形状部１２を成長させた場合には、複数の島状結晶が生じると各島状結晶にそれぞれ-ｃ面が生じ、凹部１３内に複数の-ｃ面を有する状態で結晶成長が進行する。その結果、-ｃ面に起因する積層欠陥（ＢＳＦ）が多数残留したままａ面ＧａＮ層１４が形成されてしまう。 On the other hand, as shown in FIGS. 5 (a) and 5 (b), when the convex portion 12 is grown along the c'direction, when a plurality of island-shaped crystals are formed, each island Each of the shaped crystals has a -c plane, and crystal growth proceeds in a state where the recess 13 has a plurality of -c planes. As a result, the a-plane GaN layer 14 is formed with a large number of stacking defects (BSF) due to the -c-plane remaining.
　上述したように本実施形態の半導体成長用基板１０では、凸形状部１２がｒ面サファイア基板１１のｒ軸とｒ面サファイア基板１１のｃ軸をｒ面に投影したｃ’方向とに垂直なａ軸方向に沿って形成されていることで、積層欠陥を抑制して高品質なａ面ＧａＮ層１４を得ることができる。 As described above, in the semiconductor growth substrate 10 of the present embodiment, the convex portion 12 is perpendicular to the r-axis of the r-plane sapphire substrate 11 and the c'direction in which the c-axis of the r-plane sapphire substrate 11 is projected onto the r-plane. Since it is formed along the a-axis direction, it is possible to suppress stacking defects and obtain a high-quality a-plane GaN layer 14.
　（第２実施形態）
　次に、本発明の第２実施形態について図６を用いて説明する。図６は、本実施形態における凸形状部１２の構造を模式的に示す部分拡大断面図であり、図６の（ａ）は頂部断面が半円形状の例を示し、図６の（ｂ）は頂部に稜線部が形成された例を示している。図６の（ａ）に示した例では、ｒ面サファイア基板１１の主面から側壁面部１２ａが立ち上がって形成されており、側壁面部１２ａの上方には曲面部１２ｂが形成されている。側壁面部１２ａは主面に対して垂直に形成されていることが好ましいが、主面に対して傾斜する面として形成されていてもよい。また、曲面部１２ｂは断面が半円形状に形成された曲面であり、側壁面部１２ａの幅と同程度の大きさの直径に基づく曲率で形成されている。曲面部１２ｂの最上部は、凸形状部１２の頂部１２ｃとなっている。 (Second Embodiment)
Next, the second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a partially enlarged cross-sectional view schematically showing the structure of the convex portion 12 in the present embodiment, FIG. 6A shows an example in which the top cross section has a semicircular shape, and FIG. 6B shows an example. Shows an example in which a ridgeline is formed at the top. In the example shown in FIG. 6A, the side wall surface portion 12a is formed so as to rise from the main surface of the r-plane sapphire substrate 11, and the curved surface portion 12b is formed above the side wall surface portion 12a. The side wall surface portion 12a is preferably formed perpendicular to the main surface, but may be formed as a surface inclined with respect to the main surface. Further, the curved surface portion 12b is a curved surface having a semicircular cross section, and is formed with a curvature based on a diameter having a size similar to the width of the side wall surface portion 12a. The uppermost portion of the curved surface portion 12b is the top portion 12c of the convex shape portion 12.
　図６の（ｂ）に示した例でも、ｒ面サファイア基板１１の主面から側壁面部１２ａが立ち上がって形成されており、側壁面部１２ａの上方には曲面部１２ｂが形成されている。曲面部１２ｂは凸形状部１２の幅Ｄ（側壁面部１２ａの幅）とは異なる大きさの直径に基づく曲率で形成された曲面であり、凸形状部１２の頂部１２ｃは２つの曲面部１２ｂが交わってａ軸に沿った稜線部を構成している。 Also in the example shown in FIG. 6B, the side wall surface portion 12a is formed so as to rise from the main surface of the r-plane sapphire substrate 11, and the curved surface portion 12b is formed above the side wall surface portion 12a. The curved surface portion 12b is a curved surface formed with a curvature based on a diameter different from the width D of the convex shape portion 12 (width of the side wall surface portion 12a), and the top portion 12c of the convex shape portion 12 has two curved surface portions 12b. It intersects to form a ridgeline portion along the a-axis.
　側壁面部１２ａがｒ面サファイア基板１１の主面に対して略垂直であるため、ａ面ＧａＮ層１４を結晶成長させる際には側壁面部１２ａの表面からは結晶成長しない。また、側壁面部１２ａよりも上方には曲面部１２ｂが形成されており、曲面部１２ｂが所定の曲率をもって形成されているため、サファイアにおける特定の結晶面方位が露出しない。これにより、曲面部１２ｂの表面からもａ面ＧａＮ層１４は結晶成長しにくくなる。したがって、ａ面ＧａＮ層１４は、凹部１３における主面から結晶成長する。特に、図６の（ｂ）に示す凸形状部１２の頂部１２ｃに稜線部が構成されている例では、頂部１２ｃの周辺においてもサファイアのｒ面が露出せず、頂部１２ｃからのａ面ＧａＮ層１４の結晶成長を効果的に抑制することができる。 Since the side wall surface portion 12a is substantially perpendicular to the main surface of the r-plane sapphire substrate 11, when the a-plane GaN layer 14 is crystal-grown, crystals do not grow from the surface of the side wall surface portion 12a. Further, since the curved surface portion 12b is formed above the side wall surface portion 12a and the curved surface portion 12b is formed with a predetermined curvature, a specific crystal plane orientation in the sapphire is not exposed. As a result, the a-plane GaN layer 14 is less likely to undergo crystal growth from the surface of the curved surface portion 12b. Therefore, the a-plane GaN layer 14 crystal grows from the main plane in the recess 13. In particular, in the example in which the ridgeline portion is formed on the top portion 12c of the convex shape portion 12 shown in FIG. 6B, the r-plane of the sapphire is not exposed even around the top portion 12c, and the a-plane GaN from the top portion 12c. The crystal growth of layer 14 can be effectively suppressed.
　凸形状部１２の間隔Ｓは、狭すぎるとａ面ＧａＮ層１４の結晶成長時に原料供給が阻害されて良好に結晶成長を行うことが困難になり、広すぎると結晶成長が開始する主面の面積が大きくなるため貫通転位や欠陥が発生する領域が多くなる。したがって間隔Ｓは、２００ｎｍ以上５００ｎｍ以下の範囲が好ましく、３００ｎｍ以上４００ｎｍ以下の範囲であることがより好ましい。 If the distance S between the convex portions 12 is too narrow, the supply of raw materials is hindered during crystal growth of the a-plane GaN layer 14, and it becomes difficult to perform good crystal growth. If it is too wide, the crystal growth starts on the main surface. Since the area is large, there are many areas where through dislocations and defects occur. Therefore, the interval S is preferably in the range of 200 nm or more and 500 nm or less, and more preferably in the range of 300 nm or more and 400 nm or less.
　凸形状部１２の高さＨは、低すぎると横方向成長でも側壁面部１２ａに到達せず欠陥を低減できず、高すぎるとａ面ＧａＮ層１４の結晶成長時に原料供給が阻害されて良好に結晶成長を行うことが困難になる。したがって高さＨは、５００ｎｍ以上１２００ｎｍ以下の範囲が好ましく、７００ｎｍ以上１０００ｎｍ未満の範囲であることがより好ましい。 If the height H of the convex portion 12 is too low, it will not reach the side wall surface portion 12a even in the lateral growth and defects cannot be reduced, and if it is too high, the supply of raw materials will be hindered during crystal growth of the a-plane GaN layer 14, which is good. It becomes difficult to carry out crystal growth. Therefore, the height H is preferably in the range of 500 nm or more and 1200 nm or less, and more preferably in the range of 700 nm or more and less than 1000 nm.
　凸形状部１２の幅Ｄは、大きすぎると横方向成長でａ面ＧａＮ層１４が凸形状部１２全体を埋めて成長するまでの厚さが必要になるため好ましくなく、小さすぎる凸形状部１２の上方でのａ面ＧａＮ層１４の横方向成長が継続されず、欠陥の低減が不十分になるため好ましくない。したがって幅Ｄは、３００ｎｍ以上１２００ｎｍ以下の範囲が好ましく、５００ｎｍ以上１０００ｎｍ未満の範囲であることがより好ましい。 If the width D of the convex portion 12 is too large, it is not preferable because the a-plane GaN layer 14 needs to be thick enough to fill the entire convex portion 12 and grow due to lateral growth, and the convex portion 12 is too small. The lateral growth of the a-plane GaN layer 14 above the above is not continued, and the reduction of defects is insufficient, which is not preferable. Therefore, the width D is preferably in the range of 300 nm or more and 1200 nm or less, and more preferably in the range of 500 nm or more and less than 1000 nm.
　凸形状部１２のアスペクト比Ｈ／Ｄは、ａ面ＧａＮ層１４の横方向成長で貫通転位や欠陥を側壁面部１２ａに到達させるために１以上が必要であるが、大きすぎるとａ面ＧａＮ層１４の結晶成長時に原料供給が阻害されて良好に結晶成長を行うことが困難になる。したがってアスペクト比Ｈ／Ｄは、１以上４以下の範囲が好ましく、１以上２以下の範囲であることがより好ましい。 The aspect ratio H / D of the convex portion 12 needs to be 1 or more in order for the a-plane GaN layer 14 to reach through dislocations and defects in the lateral growth of the a-plane GaN layer 14, but if it is too large, the a-plane GaN layer At the time of crystal growth of 14, the supply of raw materials is hindered, and it becomes difficult to carry out good crystal growth. Therefore, the aspect ratio H / D is preferably in the range of 1 or more and 4 or less, and more preferably in the range of 1 or more and 2 or less.
　本実施形態の半導体成長用基板１０でも、凸形状部１２がｒ面サファイア基板１１のｒ軸とｒ面サファイア基板１１のｃ軸をｒ面に投影したｃ’方向とに垂直なａ軸方向に沿って形成されていることで、積層欠陥を抑制して高品質なａ面ＧａＮ層１４を得ることができる。 Also in the semiconductor growth substrate 10 of the present embodiment, the convex portion 12 is in the a-axis direction perpendicular to the c'direction in which the r-axis of the r-plane sapphire substrate 11 and the c-axis of the r-plane sapphire substrate 11 are projected onto the r-plane. Since it is formed along the line, it is possible to suppress stacking defects and obtain a high-quality a-plane GaN layer 14.
　（第３実施形態）
　次に、本発明の第３実施形態について図７を用いて説明する。図７は本実施形態の半導体装置であるＬＥＤを示す模式断面図である。図７に示すようにＬＥＤ１００は、ｒ面サファイア基板１１、ナノサイズの凸形状部１２、ａ面ＧａＮ層１４、活性層１６、ｐ型半導体層１７、ｎ側電極１８、ｐ側電極１９を有している。 (Third Embodiment)
Next, the third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a schematic cross-sectional view showing an LED which is a semiconductor device of this embodiment. As shown in FIG. 7, the LED 100 has an r-plane sapphire substrate 11, a nano-sized convex portion 12, an a-plane GaN layer 14, an active layer 16, a p-type semiconductor layer 17, an n-side electrode 18, and a p-side electrode 19. doing.
　第１実施形態と同様に、ｒ面サファイア基板１１を用意し、ナノサイズの凸形状部１２を形成し、ＭＯＣＶＤ法でａ面ＧａＮ層１４をエピタキシャル成長させる。続いて、ＭＯＣＶＤ法で活性層１６、ｐ型半導体層１７を順次成長させて半導体基板を得る。 Similar to the first embodiment, the r-plane sapphire substrate 11 is prepared, the nano-sized convex portion 12 is formed, and the a-plane GaN layer 14 is epitaxially grown by the MOCVD method. Subsequently, the active layer 16 and the p-type semiconductor layer 17 are sequentially grown by the MOCVD method to obtain a semiconductor substrate.
　次に、フォトリソグラフィーとエッチングによりｐ型半導体層１７と活性層１６の一部を除去してａ面ＧａＮ層１４の一部を露出させる。次に、ａ面ＧａＮ層１４とｐ型半導体層１７の露出面に蒸着等により電極材料を形成し、ダイシングして個別チップ化することでＬＥＤを得る。 Next, a part of the p-type semiconductor layer 17 and the active layer 16 is removed by photolithography and etching to expose a part of the a-plane GaN layer 14. Next, an electrode material is formed on the exposed surfaces of the a-plane GaN layer 14 and the p-type semiconductor layer 17 by vapor deposition or the like, and the LEDs are obtained by dicing and forming individual chips.
　活性層１６は、ａ面ＧａＮ層１４上にエピタキシャル成長された、ａ面を主面とする半導体層であり、層内で電子と正孔が発光再結合することでＬＥＤ１００が発光する。活性層１６は、ａ面ＧａＮ層１４とｐ型半導体層１７よりもバンドギャップが小さい材料で構成されており、例えばＩｎＧａＮ、ＡｌＩｎＧａＮなどが挙げられる。活性層１６は意図的に不純物を含まないノンドープとしてもよく、ｎ型不純物を含むｎ型やｐ型不純物を含むｐ型としてもよい。活性層１６は、ａ面を主面とする半導体層なので、厚膜化してもピエゾ電界による電子と正孔の空間的な分離は生じにくく、電流密度を高くしても効率的に電子と正孔が発光再結合できる。 The active layer 16 is a semiconductor layer having the a-plane as a main surface, which is epitaxially grown on the a-plane GaN layer 14, and the LED 100 emits light when electrons and holes are luminescent and recombinated in the layer. The active layer 16 is made of a material having a bandgap smaller than that of the a-plane GaN layer 14 and the p-type semiconductor layer 17, and examples thereof include InGaN and AlInGaN. The active layer 16 may be intentionally non-doped containing impurities, or may be n-type containing n-type impurities or p-type containing p-type impurities. Since the active layer 16 is a semiconductor layer having the a-plane as the main surface, spatial separation of electrons and holes due to the piezo electric field is unlikely to occur even if the film is thickened, and even if the current density is increased, the electrons and holes are efficiently positive. The holes can be luminescent and recombined.
　ｐ型半導体層１７は、活性層１６上にエピタキシャル成長され、ａ面を主面とする半導体層であり、ｐ側電極１９から正孔が注入されて活性層１６に正孔を供給する層である。 The p-type semiconductor layer 17 is a semiconductor layer epitaxially grown on the active layer 16 and having the a-plane as the main surface, and is a layer in which holes are injected from the p-side electrode 19 to supply holes to the active layer 16. ..
　ここではａ面ＧａＮ層１４、ｐ型半導体層１７をそれぞれ単層で説明したが、それぞれ材料や組成の異なる複数の層を含んでいるとしてもよく、例えば、ａ面ＧａＮ層１４とｐ型半導体層１７にクラッド層、コンタクト層、電流拡散層、電子ブロック層、導波路層などを含めてもよい。また、活性層１６も単層で説明したが、多重量子井戸構造（ＭＱＷ：Ｍｕｌｔｉ　Ｑｕａｎｔｕｍ　Ｗｅｌｌ）などの複数層で構成してもよい。 Here, the a-plane GaN layer 14 and the p-type semiconductor layer 17 have been described as single layers, but they may include a plurality of layers having different materials and compositions, for example, the a-plane GaN layer 14 and the p-type semiconductor. The layer 17 may include a clad layer, a contact layer, a current diffusion layer, an electron block layer, a waveguide layer, and the like. Further, although the active layer 16 has been described as a single layer, it may be composed of a plurality of layers such as a multiple quantum well structure (MQW: Multi Quantum Well).
　本実施の形態でも、凸形状部１２はｒ面サファイア基板１１のｒ軸とｒ面サファイア基板１１のｃ軸をｒ面に投影したｃ’方向とに垂直なａ軸方向に沿って形成されている。したがって、第１実施形態で述べたように積層欠陥を抑制して高品質なａ面ＧａＮ層１４が得られ、欠陥密度が低減されたａ面ＧａＮ層１４上に成長された活性層１６、ｐ型半導体層１７も結晶性と表面平坦性が良好となる。これにより、活性層１６、ｐ型半導体層１７の特性も良好になり、ＬＥＤの外部量子効率の向上などが見込まれる。なお、本実施形態は、機能層として、活性層１６を備えた例である。ここで、機能層とは、半導体素子において所定の電気的、化学的な機能を発揮するための層である。 Also in the present embodiment, the convex portion 12 is formed along the a-axis direction perpendicular to the r-axis of the r-plane sapphire substrate 11 and the c-axis of the r-plane sapphire substrate 11 projected onto the r-plane. There is. Therefore, as described in the first embodiment, the active layer 16 and p are grown on the a-plane GaN layer 14 in which the stacking defects are suppressed to obtain a high-quality a-plane GaN layer 14 and the defect density is reduced. The type semiconductor layer 17 also has good crystallinity and surface flatness. As a result, the characteristics of the active layer 16 and the p-type semiconductor layer 17 are also improved, and it is expected that the external quantum efficiency of the LED will be improved. In addition, this embodiment is an example which provided the active layer 16 as a functional layer. Here, the functional layer is a layer for exerting a predetermined electrical and chemical function in the semiconductor element.
　本発明の半導体装置であるＬＥＤは、上述したようにピエゾ電界によるドループが少なく、且つａ面内での異方性が小さく良好な結晶品質であることから高輝度化を実現できるので、車両用灯具などの灯具に用いることでチップ数の低減や高出力化を図ることが可能となる。また、半導体装置はＬＥＤに限定されず、半導体レーザであってもよく、二次元電子ガスを発生させる機能層を有する高電子移動度トランジスタ（ＨＥＭＴ：Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）等の他の用途であってもよい。 As described above, the LED, which is the semiconductor device of the present invention, has less droop due to the piezo electric field, has less anisotropy in the a-plane, and has good crystal quality, so that high brightness can be realized, and thus for vehicles. By using it for lighting equipment such as lighting equipment, it is possible to reduce the number of chips and increase the output. Further, the semiconductor device is not limited to the LED, and may be a semiconductor laser, and is used for other purposes such as a high electron mobility transistor (HEMT) having a functional layer for generating two-dimensional electron gas. You may.
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.
　なお、本願は、２０１９年６月２０日付で出願された日本国特許出願（特願２０１９－１１４５７６）に基づいており、その全体が引用により援用される。また、ここに引用されるすべての参照は全体として取り込まれる。 This application is based on a Japanese patent application (Japanese Patent Application No. 2019-114576) filed on June 20, 2019, and the entire application is incorporated by citation. Also, all references cited here are taken in as a whole.
１００…ＬＥＤ
１０…半導体成長用基板
１１…ｒ面サファイア基板
１２…凸形状部
１２ａ…側壁面部
１２ｂ…曲面部
１２ｃ…頂部
１３…凹部
１４…ａ面ＧａＮ層
１５…バッファ層
１６…活性層
１７…ｐ型半導体層
１８…ｎ側電極
１９…ｐ側電極 100 ... LED
10 ... Semiconductor growth substrate 11 ... r-plane sapphire substrate 12 ... Convex shape portion 12a ... Side wall surface portion 12b ... Curved surface portion 12c ... Top 13 ... Recession 14 ... a-plane GaN layer 15 ... Buffer layer 16 ... Active layer 17 ... P-type semiconductor Layer 18 ... n-side electrode 19 ... p-side electrode

Claims (7)

  1. 　サファイアのｒ面を主面とし、前記主面にナノサイズの凸形状部が複数形成されており、
    　前記凸形状部は前記サファイアのｒ軸と前記サファイアのｃ軸を前記ｒ面に投影したｃ’方向とに垂直なａ軸方向に沿って形成されている、半導体成長用基板。     The r-plane of sapphire is the main surface, and a plurality of nano-sized convex portions are formed on the main surface.
    The convex-shaped portion is a semiconductor growth substrate formed along the a-axis direction perpendicular to the c'direction in which the r-axis of the sapphire and the c-axis of the sapphire are projected onto the r-plane.
  2. 　請求項１に記載の半導体成長用基板であって、
    　前記凸形状部の間隔が２００ｎｍ以上５００ｎｍ以下の範囲である、半導体成長用基板。     The semiconductor growth substrate according to claim 1.
    A semiconductor growth substrate in which the distance between the convex portions is in the range of 200 nm or more and 500 nm or less.
  3. 　請求項１または２に記載の半導体成長用基板であって、
    　前記凸形状部は、前記主面から立ち上がって形成された側壁面部と、前記側壁面部より上方に形成された曲面部とを有する、半導体成長用基板。     The semiconductor growth substrate according to claim 1 or 2.
    The convex-shaped portion is a semiconductor growth substrate having a side wall surface portion formed by rising from the main surface and a curved surface portion formed above the side wall surface portion.
  4. 　請求項３に記載の半導体成長用基板であって、
    　前記曲面部は、前記凸形状部の幅とは異なる大きさの直径に基づく曲率で形成されており、
    　前記凸形状部の頂部には２つの前記曲面部が交わる稜線部が形成されている、半導体成長用基板。     The semiconductor growth substrate according to claim 3.
    The curved surface portion is formed with a curvature based on a diameter having a size different from the width of the convex shape portion.
    A semiconductor growth substrate in which a ridgeline portion where two curved surface portions intersect is formed on the top of the convex shape portion.
  5. 　請求項１から４の何れか一つに記載の半導体成長用基板と、
    　前記半導体成長用基板の上に設けられた機能層と、を備える半導体素子。     The semiconductor growth substrate according to any one of claims 1 to 4.
    A semiconductor device including a functional layer provided on the semiconductor growth substrate.
  6. 　請求項１から４の何れか一つに記載の半導体成長用基板と、
    　前記半導体成長用基板の上に設けられた活性層と、を備える半導体発光素子。     The semiconductor growth substrate according to any one of claims 1 to 4.
    A semiconductor light emitting device including an active layer provided on the semiconductor growth substrate.
  7. 　ｒ面を主面とするサファイアの上に、前記サファイアのｒ軸と前記サファイアのｃ軸を前記ｒ面に投影したｃ’方向とに垂直なａ軸方向に沿って凸形状部を複数形成する工程と、
    　前記主面の上に窒化物半導体層を成長させる工程と、を備える半導体素子製造方法。     On the sapphire whose main surface is the r-plane, a plurality of convex portions are formed along the a-axis direction perpendicular to the c'direction in which the r-axis of the sapphire and the c-axis of the sapphire are projected onto the r-plane. Process and
    A semiconductor device manufacturing method comprising a step of growing a nitride semiconductor layer on the main surface.
PCT/JP2020/023827 2019-06-20 2020-06-17 Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element WO2020256028A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019114576A JP7284648B2 (en) 2019-06-20 2019-06-20 Semiconductor growth substrate, semiconductor device, semiconductor light-emitting device, and semiconductor device manufacturing method
JP2019-114576 2019-06-20

Publications (1)

Publication Number Publication Date
WO2020256028A1 true WO2020256028A1 (en) 2020-12-24

Family

ID=73994824

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/023827 WO2020256028A1 (en) 2019-06-20 2020-06-17 Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element

Country Status (2)

Country Link
JP (1) JP7284648B2 (en)
WO (1) WO2020256028A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010023846A1 (en) * 2008-08-25 2010-03-04 国立大学法人山口大学 Semiconductor substrate and method for manufacturing the same
JP2016111354A (en) * 2014-11-26 2016-06-20 旭化成イーマテリアルズ株式会社 Semiconductor template substrate for led, and led element using the same
WO2019235459A1 (en) * 2018-06-05 2019-12-12 株式会社小糸製作所 Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010023846A1 (en) * 2008-08-25 2010-03-04 国立大学法人山口大学 Semiconductor substrate and method for manufacturing the same
JP2016111354A (en) * 2014-11-26 2016-06-20 旭化成イーマテリアルズ株式会社 Semiconductor template substrate for led, and led element using the same
WO2019235459A1 (en) * 2018-06-05 2019-12-12 株式会社小糸製作所 Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element

Also Published As

Publication number Publication date
JP2021001089A (en) 2021-01-07
JP7284648B2 (en) 2023-05-31

Similar Documents

Publication Publication Date Title
JP4903189B2 (en) Method of growing semipolar nitride single crystal thin film and method of manufacturing nitride semiconductor light emitting device using the same
JP2001181096A (en) Method for producing iii group nitride compound semiconductor and iii group nitride compound semiconductor element
WO2003072856A1 (en) Process for producing group iii nitride compound semiconductor
US8759837B2 (en) Nitride semiconductor substrate
JP5861947B2 (en) Semiconductor light emitting device and manufacturing method thereof
TW201411699A (en) Epitaxial wafer, method of producing the same, and ultraviolet light emitting device
JP2008118049A (en) GaN-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE
JP2010272593A (en) Nitride semiconductor light emitting element and manufacturing method of the same
JP2009141085A (en) Nitride semiconductor device
JP7053209B2 (en) Manufacturing method of semiconductor growth substrate, semiconductor element, semiconductor light emitting element and semiconductor growth substrate
WO2020256028A1 (en) Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element
JP7305428B2 (en) Semiconductor growth substrate, semiconductor device, semiconductor light-emitting device, and semiconductor device manufacturing method
JP4255168B2 (en) Nitride semiconductor manufacturing method and light emitting device
JP2008118048A (en) GaN-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE
WO2019235459A1 (en) Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element and method for producing semiconductor element
JP7350477B2 (en) Method for manufacturing semiconductor growth substrate, semiconductor element, semiconductor light emitting device, and semiconductor growth substrate
JP2009059740A (en) Group iii nitride semiconductor element and manufacturing method thereof
JP4924498B2 (en) Nitride-based semiconductor light-emitting device, epitaxial wafer, and method for manufacturing nitride-based semiconductor light-emitting device
JP3642001B2 (en) Nitride semiconductor element, method for producing nitride semiconductor crystal, and nitride semiconductor substrate
WO2020250849A1 (en) Semiconductor growth substrate, semiconductor element, semiconductor light-emitting element, and method for manufacturing semiconductor growth substrate
WO2020075849A1 (en) Substrate for semiconductor growth, semiconductor element, semiconductor light-emitting element, and method for producing semiconductor element
WO2019039240A1 (en) Substrate for semiconductor growth, semiconductor element, semiconductor light emitting element, and method for producing semiconductor element
JP2008227103A (en) GaN-BASED SEMICONDUCTOR LIGHT EMITTING ELEMENT
JP2007324421A (en) Nitride semiconductor element
JP7430316B2 (en) Semiconductor growth substrate, semiconductor element, semiconductor light emitting element, and semiconductor element manufacturing method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20826162

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20826162

Country of ref document: EP

Kind code of ref document: A1