JP2021001089A - Substrate for semiconductor growth, semiconductor element, semiconductor light-emitting element, and manufacturing method of semiconductor element - Google Patents

Abstract

To provide a substrate (10) for semiconductor growth capable of growing a high-quality a-plane GaN layer by suppressing laminate defects, a semiconductor element, a semiconductor light-emitting element, and a manufacturing method of a semiconductor element.SOLUTION: A substrate (10) for semiconductor growth has a plurality of nano-sized convex shapes (12) formed on the principal plane which is the r-surface of sapphire. The convex shapes (12) are formed along the a-axis direction perpendicular to the r-axis and the c-axis of the sapphire.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting device, and a semiconductor element manufacturing method, and more particularly to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting device, and a semiconductor element manufacturing method for growing an a-plane GaN crystal layer.

In recent years, as an LED that emits purple to blue light used for lighting applications, an LED that forms an active layer with a GaN-based material having a non-polar or semi-polar plane orientation as a main surface has been proposed. In the GaN-based semiconductor layer, the a-plane and the m-plane are non-polar planes, and the r-plane is a typical example of the semi-polar plane. In a GaN-based semiconductor layer using a non-polar surface or a semi-polar surface, the influence of the piezoelectric field in the stacking direction can be reduced and the droop characteristics can be improved.

In Patent Document 1, a nano-sized convex shape is formed on the main surface of the r-plane sapphire substrate, and the a-plane GaN layer is grown via the buffer layer to dislocate in the laterally growing a-plane GaN layer. Has been proposed to reduce dislocations and defects that continue to the surface of the semiconductor layer.

Japanese Unexamined Patent Publication No. 2019-040898

However, in the a-plane GaN layer formed on the r-plane sapphire substrate, since the ± c-axis direction and the m-axis direction exist in the growth plane, abnormal growth is likely to occur due to in-plane anisotropy, and the a-plane GaN layer There was also a limit to the reduction of defect density. The types of defects that occur in the GaN layer include stacking defects (BSF:) that occur in the regularity of stacking of atomic planes, in addition to through dislocations (TD: Threating Dislocation) that occur due to lattice mismatch between the sapphire substrate and GaN. Bassal plane Stacking Falt) is known.

In particular, stacking defects (BSF) are known to be crystal defects that occur prominently in the a-plane GaN layer having a nitrogen-polar (000-1) plane in the crystal plane, and are known to occur in the lateral growth of the GaN layer. It was difficult to reduce stacking defects (BSF) even if the through-through dislocations (TD) were reduced.

Therefore, the present invention has been made in view of the above-mentioned conventional problems, and is a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor growth substrate capable of suppressing stacking defects and growing a high-quality a-plane GaN layer. An object of the present invention is to provide a method for manufacturing a semiconductor device.

In order to solve the above problems, the semiconductor growth substrate 10 of the present invention has the r-plane of sapphire as the main surface, and a plurality of nano-sized convex shapes are formed on the main surface, and the convex shape is that of the sapphire. It is characterized in that it is formed along the a-axis direction perpendicular to the r-axis and the c-axis.

As a result, the convex shape 12 is formed along the a-axis direction perpendicular to the r-axis and the c-axis of the r-plane sapphire substrate 11, so that the -c-plane generated between the convex shapes 12 is formed along the convex shape 12. It is possible to obtain a high-quality a-plane GaN layer 14 by suppressing stacking defects.

It is possible to suppress stacking defects and grow a high-quality a-plane GaN layer.

Further, in one aspect of the present invention, the convex spacing S is in the range of 200 nm or more and 500 nm or less.

Further, in one aspect of the present invention, the convex shape has a side wall surface portion formed by rising from the main surface and a curved surface portion formed above the side wall surface.

Further, in one aspect of the present invention, the curved surface portion is formed with a curvature having a diameter different from the width D of the convex shape, and a ridge line portion where the two curved surface portions intersect is formed at the top of the convex shape. ing.

Further, in order to solve the above problems, the semiconductor device of the present invention is characterized in that the semiconductor growth substrate according to any one of the above is used and a functional layer is provided on the semiconductor growth substrate.

Further, in order to solve the above problems, the semiconductor light emitting device of the present invention is characterized in that the semiconductor growth substrate according to any one of the above is used and an active layer is provided on the semiconductor growth substrate.

Further, in order to solve the above problems, the semiconductor device manufacturing method of the present invention forms a plurality of convex shapes on a sapphire whose main surface is the r-plane along the a-axis direction perpendicular to the r-axis and c-axis of the sapphire. It is characterized by including a step of growing a nitride semiconductor layer on the main surface.

INDUSTRIAL APPLICABILITY The present invention can provide a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method capable of suppressing stacking defects and growing a high-quality a-plane GaN layer.

It is a schematic perspective view which shows the semiconductor growth substrate 10 in 1st Embodiment. FIG. 2 (a) is a schematic cross-sectional view showing a state in which the a-plane GaN layer 14 is grown on the semiconductor growth substrate 10, FIG. 2 (a) shows an example in which the a-plane GaN layer 14 is directly grown, and FIG. Shows an example in which the buffer layer 15 is formed. FIG. 3A is an SEM image showing island-shaped crystals in the early stage of growth of the a-plane GaN layer 14, and FIG. 3B is a TEM showing a flattened surface state of the a-plane GaN layer 14 after growth. It is a statue. FIG. 4A is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex shape 12 and the concave portion 13 formed along the a-axis. FIG. 4A is a schematic plan view, and FIG. b) is a schematic cross-sectional view. FIG. 5A is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex shape 12 and the concave portion 13 formed along the c'direction. FIG. 5A is a schematic plan view, and FIG. (B) is a schematic cross-sectional view. It is a partially enlarged cross-sectional view schematically showing the structure of the convex shape 12 in the 2nd Embodiment, FIG. 6A shows an example of a semicircular cross section at the top, and FIG. 6B shows a ridgeline portion at the top. An example of the formation is shown. It is a schematic cross-sectional view which shows LED which is the semiconductor device of 3rd Embodiment.

(First Embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. FIG. 1 is a schematic perspective view showing a semiconductor growth substrate 10 according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor growth substrate 10 has a plurality of convex shapes 12 formed on the r-plane sapphire substrate 11.

The r-plane sapphire substrate 11 is a substrate composed of a single crystal of sapphire, and has a hexagonal r-plane as a main surface. Here, the just substrate having an inclination angle of 0 degrees is shown as the r-plane sapphire substrate 11, but an off-board substrate in which the r-plane is inclined by several degrees in a predetermined plane direction may be used.

The convex shape 12 is a convex portion formed on the main surface of the r-plane sapphire substrate 11, and is formed along the a-axis perpendicular to both the r-axis and the c-axis of the sapphire. As shown by the arrows in FIG. 1, the upper direction in the figure is the r-axis, the right direction in the figure is the c'direction in which the c-axis is projected onto the r-plane, and the depth direction is perpendicular to the r-axis and the c'direction. A axis. As will be described later, recesses 13 are formed between the convex shapes 12, and the r-plane, which is the main surface of the r-plane sapphire substrate 11, is exposed from the recesses 13. Here, an example in which the convex shape 12 is along the a-axis is shown, but it may extend obliquely with respect to the a-axis direction by an angle of less than 45 degrees from the a-axis.

FIG. 2 is a schematic cross-sectional view showing a state in which the a-plane GaN layer 14 is grown on the semiconductor growth substrate 10, and FIG. 2 (a) shows an example in which the a-plane GaN layer 14 is directly grown. 2 (b) shows an example in which the buffer layer 15 is formed.

As shown in FIG. 2A, the semiconductor growth substrate 10 has an a-plane GaN layer having the a-plane as the main surface from the main surface exposed by the recesses 13 between the convex portions 12 on the r-plane sapphire substrate 11. Grow 14 As shown in FIG. 2B, a buffer layer 15 for alleviating lattice mismatch may be formed between the r-plane sapphire substrate 11 and the a-plane GaN layer 14.

The a-plane GaN layer 14 is a base layer grown so that the main surface is the a-plane, and is a layer for epitaxially growing a nitride semiconductor layer on the base layer. As a method for forming the a-plane GaN layer 14, a known method such as a MOCVD method or an HVPE method (Hydride Vapor Phase Epitaxy) can be used, but it is preferable to use the MOCVD method. The film thickness of the a-plane GaN layer 14 is not particularly limited, but it is preferably formed at 1 μm or more.

The buffer layer 15 is a layer formed to alleviate the lattice mismatch between the r-plane sapphire substrate 11 and the nitride semiconductor layer 14. Examples of the material constituting the buffer layer 15 include AlN, GaN, InGaN, AlGaN, and the like, but it is preferable to use AlN. Further, as a method for forming the buffer layer 15, a sputtering method, a metalorganic vapor phase growth method (MOCVD method: Metalorganic Chemical Vapor Deposition), or the like can be used, and it is preferable to use the sputtering method. The thickness of the buffer layer 15 is preferably in the range of 5 to 300 nm, more preferably in the range of 5 to 90 nm, and even more preferably in the range of 5 to 30 nm because the crystal quality of the nitride semiconductor layer 14 deteriorates if it is made too thick.

(Production method)
Next, a method of manufacturing the semiconductor growth substrate 10 in the present embodiment will be described. As a method for forming the nano-sized convex shape 12 on the surface of the r-plane sapphire substrate 11, known nanoimprint and patterning can be used. As an example, a resist film is applied onto the r-plane sapphire substrate 11, and a mold in which a pattern corresponding to the convex shape 12 is formed is used, and the pattern is transferred to the resist film using nanoimprint technology. Next, the resist film to which the nanopattern is transferred and the r-plane sapphire substrate 11 are anisotropically etched with a chlorine-based gas to form a nano-sized convex shape 12 on the r-plane sapphire substrate 11. To.

Next, a buffer layer 15 having a film thickness of, for example, about 30 nm is formed on the r-plane sapphire substrate 11 on which a plurality of nano-sized convex shapes 12 are formed by a sputtering method or the like. As a sputtering method for forming the buffer layer 15, it is more preferable to use Ar gas with AlN as a target material. The AlN to be the target material may be a single crystal substrate or a powder-fired body, and its state and form are not limited.

Next, after cleaning the surface of the buffer layer 15, hydrogen and nitrogen are used as carrier gases, ammonia (NH ₃ ) is used as a group V raw material, and TMG (Trimethylgallium) is used as a group III raw material by the MOCVD method. The surface GaN layer 14 is grown. As an example of the growth conditions, a two-step growth sequence is used in which the temperature is raised to 1010 ° C., the growth temperature is kept constant, and the reactor pressure, V / III ratio, and growth time are changed. For example, first maintain the V / III ratio at about 4000-5000 and the pressure at 900-1000 hPa for about 10 to 20 minutes, then maintain the V / III ratio at about 100-200 and the pressure at 100-150 hPa for 90-120 minutes. To do. By growing the a-plane GaN layer 14 and then cooling it to room temperature and taking it out, a plurality of nano-sized convex shapes 12 are formed on the main surface of the r-plane sapphire substrate 11, and the buffer layer 15 and the a-plane GaN layer 14 are formed. The semiconductor growth substrate 10 of the present embodiment can be obtained.

When the a-plane GaN layer 14 grows, the penetrating dislocations generated in the recesses 13 between the convex shapes 12 are aggregated by the lateral growth and are aggregated near the vertices of the convex shape 12. Therefore, the density of through dislocations (TD) extending to the outermost surface of the a-plane GaN layer 14 becomes small. As a result, the semiconductor growth substrate 10 of the present embodiment can grow a high-quality a-plane GaN layer having good crystallinity and excellent surface flatness.

Next, the stacking defects (BSF) generated in the a-plane GaN layer 14 and the method for reducing them will be described with reference to FIGS. 3 and 4. FIG. 3 is a TEM image showing the crystal growth of the a-plane GaN layer 14, FIG. 3 (a) shows island-shaped crystals in the early stage of growth, and FIG. 3 (b) shows the a-plane GaN layer 14 after growth flat. It shows a crystallized surface condition.

As shown in FIG. 3A, when the a-plane GaN layer 14 is crystal-grown on the main surface of the r-plane sapphire substrate 11, a plurality of island-shaped crystals as growth nuclei are generated on the main surface in the initial stage of growth. .. The island-shaped crystal is a single crystal made of GaN, and it is known that the crystal size increases with the (000-1) plane, the (1-100) plane, and the (1-101) plane as facets. When the crystal growth of the a-plane GaN layer 14 is continued, a plurality of island-shaped crystals are bonded to obtain a large-sized single crystal.

However, in the crystal growth of GaN, it is known that the rate of crystal growth differs for each facet such as the (000-1) plane, the (1-100) plane, and the (1-101) plane, and further -c. The (000-1) plane, which is a plane, has a nitrogen polarity. As a result, when the facet growth on the -c plane and the facet growth on the (1-101) plane are combined, a stacking defect (BSF) as shown in FIG. 3 (b) is contained in the a-plane GaN layer 14. ) Will occur innumerably.

FIG. 4 is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex shape 12 and the concave portion 13 formed along the a-axis, and FIG. 4A is a schematic plan view. , FIG. 4B is a schematic cross-sectional view. FIG. 5 is a diagram schematically showing the state of the initial stage of growth of the a-plane GaN layer 14 from the convex shape 12 and the concave portion 13 formed along the c'direction, and FIG. 5 (a) is a schematic plan view. Yes, FIG. 5B is a schematic cross-sectional view. The arrow shown in the figure indicates the position of the -c plane of the island-shaped crystal, which is a growth nucleus generated on the main plane in the initial stage of growth of the a-plane GaN layer 14.

As shown in FIGS. 4A and 4B, when the convex shape 12 is formed along the a-axis, the -c planes of the plurality of island-shaped crystals are oriented along the a-axis, so that the-c plane in the recess 13 is-. The c-plane is gathered in a straight line along the convex shape 12, and crystal growth proceeds. This makes it possible to reduce stacking defects (BSF) caused by the -c plane in the a-plane GaN layer 14.

On the other hand, as shown in FIGS. 5A and 5B, when the convex shape 12 is grown along the c'direction, when a plurality of island-shaped crystals are generated, each island-shaped crystal has a -c plane. Is generated, and crystal growth proceeds in a state where the recess 13 has a plurality of -c planes. As a result, the a-plane GaN layer 14 is formed with a large number of stacking defects (BSF) due to the -c-plane remaining.

As described above, in the semiconductor growth substrate 10 of the present embodiment, the convex shape 12 is formed along the a-axis direction perpendicular to the r-axis and the c-axis of the r-plane sapphire substrate 11 to suppress stacking defects. Therefore, a high-quality a-plane GaN layer 14 can be obtained.

(Second Embodiment)
Next, the second embodiment of the present invention will be described with reference to FIG. 6A and 6B are partially enlarged cross-sectional views schematically showing the structure of the convex shape 12 in the present embodiment, FIG. 6A shows an example in which the top cross section has a semicircular shape, and FIG. 6B shows the top. An example in which a ridgeline portion is formed is shown. In the example shown in FIG. 6A, the side wall surface portion 12a is formed so as to rise from the main surface of the r-plane sapphire substrate 11, and the curved surface portion 12b is formed above the side wall surface portion 12a. The side wall surface portion 12a is preferably formed perpendicular to the main surface, but may be formed as a surface inclined with respect to the main surface. Further, the curved surface portion 12b is a curved surface having a semicircular cross section, and the width and diameter of the side wall surface portion 12a are formed with a curvature of about the same. The uppermost portion of the curved surface portion 12b is the top portion 12c of the convex shape 12.

Also in the example shown in FIG. 6B, the side wall surface portion 12a is formed so as to rise from the main surface of the r-plane sapphire substrate 11, and the curved surface portion 12b is formed above the side wall surface portion 12a. The curved surface portion 12b is a curved surface formed with a curvature having a diameter different from that of the convex width D, and the top portion 12c of the convex shape 12 is formed by the intersection of the two curved surface portions 12b to form a ridgeline portion along the c-axis. ..

Since the side wall surface portion 12a is substantially perpendicular to the main surface of the r-plane sapphire substrate 11, crystals do not grow from the surface of the side wall surface portion 12a when the a-plane GaN layer 14 is crystal-grown. Further, since the curved surface portion 12b is formed above the side wall surface portion 12a and the curved surface portion 12b is formed with a predetermined curvature, a specific crystal plane orientation in the sapphire is not exposed. As a result, the a-plane GaN layer 14 is less likely to undergo crystal growth from the surface of the curved surface portion 12b. Therefore, the a-plane GaN layer 14 crystal grows from the main plane in the recess 13. In particular, in the example in which the ridgeline portion is formed on the top portion 12c of the convex shape 12 shown in FIG. 6B, the r-plane of the sapphire is not exposed even around the top portion 12c, and the a-plane GaN layer 14 from the top portion 12c Crystal growth can be effectively suppressed.

If the interval S of the convex shapes 12 is too narrow, the supply of raw materials is hindered during crystal growth of the a-plane GaN layer 14, and it becomes difficult to perform good crystal growth. If it is too wide, the area of the main surface where crystal growth starts. Therefore, there are many areas where through-translocations and defects occur. Therefore, the interval S is preferably in the range of 200 nm or more and 500 nm or less, and more preferably in the range of 300 nm or more and 400 nm or less.

If the height H of the convex shape 12 is too low, as shown in FIG. 12, it does not reach the side wall surface portion 12a even in lateral growth and defects cannot be reduced. If it is too high, the raw material is supplied during crystal growth of the a-plane GaN layer 14. Is inhibited and it becomes difficult to carry out good crystal growth. Therefore, the height H is preferably in the range of 500 nm or more and 1200 nm or less, and more preferably in the range of 700 nm or more and less than 1000 nm.

If the width D of the convex shape 12 is too large, it is not preferable because the a-plane GaN layer 14 needs to be thick enough to fill the entire convex shape 12 and grow in the lateral direction, and above the convex shape 12 that is too small. The lateral growth of the a-plane GaN layer 14 is not continued, and the reduction of defects is insufficient, which is not preferable. Therefore, the width D is preferably in the range of 300 nm or more and 1200 nm or less, and more preferably in the range of 500 nm or more and less than 1000 nm.

The aspect ratio H / D of the convex shape 12 needs to be 1 or more in order for the a-plane GaN layer 14 to reach the side wall surface portion 12a due to the lateral growth of the a-plane GaN layer 14, but if it is too large, the a-plane GaN layer 14 When the crystal grows, the supply of raw materials is hindered and it becomes difficult to perform good crystal growth. Therefore, the aspect ratio H / D is preferably in the range of 1 or more and 4 or less, and more preferably in the range of 1 or more and 2 or less.

Even in the semiconductor growth substrate 10 of the present embodiment, since the convex shape 12 is formed along the a-axis direction perpendicular to the r-axis and c-axis of the r-plane sapphire substrate 11, stacking defects are suppressed and high quality is achieved. A-plane GaN layer 14 can be obtained.

(Third Embodiment)
Next, the third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a schematic cross-sectional view showing an LED which is a semiconductor device of this embodiment. As shown in FIG. 7, the LED 100 has an r-plane sapphire substrate 11, a nano-sized convex shape 12, an a-plane GaN layer 14, an active layer 16, a p-type semiconductor layer 17, an n-side electrode 18, and a p-side electrode 19. ing.

Similar to the first embodiment, the r-plane sapphire substrate 11 is prepared, the nano-sized convex shape 12 is formed, and the a-plane GaN layer 14 is epitaxially grown by the MOCVD method. Subsequently, the active layer 16 and the p-type semiconductor layer 17 are sequentially grown by the MOCVD method to obtain a semiconductor substrate.

Next, a part of the p-type semiconductor layer 17 and the active layer 16 is removed by photolithography and etching to expose a part of the a-plane GaN layer 14. Next, an electrode material is formed on the exposed surfaces of the a-plane GaN layer 14 and the p-type semiconductor layer 17 by vapor deposition or the like, and the LEDs are obtained by dicing and forming individual chips.

The active layer 16 is a semiconductor layer epitaxially grown on the a-plane GaN layer 14 and having the a-plane as the main surface, and the LED 100 emits light when electrons and holes are luminescent and recombinated in the layer. The active layer 16 is made of a material having a bandgap smaller than that of the a-plane GaN layer 14 and the p-type semiconductor layer 17, and examples thereof include InGaN and AlInGaN. The active layer 16 may be intentionally non-doped containing impurities, or may be n-type containing n-type impurities or p-type containing p-type impurities. Since the active layer 16 is a semiconductor layer having the a-plane as the main surface, spatial separation of electrons and holes due to the piezo electric field is unlikely to occur even if the film is thickened, and even if the current density is increased, the electrons and holes are efficiently positive. The holes can be luminescent and recombined.

The p-type semiconductor layer 17 is a semiconductor layer epitaxially grown on the active layer 16 and having the a-plane as the main surface, and is a layer in which holes are injected from the p-side electrode 19 to supply holes to the active layer 16. ..

Here, the a-plane GaN layer 14 and the p-type semiconductor layer 17 have been described as single layers, but each may include a plurality of layers having different materials and compositions. For example, the a-plane GaN layer 14 and the p-type semiconductor may be included. The layer 17 may include a clad layer, a contact layer, a current diffusion layer, an electron block layer, a waveguide layer, and the like. Further, although the active layer 16 has been described as a single layer, it may be composed of a plurality of layers such as a multiple quantum well structure (MQW: Multi Quantum Well).

Also in this embodiment, the convex shape 12 is formed along the a-axis direction perpendicular to the r-axis and c-axis of the r-plane sapphire substrate 11. Therefore, as described in the first embodiment, the active layer 16 and p are grown on the a-plane GaN layer 14 in which the stacking defects are suppressed to obtain a high-quality a-plane GaN layer 14 and the defect density is reduced. The type semiconductor layer 17 also has good crystallinity and surface flatness. As a result, the characteristics of the active layer 16 and the p-type semiconductor layer 17 are also improved, and it is expected that the external quantum efficiency of the LED will be improved.

As described above, the LED, which is the semiconductor device of the present invention, has less droop due to the piezo electric field, has less anisotropy in the a-plane, and has good crystal quality, so that high brightness can be realized, and thus for vehicles. By using it for lighting equipment such as lighting equipment, it is possible to reduce the number of chips and increase the output. Further, the semiconductor device is not limited to an LED, and may be a semiconductor laser, and has other uses such as a high electron mobility transistor (HEMT) having a functional layer for generating two-dimensional electron gas. You may.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.

100 ... LED
10 ... Semiconductor growth substrate 11 ... r-plane sapphire substrate 12 ... Convex shape 12a ... Side wall surface 12b ... Curved surface 12c ... Top 13 ... Recess 14 ... a-plane GaN layer 15 ... Buffer layer 16 ... Active layer 17 ... P-type semiconductor layer 18 ... n-side electrode 19 ... p-side electrode

Claims (7)

The r-plane of sapphire is the main surface, and a plurality of nano-sized convex shapes are formed on the main surface.
A semiconductor growth substrate characterized in that the convex shape is formed along the a-axis direction perpendicular to the r-axis and c-axis of the sapphire. The semiconductor growth substrate according to claim 1.
A semiconductor growth substrate, wherein the convex spacing S is in the range of 200 nm or more and 500 nm or less. The semiconductor growth substrate according to claim 1 or 2.
The convex shape is a semiconductor growth substrate having a side wall surface portion formed by rising from the main surface and a curved surface portion formed above the side wall surface. The semiconductor growth substrate according to claim 3.
The curved surface portion is formed with a curvature having a diameter different from that of the convex width D.
A semiconductor growth substrate characterized in that a ridgeline portion where two curved surface portions intersect is formed on the top of the convex shape. Using the semiconductor growth substrate according to any one of claims 1 to 4,
A semiconductor device characterized in that a functional layer is provided on the semiconductor growth substrate. Using the semiconductor growth substrate according to any one of claims 1 to 4,
A semiconductor light emitting device comprising an active layer on the semiconductor growth substrate. A step of forming a plurality of convex shapes along the a-axis direction perpendicular to the r-axis and c-axis of the sapphire on the sapphire whose main surface is the r-plane.
A semiconductor device manufacturing method comprising a step of growing a nitride semiconductor layer on the main surface.