JP2009059740A - Group iii nitride semiconductor element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable, high-performance group III nitride semiconductor element that has extremely few crystal defects and impurities and achieves a high-quality crystal, and also to provide a manufacturing method of the group III nitride semiconductor element. <P>SOLUTION: The group III nitride semiconductor element is composed of: a substrate (GaN substrate 101); and group III nitride semiconductor layers (n-type GaN layer 102, n-type cladding layer 104, and n-type optical confinement layer 106). A multilayer film forming a laser structure is laminated in an upper portion of the structure where a ridge section 140 is provided. The ridge section 140 is formed by a top surface having a (0001) plane, and an inclined surface for connecting a side surface, the top surface, and a side surface. The combination of each orientation of the side and inclined surfaces is either a ä1-100} plane for the side surface and a ä1-101} plane for the inclined surface (a), or a ä11-20} plane for the side surface, and a ä11-22} plane for the inclined surface (b). A light emitting region is formed at least in either one of the inclined surface and side surface of the ridge section 140. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a group III nitride semiconductor device, in particular, a group III nitride semiconductor optical device and a method for manufacturing the same.

  The group III nitride semiconductor material has a sufficiently large forbidden band width and a direct transition type between band transitions. Therefore, application to a short wavelength light emitting element has been actively studied. In particular, since the mid-1990s, the performance of light emitting diodes (LEDs) in the ultraviolet, blue, and green wavelength regions using Group III nitride semiconductors for lighting and various display applications has been drastically improved. The range of application of LEDs using materials has greatly expanded to form a very large market. This material is also important as a light source for next-generation high-density optical discs, and research and development of a semiconductor laser (Laser Diode: LD) having an oscillation wavelength of 405 nm has been vigorously advanced, and commercialization has already started.

  In this group III nitride semiconductor light emitting device, since a laminated structure is generally formed on a hexagonal (0001) polar face, the influence of the internal electric field due to piezo polarization or spontaneous polarization cannot be ignored and the light emission efficiency is lowered. It is a cause. In particular, in a light emitting device in the visible region using InGaN as an active layer, the lattice mismatch strain increases with the increase of the In composition, and the influence of the internal electric field increases. Therefore, the emission efficiency rapidly decreases as the emission wavelength becomes longer. End up.

  Therefore, in order to avoid the influence of this internal electric field, device fabrication on a nonpolar plane such as {1-100} or {11-20} or a semipolar plane such as {1-101} or {11-22} is performed. Has been tried.

For example, Patent Document 1 discloses an LD structure in which nitride semiconductors on a {1-101} or {11-22} semipolar plane are stacked. As shown in FIG. 8, in this structure, a selection mask 12 such as SiO ₂ having an opening 13 is first formed on a substrate 11. Next, the Si-doped GaN layer 14, the In _0.05 Ga _0.95 N guide layer 15, the In _0.2 Ga _0.8 N active layer 16, and the In _0.05 Ga _0.95 N guide layer 17 are formed _thereon. Then, an Mg-doped GaN layer 18 and an insulating film 21 such as SiO ₂ are sequentially formed. Further, an opening 20 is provided in a part of the insulating film 21 to form the p-side electrode layer 19. The selection mask 12 and the insulating film 21 are opened beside the semiconductor layer having a triangular cross section, and the n-side electrode layer 22. Is formed.

  Further, for example, in Patent Document 2, a faceted surface such as a {1-101} plane or a {11-22} plane formed by forming a striped ridge on a GaN layer provided on a substrate and performing regrowth An upward LD structure is disclosed.

JP 2003-198062 A JP 2002-185040 A

  However, in the structure as shown in FIG. 8, since polycrystalline GaN or the like is deposited on the selective mask 12, a {1-101} plane or a {11-22} plane semipolar plane with good flatness. Cannot be obtained, and the crystal defect density is also increased. Further, it has been difficult to produce a high-performance and highly reliable element due to the swell of impurities from the selective mask material.

  Further, according to the examination results of the present inventors, facets such as {1-101} planes and {11-22} planes having good flatness can be obtained even if stripe ridges are simply provided on a GaN template and regrowth is performed. No surface was obtained, and it was found that the inclination angle from the (0001) plane was continuously changed, and an inclined surface having large waviness in the stripe axis direction was obtained. Even if an LD structure is manufactured on such an inclined surface, it is difficult to manufacture a high-performance and highly reliable device having a high crystal defect density.

  As described above, even if the influence of the internal electric field can be reduced, a high-quality crystal cannot be obtained, and the luminous efficiency decreases due to an increase in defect density. It is difficult to obtain.

  An object of the present invention is to provide a high-performance and high-reliability group III nitride semiconductor device and a method for manufacturing the same, realizing a high-quality crystal with very few crystal defects and impurities, which is the above-described problem.

According to the present invention, on the structure formed of the substrate and the group III nitride semiconductor layer and provided with the ridge portion,
A group III nitride semiconductor device in which a multilayer film having a laser structure is laminated,
The ridge portion is formed by a top surface having a (0001) surface, a side surface, and a slope connecting the top surface and the side surface,
The combination of the respective plane orientations of the side surface and the slope is either of the following (a) or (b):
(A) The side is a {1-100} plane, the slope is a {1-101} plane (b) The side is a {11-20} plane, and the slope is a {11-22} plane The slope of the ridge portion And a Group III nitride semiconductor device, wherein a light emitting region is formed on at least one of the side surfaces.

  In the group III nitride semiconductor device of the present invention, the ridge portion is formed by a top surface having a (0001) plane, a side surface, and a slope connecting the top surface and the side surface. (A) the side surface is a {1-100} plane, the slope is a {1-101} plane, or (b) the side surface is a {11-20} plane, and the slope is {11-22. } Is one of the faces. By making the ridge part into such a shape, a semipolar plane slope and a nonpolar side face with good crystallinity are obtained, and by forming a light emitting region on at least one of the slope and side face, it is good A high-performance and highly reliable group III nitride semiconductor device exhibiting excellent luminous efficiency is obtained. Further, the ridge portion is composed of a substrate and a group III nitride semiconductor layer and does not include a selection mask, so that the influence of impurity contamination and the like can be suppressed.

According to the present invention, a step of selectively etching the substrate to form a convex portion including a top surface having a (0001) surface and side surfaces;
By epitaxially growing a group III nitride semiconductor layer on the substrate, a top surface having a (0001) plane, a side surface, and a slope connecting the top surface and the side surface are formed.
Forming a structure having a ridge portion in which the combination of the plane orientations of the side surface and the slope is any of the following (a) or (b):
(A) The side is a {1-100} plane, the slope is a {1-101} plane (b) The side is a {11-20} plane, and the slope is a {11-22} plane Above the structure A step of laminating a multilayer film having a laser structure;
Forming a light emitting region on at least one of the slope and the side surface of the ridge portion;
There is provided a method for manufacturing a group III nitride semiconductor device comprising:

  According to the present invention, a group III nitride semiconductor layer is epitaxially grown on a convex portion formed by selectively etching a substrate and having a (0001) plane top surface and side surfaces. A structure having a shaped ridge portion can be formed. Thereby, a semipolar plane slope and a nonpolar plane side face with good crystallinity are obtained, and a group III nitride exhibiting good luminous efficiency by forming a light emitting region on at least one of the slope face and the side face A semiconductor element is obtained. In addition, when the group III nitride semiconductor layer is epitaxially grown, since no selection mask is required, the influence of impurity contamination from the mask material can be suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the high quality crystal | crystallization with very few crystal defects and impurities is implement | achieved, and a high performance and highly reliable group III nitride semiconductor element and its manufacturing method are provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
The group III nitride semiconductor device in this embodiment will be described with reference to FIG. The group III nitride semiconductor device according to this embodiment includes a substrate (GaN substrate 101) and a group III nitride semiconductor layer (n-type GaN layer 102, n-type cladding layer 104, n-type optical confinement layer 106). A multilayer film having a laser structure is laminated on the upper portion of the structure provided with the ridge portion 140. The ridge portion 140 is formed by a top surface having a (0001) surface, a side surface, and a slope connecting the top surface and the side surface, and the combination of the surface orientations of the side surface and the slope is as follows: The {1-100} plane, the slope is the {1-101} plane, the (b) side face is the {11-20} plane, and the slope is the {11-22} plane.
A light emitting region is formed on at least one of the slope and the side surface of the ridge portion 140.

In this embodiment, an example applied to an LD in which a light emitting region is formed on the slope of the ridge 140 will be described.
On the surface of the (0001) GaN substrate 101, convex portions 150 whose side surfaces are {1-100} planes or {11-20} planes are striped in the <11-20> direction or the <1-100> direction, respectively. Is formed. Here, the {h, k, l, m} plane represents all planes equivalent to the (h, k, l, m) plane.
The convex portion 150 is formed to have a width of 2 μm and a height of 7 μm, for example. A Si-doped n-type GaN layer 102, an n-type cladding layer 104, an n-type optical confinement layer 106 are formed thereon, and a ridge portion 140 is provided. Furthermore, it has a structure in which a multiple quantum well (MQW) layer 108 serving as an active layer, a cap layer (not shown), and a p-type GaN guide layer 110 are stacked.

Here, the substrate is a GaN substrate, but any substrate that can grow a wurtzite group III nitride semiconductor layer may be used. The Si-doped n-type GaN layer 102 can have a Si concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 1 μm, for example. The n-type cladding layer 104 can be a layer composed of Si-doped n-type Al _0.07 Ga _0.93 N having a Si concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 2 μm. The n-type optical confinement layer 106 can be a layer composed of Si-doped n-type GaN having a Si concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 0.1 μm. Further, the multiple quantum well (MQW) layer 108 is composed of, for example, an In _0.2 Ga _0.8 N well layer having a thickness of 3 nm and an undoped In _0.02 Ga _0.08 N barrier layer having a thickness of 10 nm. It can be a two-period multiple quantum well layer. As the cap layer, for example, a layer composed of Mg-doped p-type Al _0.2 Ga _0.8 N can be used, and the p-type GaN guide layer 110 has an Mg concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness. It can be a layer composed of 0.1 μm Mg-doped p-type GaN. The impurity concentration and layer thickness of each layer are all values on the {1-101} plane or {11-22} plane.

  The ridge portion 140 is formed by a top surface having a (0001) plane, a side surface, and a slope connecting the top surface and the side surface, and the combination of the surface orientations of the side surface and the slope is (a) The side surface is the {1-100} plane, the slope is the {1-101} plane, the (b) side surface is the {11-20} plane, or the slope is the {11-22} plane.

When the combination of the surface orientations of the side surface and the slope of the ridge portion 140 is the combination of (a), the ridge portion 140 is formed in a stripe shape in the <11-20> direction.
Further, when the combination of the surface orientations of the side surface and the slope of the ridge portion 140 is the combination of (b), the ridge portion 140 is formed in a stripe shape in the <1-100> direction.

  Further, in the ridge portion 140, the width w in the <0001> direction of the side surface is preferably 5 μm ≦ w ≦ 30 μm. By setting the width w to 5 μm or more, it is possible to obtain a {1-101} plane or a {11-22} plane which is flat at the atomic level and has good crystallinity. The width w is preferably 30 μm or less from the viewpoint of productivity.

  Further, a current confinement layer 112 made of AlN, a p-type cladding layer 114, and a p-type contact layer 116 are laminated on the p-type GaN guide layer 110. A p-type electrode 118 is provided on the upper portion of the laminated structure via an insulating layer 117, and an n-type electrode 119 is provided on the back surface of the GaN substrate 101. Here, the current confinement layer 112 is formed by forming a non-crystalline layer by low-temperature deposition, then providing an opening 120 in the non-crystalline layer on the slope of the ridge by etching, and then forming a layer above the p-type cladding layer 114. The amorphous layer is converted into a crystalline layer by high-temperature heat treatment in the process.

Here, the p-type cladding layer 114 can be a layer composed of, for example, Mg-doped p-type Al _0.07 Ga _0.93 N having an Mg concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 0.5 μm. . The p-type contact layer 116 can be a layer composed of Mg-doped p-type GaN having an Mg concentration of 2 × 10 ²⁰ cm ⁻³ or less and a thickness of 0.02 μm.

  The opening 120 on the slope of the current confinement layer 112 is formed into a stripe-shaped opening by lithography such as light exposure or electron beam exposure, and selective etching using, for example, a phosphoric acid-containing liquid disclosed in JP-A-2003-78215. 120 is formed.

  As described above, the multiple quantum well layer 108 serving as the light emitting layer is formed on the ridge 140, the current confinement layer 112 is formed so as to cover the light emitting layer, and the multiple quantum well in the region corresponding to the opening 120 is formed. The layer 108 becomes a light emitting region.

  Here, as shown in FIG. 6, a plurality of stripe-shaped periodic grooves 170 extending perpendicularly to the extending direction of the ridge 140 can be formed in parallel on the slope of the ridge 140. The periodic grooves are formed by controlling the growth conditions of the group III nitride semiconductor layer. In this way, when the active layer is grown on the ridge 140 where the groove 170 is formed, the active layer 109 in which the multiple quantum well layer 108 is divided into thin lines can be formed. In FIG. 6, only the active layer 109 formed on the slope is shown. Since the individual thin wires are separated from each other by the periodic grooves, the growth of defects is suppressed, and a light emitting layer exhibiting good crystallinity can be obtained. The thin-line active layer 109 can be selectively formed in each periodic groove of the groove portion 170 because the raw material concentration is increased at the bottom of the groove portion 170 due to the diffusion of the raw material.

Next, the manufacturing method of the group III nitride semiconductor device of this embodiment will be described in detail.
2 and 3 are process cross-sectional views illustrating the method for manufacturing the group III nitride semiconductor device of this embodiment. In the method for manufacturing a group III nitride semiconductor device according to the present embodiment, a step of selectively etching the substrate 101 to form a convex portion 150 including a top surface having a (0001) plane and side surfaces, The group III nitride semiconductor layer is formed by epitaxial growth, and is formed by a top surface having a (0001) plane, a side surface, a top surface, and a slope connecting the side surface, and the combination of the respective plane orientations of the side surface and the slope is (A) Ridge portion 140 whose side surface is one of {1-100} plane, slope is {1-101} plane, or (b) side surface is {11-20} plane, and slope is {11-22} plane. Forming a structure having a structure, laminating a multilayer film having a laser structure on the structure, and forming a light emitting region on at least one of the slope and the side surface of the ridge portion. .

  Hereinafter, each process of the group III nitride semiconductor device of this embodiment is explained in full detail.

First, after a SiO ₂ film is formed on the GaN substrate 101 by CVD, a SiO ₂ stripe 160 having a width of about 2 μm is formed in the <11-20> or <1-100> direction in the GaN substrate 101 plane by a lithography process. (FIG. 2A).
Next, using this as a mask, a convex portion 150 of <11-20> direction or <1-100> direction having a height of 7 μm and a width of 2 μm is formed by a dry etching apparatus (FIG. 2B).

Next, the n-type GaN layer 102, the n-type cladding layer 104, and the n-type optical confinement layer 106 are stacked on the GaN substrate 101 by, for example, a metal organic chemical vapor deposition method (hereinafter referred to as MOVPE method).
As a result, the ridge portion 140 formed by the top surface having the (0001) plane, the side surface, and the slope connecting the top surface and the side surface is obtained. In this ridge portion 140, the combinations of the plane orientations of the side surface and the slope are as follows: (a) the {1-100} plane is the side, the {1-101} plane is the slope, or the {11-20} side is the (b) side. The surface and the slope are either {11-22} surfaces.
Further, when the combination of the surface orientations of the side surface and the slope of the ridge portion 140 is the combination of (a), the ridge portion 140 is formed in a stripe shape in the <11-20> direction.
When the combination of the surface orientations of the side surface and the slope of the ridge portion 140 is the combination of (b), the ridge portion 140 is formed in a stripe shape in the <1-100> direction.

  Further, a multiple quantum well layer 108 serving as an active layer, a cap layer (not shown), and a p-type GaN guide layer 110 are sequentially deposited on the ridge portion 140.

After depositing these structures, an amorphous AlN layer (later crystallized to become the current confinement layer 112) is deposited (FIG. 2 (c)).
Next, a stripe-shaped opening 120 is formed in the amorphous AlN layer on the slope. After depositing SiO ₂ to a thickness of 100 nm on the amorphous AlN layer and applying a resist, a stripe pattern having a width of 1.5 μm is formed on a slope having a {1-101} plane or a {11-22} plane by photolithography.
Next, after etching SiO ₂ using buffered hydrofluoric acid as a mask, the resist is removed with an organic solvent and washed with water. The amorphous AlN layer is not etched or damaged in each step of buffered hydrofluoric acid, organic solvent, and water washing.

Next, the amorphous AlN layer is etched using SiO ₂ as a mask. As the etching solution, for example, a solution in which phosphoric acid and sulfuric acid are mixed at a volume ratio of 1: 1 can be used. The amorphous AlN layer in the region not covered with the SiO ₂ mask is removed by, for example, etching for 8.5 minutes in the solution kept at 90 ° C., and the {1-101} plane or the {11-22} plane is used. A stripe-shaped opening 120 can be obtained on a certain slope. Thereafter, SiO ₂ used as a mask is further removed with buffered hydrofluoric acid, and a 1.5 μm-wide stripe-shaped inverted mesa is formed on the amorphous AlN layer on the slope which is the {1-101} plane or the {11-22} plane. A structure having a shape (not shown) opening 120 is obtained (FIG. 3A).

  The p-type cladding layer 114 is buried and regrown with respect to the structure having the stripe-shaped opening 120 on the {1-101} plane or the {11-22} plane which is obtained as described above, and further p-type. A contact layer 116 is stacked. The p-type cladding layer 114 and the p-type contact layer 116 are formed by, for example, the MOVPE method. The amorphous AlN layer is thermally crystallized by the influence of the high temperature heat treatment during the regrowth process of the clad layer to obtain the current confinement layer 112 (FIG. 3B). An insulating layer 117 having an opening corresponding to the opening 120 is formed on the LD wafer obtained by the above processing, and a p-type electrode 118 is formed on the insulating layer 117 by, for example, a vacuum evaporation method. Further, an n-type electrode 119 is formed on the back surface of the GaN substrate 101 by, for example, a vacuum deposition method (FIG. 3C).

Hereinafter, the effect of this embodiment will be described.
In the group III nitride semiconductor device of the present invention, the ridge portion 140 is formed by a top surface having a (0001) plane, a side surface, and a slope connecting the top surface and the side surface. The combinations of the respective plane orientations are: (a) the side is {1-100} plane, the slope is {1-101} plane or (b) the side is {11-20} plane, and the slope is {11-22} plane Either. By making the ridge portion 140 into such a shape, a semipolar plane slope and a nonpolar side face having good crystallinity can be obtained. A multiple quantum well layer 108 serving as a light emitting layer is formed on the inclined surface of the semipolar plane, whereby a highly reliable group III nitride semiconductor device exhibiting good light emission efficiency can be obtained. Further, since a selection mask for growing the group III nitride semiconductor layer is not included, the influence of impurity contamination from the mask material can be suppressed.

  Furthermore, by setting the width w in the <0001> direction of the {1-100} plane or the {11-20} plane in the range of 5 μm ≦ w ≦ 30 μm, for example, the influence of crystal growth on the (0001) plane Since it becomes difficult to receive, {1-101} or {11-22} semipolar plane, {1-100}, {11-20} nonpolar plane flat at the atomic level can be easily obtained, and the device yield is improved. Productivity is improved.

  A plurality of periodic lines extending in a direction perpendicular to the intersection line with the (0001) plane on the {1-101} plane, the {11-22} plane, the {1-100} plane, and the {11-20} plane. By adopting a structure in which the active layer is embedded in the groove, the number of crystal defects formed in the active layer is suppressed, so that the light emission efficiency and reliability can be improved.

(Second embodiment)
The group III nitride semiconductor device according to this embodiment will be described with reference to FIGS.
The group III nitride semiconductor device according to the present embodiment is different from the first embodiment in that the light emitting region is provided on the {1-100} plane or the {11-20} plane that is the side surface of the ridge portion. Is the same as in the first embodiment.
As shown in FIG. 4, convex portions 250 whose side surfaces are {1-100} planes or {11-20} planes on the surface of the (0001) GaN substrate 201 are in the <11-20> direction or <1- It is formed in a stripe shape in the 100> direction. On top of this, an n-type GaN layer 202, an n-type cladding layer 204, an n-type optical confinement layer 206 are formed, and a ridge portion 240 is provided. Furthermore, it has a structure in which a two-period multiple quantum well (MQW) layer 208, a cap layer (not shown), and a p-type guide layer 210 are laminated.

  Here, the ridge portion 240 is formed by a top surface having a (0001) plane, a side surface, and a slope connecting the top surface and the side surface, and a combination of surface orientations of the side surface and the slope is (a ) Side surface is {1-100} plane, slope is {1-101} plane, or (b) side surface is {11-20} plane, slope is {11-22} plane.

When the combination of the surface orientations of the side surface and the slope of the ridge portion 240 is the combination of (a), the ridge portion 240 is formed in a stripe shape in the <11-20> direction.
Further, when the combination of the surface orientations of the side surface and the slope of the ridge portion 240 is the combination of (b), the ridge portion 240 is formed in a stripe shape in the <1-100> direction.

  In the ridge portion 240, the width w in the <0001> direction of the side surface is preferably 5 μm ≦ w ≦ 30 μm. By setting the width w to 5 μm or more, it is possible to obtain a {1-101} plane or a {11-22} plane which is flat at the atomic level and has good crystallinity. The width w is preferably 30 μm or less from the viewpoint of productivity.

  Further, a current confinement layer 212, a p-type cladding layer 214, and a p-type contact layer 216 are stacked on the p-type guide layer 210. An n-type electrode 219 is provided on the back surface of the p-type electrode 218 and the substrate 201 with an insulating layer 217 interposed therebetween at the upper part of the laminated structure. Here, the current confinement layer 212 is formed by forming a non-crystalline layer by low-temperature deposition, then providing an opening 220 in the non-crystalline layer on the side surface of the ridge by etching, and then forming a layer above the p-type cladding layer 214. The amorphous layer is converted into a crystalline layer by high-temperature heat treatment in the process.

  As described above, the multiple quantum well layer 208 serving as the light emitting layer is formed on the ridge portion 240, the current confinement layer 212 is formed so as to cover the light emitting layer, and the multiple quantum well in the region corresponding to the opening 220 is formed. The layer 208 becomes a light emitting region.

  Here, as shown in FIG. 7, a plurality of striped periodic grooves extending perpendicularly to the extending direction of the ridge 240 can be formed in parallel on the side surface of the ridge 240. The periodic grooves are formed by controlling the growth conditions of the group III nitride semiconductor layer. In this way, when the active layer is grown on the ridge 240 where the groove 270 is formed, the active layer 209 in which the multiple quantum well layer 207 is divided into thin lines can be formed. In FIG. 7, only the active layer 209 formed on the slope is shown. Since the individual thin wires are separated from each other by the periodic grooves, the growth of defects is suppressed, and a light emitting layer exhibiting good crystallinity can be obtained. The thin-line active layer 209 can be selectively formed in each periodic groove of the groove portion 270 because the raw material concentration is increased at the bottom of the groove portion 270 due to the diffusion of the raw material.

Next, the processes up to the formation of the p-type guide layer 210 are the same as those described in the first embodiment with reference to FIG.
After forming the p-type guide layer 210, a stripe-shaped opening 220 is formed in the amorphous AlN layer on the side surface of the ridge 140. After depositing 100 nm of SiO ₂ on the amorphous AlN layer and applying a resist, a stripe pattern having a width of 1.5 μm is formed on the side surface of the {1-100} plane or {11-20} plane by photolithography.

Next, for example, after etching SiO ₂ using buffered hydrofluoric acid as a mask, the resist is removed with an organic solvent and washed with water.
Next, the amorphous AlN layer is etched using SiO ₂ as a mask. Thereby, the stripe-shaped opening 220 is obtained on the side surface which is the {1-100} plane or the {11-20} plane. Thereafter, SiO ₂ used as a mask is further removed with buffered hydrofluoric acid, and a 1.5 μm-wide striped reverse mesa is formed on the amorphous AlN layer on the side surface which is the {1-100} plane or the {11-20} plane. A structure having a shape (not shown) opening 220 is obtained (FIG. 5A).

The p-type cladding layer 214 is buried and regrown with respect to the structure having the stripe-shaped opening 220 on the side surface which is the {1-100} plane or {11-20} plane obtained as described above. A contact layer 216 is stacked. The p-type cladding layer 214 and the p-type contact layer 216 are formed by, for example, the MOVPE method. The amorphous AlN layer is thermally crystallized by the influence of the high temperature heat treatment in the regrowth process of the cladding layer, and the current confinement layer 212 is obtained. An insulating layer 217 having an opening corresponding to the opening 220 is formed on the LD wafer obtained by the above processing, and a p-type electrode 218 is formed on the insulating layer 217 by, for example, a vacuum evaporation method. Further, an n-type electrode 219 is formed on the back surface of the GaN substrate 201 by, for example, a vacuum evaporation method.
Also in this embodiment, the same effect as the first embodiment can be obtained.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  For example, in the above embodiment, the light emitting region is formed on the slope or side surface of the ridge 140, but it may be formed on both the slope and side surface. Further, a plurality of light emitting regions may be formed on the slope or side surface.

A group III nitride semiconductor device similar to that of the first embodiment was produced. First, as the GaN substrate 101, an n-type GaN (0001) substrate having an n-type carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ was used. A dry etching apparatus was used to form the convex portion 150 on the surface of the GaN substrate 101, and chlorine (Cl ₂ ) was used as an etching gas. A 400 hPa reduced pressure MOVPE apparatus was used to fabricate the element structure on the substrate. A mixed gas of hydrogen and nitrogen is used as a carrier gas, trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMIn) are used as Ga, Al, and In sources, silane (SiH ₄ ), p Biscyclopentadienyl magnesium (Cp ₂ Mg) was used as the type dopant.

First, a ridge stripe (projection 150) having a height of 7 μm is formed on an n-type GaN substrate 101. Hereinafter, this process is referred to as a “ridge stripe forming process”. After a SiO ₂ film was formed on the GaN substrate 101 by CVD, a SiO ₂ stripe having a width of about 2 μm was formed in the <11-20> direction in the GaN substrate 101 plane by a lithography process (FIG. 2A).
Next, using this as a mask, a convex portion 150 in the <11-20> direction having a height of 7 μm and a width of 2 μm was formed by a dry etching apparatus (FIG. 2B).

  Next, an n-type GaN layer 102, an n-type cladding layer 104, an n-type optical confinement layer 106, a multiple quantum well layer 108, a p-type guide layer 110, and amorphous AlN for current confinement are grown on the GaN substrate 101. . Hereinafter, this process is referred to as an “active layer growth process”.

After the GaN substrate 101 having the convex portions 150 formed thereon was put into a growth apparatus, the substrate was heated while supplying NH ₃ , and growth was started when the growth temperature was reached. Si-doped n-type GaN layer 102 (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 1 μm), Si-doped n-type Al _0.07 Ga _0.93 N (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 2 μm) And an n-type optical confinement layer 106 made of Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 0.1 μm). Thereby, the ridge part 140 formed by the top surface having the (0001) surface, the side surface of the {1-100} surface, and the slope of the {1-101} surface connecting the top surface and the side surface was obtained. .

Further, a two-period multiple quantum well comprising an In _0.2 Ga _0.8 N (thickness 3 nm) well layer and an undoped In _0.02 Ga _0.08 N (thickness 10 nm) barrier layer on the ridge 140. Layer 108, cap layer (not shown) made of Mg-doped p-type Al _0.2 Ga _0.8 N, p made of Mg-doped p-type GaN (Mg concentration 2 × 10 ¹⁹ cm ⁻³ , thickness 0.1 μm). The mold guide layers 110 are sequentially deposited (FIG. 2C).

Here, the substrate temperature is 1080 ° C., the TMG supply amount is 58 μmol / min, the NH ₃ supply amount is 0.36 mol / min, and the AlGaN growth is the substrate temperature 1080 ° C., the TMA supply amount is 49 μmol / min, and the TMG supply amount is 58 μmol / min. The NH ₃ supply rate was 0.36 mol / min. InGaN growth (MQW growth) was performed at a substrate temperature of 800 ° C., a TMG supply rate of 8 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. The TMI supply rate was 48 μmol / min for the well layer and 3 μmol / min for the barrier layer. did.

After depositing these structures, the substrate temperature was lowered to about 400 ° C., and an amorphous AlN layer (which was later crystallized to become the current confinement layer 112) was deposited. The supply amounts of TMA and NH ₃ during deposition of the amorphous AlN layer were 36 μmol / min and 0.36 mol / min, respectively, and the deposited film thickness was 0.1 μm. Here, the impurity concentration and thickness of each of the layers are all values on the slope.

Next, a stripe-shaped opening 120 is formed in the amorphous AlN layer on the slope. Hereinafter, this process is referred to as a “stripe formation process”. After depositing SiO ₂ to a thickness of 100 nm on the amorphous AlN layer and applying a resist, a stripe pattern having a width of 1.5 μm was formed on the slope of the {1-101} plane by photolithography.
Next, SiO ₂ was etched using buffered hydrofluoric acid as a mask, after which the resist was removed with an organic solvent and washed with water. Here, the amorphous AlN layer is not etched or damaged in each step of buffered hydrofluoric acid, organic solvent, and water washing.

Next, the amorphous AlN layer was etched using SiO ₂ as a mask. As the etching solution, a solution in which phosphoric acid and sulfuric acid are mixed at a volume ratio of 1: 1 can be used. The amorphous AlN layer in the region not covered with the SiO ₂ mask is removed by etching for 8.5 minutes in a solution maintained at 90 ° C., and the stripe-shaped opening 120 is formed on the slope that is the {1-101} plane. Got. Thereafter, SiO ₂ used as a mask is further removed with buffered hydrofluoric acid, and a 1.5 μm-wide striped inverted mesa (not shown) opening is formed in the non-crystalline AlN layer having a {1-101} plane. A structure having a portion 120 was obtained (FIG. 3A).

The p-type AlGaN cladding layer is regrowth regrowth with respect to the structure having the stripe-shaped opening on the slope that is the {1-101} plane obtained as described above. Hereinafter, this process is referred to as a “p-type cladding layer regrowth process”. After charging the MOVPE apparatus, the temperature was raised to 1100 ° C., which is the growth temperature, at a NH ₃ supply rate of 0.36 mol / min. After reaching 1100 ° C., a p-type cladding layer 114 made of Mg-doped p-type Al _0.07 Ga _0.93 N (Mg concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 0.5 μm) is deposited, and the substrate temperature Then, the p-type contact layer 116 made of Mg-doped p-type GaN (Mg concentration 1 × 10 ²⁰ cm ⁻³ , thickness 0.02 μm) was deposited. The amorphous AlN layer is thermally crystallized by the influence of the high temperature heat treatment during the regrowth process of the cladding layer, and the current confinement layer 112 is obtained. The deposition conditions of AlGaN and GaN were the same as those in the above-described active layer growth step except for the difference in dopant. A p-type electrode 118 and an n-type electrode 119 were formed on the LD wafer obtained by the above processing by a vacuum deposition method.
After electrode formation, the LD wafer was cleaved in the direction perpendicular to the stripe, and the element length was 500 μm. The uncoated LD chip thus obtained was fused to a heat sink and examined for light emission characteristics. As a result, laser oscillation occurred at a wavelength of 450 nm, a current density of 3.0 kA / cm ² , and a voltage of 4.5 V. The average life at 500 mW output was 10,000 hours or more.

  On the other hand, when the height of the convex portion 150 formed on the GaN substrate 101 is about 3 μm and the width w in the <0001> direction of the {1-100} surface or {11-20} surface of the ridge portion 140 is 2 μm. In this case, a slope having a large undulation in the stripe axis direction appeared with the angle continuously changing from the (0001) plane, and a {1-101} plane having good flatness was not obtained. Further, even if an LD chip was manufactured and current was injected, LD oscillation could not be performed.

It is a perspective view which shows the structure of the group III nitride semiconductor element in embodiment. FIG. 3 is a process cross-sectional view illustrating a method for manufacturing the group III nitride semiconductor device of FIG. 1. FIG. 3 is a process cross-sectional view illustrating a method for manufacturing the group III nitride semiconductor device of FIG. 1. It is a perspective view which shows the structure of the group III nitride semiconductor element in embodiment. It is process sectional drawing which shows the manufacturing method of the group III nitride semiconductor element of FIG. It is a figure which shows the periodic groove part formed in the ridge part of FIG. It is a figure which shows the periodic groove part formed in the ridge part of FIG. It is sectional drawing which shows the structure of the conventional group III nitride semiconductor element.

Explanation of symbols

_DESCRIPTION OF _SYMBOLS 11 Substrate 12 Selection mask 13 Opening 14 Si doped GaN layer 15 In _0.05 Ga _0.95 N guide layer 16 In _0.2 Ga _0.8 N active layer 17 In _0.05 Ga _0.95 N guide layer 18 Mg-doped GaN layer 19 p-side electrode layer 20 opening 21 insulating film 22 n-side electrode layer 101 GaN substrate 102 n-type GaN layer 104 n-type cladding layer 106 n-type optical confinement layer 108 multiple quantum well layer 109 thin linear active layer 110 p-type GaN guide layer 112 current confinement layer 114 p-type cladding layer 116 p-type contact layer 117 insulating layer 118 p-type electrode 119 n-type electrode 120 opening 140 ridge 150 convex portion 160 SiO ₂ stripe 170 groove 201 GaN substrate 202 n N-type GaN layer 204 n-type cladding layer 206 n-type optical confinement layer 208 heavy Well layer 209 thin wires active layer 210 p-type guide layer 212 current confinement layer 214 p-type cladding layer 216 p-type contact layer 217 insulating layer 218 p-type electrode 219 n-type electrode 220 opening 240 ridge 250 protruding portion 270 groove

Claims (12)

Constructed from a substrate and a group III nitride semiconductor layer, on a structure provided with a ridge portion,
A group III nitride semiconductor device in which a multilayer film having a laser structure is laminated,
The ridge portion is formed by a top surface having a (0001) surface, a side surface, and a slope connecting the top surface and the side surface,
The combination of the respective plane orientations of the side surface and the slope is either of the following (a) or (b):
(A) The side is a {1-100} plane, the slope is a {1-101} plane (b) The side is a {11-20} plane, and the slope is a {11-22} plane The slope of the ridge portion And a Group III nitride semiconductor device, wherein a light emitting region is formed on at least one of the side surfaces.   A light emitting layer is formed on the ridge portion, a current confinement layer is formed so as to cover the light emission layer, an opening provided in the current confinement layer is formed, and a region corresponding to the opening is formed. The group III nitride semiconductor device according to claim 1, wherein the light emitting layer is the light emitting region.   3. The group III nitride semiconductor device according to claim 2, wherein a width w of the side surface in the <0001> direction in the ridge portion is 5 μm ≦ w ≦ 30 μm.   A plurality of stripe-like periodic grooves extending in a direction perpendicular to the extending direction of the ridge are provided in parallel on the slope or the side surface of the ridge, and the thin light emitting layer is formed in the groove. The group III nitride semiconductor device according to claim 3, wherein:   The combination of the surface orientations of the side surface and the slope is the combination of (a), and the ridge portion is formed in a stripe shape in the <11-20> direction. 5. The group III nitride semiconductor device according to 4.   The combination of the surface orientations of the side surface and the slope is the combination of (b), and the ridge portion is formed in a stripe shape in the <1-100> direction. 5. The group III nitride semiconductor device according to 4. A step of selectively etching the substrate to form a convex portion including a top surface having a (0001) plane and a side surface;
By epitaxially growing a group III nitride semiconductor layer on the substrate, a top surface having a (0001) plane, a side surface, and a slope connecting the top surface and the side surface are formed.
Forming a structure having a ridge portion in which the combination of the plane orientations of the side surface and the slope is any of the following (a) or (b):
(A) The side is a {1-100} plane, the slope is a {1-101} plane (b) The side is a {11-20} plane, and the slope is a {11-22} plane Above the structure A step of laminating a multilayer film having a laser structure;
Forming a light emitting region on at least one of the slope and the side surface of the ridge portion;
A method for manufacturing a group III nitride semiconductor device comprising: In the step of laminating the multilayer film,
Forming a light emitting layer on the ridge, and forming a current confinement layer so as to cover the light emitting layer;
8. The method for manufacturing a group III nitride semiconductor device according to claim 7, wherein in the step of forming the light emitting region, an opening is provided in the current confinement layer on at least one of the inclined surface and the side surface of the ridge portion. In the step of forming the structure having the ridge portion,
The method for manufacturing a group III nitride semiconductor device according to claim 8, wherein a width w of the side surface in the ridge portion in the <0001> direction is 5 μm ≦ w ≦ 30 μm. In the step of forming the structure having the ridge portion,
A plurality of striped periodic grooves extending in a direction perpendicular to the extending direction of the ridge portion are provided in parallel on the slope or the side surface of the ridge portion,
In the step of laminating the multilayer film,
The method for manufacturing a group III nitride semiconductor device according to claim 9, wherein the light emitting layer having a thin line shape is formed in the groove portion of the ridge portion. In the step of forming the structure having the ridge portion,
The combination of the surface orientations of the side surface and the slope of the ridge portion is the combination of (a), and the ridge portion is formed in a stripe shape in the <11-20> direction. A method for producing a group III nitride semiconductor device of In the step of forming the structure having the ridge portion,
The combination of the surface orientations of the side surface and the inclined surface of the ridge portion is the combination of (b), and the ridge portion is formed in a stripe shape in the <1-100> direction. A method for producing a group III nitride semiconductor device of

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