WO2020252885A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

Info

Publication number
WO2020252885A1
WO2020252885A1 PCT/CN2019/101664 CN2019101664W WO2020252885A1 WO 2020252885 A1 WO2020252885 A1 WO 2020252885A1 CN 2019101664 W CN2019101664 W CN 2019101664W WO 2020252885 A1 WO2020252885 A1 WO 2020252885A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
flat
insulating layer
disposed
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/101664
Other languages
English (en)
French (fr)
Inventor
唐维
卢改平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/615,871 priority Critical patent/US11573471B2/en
Publication of WO2020252885A1 publication Critical patent/WO2020252885A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers

Definitions

  • This application relates to the field of display technology, in particular to an array substrate and a liquid crystal display panel.
  • in-plane digging technology appears in people's field of vision.
  • the current in-plane digging technology still has many problems. For example, the blind holes are prone to strip interference patterns during optical testing.
  • the present application provides a liquid crystal display panel, which can solve the technical problem that the existing liquid crystal display panel easily generates interference patterns at the blind holes.
  • An embodiment of the application provides an array substrate, including:
  • a substrate including a display area and a light-transmitting functional area
  • a buffer layer which is disposed on the substrate and covers the display area and the transparent functional area;
  • a thin film transistor array layer is arranged on the buffer layer, the thin film transistor array layer is provided with openings, and the openings and the light-transmitting functional area are directly opposite to each other;
  • the supporting and filling structure is arranged in the opening.
  • the thin film transistor array layer includes a first metal layer, a semiconductor layer, a second metal layer, a first insulating layer, a second insulating layer, and a first flat layer;
  • the first insulating layer is located on the buffer layer, the first flat layer is disposed on the first insulating layer, and the second insulating layer is disposed on the first flat layer.
  • the supporting and filling structure includes a plurality of supporting pillars evenly spaced in the openings, and the openings are through holes penetrating to the upper surface of the buffer layer.
  • the supporting pillars are formed by sequentially stacking the first insulating layer, the first flat layer, and the second insulating layer remaining after grooving on the thin film transistor array layer.
  • the supporting column is in the shape of a large truncated cone with a small top and a bottom.
  • the openings include a first through hole in the first insulating layer, a second through hole in the second insulating layer, and a third through hole in the flat layer. The radii of the third through hole, the second through hole, and the first through hole are sequentially reduced.
  • the supporting and filling structure is a second flat layer disposed in the opening and located in the light-transmitting functional area of the buffer layer, and the upper surface of the second flat layer The height of is lower than the height of the upper surface of the first flat layer.
  • the first flat layer is connected to the second flat layer, and is formed by a single photomask.
  • the first metal layer is disposed on the buffer layer and located in the display area for forming gate metal
  • the semiconductor layer is disposed on the first insulating layer
  • the second metal layer is disposed on the first flat layer for forming a source and drain metal layer.
  • An embodiment of the present application also provides a liquid crystal display panel, which includes an array substrate, and the array substrate includes:
  • a substrate which includes a display area and a light-transmitting functional area
  • a buffer layer which is disposed on the substrate and covers the display area and the transparent functional area;
  • a thin film transistor array layer is arranged on the buffer layer, the thin film transistor array layer is provided with openings, and the openings and the light-transmitting functional area are directly opposite to each other;
  • the supporting and filling structure is arranged in the opening.
  • the thin film transistor array layer includes a first metal layer, a semiconductor layer, a second metal layer, a first insulating layer, a second insulating layer, and a first flat layer;
  • the first insulating layer is located on the buffer layer, the first flat layer is disposed on the first insulating layer, and the second insulating layer is disposed on the first flat layer.
  • the supporting and filling structure includes a plurality of supporting pillars evenly spaced and distributed in the openings, and the openings are through holes penetrating to the upper surface of the buffer layer.
  • the supporting pillars are formed by sequentially stacking the first insulating layer, the first flat layer, and the second insulating layer remaining after the thin film transistor array layer is slotted.
  • the supporting column is in the shape of a large circular truncated cone with a small top and a bottom.
  • the opening includes a first through hole located in the first insulating layer, a second through hole located in the second insulating layer, and a third through hole located in the flat layer. Through holes, the radii of the third through holes, the second through holes, and the first through holes are sequentially reduced.
  • the supporting and filling structure is a second flat layer disposed in the opening and located in the light-transmitting functional area of the buffer layer, and the second flat layer is The height of the surface is lower than the height of the upper surface of the first flat layer.
  • the first flat layer is connected to the second flat layer, and is formed by a primary mask.
  • the first metal layer is disposed on the buffer layer and located in the display area for forming gate metal, and the semiconductor layer is disposed on the first insulating layer
  • the upper layer is used to form a channel layer
  • the second metal layer is disposed on the first flat layer to form a source and drain metal layer.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a structure of an opening of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of another structure of an array substrate provided by an embodiment of the application.
  • FIG. 4 is another schematic diagram of the structure of the opening of the array substrate provided by the embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of this application, “multiple” means two or more than two, unless otherwise specifically defined.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • the array substrate includes: a substrate 10, a buffer layer 20, a thin film transistor array layer A, and a supporting and filling structure 60.
  • the substrate 10 includes a display area 11 and a light-transmitting functional area 12;
  • the buffer layer 20 is disposed on the substrate 10 and covers the display area 11 and the light-transmitting functional area 12.
  • the thin film transistor array layer A is disposed on the buffer layer 20.
  • the thin film transistor array layer is provided with an opening 100, and the opening 100 and the light-transmitting functional area 12 are directly opposite to each other; the supporting and filling structure 60 is disposed in the opening 100.
  • the light-transmitting functional area 12 is used for a camera or a photosensitive sensor disposed below to collect light.
  • a camera or a photosensitive sensor disposed below to collect light.
  • it is not limited to this.
  • the thin film transistor array layer includes a first metal layer, a semiconductor layer, a second metal layer, a first insulating layer 30, a second insulating layer 50, and a first flat layer 40; a first insulating layer 30 is located on the buffer layer 20, the first flat layer 40 is disposed on the first insulating layer 30, and the second insulating layer 50 is disposed on the first flat layer 40.
  • the first metal layer is disposed on the buffer layer 20 and located in the display area 11 for forming a gate metal
  • the semiconductor layer is disposed on the first insulating layer 30 for forming a channel layer
  • the second metal layer is disposed on the first flat layer 40 for forming a source and drain metal layer.
  • the order of the first metal layer, the semiconductor layer, and the second metal layer can be changed, which belongs to the prior art and does not need to be described too much.
  • the supporting and filling structure 60 includes a plurality of supporting pillars 61 evenly spaced in the openings 100, and the openings 100 are through holes penetrating to the upper surface of the buffer layer 20.
  • the first insulating layer 30, the second insulating layer 50, and the first flat layer 40 can all be formed by using insulating materials such as silicon nitride or silicon dioxide using a chemical vapor deposition process.
  • the supporting pillar 61 is formed by sequentially stacking the first insulating layer 30, the first flat layer 50, and the second insulating layer 40 remaining after the TFT array layer is slotted. That is to say, when the opening 100 is formed by a photolithography process, the area directly facing each support pillar 61 is a light-shielding area on the corresponding mask.
  • the support column 61 is in the shape of a truncated cone with a small top and a large bottom. Of course, the support column 61 may also be cylindrical or conical, but of course, it is not limited to this.
  • FIG. 2 is a schematic diagram of the structure of the opening of the array substrate provided by an embodiment of the application.
  • the opening 100 includes a first through hole 31 in the first insulating layer 30, a second through hole 51 in the second insulating layer 50, and a third through hole 41 in the flat layer 40, The radii of the third through hole 41, the second through hole 51, and the first through hole 31 decrease in order.
  • a supporting and filling structure (a plurality of supporting pillars) is added in the opening, thereby improving the flatness and avoiding interference fringes at the opening. Improve display quality.
  • FIG. 3 is a schematic diagram of another structure of an array substrate provided by an embodiment of the application.
  • the array substrate includes: a substrate 10, a buffer layer 20, a thin film transistor array layer A, and a supporting and filling structure 60.
  • the substrate 10 includes a display area 11 and a light-transmitting functional area 12;
  • the buffer layer 20 is disposed on the substrate 10 and covers the display area 11 and the light-transmitting functional area 12.
  • the thin film transistor array layer A is disposed on the buffer layer 20.
  • the thin film transistor array layer is provided with an opening 100, and the opening 100 and the light-transmitting functional area 12 are directly opposite to each other; the supporting and filling structure 60 is disposed in the opening 100.
  • the thin film transistor array layer includes a first metal layer, a semiconductor layer, a second metal layer, a first insulating layer 30, a second insulating layer 50, and a first flat layer 40; a first insulating layer 30 is located on the buffer layer 20, the first flat layer 40 is disposed on the first insulating layer 30, and the second insulating layer 50 is disposed on the first flat layer 40.
  • the first metal layer is disposed on the buffer layer 20 and located in the display area 11 for forming a gate metal
  • the semiconductor layer is disposed on the first insulating layer for forming a channel layer
  • the second metal layer is disposed on the first flat layer 40 for forming a source and drain metal layer.
  • the order of the first metal layer, the semiconductor layer, and the second metal layer can be changed, which belongs to the prior art and does not need to be described too much.
  • the supporting and filling structure 60 is a second flat layer disposed in the opening 100 and located in the transparent functional area 12 of the buffer layer 20, and the upper surface of the second flat layer The height is lower than the height of the upper surface of the first flat layer 40.
  • the first flat layer 40 is connected to the second flat layer and is formed by a one-time photomask, that is, the first flat layer 40 and the second flat layer are an integral structure. Of course, it is not limited to this.
  • FIG. 4 is another structural diagram of the opening of the array substrate provided by the embodiment of the application.
  • the opening 100 includes a first through hole 31 in the first insulating layer 30, a second through hole 51 in the second insulating layer 50, and a third through hole 41 in the flat layer 40.
  • the radius of the through hole 51, the first through hole 31, and the third through hole 41 decrease in order.
  • a supporting and filling structure (second flat layer) is added therein, thereby improving the smoothness and avoiding interference fringes at the opening. Improve display quality.
  • the application also provides a liquid crystal display panel, including the above-mentioned array substrate.
  • a supporting and filling structure (such as a second flat layer or a plurality of supporting pillars) is added in the opening to improve the flatness and avoid the opening in the opening. Interference fringes are generated everywhere, which can improve the display quality.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及液晶显示面板，阵列基板包括：基板（10），包括显示区域（11）以及透光功能区域（12）；缓冲层（20），设置在基板（10）上，并覆盖显示区域（11）以及透光功能区域（12）；薄膜晶体管阵列层（A），设置在缓冲层（20）上，薄膜晶体管阵列层（A）上设有开孔（100），开孔（100）与透光功能区域（12）相互正对；以及支撑填充结构（60），设置在开孔（100）中。

Description

阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及液晶显示面板。
 背景技术
随着人们对电子设备的美观性要求越来越高，面内挖孔技术出现在人们的视野中。然而，目前面内挖孔技术仍存在比较多的问题点，例如：盲孔处易在光学测试时出现条状干涉纹。
 技术问题
本申请提供一种液晶显示面板，可以解决现有的液晶显示面板极易在盲孔处产生干涉纹的技术问题。
 技术解决方案
本申请实施例提供一种阵列基板，包括：
基板，所述基板包括显示区域以及透光功能区域；
缓冲层，所述设置在所述基板上，并覆盖所述显示区域以及透光功能区域；
薄膜晶体管阵列层，所述薄膜晶体管阵列层设置在所述缓冲层上，所述薄膜晶体管阵列层上设有开孔，所述开孔与所述透光功能区域相互正对；以及
支撑填充结构，所述支撑填充结构设置在所述开孔中。
在本申请所述的阵列基板中，所述薄膜晶体管阵列层包括第一金属层、半导体层、第二金属层、第一绝缘层、第二绝缘层以及第一平坦层；
所述第一绝缘层位于所述缓冲层上，所述第一平坦层设置在所述第一绝缘层上，所述第二绝缘层设置在所述第一平坦层上。
在本申请所述的阵列基板中，所述支撑填充结构包括多个均匀间隔分布于所述开孔中的支撑柱，所述开孔为贯穿至所述缓冲层上表面的通孔。
在本申请所述的阵列基板中，所述支撑柱为在所述薄膜晶体管阵列层上开槽后残留的第一绝缘层、第一平坦层以及第二绝缘层依次堆叠形成。
在本申请所述的阵列基板中，所述支撑柱呈上小下大圆台状。
在本申请所述的阵列基板中，所述开孔包括位于所述第一绝缘层的第一通孔，位于所述第二绝缘层的第二通孔以及位于所述平坦层的第三通孔，所述第三通孔、所述第二通孔、以及所述第一通孔的半径依次减小。
在本申请所述的阵列基板中，所述支撑填充结构为设置在于所述开孔中且位于所述缓冲层的透光功能区域的第二平坦层，且所述第二平坦层的上表面的高度低于所述第一平坦层的上表面的高度。
在本申请所述的阵列基板中，所述第一平坦层与所述第二平坦层相连，且为一次光罩形成。
在本申请所述的阵列基板中，所述第一金属层设置在所述缓冲层上并位于所述显示区域以用于形成栅极金属，所述半导体层设置在所述第一绝缘层上以用于形成沟道层，所述第二金属层设置在所述第一平坦层上以用于形成源漏金属层。
本申请实施例还提供一种液晶显示面板，其包括阵列基板，所述阵列基板包括：
基板，所述基板包括显示区域以及透光功能区域；
缓冲层，所述设置在所述基板上，并覆盖所述显示区域以及透光功能区域；
薄膜晶体管阵列层，所述薄膜晶体管阵列层设置在所述缓冲层上，所述薄膜晶体管阵列层上设有开孔，所述开孔与所述透光功能区域相互正对；以及
支撑填充结构，所述支撑填充结构设置在所述开孔中。
在本申请所述的液晶显示面板中，所述薄膜晶体管阵列层包括第一金属层、半导体层、第二金属层、第一绝缘层、第二绝缘层以及第一平坦层；
所述第一绝缘层位于所述缓冲层上，所述第一平坦层设置在所述第一绝缘层上，所述第二绝缘层设置在所述第一平坦层上。
在本申请所述的液晶显示面板中，所述支撑填充结构包括多个均匀间隔分布于所述开孔中的支撑柱，所述开孔为贯穿至所述缓冲层上表面的通孔。
在本申请所述的液晶显示面板中，所述支撑柱为在所述薄膜晶体管阵列层上开槽后残留的第一绝缘层、第一平坦层以及第二绝缘层依次堆叠形成。
在本申请所述的液晶显示面板中，所述支撑柱呈上小下大圆台状。
在本申请所述的液晶显示面板中，所述开孔包括位于所述第一绝缘层的第一通孔，位于所述第二绝缘层的第二通孔以及位于所述平坦层的第三通孔，所述第三通孔、所述第二通孔、以及所述第一通孔的半径依次减小。
在本申请所述的液晶显示面板中，所述支撑填充结构为设置在于所述开孔中且位于所述缓冲层的透光功能区域的第二平坦层，且所述第二平坦层的上表面的高度低于所述第一平坦层的上表面的高度。
在本申请所述的液晶显示面板中，所述第一平坦层与所述第二平坦层相连，且为一次光罩形成。
在本申请所述的液晶显示面板中，所述第一金属层设置在所述缓冲层上并位于所述显示区域以用于形成栅极金属，所述半导体层设置在所述第一绝缘层上以用于形成沟道层，所述第二金属层设置在所述第一平坦层上以用于形成源漏金属层。
 有益效果
本申请实施例提供的阵列基板及液晶显示面板，通过改变该开孔中的结构，在其中增加一支撑填充结构，从而提高平缓度，避免在该开孔处产生干涉条纹，可以提高显示质量。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的结构示意图。
图2为本申请实施例提供的阵列基板的开孔的结构示意图。
图3为本申请实施例提供阵列基板的另一种结构示意图。
图4为本申请实施例提供阵列基板的开孔的另一结构示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
请参阅图1，图1为本申请实施例提供的阵列基板的结构示意图。在该实施例中，该阵列基板，包括：基板10、缓冲层20、薄膜晶体管阵列层A以及支撑填充结构60。其中，该基板10包括显示区域11以及透光功能区域12；缓冲层20设置于所述基板10上，并覆盖所述显示区域11以及透光功能区域12。薄膜晶体管阵列层A设置于所述缓冲层20。薄膜晶体管阵列层上开设有开孔100，所述开孔100与所述透光功能区域12相互正对；支撑填充结构60设置于开孔100中。
其中，在一些实施例中，该透光功能区域12用于供设置于该处下方的摄像头或者感光传感器采集光线。当然，其并不限于此。
具体地，在一些实施例中，该薄膜晶体管阵列层包括第一金属层、半导体层、第二金属层、第一绝缘层30、第二绝缘层50以及第一平坦层40；第一绝缘层30位于缓冲层20上，所述第一平坦层40设置于所述第一绝缘层30上，所述第二绝缘层50设置于所述第一平坦层40上。其中，该第一金属层设置于所述缓冲层20上并位于所述显示区域11以用于形成栅极金属，该半导体层设置于所述第一绝缘层30上以用于形成沟道层，所述第二金属层设置于所述第一平坦层40上以用于形成源漏金属层。第一金属层、半导体层、第二金属层的顺序可以改变，其属于现有技术，无需过多描述。
在本实施例中，该支撑填充结构60包括多个均匀间隔分布于所述开孔100中的支撑柱61，所述开孔100为贯穿至所述缓冲层20上表面的通孔。
其中，该第一绝缘层30、第二绝缘层50以及第一平坦层40均可以采用氮化硅或者二氧化硅等绝缘材料采用化学气相沉淀工艺形成。
在一些实施例中，该支撑柱61为在所述薄膜晶体管阵列层上开槽后残留的第一绝缘层30、第一平坦层50以及第二绝缘层40依次堆叠形成。也即是说，在采用光刻工艺形成该开孔100时，每一支撑柱61正对的区域都是对应掩膜板上的遮光区域。该支撑柱61呈上小下大的圆台状。当然，该支撑柱61还可以为圆柱状，或者圆锥状，当然，其并不限于此。
请同时参照图2，图2为本申请实施例提供的阵列基板的开孔的结构示意图。其中，该开孔100包括位于所述第一绝缘层30的第一通孔31，位于所述第二绝缘层50的第二通孔51以及位于所述平坦层40的第三通孔41，所述第三通孔41、所述第二通孔51、以及所述第一通孔31的半径依次减小。
本申请提供的阵列基板及液晶显示面板，通过改变该开孔中的结构，在其中增加一支撑填充结构（多个支撑柱），从而提高平缓度，避免在该开孔处产生干涉条纹，可以提高显示质量。
请参阅图3，图3为本申请实施例提供阵列基板的另一种结构示意图。在该实施例中，该阵列基板包括：基板10、缓冲层20、薄膜晶体管阵列层A以及支撑填充结构60。其中，该基板10包括显示区域11以及透光功能区域12；缓冲层20设置于所述基板10上，并覆盖所述显示区域11以及透光功能区域12。薄膜晶体管阵列层A设置于所述缓冲层20。薄膜晶体管阵列层上开设有开孔100，所述开孔100与所述透光功能区域12相互正对；支撑填充结构60设置于开孔100中。
具体地，在一些实施例中，该薄膜晶体管阵列层包括第一金属层、半导体层、第二金属层、第一绝缘层30、第二绝缘层50以及第一平坦层40；第一绝缘层30位于缓冲层20上，所述第一平坦层40设置于所述第一绝缘层30上，所述第二绝缘层50设置于所述第一平坦层40上。其中，该第一金属层设置于所述缓冲层20上并位于所述显示区域11以用于形成栅极金属，所述半导体层设置于所述第一绝缘层上以用于形成沟道层，所述第二金属层设置于所述第一平坦层40上以用于形成源漏金属层。第一金属层、半导体层、第二金属层的顺序可以改变，其属于现有技术，无需过多描述。
在一些实施例中，该支撑填充结构60为设置于所述开孔100中且位于所述缓冲层20的透光功能区域12的第二平坦层，且所述第二平坦层的上表面的高度低于所述第一平坦层40的上表面的高度。第一平坦层40与所述第二平坦层相连，且为一次光罩形成，也即是说，该第一平坦层40与该第二平坦层为一体结构。当然，其并不限于此。
请同时参照图4，图4为本申请实施例提供阵列基板的开孔的另一结构示意图。该开孔100包括位于所述第一绝缘层30的第一通孔31，位于所述第二绝缘层50的第二通孔51以及位于所述平坦层40的第三通孔41，第二通孔51、第一通孔31、第三通孔41的半径依次减小。
本申请提供的阵列基板及液晶显示面板，通过改变该开孔中的结构，在其中增加一支撑填充结构（第二平坦层），从而提高平缓度，避免在该开孔处产生干涉条纹，可以提高显示质量。
本申请还提供了一种液晶显示面板，包括以上所述的阵列基板。
本申请提供的阵列基板及液晶显示面板，通过改变该开孔中的结构，在其中增加一支撑填充结构（例如第二平坦层或者多个支撑柱），从而提高平缓度，避免在该开孔处产生干涉条纹，可以提高显示质量。
在本说明书的描述中，参考术语“一个实施方式”、“某些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本实用新型的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板，其包括：
    基板，所述基板包括显示区域以及透光功能区域；
    缓冲层，所述设置在所述基板上，并覆盖所述显示区域以及透光功能区域；
    薄膜晶体管阵列层，所述薄膜晶体管阵列层设置在所述缓冲层上，所述薄膜晶体管阵列层上设有开孔，所述开孔与所述透光功能区域相互正对；以及
    支撑填充结构，所述支撑填充结构设置在所述开孔中。
  2. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管阵列层包括第一金属层、半导体层、第二金属层、第一绝缘层、第二绝缘层以及第一平坦层；
    所述第一绝缘层位于所述缓冲层上，所述第一平坦层设置在所述第一绝缘层上，所述第二绝缘层设置在所述第一平坦层上。
  3. 根据权利要求2所述的阵列基板，其中，所述支撑填充结构包括多个均匀间隔分布于所述开孔中的支撑柱，所述开孔为贯穿至所述缓冲层上表面的通孔。
  4. 根据权利要求3所述的阵列基板，其中，所述支撑柱为在所述薄膜晶体管阵列层上开槽后残留的第一绝缘层、第一平坦层以及第二绝缘层依次堆叠形成。
  5. 根据权利要求3所述的阵列基板，其中，所述支撑柱呈上小下大圆台状。
  6. 根据权利要求3所述的阵列基板，其中，所述开孔包括位于所述第一绝缘层的第一通孔，位于所述第二绝缘层的第二通孔以及位于所述平坦层的第三通孔，所述第三通孔、所述第二通孔、以及所述第一通孔的半径依次减小。
  7. 根据权利要求2所述的阵列基板，其中，所述支撑填充结构为设置在于所述开孔中且位于所述缓冲层的透光功能区域的第二平坦层，且所述第二平坦层的上表面的高度低于所述第一平坦层的上表面的高度。
  8. 根据权利要求7所述的阵列基板，其中，所述第一平坦层与所述第二平坦层相连，且为一次光罩形成。
  9. 根据权利要求2所述的阵列基板，其中，所述第一金属层设置在所述缓冲层上并位于所述显示区域以用于形成栅极金属，所述半导体层设置在所述第一绝缘层上以用于形成沟道层，所述第二金属层设置在所述第一平坦层上以用于形成源漏金属层。
  10. 一种液晶显示面板，其包括阵列基板，所述阵列基板包括：
    基板，所述基板包括显示区域以及透光功能区域；
    缓冲层，所述设置在所述基板上，并覆盖所述显示区域以及透光功能区域；
    薄膜晶体管阵列层，所述薄膜晶体管阵列层设置在所述缓冲层上，所述薄膜晶体管阵列层上设有开孔，所述开孔与所述透光功能区域相互正对；以及
    支撑填充结构，所述支撑填充结构设置在所述开孔中。
  11. 根据权利要求10所述的液晶显示面板，其中，所述薄膜晶体管阵列层包括第一金属层、半导体层、第二金属层、第一绝缘层、第二绝缘层以及第一平坦层；
    所述第一绝缘层位于所述缓冲层上，所述第一平坦层设置在所述第一绝缘层上，所述第二绝缘层设置在所述第一平坦层上。
  12. 根据权利要求11所述的液晶显示面板，其中，所述支撑填充结构包括多个均匀间隔分布于所述开孔中的支撑柱，所述开孔为贯穿至所述缓冲层上表面的通孔。
  13. 根据权利要求12所述的液晶显示面板，其中，所述支撑柱为在所述薄膜晶体管阵列层上开槽后残留的第一绝缘层、第一平坦层以及第二绝缘层依次堆叠形成。
  14. 根据权利要求12所述的液晶显示面板，其中，所述支撑柱呈上小下大圆台状。
  15. 根据权利要求12所述的液晶显示面板，其中，所述开孔包括位于所述第一绝缘层的第一通孔，位于所述第二绝缘层的第二通孔以及位于所述平坦层的第三通孔，所述第三通孔、所述第二通孔、以及所述第一通孔的半径依次减小。
  16. 根据权利要求11所述的液晶显示面板，其中，所述支撑填充结构为设置在于所述开孔中且位于所述缓冲层的透光功能区域的第二平坦层，且所述第二平坦层的上表面的高度低于所述第一平坦层的上表面的高度。
  17. 根据权利要求16所述的液晶显示面板，其中，所述第一平坦层与所述第二平坦层相连，且为一次光罩形成。
  18. 根据权利要求11所述的液晶显示面板，其中，所述第一金属层设置在所述缓冲层上并位于所述显示区域以用于形成栅极金属，所述半导体层设置在所述第一绝缘层上以用于形成沟道层，所述第二金属层设置在所述第一平坦层上以用于形成源漏金属层。
PCT/CN2019/101664 2019-06-17 2019-08-21 阵列基板及液晶显示面板 Ceased WO2020252885A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/615,871 US11573471B2 (en) 2019-06-17 2019-08-21 Array substrate and liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910520389.5A CN110244483A (zh) 2019-06-17 2019-06-17 阵列基板及液晶显示面板
CN201910520389.5 2019-06-17

Publications (1)

Publication Number Publication Date
WO2020252885A1 true WO2020252885A1 (zh) 2020-12-24

Family

ID=67887314

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/101664 Ceased WO2020252885A1 (zh) 2019-06-17 2019-08-21 阵列基板及液晶显示面板

Country Status (3)

Country Link
US (1) US11573471B2 (zh)
CN (1) CN110244483A (zh)
WO (1) WO2020252885A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111025719A (zh) * 2019-12-13 2020-04-17 武汉华星光电技术有限公司 显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100315570A1 (en) * 2009-06-11 2010-12-16 Mathew Dinesh C Portable computer display structures
CN102636896A (zh) * 2011-02-14 2012-08-15 乐金显示有限公司 显示装置
CN103365354A (zh) * 2012-03-28 2013-10-23 乐金显示有限公司 显示设备
CN108594524A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 显示装置
CN109100891A (zh) * 2018-08-10 2018-12-28 厦门天马微电子有限公司 一种显示面板及显示装置
CN109307962A (zh) * 2018-11-13 2019-02-05 华为技术有限公司 一种液晶显示面板、液晶显示屏及电子设备
CN109459879A (zh) * 2018-11-29 2019-03-12 武汉华星光电技术有限公司 一种液晶显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321176B (zh) * 2018-02-02 2020-07-03 京东方科技集团股份有限公司 一种柔性显示面板、其制作方法及显示装置
KR102583898B1 (ko) * 2018-04-30 2023-10-04 삼성디스플레이 주식회사 표시 패널 및 이의 제조 방법
CN110618549B (zh) * 2018-12-03 2024-10-29 鸿富锦精密工业（深圳）有限公司 显示装置
CN109560114B (zh) * 2018-12-06 2021-01-26 京东方科技集团股份有限公司 显示面板的制造方法、显示面板和显示装置
CN109581745B (zh) * 2018-12-25 2021-09-28 厦门天马微电子有限公司 显示装置及其装配工艺
US10928684B2 (en) * 2019-03-27 2021-02-23 Sharp Kabushiki Kaisha Display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100315570A1 (en) * 2009-06-11 2010-12-16 Mathew Dinesh C Portable computer display structures
CN102636896A (zh) * 2011-02-14 2012-08-15 乐金显示有限公司 显示装置
CN103365354A (zh) * 2012-03-28 2013-10-23 乐金显示有限公司 显示设备
CN108594524A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 显示装置
CN109100891A (zh) * 2018-08-10 2018-12-28 厦门天马微电子有限公司 一种显示面板及显示装置
CN109307962A (zh) * 2018-11-13 2019-02-05 华为技术有限公司 一种液晶显示面板、液晶显示屏及电子设备
CN109459879A (zh) * 2018-11-29 2019-03-12 武汉华星光电技术有限公司 一种液晶显示面板

Also Published As

Publication number Publication date
CN110244483A (zh) 2019-09-17
US11573471B2 (en) 2023-02-07
US20220214572A1 (en) 2022-07-07

Similar Documents

Publication Publication Date Title
CN109599402B (zh) 显示基板和显示装置
US8755018B2 (en) Liquid crystal display mother panel comprising primary spacers and secondary spacers wherein the primary spacers are surrounded by a primary sealant element
US10162236B2 (en) Array substrate and liquid crystal display device comprising the same
WO2017008369A1 (zh) Coa型液晶显示面板及其制作方法
CN205248273U (zh) 一种用于液晶显示器的阵列基板
CN104600079A (zh) 一种液晶显示装置、薄膜晶体管阵列基板及其制作方法
US11644719B2 (en) Liquid crystal display panel having pad structures and liquid crystal display device
WO2017008370A1 (zh) 阵列彩膜集成式液晶显示面板的制作方法及其结构
US10088723B2 (en) Pixel structure, array substrate and display device
WO2016078229A1 (zh) 液晶显示像素结构及其制作方法
WO2020228168A1 (zh) 阵列基板及其制作方法
WO2018176629A1 (zh) 显示面板及其制造方法
WO2017193633A1 (zh) 显示基板及其制备方法、显示装置
WO2016206164A1 (zh) 液晶显示面板及液晶显示面板的制造方法
WO2016074413A1 (zh) 显示基板及其制作方法、显示面板及显示装置
WO2019184607A1 (zh) 电极排气结构、电极、显示面板及其制备方法、显示装置
WO2018157725A1 (zh) 显示面板以及显示设备
WO2019085224A1 (zh) 阵列基板及显示面板
CN109270759A (zh) 阵列基板和显示面板
WO2019184543A1 (zh) 显示面板及其制作方法以及显示装置
CN108254983A (zh) 显示基板及其制备方法、触控显示装置
WO2021017275A1 (zh) 液晶显示面板及基板制作方法
WO2022000747A1 (zh) 阵列基板制备方法、阵列基板以及显示面板
WO2020252885A1 (zh) 阵列基板及液晶显示面板
WO2018205524A1 (zh) 一种阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19934177

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19934177

Country of ref document: EP

Kind code of ref document: A1