WO2020248834A1 - Circuit de lecture permettant de lire l'état de résistance d'une unité de stockage - Google Patents

Circuit de lecture permettant de lire l'état de résistance d'une unité de stockage Download PDF

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Publication number
WO2020248834A1
WO2020248834A1 PCT/CN2020/093193 CN2020093193W WO2020248834A1 WO 2020248834 A1 WO2020248834 A1 WO 2020248834A1 CN 2020093193 W CN2020093193 W CN 2020093193W WO 2020248834 A1 WO2020248834 A1 WO 2020248834A1
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WO
WIPO (PCT)
Prior art keywords
unit
read
current
output
power
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PCT/CN2020/093193
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English (en)
Chinese (zh)
Inventor
熊保玉
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浙江驰拓科技有限公司
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Publication of WO2020248834A1 publication Critical patent/WO2020248834A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Definitions

  • the present invention relates to the field of memory technology, and in particular to a read circuit for reading the resistance state of a memory cell.
  • MRAM Magnetic Random Access Memory
  • MTJ Magnetic Tunnel Junction
  • STT-MRAM Spin Transfer Torque Magnetic Random Access Memory
  • the core memory cell of STT-MRAM is shown in Figure 1, including MTJ and an NMOS tube.
  • MTJ can obtain different resistance states by changing the relative magnetic field polarization directions of the upper and lower ferromagnetic layers, that is, when parallel, it presents a low resistance state.
  • R p presents a high resistance state R ap when anti-parallel.
  • the different resistance states of MTJ can be used to store data information, for example, R p corresponds to data “0”, R ap corresponds to data “1”, or vice versa.
  • the commonly used read circuit at present provides a reference cell, and simultaneously applies a read voltage to the reference cell and the memory cell to be read. The output current of the two enters the sense amplifier, and the sense amplifier is compared to identify the high impedance state and the memory cell. Low resistance state.
  • the existing read circuit needs to use a sensitive amplifier, and the sensitive amplifier requires very high accuracy, and there are certain difficulties in circuit implementation.
  • the present invention provides a reading circuit for reading the resistance state of a memory cell, which eliminates the need for a high-precision sensitive amplifier and makes the circuit easier to implement.
  • the present invention provides a read circuit for reading the resistance state of a memory cell, including a power-on unit, a current mirror unit, and an output unit, wherein:
  • the first terminal of the power-on unit is connected to a read voltage signal
  • the second terminal of the power-on unit is connected to the bit line of the memory cell to be read
  • the power-on unit provides a read operation for the memory cell to be read A required reading voltage to generate a reading current, the reading current being output by the third terminal of the power-on unit;
  • the input terminal of the current mirror unit is connected to the third terminal of the power-on unit to receive the read current, and the output terminal of the current mirror unit outputs a mirror current, and the mirror current is proportional to the read current. proportion;
  • the output unit is configured to output the reading result according to the mirror current.
  • the current mirror unit is a current mirror with a mirroring coefficient of 1:N, where N is an integer equal to or greater than 1.
  • the power-on unit includes an operational amplifier and an NMOS tube
  • the non-inverting input terminal of the operational amplifier is the first terminal of the power-on unit
  • the output terminal of the operational amplifier is connected to the gate of the NMOS tube.
  • the source of the NMOS tube is connected to the inverting input terminal of the operational amplifier
  • the source of the NMOS tube is the second terminal of the power-on unit
  • the drain of the NMOS tube is the power-on unit The third end.
  • the NMOS tube has a planar MOSFET structure or a FINFET structure.
  • the output unit includes an output resistor and a comparator, one end of the output resistor is grounded, the other end is connected to the output terminal of the current mirror unit to generate an output voltage signal, and the input terminal of the comparator is connected To the output terminal of the current mirror unit, and output the read result according to the output voltage signal.
  • the comparator adopts an inverter or a single-input single-ended comparator.
  • the memory cell to be read is an MRAM memory cell, a resistive change memory cell, or a phase change memory cell.
  • the read circuit for reading the resistance state of the memory cell provided by the present invention no longer needs to read the reference cell, nor does it use a sensitive amplifier for comparison, but uses a current mirror unit to mirror the read current and read it in cooperation with the output unit.
  • the resistance state of the memory cell is displayed, and the circuit structure is simple and easy to implement.
  • FIG. 1 is a schematic diagram of the structure of an existing MRAM memory cell
  • FIG. 2 is a schematic structural diagram of a read circuit for reading the resistance state of a memory cell according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a read circuit for reading the resistance state of a memory cell according to another embodiment of the present invention.
  • An embodiment of the present invention provides a read circuit for reading the resistance state of a memory cell, as shown in FIG. 2, comprising: a power-on unit 201, a current mirror unit 202, and an output unit 203, wherein:
  • the power-on unit 201 has three connection terminals. The first terminal of the power-on unit 201 is connected to the read voltage signal Vread , and the second terminal of the power-on unit 201 is connected to the bit line BL of the memory cell to be read.
  • the MRAM memory cell is illustrated as an example.
  • the MRAM memory cell includes a magnetic tunnel junction MTJ0 and an NMOS transistor NM0.
  • the gate of NM0 is connected to the word line WL, and the source of NM0 is grounded.
  • the power-on unit 201 provides the memory for reading.
  • the unit provides a read voltage V read required for a read operation to generate a read current I read , the read current I read is output from the third terminal of the power-on unit 201; the input terminal of the current mirror unit 202 is connected to the upper
  • the third terminal of the electric unit 201 is configured to receive the read current I read , and the output terminal of the current mirror unit outputs a mirror current I out , and the mirror current I out is proportional to the read current I read ;
  • the output unit 203 is configured to output the reading result according to the mirror current I out .
  • the power-on unit 301 includes an operational amplifier A1 and an NMOS transistor NM1.
  • the non-inverting input terminal of the operational amplifier A1 is the first terminal of the power-on unit 301 for accessing the read voltage signal V read
  • the output terminal of the operational amplifier A1 is connected to the gate of the NMOS transistor NM1, so
  • the source of the NMOS tube NM1 is connected to the inverting input terminal of the operational amplifier A1, and the source of the NMOS tube NM1 is used to connect to the bit line BL of the memory cell to be read.
  • the drain of the NMOS tube NM1 is the third terminal of the power-on unit, and outputs a read current I read .
  • NM1 is a planar MOSFET structure or a FINFET structure.
  • the current mirror unit 302 is a current mirror with a mirroring coefficient of 1:N, where N is an integer equal to or greater than 1.
  • the current mirror circuit is a current control current source, which is used to convert the input current at the input end of the current mirror circuit into the output current at the output end of the current mirror circuit according to the mirror coefficient, where the input current at the input end is a reference current given by the outside.
  • the output current of the output terminal is proportional to the input current according to the mirror coefficient of the current mirror, and the current mirror coefficient is adjustable.
  • the comparator U2 uses an inverter or a single-input single-ended comparator.
  • the resistance value of the output resistor R out is M times the average anti-parallel resistance value R ap of the MTJ unit, where M is an integer equal to or greater than 1.
  • V out I out .R out
  • the read circuit shown in FIG. 3 Take the read circuit shown in FIG. 3 as an example, read the resistance state of the MRAM memory cell, and analyze the process of the read operation.
  • the word line WL inputs a high level to turn on the NMOS tube NM0 inside the MRAM memory cell, and the read voltage V read is applied to the non-inverting input terminal of the operational amplifier A1.
  • V read is generally 0.1V, according to the characteristics of the operational amplifier , NMOS transistor NM1 equal to the source voltage V read, i.e. applied to V read bit lines of the MRAM memory cells to generate the read current I read, the read current I read is the drain current of the output NMOS transistor NM1, and I read It is a constant current.
  • I read is input to the input end of the current mirror, through the mirroring effect of the current mirror, a mirror current I out is generated, and I out is N times of I read .
  • I out divided voltage V out is generated on R out, V out output obtained through the comparison result of the comparator OUT.
  • the comparator uses a conventional single-ended comparator, when OUT is high, it means that I read is relatively large at this time, that is, MTJ is in a low impedance state; when OUT is low, it means that I read is relatively small at this time, and That is, MTJ is in a high impedance state.
  • the comparator uses an inverter, when OUT is high, MTJ is in a high impedance state; when OUT is low, MTJ is in a low impedance state. During the MTJ reading process, the free layer magnetic moment of the MTJ does not reverse.
  • the memory cell to be read in the foregoing embodiment may also be a resistive change memory cell or a phase change memory cell.
  • the reading circuit no longer needs to read the reference unit, nor does it use a sensitive amplifier for comparison, but uses a current mirror or a resistor to compare the V in the two states of R P and R AP .
  • the out difference is amplified, so that a simple comparator, such as an inverter, can distinguish between the two states of R P and R AP , which greatly reduces the requirements for device accuracy.
  • V out is amplified, the comparator can be read quickly, which improves the reading speed.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

La présente invention concerne un circuit de lecture permettant de lire l'état de résistance d'une unité de stockage, comprenant : une unité de mise sous tension, une unité de miroir de courant, et une unité de sortie, la première extrémité de l'unité de mise sous tension étant connectée à un signal de tension de lecture, la seconde extrémité de l'unité de mise sous tension étant connectée à la ligne de bits d'une unité de stockage à lire, et l'unité de mise sous tension fournit à ladite unité de stockage une tension de lecture requise pour une opération de lecture afin de générer un courant de lecture, le courant de lecture étant délivré en sortie par la troisième extrémité de l'unité de mise sous tension ; l'extrémité d'entrée de l'unité de miroir de courant est connectée à la troisième extrémité de l'unité de mise sous tension afin de recevoir le courant de lecture, et l'extrémité de sortie de l'unité de miroir de courant délivre en sortie un courant de miroir, et le courant de miroir est proportionnel au courant de lecture ; et l'unité de sortie est configurée pour délivrer en sortie le résultat de lecture selon le courant de miroir. Le circuit de lecture de la présente invention présente une structure simple et est facile à mettre en œuvre.
PCT/CN2020/093193 2019-06-14 2020-05-29 Circuit de lecture permettant de lire l'état de résistance d'une unité de stockage WO2020248834A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910514561.6A CN112086113A (zh) 2019-06-14 2019-06-14 用于读取存储单元的电阻状态的读电路
CN201910514561.6 2019-06-14

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WO2020248834A1 true WO2020248834A1 (fr) 2020-12-17

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110080773A1 (en) * 2009-10-05 2011-04-07 Crocus Technology Sa Circuit for generating adjustable timing signals for sensing a self-referenced mram cell
CN103165184A (zh) * 2011-12-12 2013-06-19 三星电子株式会社 存储装置、执行读或写操作的方法和包括其的存储器系统
CN108288481A (zh) * 2018-01-19 2018-07-17 上海磁宇信息科技有限公司 一种可调电压的mram读出电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148051B (zh) * 2010-02-10 2015-05-27 上海华虹宏力半导体制造有限公司 存储器和灵敏放大器
CN102339643B (zh) * 2011-05-06 2016-06-08 上海华虹宏力半导体制造有限公司 存储器及其读取电路
CN102855931B (zh) * 2012-09-19 2017-06-06 上海华虹宏力半导体制造有限公司 存储器及其读取电路
CN102930891B (zh) * 2012-10-25 2017-08-08 上海华虹宏力半导体制造有限公司 读出电路
CN104347113B (zh) * 2014-11-21 2017-10-27 中国科学院上海微系统与信息技术研究所 一种相变存储器的读出电路及读出方法
TWI600009B (zh) * 2016-11-04 2017-09-21 財團法人工業技術研究院 可變電阻記憶體電路以及可變電阻記憶體電路之寫入方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110080773A1 (en) * 2009-10-05 2011-04-07 Crocus Technology Sa Circuit for generating adjustable timing signals for sensing a self-referenced mram cell
CN103165184A (zh) * 2011-12-12 2013-06-19 三星电子株式会社 存储装置、执行读或写操作的方法和包括其的存储器系统
CN108288481A (zh) * 2018-01-19 2018-07-17 上海磁宇信息科技有限公司 一种可调电压的mram读出电路

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