WO2020248834A1 - Reading circuit for reading resistance state of storage unit - Google Patents

Reading circuit for reading resistance state of storage unit Download PDF

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Publication number
WO2020248834A1
WO2020248834A1 PCT/CN2020/093193 CN2020093193W WO2020248834A1 WO 2020248834 A1 WO2020248834 A1 WO 2020248834A1 CN 2020093193 W CN2020093193 W CN 2020093193W WO 2020248834 A1 WO2020248834 A1 WO 2020248834A1
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unit
read
current
output
power
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PCT/CN2020/093193
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French (fr)
Chinese (zh)
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熊保玉
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浙江驰拓科技有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Definitions

  • the present invention relates to the field of memory technology, and in particular to a read circuit for reading the resistance state of a memory cell.
  • MRAM Magnetic Random Access Memory
  • MTJ Magnetic Tunnel Junction
  • STT-MRAM Spin Transfer Torque Magnetic Random Access Memory
  • the core memory cell of STT-MRAM is shown in Figure 1, including MTJ and an NMOS tube.
  • MTJ can obtain different resistance states by changing the relative magnetic field polarization directions of the upper and lower ferromagnetic layers, that is, when parallel, it presents a low resistance state.
  • R p presents a high resistance state R ap when anti-parallel.
  • the different resistance states of MTJ can be used to store data information, for example, R p corresponds to data “0”, R ap corresponds to data “1”, or vice versa.
  • the commonly used read circuit at present provides a reference cell, and simultaneously applies a read voltage to the reference cell and the memory cell to be read. The output current of the two enters the sense amplifier, and the sense amplifier is compared to identify the high impedance state and the memory cell. Low resistance state.
  • the existing read circuit needs to use a sensitive amplifier, and the sensitive amplifier requires very high accuracy, and there are certain difficulties in circuit implementation.
  • the present invention provides a reading circuit for reading the resistance state of a memory cell, which eliminates the need for a high-precision sensitive amplifier and makes the circuit easier to implement.
  • the present invention provides a read circuit for reading the resistance state of a memory cell, including a power-on unit, a current mirror unit, and an output unit, wherein:
  • the first terminal of the power-on unit is connected to a read voltage signal
  • the second terminal of the power-on unit is connected to the bit line of the memory cell to be read
  • the power-on unit provides a read operation for the memory cell to be read A required reading voltage to generate a reading current, the reading current being output by the third terminal of the power-on unit;
  • the input terminal of the current mirror unit is connected to the third terminal of the power-on unit to receive the read current, and the output terminal of the current mirror unit outputs a mirror current, and the mirror current is proportional to the read current. proportion;
  • the output unit is configured to output the reading result according to the mirror current.
  • the current mirror unit is a current mirror with a mirroring coefficient of 1:N, where N is an integer equal to or greater than 1.
  • the power-on unit includes an operational amplifier and an NMOS tube
  • the non-inverting input terminal of the operational amplifier is the first terminal of the power-on unit
  • the output terminal of the operational amplifier is connected to the gate of the NMOS tube.
  • the source of the NMOS tube is connected to the inverting input terminal of the operational amplifier
  • the source of the NMOS tube is the second terminal of the power-on unit
  • the drain of the NMOS tube is the power-on unit The third end.
  • the NMOS tube has a planar MOSFET structure or a FINFET structure.
  • the output unit includes an output resistor and a comparator, one end of the output resistor is grounded, the other end is connected to the output terminal of the current mirror unit to generate an output voltage signal, and the input terminal of the comparator is connected To the output terminal of the current mirror unit, and output the read result according to the output voltage signal.
  • the comparator adopts an inverter or a single-input single-ended comparator.
  • the memory cell to be read is an MRAM memory cell, a resistive change memory cell, or a phase change memory cell.
  • the read circuit for reading the resistance state of the memory cell provided by the present invention no longer needs to read the reference cell, nor does it use a sensitive amplifier for comparison, but uses a current mirror unit to mirror the read current and read it in cooperation with the output unit.
  • the resistance state of the memory cell is displayed, and the circuit structure is simple and easy to implement.
  • FIG. 1 is a schematic diagram of the structure of an existing MRAM memory cell
  • FIG. 2 is a schematic structural diagram of a read circuit for reading the resistance state of a memory cell according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a read circuit for reading the resistance state of a memory cell according to another embodiment of the present invention.
  • An embodiment of the present invention provides a read circuit for reading the resistance state of a memory cell, as shown in FIG. 2, comprising: a power-on unit 201, a current mirror unit 202, and an output unit 203, wherein:
  • the power-on unit 201 has three connection terminals. The first terminal of the power-on unit 201 is connected to the read voltage signal Vread , and the second terminal of the power-on unit 201 is connected to the bit line BL of the memory cell to be read.
  • the MRAM memory cell is illustrated as an example.
  • the MRAM memory cell includes a magnetic tunnel junction MTJ0 and an NMOS transistor NM0.
  • the gate of NM0 is connected to the word line WL, and the source of NM0 is grounded.
  • the power-on unit 201 provides the memory for reading.
  • the unit provides a read voltage V read required for a read operation to generate a read current I read , the read current I read is output from the third terminal of the power-on unit 201; the input terminal of the current mirror unit 202 is connected to the upper
  • the third terminal of the electric unit 201 is configured to receive the read current I read , and the output terminal of the current mirror unit outputs a mirror current I out , and the mirror current I out is proportional to the read current I read ;
  • the output unit 203 is configured to output the reading result according to the mirror current I out .
  • the power-on unit 301 includes an operational amplifier A1 and an NMOS transistor NM1.
  • the non-inverting input terminal of the operational amplifier A1 is the first terminal of the power-on unit 301 for accessing the read voltage signal V read
  • the output terminal of the operational amplifier A1 is connected to the gate of the NMOS transistor NM1, so
  • the source of the NMOS tube NM1 is connected to the inverting input terminal of the operational amplifier A1, and the source of the NMOS tube NM1 is used to connect to the bit line BL of the memory cell to be read.
  • the drain of the NMOS tube NM1 is the third terminal of the power-on unit, and outputs a read current I read .
  • NM1 is a planar MOSFET structure or a FINFET structure.
  • the current mirror unit 302 is a current mirror with a mirroring coefficient of 1:N, where N is an integer equal to or greater than 1.
  • the current mirror circuit is a current control current source, which is used to convert the input current at the input end of the current mirror circuit into the output current at the output end of the current mirror circuit according to the mirror coefficient, where the input current at the input end is a reference current given by the outside.
  • the output current of the output terminal is proportional to the input current according to the mirror coefficient of the current mirror, and the current mirror coefficient is adjustable.
  • the comparator U2 uses an inverter or a single-input single-ended comparator.
  • the resistance value of the output resistor R out is M times the average anti-parallel resistance value R ap of the MTJ unit, where M is an integer equal to or greater than 1.
  • V out I out .R out
  • the read circuit shown in FIG. 3 Take the read circuit shown in FIG. 3 as an example, read the resistance state of the MRAM memory cell, and analyze the process of the read operation.
  • the word line WL inputs a high level to turn on the NMOS tube NM0 inside the MRAM memory cell, and the read voltage V read is applied to the non-inverting input terminal of the operational amplifier A1.
  • V read is generally 0.1V, according to the characteristics of the operational amplifier , NMOS transistor NM1 equal to the source voltage V read, i.e. applied to V read bit lines of the MRAM memory cells to generate the read current I read, the read current I read is the drain current of the output NMOS transistor NM1, and I read It is a constant current.
  • I read is input to the input end of the current mirror, through the mirroring effect of the current mirror, a mirror current I out is generated, and I out is N times of I read .
  • I out divided voltage V out is generated on R out, V out output obtained through the comparison result of the comparator OUT.
  • the comparator uses a conventional single-ended comparator, when OUT is high, it means that I read is relatively large at this time, that is, MTJ is in a low impedance state; when OUT is low, it means that I read is relatively small at this time, and That is, MTJ is in a high impedance state.
  • the comparator uses an inverter, when OUT is high, MTJ is in a high impedance state; when OUT is low, MTJ is in a low impedance state. During the MTJ reading process, the free layer magnetic moment of the MTJ does not reverse.
  • the memory cell to be read in the foregoing embodiment may also be a resistive change memory cell or a phase change memory cell.
  • the reading circuit no longer needs to read the reference unit, nor does it use a sensitive amplifier for comparison, but uses a current mirror or a resistor to compare the V in the two states of R P and R AP .
  • the out difference is amplified, so that a simple comparator, such as an inverter, can distinguish between the two states of R P and R AP , which greatly reduces the requirements for device accuracy.
  • V out is amplified, the comparator can be read quickly, which improves the reading speed.

Abstract

The present invention provides a reading circuit for reading the resistance state of a storage unit, comprising: a power-on unit, a current mirror unit, and an output unit, wherein the first end of the power-on unit is connected to a read voltage signal, the second end of the power-on unit is connected to the bit line of a storage unit to be read, and the power-on unit provides said storage unit with a read voltage required for a read operation to generate a read current, the read current being output by the third end of the power-on unit; the input end of the current mirror unit is connected to the third end of the power-on unit to receive the read current, and the output end of the current mirror unit outputs a mirror current, and the mirror current is proportional to the read current; and the output unit is configured to output the reading result according to the mirror current. The reading circuit of the present invention has a simple structure and is easy to implement.

Description

用于读取存储单元的电阻状态的读电路Reading circuit for reading resistance state of memory cell 技术领域Technical field
本发明涉及存储器技术领域，尤其涉及一种用于读取存储单元的电阻状态的读电路。The present invention relates to the field of memory technology, and in particular to a read circuit for reading the resistance state of a memory cell.
背景技术Background technique
近年来，采用MTJ(Magnetic Tunnel Junction，磁性隧道结)的磁电阻效应的MRAM(Magnetic Random Access Memory，磁性随机存储器)被认为是未来的固态非易失性记忆体，相比于目前其他类型的存储器，具有读写速度快、可实现无限次擦写、易于与目前的半导体工艺相兼容等优点，此外利用自旋流来实现磁矩翻转的自旋转移矩磁性随机存储器STT-MRAM(Spin Transfer Torque Magnetic Random Access Memory)被证明具有很好的应用前景。In recent years, MRAM (Magnetic Random Access Memory), which uses the magnetoresistance effect of MTJ (Magnetic Tunnel Junction), is considered to be the future solid-state non-volatile memory. Compared with other current types The memory has the advantages of fast read and write speed, unlimited erasing and writing, and easy compatibility with current semiconductor technology. In addition, the spin transfer torque magnetic random access memory STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory has proved to have a good application prospect.
STT-MRAM的核心存储单元如图1所示，包括MTJ和一NMOS管，MTJ通过改变上下两个铁磁层的相对磁场极化方向可以得到不同的电阻状态，即平行时呈现出低阻态R p，反平行时呈现出高阻态R ap，利用MTJ不同的电阻状态可以用来存储数据信息，例如R p对应数据“0”，R ap对应数据“1”，或者反之亦可。要读出MTJ的电阻状态，需要对应的读电路。目前常用的读电路，提供一个参考单元，对参考单元和待读取的存储单元同时施加读电压，二者的输出电流进入灵敏放大器，通过灵敏放大器进行对比，以识别存储单元的高阻态和低阻态。 The core memory cell of STT-MRAM is shown in Figure 1, including MTJ and an NMOS tube. MTJ can obtain different resistance states by changing the relative magnetic field polarization directions of the upper and lower ferromagnetic layers, that is, when parallel, it presents a low resistance state. R p , presents a high resistance state R ap when anti-parallel. The different resistance states of MTJ can be used to store data information, for example, R p corresponds to data “0”, R ap corresponds to data “1”, or vice versa. To read the resistance state of MTJ, a corresponding read circuit is required. The commonly used read circuit at present provides a reference cell, and simultaneously applies a read voltage to the reference cell and the memory cell to be read. The output current of the two enters the sense amplifier, and the sense amplifier is compared to identify the high impedance state and the memory cell. Low resistance state.
在实现本发明的过程中，发明人发现现有技术中至少存在如下技术问题：In the process of implementing the present invention, the inventor found that at least the following technical problems exist in the prior art:
现有的读电路需要用到灵敏放大器，而灵敏放大器要求具有非常高的精度，电路实现存在一定的困难。The existing read circuit needs to use a sensitive amplifier, and the sensitive amplifier requires very high accuracy, and there are certain difficulties in circuit implementation.
发明内容Summary of the invention
为解决上述问题，本发明提供一种用于读取存储单元的电阻状态的读电路，省掉了高精度的灵敏放大器，电路更加容易实现。In order to solve the above problems, the present invention provides a reading circuit for reading the resistance state of a memory cell, which eliminates the need for a high-precision sensitive amplifier and makes the circuit easier to implement.
本发明提供一种用于读取存储单元的电阻状态的读电路，包括：上电单元、电流镜像单元以及输出单元，其中，The present invention provides a read circuit for reading the resistance state of a memory cell, including a power-on unit, a current mirror unit, and an output unit, wherein:
所述上电单元的第一端接入读电压信号，所述上电单元的第二端连接至待读存储单元的位线，通过所述上电单元为所述待读存储单元提供读操作需要的读电压以产生读电流，所述读电流由所述上电单元的第三端输出；The first terminal of the power-on unit is connected to a read voltage signal, the second terminal of the power-on unit is connected to the bit line of the memory cell to be read, and the power-on unit provides a read operation for the memory cell to be read A required reading voltage to generate a reading current, the reading current being output by the third terminal of the power-on unit;
所述电流镜像单元的输入端连接至所述上电单元的第三端，以接收所述读电流，所述电流镜像单元的输出端输出一镜像电流，所述镜像电流与所述读电流成比例；The input terminal of the current mirror unit is connected to the third terminal of the power-on unit to receive the read current, and the output terminal of the current mirror unit outputs a mirror current, and the mirror current is proportional to the read current. proportion;
所述输出单元，用于根据所述镜像电流输出读取结果。The output unit is configured to output the reading result according to the mirror current.
可选地，所述电流镜像单元为镜像系数1：N的电流镜，其中N取等于或者大于1的整数。Optionally, the current mirror unit is a current mirror with a mirroring coefficient of 1:N, where N is an integer equal to or greater than 1.
可选地，所述上电单元包括运算放大器和NMOS管，所述运算放大器的同相输入端为所述上电单元的第一端，所述运算放大器的输出端连接至所述NMOS管的栅极，所述NMOS管的源极连接至所述运算放大器的反相输入端，所述NMOS管的源极为所述上电单元的第二端，所述NMOS管的漏极为所述上电单元的第三端。Optionally, the power-on unit includes an operational amplifier and an NMOS tube, the non-inverting input terminal of the operational amplifier is the first terminal of the power-on unit, and the output terminal of the operational amplifier is connected to the gate of the NMOS tube. The source of the NMOS tube is connected to the inverting input terminal of the operational amplifier, the source of the NMOS tube is the second terminal of the power-on unit, and the drain of the NMOS tube is the power-on unit The third end.
可选地，所述NMOS管为平面MOSFET结构或者FINFET结构。Optionally, the NMOS tube has a planar MOSFET structure or a FINFET structure.
可选地，所述输出单元包括输出电阻和比较器，所述输出电阻的一端接地，另一端连接至所述电流镜像单元的输出端以产生一输出电压信号，所述比较器的输入端连接至所述电流镜像单元的输出端，根据所述输出电压信号输出读取结果。Optionally, the output unit includes an output resistor and a comparator, one end of the output resistor is grounded, the other end is connected to the output terminal of the current mirror unit to generate an output voltage signal, and the input terminal of the comparator is connected To the output terminal of the current mirror unit, and output the read result according to the output voltage signal.
可选地，所述比较器采用反相器或者单输入的单端比较器。Optionally, the comparator adopts an inverter or a single-input single-ended comparator.
可选地，所述待读存储单元为MRAM存储单元、阻变存储单元或者相变存储单元。Optionally, the memory cell to be read is an MRAM memory cell, a resistive change memory cell, or a phase change memory cell.
本发明提供的用于读取存储单元的电阻状态的读电路，不再需要读参考单元，也不使用灵敏放大器进行比较，而是采用电流镜像单元对读电流进行镜像输出，并配合输出单元读出存储单元的电阻状态，电路结构简单，容易实现。The read circuit for reading the resistance state of the memory cell provided by the present invention no longer needs to read the reference cell, nor does it use a sensitive amplifier for comparison, but uses a current mirror unit to mirror the read current and read it in cooperation with the output unit. The resistance state of the memory cell is displayed, and the circuit structure is simple and easy to implement.
附图说明Description of the drawings
图1为现有的MRAM存储单元的结构示意图；FIG. 1 is a schematic diagram of the structure of an existing MRAM memory cell;
图2为本发明一实施例的用于读取存储单元的电阻状态的读电路的结构示意图；2 is a schematic structural diagram of a read circuit for reading the resistance state of a memory cell according to an embodiment of the present invention;
图3为本发明另一实施例的用于读取存储单元的电阻状态的读电路的结构示意图。3 is a schematic structural diagram of a read circuit for reading the resistance state of a memory cell according to another embodiment of the present invention.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
本发明一实施例提供一种用于读取存储单元的电阻状态的读电路，如图2所示，包括：上电单元201、电流镜像单元202以及输出单元203，其中，An embodiment of the present invention provides a read circuit for reading the resistance state of a memory cell, as shown in FIG. 2, comprising: a power-on unit 201, a current mirror unit 202, and an output unit 203, wherein:
上电单元201具有三个连接端，上电单元201的第一端接入读电压信号V read，所述上电单元201的第二端连接至待读存储单元的位线BL，这里是以MRAM存储单元为例进行图示，MRAM存储单元包括磁性隧道结MTJ0和 NMOS晶体管NM0，NM0的栅极连接字线WL，NM0的源极接地，通过所述上电单元201为所述待读存储单元提供读操作需要的读电压V read以产生读电流I read，所述读电流I read由所述上电单元201的第三端输出；所述电流镜像单元202的输入端连接至所述上电单元201的第三端，以接收所述读电流I read，所述电流镜像单元的输出端输出一镜像电流I out，所述镜像电流I out与所述读电流I read成比例；所述输出单元203，用于根据所述镜像电流I out输出读取结果。 The power-on unit 201 has three connection terminals. The first terminal of the power-on unit 201 is connected to the read voltage signal Vread , and the second terminal of the power-on unit 201 is connected to the bit line BL of the memory cell to be read. The MRAM memory cell is illustrated as an example. The MRAM memory cell includes a magnetic tunnel junction MTJ0 and an NMOS transistor NM0. The gate of NM0 is connected to the word line WL, and the source of NM0 is grounded. The power-on unit 201 provides the memory for reading. The unit provides a read voltage V read required for a read operation to generate a read current I read , the read current I read is output from the third terminal of the power-on unit 201; the input terminal of the current mirror unit 202 is connected to the upper The third terminal of the electric unit 201 is configured to receive the read current I read , and the output terminal of the current mirror unit outputs a mirror current I out , and the mirror current I out is proportional to the read current I read ; The output unit 203 is configured to output the reading result according to the mirror current I out .
进一步地，本发明另一实施例给出了一种更加具体的用于读取存储单元的电阻状态的读电路，如图3所示，上电单元301包括运算放大器A1和NMOS管NM1，所述运算放大器A1的同相输入端为所述上电单元301的第一端，用于接入读电压信号V read，所述运算放大器A1的输出端连接至所述NMOS管NM1的栅极，所述NMOS管NM1的源极连接至所述运算放大器A1的反相输入端，所述NMOS管NM1的源极为所述上电单元的第二端，用于连接待读存储单元的位线BL，所述NMOS管NM1的漏极为所述上电单元的第三端，输出读电流I read。本实施例中，NM1为平面MOSFET结构或者FINFET结构。 Further, another embodiment of the present invention provides a more specific read circuit for reading the resistance state of a memory cell. As shown in FIG. 3, the power-on unit 301 includes an operational amplifier A1 and an NMOS transistor NM1. The non-inverting input terminal of the operational amplifier A1 is the first terminal of the power-on unit 301 for accessing the read voltage signal V read , the output terminal of the operational amplifier A1 is connected to the gate of the NMOS transistor NM1, so The source of the NMOS tube NM1 is connected to the inverting input terminal of the operational amplifier A1, and the source of the NMOS tube NM1 is used to connect to the bit line BL of the memory cell to be read. The drain of the NMOS tube NM1 is the third terminal of the power-on unit, and outputs a read current I read . In this embodiment, NM1 is a planar MOSFET structure or a FINFET structure.
电流镜像单元302为镜像系数1：N的电流镜，其中N取等于或者大于1的整数。电流镜电路是一种电流控制电流源，用于将电流镜电路的输入端的输入电流按照镜像系数转换为电流镜电路的输出端的输出电流，其中，输入端的输入电流是由外部给定的基准电流，输出端的输出电流与输入电流按照电流镜的镜像系数成比例，该电流镜像系数是可调节的。本实施例中，电流镜的输入端输入读电流I read，输出端输出镜像电流I out，I read：I out＝1：N。 The current mirror unit 302 is a current mirror with a mirroring coefficient of 1:N, where N is an integer equal to or greater than 1. The current mirror circuit is a current control current source, which is used to convert the input current at the input end of the current mirror circuit into the output current at the output end of the current mirror circuit according to the mirror coefficient, where the input current at the input end is a reference current given by the outside. , The output current of the output terminal is proportional to the input current according to the mirror coefficient of the current mirror, and the current mirror coefficient is adjustable. In this embodiment, the input terminal of the current mirror inputs the read current I read , and the output terminal outputs the mirror current I out , I read : I out =1:N.
输出单元303包括输出电阻R out和比较器U2，所述输出电阻R out的一端接地，另一端连接至所述电流镜像单元302的输出端以产生一输出电压信号V out，V out＝I out.R out，所述比较器U2的输入端连接至所述电流镜像单元302的 输出端，根据所述输出电压信号V out输出读取结果OUT。其中，比较器U2采用反相器或者单输入的单端比较器。所述输出电阻R out的阻值为MTJ单元的反平行态阻值均值R ap的M倍，其中M取等于或者大于1的整数。 The output unit 303 includes an output resistor R out and a comparator U2. One end of the output resistor R out is grounded, and the other end is connected to the output terminal of the current mirror unit 302 to generate an output voltage signal V out , V out =I out . R out , the input terminal of the comparator U2 is connected to the output terminal of the current mirror unit 302, and the read result OUT is output according to the output voltage signal V out . Among them, the comparator U2 uses an inverter or a single-input single-ended comparator. The resistance value of the output resistor R out is M times the average anti-parallel resistance value R ap of the MTJ unit, where M is an integer equal to or greater than 1.
由于V out＝I out.R out，要调节V out，可以通过调节电流镜的镜像系数实现，也可以通过调节输出电阻R out的阻值实现。例如，要放大5倍，可以使用1:1的电流镜，使R out的阻值是R ap的5倍；或者，使用1:5的电流镜，使R out＝R ap。 Since V out = I out .R out, to adjust V out, can be achieved by adjusting the coefficients of the current mirror mirroring, may be realized by adjusting the resistance of the output resistance R out. For example, to magnify 5 times, you can use a 1:1 current mirror to make the resistance of R out 5 times that of R ap ; or use a 1:5 current mirror to make R out =R ap .
以图3所示的读电路为例，读取MRAM存储单元的阻态，分析读操作的过程。读操作时，字线WL输入高电平，使MRAM存储单元内部的NMOS管NM0导通，在运算放大器A1的同相输入端施加读电压V read，V read一般为0.1V，根据运算放大器的特性，NMOS管NM1的源极电压等于V read，即在MRAM存储单元的位线施加V read，从而产生读电流I read，该读电流I read也就是NMOS管NM1的漏极输出电流，而且I read是个恒流。I read输入电流镜的输入端，通过电流镜的镜像作用，生成镜像电流I out，I out为I read的N倍。I out在R out上产生分压V out，V out经过比较器比较得到输出结果OUT。比较器采用常规的单端比较器时，当OUT为高时，说明此时I read相对较大，也就是MTJ为低阻态；当OUT为低时，说明此时I read相对较小，也就是MTJ为高阻态。比较器如果采用反相器，当OUT为高时，MTJ为高阻态；当OUT为低时，MTJ为低阻态。在MTJ读取过程中，MTJ的自由层磁矩不发生翻转。 Take the read circuit shown in FIG. 3 as an example, read the resistance state of the MRAM memory cell, and analyze the process of the read operation. During the read operation, the word line WL inputs a high level to turn on the NMOS tube NM0 inside the MRAM memory cell, and the read voltage V read is applied to the non-inverting input terminal of the operational amplifier A1. V read is generally 0.1V, according to the characteristics of the operational amplifier , NMOS transistor NM1 equal to the source voltage V read, i.e. applied to V read bit lines of the MRAM memory cells to generate the read current I read, the read current I read is the drain current of the output NMOS transistor NM1, and I read It is a constant current. I read is input to the input end of the current mirror, through the mirroring effect of the current mirror, a mirror current I out is generated, and I out is N times of I read . I out divided voltage V out is generated on R out, V out output obtained through the comparison result of the comparator OUT. When the comparator uses a conventional single-ended comparator, when OUT is high, it means that I read is relatively large at this time, that is, MTJ is in a low impedance state; when OUT is low, it means that I read is relatively small at this time, and That is, MTJ is in a high impedance state. If the comparator uses an inverter, when OUT is high, MTJ is in a high impedance state; when OUT is low, MTJ is in a low impedance state. During the MTJ reading process, the free layer magnetic moment of the MTJ does not reverse.
另外说明的是，上述实施例中的待读存储单元还可以为阻变存储单元或相变存储单元。In addition, it should be noted that the memory cell to be read in the foregoing embodiment may also be a resistive change memory cell or a phase change memory cell.
通过上述分析可以看出，本发明实施例提供的读电路，不再需要读参考单元，也不使用灵敏放大器进行比较，而是采用电流镜或电阻将R P和R AP两种状态下的V out差别放大，使得用简单的比较器，如反相器就可以区分R P和R AP 两种状态，对器件精度的要求大大降低。并且因为V out被放大了，比较器可以快速读取，提高了读取速度。 From the above analysis, it can be seen that the reading circuit provided by the embodiment of the present invention no longer needs to read the reference unit, nor does it use a sensitive amplifier for comparison, but uses a current mirror or a resistor to compare the V in the two states of R P and R AP . The out difference is amplified, so that a simple comparator, such as an inverter, can distinguish between the two states of R P and R AP , which greatly reduces the requirements for device accuracy. And because V out is amplified, the comparator can be read quickly, which improves the reading speed.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (7)

  1. 一种用于读取存储单元的电阻状态的读电路，其特征在于，包括：上电单元、电流镜像单元以及输出单元，其中，A read circuit for reading the resistance state of a memory cell is characterized by comprising: a power-on unit, a current mirror unit and an output unit, wherein:
    所述上电单元的第一端接入读电压信号，所述上电单元的第二端连接至待读存储单元的位线，通过所述上电单元为所述待读存储单元提供读操作需要的读电压以产生读电流，所述读电流由所述上电单元的第三端输出；The first terminal of the power-on unit is connected to a read voltage signal, the second terminal of the power-on unit is connected to the bit line of the memory cell to be read, and the power-on unit provides a read operation for the memory cell to be read A required reading voltage to generate a reading current, the reading current being output by the third terminal of the power-on unit;
    所述电流镜像单元的输入端连接至所述上电单元的第三端，以接收所述读电流，所述电流镜像单元的输出端输出一镜像电流，所述镜像电流与所述读电流成比例；The input terminal of the current mirror unit is connected to the third terminal of the power-on unit to receive the read current, and the output terminal of the current mirror unit outputs a mirror current, and the mirror current is proportional to the read current. proportion;
    所述输出单元，用于根据所述镜像电流输出读取结果。The output unit is configured to output the reading result according to the mirror current.
  2. 根据权利要求1所述的电路，其特征在于，所述电流镜像单元为镜像系数1：N的电流镜，其中N取等于或者大于1的整数。The circuit according to claim 1, wherein the current mirror unit is a current mirror with a mirroring coefficient of 1:N, wherein N is an integer equal to or greater than 1.
  3. 根据权利要求1所述的电路，其特征在于，所述上电单元包括运算放大器和NMOS管，所述运算放大器的同相输入端为所述上电单元的第一端，所述运算放大器的输出端连接至所述NMOS管的栅极，所述NMOS管的源极连接至所述运算放大器的反相输入端，所述NMOS管的源极为所述上电单元的第二端，所述NMOS管的漏极为所述上电单元的第三端。The circuit according to claim 1, wherein the power-on unit includes an operational amplifier and an NMOS tube, the non-inverting input terminal of the operational amplifier is the first terminal of the power-on unit, and the output of the operational amplifier Terminal is connected to the gate of the NMOS tube, the source of the NMOS tube is connected to the inverting input terminal of the operational amplifier, the source of the NMOS tube is connected to the second terminal of the power-on unit, the NMOS tube The drain of the tube is the third end of the power-on unit.
  4. 根据权利要求3所述的电路，其特征在于，所述NMOS管为平面MOSFET结构或者FINFET结构。3. The circuit of claim 3, wherein the NMOS transistor is a planar MOSFET structure or a FINFET structure.
  5. 根据权利要求1所述的电路，其特征在于，所述输出单元包括输出电阻和比较器，所述输出电阻的一端接地，另一端连接至所述电流镜像单元的输出端以产生一输出电压信号，所述比较器的输入端连接至所述电流镜像单元的 输出端，根据所述输出电压信号输出读取结果。The circuit according to claim 1, wherein the output unit comprises an output resistor and a comparator, one end of the output resistor is grounded, and the other end is connected to the output terminal of the current mirror unit to generate an output voltage signal The input terminal of the comparator is connected to the output terminal of the current mirror unit, and the reading result is output according to the output voltage signal.
  6. 根据权利要求5所述的电路，其特征在于，所述比较器采用反相器或者单输入的单端比较器。The circuit according to claim 5, wherein the comparator is an inverter or a single-input single-ended comparator.
  7. 根据权利要求1所述的电路，其特征在于，所述待读存储单元为MRAM存储单元、阻变存储单元或者相变存储单元。The circuit according to claim 1, wherein the memory cell to be read is an MRAM memory cell, a resistive change memory cell, or a phase change memory cell.
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