WO2022127428A1

WO2022127428A1 - Magnetic random access memory and read circuit thereof

Info

Publication number: WO2022127428A1
Application number: PCT/CN2021/128924
Authority: WO
Inventors: 熊保玉; 沈岙
Original assignee: 浙江驰拓科技有限公司
Priority date: 2020-12-15
Filing date: 2021-11-05
Publication date: 2022-06-23
Also published as: CN114639410A

Abstract

A magnetic random access memory and a read circuit thereof. The read circuit comprises a sense amplifier, a reference array, and a read array. The reference array comprises a first reference resistor, a second reference resistor, a first storage unit, a second storage unit, a first controllable switch, a second controllable switch, and a switch transistor; a first end of the first reference resistor and a first end of the second reference resistor are separately connected to the switch transistor; a first end of the first storage unit is separately connected to a second end of the first reference resistor and a second end of the second reference resistor; a first end of the second storage unit is separately connected to the second end of the first reference resistor and the second end of the second reference resistor; the second end of the first storage unit is connected to a second end of the first controllable switch; the second end of the second storage unit is connected to a second end of the second controllable switch; a first end of the first controllable switch and a first end of the second controllable switch are separately connected to a reference word line; a third end of the first controllable switch and a third end of the second controllable switch are separately grounded. Thus, the window of a reference voltage is enlarged, and the read yield is increased.

Description

A magnetic random access memory and its reading circuit

This application claims the priority of the Chinese patent application with the application number 202011473066.4 and the invention titled "A Magnetic Random Access Memory and Its Read Circuit" filed with the China Patent Office on December 15, 2020, the entire contents of which are incorporated herein by reference Applying.

technical field

The present application relates to the technical field of magnetic memory, and in particular, to a magnetic random access memory and a read circuit thereof.

Background technique

Magnetic random access memory (Magnetic Random Access Memory, referred to as MRAM) has the high-speed read and write capabilities of static random access memory (SRAM), and the high integration of dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM), and basically unlimited Write repeatedly.

At present, in the read circuit of MRAM, a sense amplifier (Sense Amplifier, SA for short) is used to compare the current flowing through the reference resistor R _ref with the current of the MTJ (Magnetic Tunnel Junctions, Magnetic Tunnel Junctions) bit to identify the MTJ bit. high resistance and low resistance. However, on the one hand, the TMR (Tunnel Magneto Resistance) of the MTJ decreases at high temperature, and the resistance in the antiparallel state becomes smaller; on the other hand, the resistance temperature coefficient of the reference resistor in the reference array is small, which cannot be adaptively adjusted with temperature, and further As a result, the relative resistance values of the reference array resistance and the read array resistance change greatly due to temperature, so that the resistance value of the reference array and the resistance score distribution of the read array overlap, the read window becomes smaller at high temperature, and the read yield decreases.

Therefore, how to solve the above technical problems should be the focus of those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a magnetic random access memory and a read circuit thereof, so as to solve the problem that the circuit read window becomes smaller due to temperature changes, and to improve the read yield.

In order to solve the above technical problems, the present application provides a magnetic random access memory read circuit, including a sense amplifier, a reference array, and a read array;

The reference array includes a first reference resistor, a second reference resistor, a first storage unit, a second storage unit, a first controllable switch, a second controllable switch, and a switch tube; a first end of the first reference resistor, a second The first end of the reference resistor is respectively connected to the switch tube, the first end of the first storage unit is respectively connected to the second end of the first reference resistor and the second end of the second reference resistor, and the first end of the second storage unit is respectively connected to the The second end of the first reference resistor is connected to the second end of the second reference resistor, the second end of the first storage unit is connected to the second end of the first controllable switch, and the second end of the second storage unit is connected to the second controllable switch The second end is connected, the first end of the first controllable switch and the first end of the second controllable switch are respectively connected to the reference word line, and the third end of the first controllable switch and the third end of the second controllable switch are respectively grounded;

The read array includes a first magnetic tunnel junction and NMOS transistors respectively connected at both ends of the first magnetic tunnel junction.

Optionally, the first storage unit and the second storage unit are a second magnetic tunnel junction or a resistive storage unit, wherein an initial state of the second magnetic tunnel junction is an antiparallel state.

Optionally, the resistive memory unit is a resistive memory or a phase change memory.

Optionally, the initialization manner of the initial state of the second magnetic tunnel junction includes magnetic field initialization and writing circuit initialization.

Optionally, the preset resistance values of the first reference resistor and the second reference resistor are both the parallel state resistance values of the second magnetic tunnel junction, and the adjustment range of the preset resistance value is the Plus or minus 30% of the parallel state resistance.

Optionally, the first controllable switch and the second controllable switch are any of the following:

NMOS tube, PMOS tube, transmission gate, triode.

Optionally, the range of the reference voltage of the switch tube is between 0.3V and 1.0V.

Optionally, the first reference resistor and the second reference resistor are any of the following:

Poly resistor, well resistor, metal resistor.

The present application also provides a magnetic random access memory, the magnetic random access memory including any one of the magnetic random access memory read circuits described above.

A magnetic random access memory read circuit provided by this application includes a sense amplifier, a reference array, and a read array; the reference array includes a first reference resistor, a second reference resistor, a first storage unit, a second storage unit, a first A controllable switch, a second controllable switch and a switch tube; the first end of the first reference resistor and the first end of the second reference resistor are respectively connected to the switch tube, and the first end of the first storage unit is respectively connected to the first end of the first reference resistor The two terminals are connected to the second terminal of the second reference resistor, the first terminal of the second storage unit is connected to the second terminal of the first reference resistor and the second terminal of the second reference resistor respectively, and the second terminal of the first storage unit is connected to the second terminal of the first reference resistor and the second terminal of the second reference resistor respectively. The second end of the first controllable switch is connected to the second end, the second end of the second storage unit is connected to the second end of the second controllable switch, the first end of the first controllable switch and the first end of the second controllable switch are respectively connected to the reference word line , the third end of the first controllable switch and the third end of the second controllable switch are grounded respectively; the read array includes a first magnetic tunnel junction and NMOS transistors respectively connected to both ends of the first magnetic tunnel junction.

It can be seen that the magnetic random access memory read circuit of the present application includes a sense amplifier, a reference array, and a read array. In addition to the switch tube, the first reference resistor, and the second reference resistor, the reference array also includes a first storage unit, a second storage unit, and a first storage unit. A controllable switch and a second controllable switch, the first storage unit and the second storage unit are correspondingly connected to the first controllable switch and the second controllable switch, the first storage unit and the second storage unit are connected in parallel, the first reference resistance and The second reference resistors are connected in parallel, and the paralleled first and second storage cells are connected in series with the paralleled first and second reference resistors. In this application, the paralleled first and second storage cells are added as separate The reference bit used for reference uses the first memory cell and the second memory cell connected in parallel as a reference when reading the array, so that the resistance value of the reference array at different temperatures changes with the resistance value of the read array, and the direction of the resistance value changes It is basically the same as the size, reducing the relative resistance change of the read array and the reference array, and the resistance value of the reference array and the resistance value distribution of the read array will not overlap, thereby increasing the reference voltage window and improving the read yield; In addition, in this application The circuit structure is simple, and no additional writing circuit is required.

In addition, the present application also provides a magnetic random access memory having the above advantages.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application or the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only For some embodiments of the present application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

1 is a circuit diagram of a magnetic random access memory read circuit provided by an embodiment of the present application;

FIG. 2 is a circuit diagram of another magnetic random access memory read circuit provided by an embodiment of the present application.

Detailed ways

In order to make those skilled in the art better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can do so without departing from the connotation of the present invention. Similar promotion, therefore, the present invention is not limited by the specific embodiments disclosed below.

As described in the background art section, in the current read circuit, a sense amplifier is used to compare the current flowing through the reference resistor and the MTJ, so as to identify the high-impedance state and the low-impedance state of the MTJ bit. Since the TMR of the MTJ decreases at high temperature, the resistance in the antiparallel state becomes smaller, and the temperature coefficient of resistance of the reference resistor is small, which cannot be adjusted adaptively with the temperature, which leads to the relative resistance value of the reference array resistor and the read array resistor due to temperature reasons. There is a large change, the distribution of resistance values overlaps, the read window becomes smaller at high temperatures, and the read yield decreases.

In view of this, the present application provides a magnetic random access memory read circuit. Please refer to FIG. 1 , which is a circuit diagram of a magnetic random access memory read circuit provided by an embodiment of the present application, including:

Sense amplifier SA, reference array, read array;

The reference array includes a first reference resistor R1, a second reference resistor R2, a first storage unit M1, a second storage unit M2, a first controllable switch Q1, a second controllable switch Q2, and a switch Q4; the first reference The first end of the resistor R1 and the first end of the second reference resistor R2 are respectively connected to the switch tube Q4, and the first end of the first memory unit M1 is respectively connected to the second end of the first reference resistor R1 and the second end of the second reference resistor R2 The first end of the second memory unit M2 is connected to the second end of the first reference resistor R1 and the second end of the second reference resistor R2 respectively, and the second end of the first memory unit M1 is connected to the first controllable switch Q1 The second end is connected to the second end, the second end of the second memory unit M2 is connected to the second end of the second controllable switch Q2, the first end of the first controllable switch Q1 and the first end of the second controllable switch Q2 are respectively connected to the reference word line, The third end of the first controllable switch Q1 and the third end of the second controllable switch Q2 are grounded respectively;

The read array includes a first magnetic tunnel junction and NMOS transistors respectively connected to both ends of the first magnetic tunnel junction.

Specifically, the switch transistor Q4 is an NMOS transistor, the drain terminal is connected to the sense amplifier, the gate terminal is connected to the reference voltage Vref, and the source terminal is connected to the first terminal of the first reference resistor R1 and the first terminal of the second reference resistor R2. The range of the reference voltage Vref of the switch Q4 is between 0.3V and 1.0V.

The first reference resistor R1 and the second reference resistor R2 in this application are any of the following:

Poly resistor, well resistor, metal resistor.

Specifically, the resistance values of the first reference resistor R1 and the second reference resistor R2 may both be 3k ohms.

For ease of description, the two NMOS transistors in the read array are named as the first NMOS transistor Q31 and the second NMOS transistor Q32. Specifically, one end of the first magnetic tunnel junction is connected to the source end of the first NMOS transistor Q31, and the first The other end of the magnetic tunnel junction is connected to the drain end of the second NMOS transistor Q32, the drain end of the first NMOS transistor Q31 is connected to the sense amplifier, the gate end of the first NMOS transistor Q31 is connected to the clamping voltage Vclamp, and the The source terminal is grounded, and the gate terminal of the second NMOS transistor Q32 is connected to the word line WL.

Optionally, the first storage unit M1 and the second storage unit M2 are a second magnetic tunnel junction or a resistive storage unit, wherein an initial state of the second magnetic tunnel junction is an antiparallel state. For example, the first storage unit M1 and the second storage unit M2 are both second magnetic tunnel junctions, or the first storage unit M1 and the second storage unit M2 are both resistive storage units. The reason why the initial state of the second magnetic tunnel junction is the anti-parallel state is that the second magnetic tunnel junction in the anti-parallel state changes with temperature, while the parallel state does not change with temperature. Wherein, the initialization mode of the initial state of the second magnetic tunnel junction includes magnetic field initialization and writing circuit initialization.

When both the first storage unit M1 and the second storage unit M2 are second magnetic tunnel junction storage units, the preset resistance values of the first reference resistor R1 and the second reference resistor R2 are both the second magnetic tunnel junction storage unit. The parallel state resistance value of the tunnel junction, and the adjustment range of the preset resistance value is plus or minus 30% of the parallel state resistance value. Specifically, the parallel state resistance of the second magnetic tunnel junction may be 3.2k ohms, and the antiparallel state resistance of the second magnetic tunnel junction may be 8.636k ohms.

It should be noted that the resistive memory cells are not specifically limited in this application, and can be selected by themselves. For example, the resistive memory unit is a Resistive Random Access Memory (RRAM for short) or a Phase Change Random Access Memory (PCRAM for short).

It should also be noted that, in this application, the types of the first controllable switch Q1 and the second controllable switch Q2 are not specifically limited, depending on the situation. For example, the first controllable switch Q1 and the second controllable switch Q2 are any of the following:

NMOS tube, PMOS tube, transmission gate, triode.

The types of the first controllable switch Q1 and the second controllable switch Q2 are the same.

The first controllable switch Q1 and the second controllable switch Q2 are both NMOS transistors, and the circuit diagram when the first memory unit M1 and the second memory unit M2 are both the second magnetic tunnel junction is shown in FIG. 2 , the gate terminal of the NMOS transistor is shown in FIG. The reference word line WL_REF is connected, the source terminal is grounded, and the drain terminal is connected to the second magnetic tunnel junction.

The magnetic random access memory read circuit of the present application includes a sense amplifier, a reference array, and a read array. In addition to the switch Q4, the first reference resistor R1, and the second reference resistor R2, the reference array also includes a first storage unit M1 and a second storage unit. M2, the first controllable switch Q1, the second controllable switch Q2, the first storage unit M1, the second storage unit M2 are correspondingly connected to the first controllable switch Q1, the second controllable switch Q2, the first storage unit M1 and the second controllable switch Q2. Two memory cells M2 are connected in parallel, the first reference resistor R1 and the second reference resistor R2 are connected in parallel, and the first memory cell M1 and the second memory cell M2 connected in parallel are connected in series with the first reference resistor R1 and the second reference resistor R2 connected in parallel. In this application, the parallel first memory cell M1 and the second memory cell M2 are added as reference bits used for reference alone, and the parallel first memory cell M1 and the second memory cell M2 are used as a reference when reading the array, so that the reference array is The resistance value at different temperatures changes with the resistance value of the read array, and the direction and size of the resistance value change are basically the same, reducing the relative resistance change of the read array and the reference array. The resistance value of the reference array and the resistance value distribution of the read array There is no overlap, thereby increasing the reference voltage window and improving the read yield; in addition, the circuit structure in the present application is simple, and no additional writing circuit is required.

The present application further provides a magnetic random access memory, the magnetic random access memory including the magnetic random access memory read circuit described in the above embodiments.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The magnetic random access memory provided by the present application and the read circuit thereof have been introduced in detail above. Specific examples are used herein to illustrate the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

A magnetic random access memory read circuit, characterized in that it includes a sense amplifier, a reference array, and a read array;

The reference array includes a first reference resistor, a second reference resistor, a first storage unit, a second storage unit, a first controllable switch, a second controllable switch, and a switch tube; a first end of the first reference resistor, a second The first end of the reference resistor is respectively connected to the switch tube, the first end of the first storage unit is respectively connected to the second end of the first reference resistor and the second end of the second reference resistor, and the first end of the second storage unit is respectively connected to the The second end of the first reference resistor is connected to the second end of the second reference resistor, the second end of the first storage unit is connected to the second end of the first controllable switch, and the second end of the second storage unit is connected to the second controllable switch The second end is connected, the first end of the first controllable switch and the first end of the second controllable switch are respectively connected to the reference word line, and the third end of the first controllable switch and the third end of the second controllable switch are respectively grounded;

The read array includes a first magnetic tunnel junction and NMOS transistors respectively connected at both ends of the first magnetic tunnel junction.
The magnetic random access memory read circuit of claim 1, wherein the first storage unit and the second storage unit are a second magnetic tunnel junction or a resistive storage unit, wherein the second magnetic tunnel The initial state of the junction is the antiparallel state.
The magnetic random access memory read circuit according to claim 2, wherein the resistive memory unit is a resistive memory or a phase change memory.
The magnetic random access memory read circuit according to claim 2, wherein the initialization method of the initial state of the second magnetic tunnel junction includes magnetic field initialization and write circuit initialization.
The magnetic random access memory read circuit according to claim 2, wherein the preset resistance values of the first reference resistor and the second reference resistor are both parallel state resistance values of the second magnetic tunnel junction, And the adjustment range of the preset resistance value is plus or minus 30% of the parallel state resistance value.
The magnetic random access memory read circuit according to claim 1, wherein the first controllable switch and the second controllable switch are any of the following:

NMOS tube, PMOS tube, transmission gate, triode.
The magnetic random access memory read circuit according to claim 1, wherein the reference voltage of the switch tube is in the range of 0.3V to 1.0V.
The magnetic random access memory read circuit according to any one of claims 1 to 7, wherein the first reference resistor and the second reference resistor are any of the following:

Poly resistor, well resistor, metal resistor.
A magnetic random access memory, characterized in that the magnetic random access memory comprises the magnetic random access memory read circuit according to any one of claims 1 to 8.