TWI829271B - Semiconductor memory device - Google Patents

Abstract

In general, according to one embodiment, a memory device includes a first memory cell; and a control circuit. A first memory cell includes a first variable resistance element and a first switching element. A control circuit is configured to execute first detection of detecting a first value of a first physical quantity related to the first memory cell, execute first write for storing first data in the first memory cell, execute second detection of detecting a second value of the first physical quantity related to the first memory cell following the first write, and read second data related to the first memory cell based on the first value and the second value. At least one of the first value and the second value is a value during a change in the first physical quantity related to the first memory cell.

Description

semiconductor memory device

This application is based on Japanese Patent Application No. 2021-152414 filed on September 17, 2021 and US Patent Application No. 17/691198 filed on March 10, 2022, and claims priority rights thereto. , the entire contents of the Japanese patent application and the U.S. patent application are incorporated into this case for reference.

The embodiments described herein generally relate to a memory device.

Memory devices with magnetic elements are known.

Generally speaking, according to one embodiment, a memory device includes a first memory cell and a control circuit.

The first memory cell includes a first variable resistance element and a first switching element. The control circuit is configured to: perform a first detection of a first value of a first physical quantity associated with the first memory cell, and perform a first step for storing the first data in the first memory cell. Write, after the first write, perform a second detection of a second value of the first physical quantity associated with the first memory cell, and read the second value of the first physical quantity associated with the first memory cell based on the first value and the second value. Secondary information related to somatic cells. Between the first value and the second value At least one of is a value during a change of the first physical quantity associated with the first memory cell.

1. 1a: Memory device

2:Memory controller

3. 3a: Memory system

4: Host device (external device)

11: Core circuit

12: Line decoder

13: Column decoder

14: Command/address input circuit

15, 15a: Sequencer

16:Input/output circuit

151:Voltage generator

152: Group determination circuit

A1: Arrow/Direction

A2:Arrow

AMP: operational amplifier circuit

BL, BL0, BL1~BL(m-1): bit lines

CNT: external control signal

CPC, RPC: precharge circuit

CS1, CS2: current source

CTr0, CTr1~CTr(m-1), RTr0, RTr1~RTr(n-1), Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7, Tr8: transistor

CTS: line transfer switch group

CWD, RWD: write drive

D1: first direction

D2: second direction

D3: Third direction

DQ: data signal

GBL: global bit line

GWL: global character line

HRS: high resistance state

IMC, IS: current

LRS: low resistance state

MC: memory cell

MCA: memory cell array

RL, SL: ferromagnet (ferromagnetic layer)

RS: read slot

RTS: column transfer switch set

S: switching element

S1, S2, S3, S4, S5, S6, S7: control signal

SA: sense amplifier

SADOUT: signal

SW1, SW2, SW3: switch

T00, T01, T02, T03, T04, T04s, T11, T12, T21, T22, T23, T24, T24s, T30, T31, T32, T33, T34, T35, T41, T42, T51, T52, T53, T54, T55, △t1, △t1f, △t1n, △t2, △t2f, △t2n, △t3, △t3f, △t3n, △th, △ts: time

TB: non-magnetic body (non-magnetic layer)

V1, VBLP, VCLMP, Veval, VHH, VhldL, VhldH, VMC, VPRE, VS, VSB, Vsmpl, VSS, VWT: Voltage

V2: Positive voltage/voltage

VD1, VD1x, VD2, VD2x: voltage difference

WL, WL0, WL1~WL(n-1): word lines

FIG. 1 is a block diagram showing an example of the configuration of the memory device according to the first embodiment.

2 is a block diagram showing an example of the configuration of a core circuit of the memory device according to the first embodiment.

3 is a diagram showing an example of a circuit configuration of a memory cell array of the memory device according to the first embodiment.

4 is a diagram showing an example of a part of the structure of a memory cell array of the memory device according to the first embodiment.

5 is a cross-sectional view showing an example of the configuration of a specific memory cell of the memory device according to the first embodiment.

FIG. 6 is a diagram illustrating an example of a graph representing current-voltage (I-V) characteristics of a switching element of a memory cell.

FIG. 7 is a diagram showing an example of a graph showing the I-V characteristics of a memory cell.

8 is a diagram illustrating each of a specific write driver, a specific precharge circuit, a sense amplifier, another write driver, another precharge circuit, and a read slot of the memory device according to the first embodiment. Diagram of an example circuit configuration.

9 is a diagram illustrating an example of a timing chart illustrating the timing applied to and selected when the memory device according to the first embodiment performs a specific read operation. The time changes of the voltages of the bit lines and word lines corresponding to the memory cells.

FIG. 10 is a diagram for explaining the timing of voltage sampling performed by the sense amplifier of the memory device according to the first embodiment in the first sensing operation and the second sensing operation.

FIG. 11 is a diagram for explaining further advantageous effects obtainable by the memory device according to the first embodiment.

12 is a diagram illustrating an example of a timing diagram illustrating an application to a bit corresponding to a selected memory cell when the memory device according to the modification of the first embodiment performs a specific read operation. The time variation of the voltage of the element line and the word line.

13 is a diagram for explaining the timing of voltage sampling performed by the sense amplifier of the memory device according to the modification of the first embodiment in the first sensing operation and the second sensing operation.

14 is a block diagram showing an example of the configuration of the memory device according to the second embodiment.

15 is a diagram illustrating an example of the layout of various interconnections that may be used as voltage transfer paths to each memory cell of the memory device according to the second embodiment.

16 is a diagram for explaining grouping of memory cells for timing control performed in a read operation by the memory device according to the second embodiment.

17 is a diagram for explaining the timing of voltage sampling performed by the sense amplifier of the memory device according to the second embodiment in the first sensing operation and the second sensing operation.

Hereinafter, embodiments will be explained with reference to the drawings. In the following description, components with the same function and configuration are designated by the same reference numbers. When distinguishing between multiple components having a common reference number, a suffix is added to the common reference number to differentiate. In cases where there is no need to specifically distinguish a plurality of components, then only a common reference number is appended to the plurality of components without appending a suffix.

Each functional block can be implemented by either hardware and software or a combination of both. Additionally, it is not important to differentiate functional blocks as described below. For example, some functions may be performed by functional blocks that differ from the example functional blocks. Additionally, the exemplary functional blocks may be divided into more granular functional sub-blocks. In addition, the names of functional blocks and components in the following description are for convenience, but do not limit the configuration and operation of functional blocks and components.

<First Embodiment>

In the following, the memory device 1 according to the first embodiment will be explained.

[Configuration example]

(1)Memory device

FIG. 1 is a block diagram showing an example of the configuration of the memory device 1 according to the first embodiment.

The memory device 1 according to the first embodiment can store data in a non-volatile manner. More specifically, the memory device 1 is, for example, a perpendicularly magnetized magnetoresistive memory device (magnetoresistive random access memory (MRAM)) using a variable resistance element as a memory element. Variable resistance elements are utilized through magnetic tunnel junction (MTJ) Tunneling magnetoresistance (TMR) effect. The TMR effect is a phenomenon in which, for example, the magnetization direction of a ferromagnet changes due to the application of a magnetic field or electric current, whereby when a tunneling current flows, the resistance of the element changes.

In FIG. 1 , in addition to the memory device 1 , a memory controller 2 and a host device 4 are also shown. The memory device 1 and the memory controller 2 constitute the memory system 3 .

The memory controller 2 receives a host command from a host device (external device) 4 such as a personal computer, and controls the memory device 1 based on the host command. Under the control, various operations are performed, such as operations of storing data in the memory device 1 (hereinafter referred to as write operations) and operations of reading data from the memory device 1 (hereinafter referred to as read operations). fetch operation).

The signals transmitted between the memory controller 2 and the memory device 1 related to the control will be explained.

Memory controller 2 is coupled to memory device 1 via a memory bus. The memory bus transmits data signals DQ and external control signals CNT, for example. The data signal DQ includes writing data or reading data. The external control signal CNT includes, for example, command and address information.

Next, details of the configuration of the memory device 1 will be explained.

The memory device 1 includes a core circuit 11 , a row decoder 12 , a column decoder 13 , a command/address input circuit 14 , a sequencer 15 and an input/output circuit 16 .

Core circuit 11 includes a plurality of non-volatile memory cells associated with word lines and bit lines. Character lines include global character lines and local character lines. Bit lines include global bit lines and local bit lines. In the following, local character lines are simply referred to as character lines. Similarly, local bit lines are simply called bit lines. In the write operation, the write data is stored in the memory cells of the core circuit 11 . In a read operation, read data is read from the memory cells in the core circuit 11 .

The command/address input circuit 14 receives the external control signal CNT transmitted from the memory controller 2 and transmits the command and address information in the external control signal CNT to the sequencer 15 .

The sequencer 15 controls the memory device 1 based on the transmitted commands and address information. For example, the sequencer 15 controls the core circuit 11, the row decoder 12, the column decoder 13, the input/output circuit 16 and similar components to perform various operations such as write operations and read operations.

The sequencer 15 includes a voltage generator 151 . The voltage generator 151 generates various voltages for write operations, read operations, and the like. The sequencer 15 supplies the voltage generated by the voltage generator 151 to the core circuit 11 .

The input/output circuit 16 receives the write data in the data signal DQ transmitted from the memory controller 2 and transmits the write data to the core circuit 11 . The input/output circuit 16 also receives read data from the core circuit 11 and temporarily holds the read data. The input/output circuit 16 transmits the read data to the memory controller 2 .

Row decoder 12 receives address information from sequencer 15 . row decoder 12 A signal related to the selection of the bit line is generated based on the address information and transmitted to the core circuit 11 .

The column decoder 13 receives address information from the sequencer 15 . The column decoder 13 generates a signal related to word line selection based on the address information, and transmits the signal to the core circuit 11 .

(2)Core circuit

FIG. 2 is a block diagram showing an example of the configuration of the core circuit 11 of the memory device 1 according to the first embodiment.

The core circuit 11 includes a memory cell array MCA, a column transfer switch group CTS, a write driver CWD, a precharge circuit CPC, a sense amplifier SA, a row transfer switch group RTS, Write driver RWD, precharge circuit RPC and read sink RS.

The memory cell array MCA includes the above-mentioned plurality of memory cells.

The write driver CWD, the precharge circuit CPC, the sense amplifier SA and the row transfer switch group CTS are coupled to the global bit line GBL. The row transfer switch group CTS is coupled to a plurality of memory cells in the memory cell array MCA via a plurality of bit lines. A single memory cell is coupled to a single bit line.

For example, the row transfer switch set CTS self-decoder 12 receives a signal related to the selection of a bit line and, based on the signal, couples the bit to the memory cell that is the target of an operation performed by the memory device 1 The element line is electrically coupled to the global bit line GBL.

Write driver CWD controls the current flowing through global bit line GBL during write operations. Electrical current flows through the memory cell that is the target of the write operation. Therefore, the write data received by the input/output circuit 16 and transmitted to the core circuit 11 can be written to the write target memory cell.

The precharge circuit CPC applies a specific voltage supplied from the sequencer 15 to the global bit line GBL, for example during a read operation. The voltage is transferred to, for example, a bit line BL coupled to the memory cell that is the target of a read operation.

The sense amplifier SA applies a voltage based on a specific voltage supplied from the sequencer 15 to the global bit line GBL, for example during a read operation. The voltage is transferred to, for example, a bit line BL coupled to the memory cell that is the target of a read operation. Additionally, the sense amplifier SA detects the voltage associated with the memory cell that is the target of the read operation via the global bit line GBL during the read operation. Therefore, the sense amplifier SA reads the data stored in the memory cell and transmits the read data to the input/output circuit 16 .

The write driver RWD, the precharge circuit RPC, the read slot RS and the column transfer switch group RTS are coupled to the global word line GWL. The column transfer switch group RTS is coupled to a plurality of memory cells in the memory cell array MCA via a plurality of word lines. A single memory cell is coupled to a single word line.

For example, the column transfer switch set RTS receives a signal related to the selection of a word line from the column decoder 13 and based on the signal will be coupled with the memory cell that is the target of the operation performed by the memory device 1 The word lines are electrically coupled to the global word lines GWL.

The write driver RWD controls the current flowing through the global word line GWL during write operations. Electrical current flows through the memory cell that is the target of the write operation.

The precharge circuit RPC applies a specific voltage supplied from the sequencer 15 to the global word line GWL, for example during a read operation. The voltage is transferred to, for example, a word line WL coupled to the memory cell that is the target of a read operation.

The read slot RS fixes the potential of the word line coupled to the memory cell that is the target of the read operation via the global word line GWL to, for example, ground potential during the read operation.

(3) Memory cell array

FIG. 3 shows an example of the circuit configuration of the memory cell array MCA of the memory device 1 according to the first embodiment. In FIG. 3 , in addition to the circuit configuration of the memory cell array MCA, an example of the circuit configuration of the row transfer switch group CTS and the column transfer switch group RTS is also shown.

First, the circuit configuration of the row transfer switch group CTS and the column transfer switch group RTS will be explained.

The row transmission switch group CTS includes transistors CTr0, CTr1, ... and CTr(m-1) (m is an integer of 1 or greater than 1). Each of the transistors is, for example, a field effect transistor (FET), such as an n-channel metal oxide semiconductor (MOS) transistor. Unless otherwise stated, this also applies to components called transistors in this specification.

A first terminal of transistor CTr0 is coupled to global bit line GBL, and a second terminal of transistor CTr0 is coupled to bit line BL0. The first terminal of transistor CTr1 is also coupled is coupled to global bit line GBL, and the second end of transistor CTr1 is coupled to bit line BL1. This also applies below, and finally, the first end of transistor CTr(m-1) is also coupled to global bit line GBL, and the second end of transistor CTr(m-1) is coupled to bit line BL( m-1). In this way, the first terminals of the transistors CTr0 to CTr(m-1) are commonly coupled to the global bit line GBL, and the second terminals of the transistors CTr0 to CTr(m-1) are in a one-to-one relationship. are coupled to bit lines BL0 to BL(m-1) respectively.

For example, a voltage based on a signal related to the selection of a bit line is applied to the control gates (hereinafter also referred to as gates or control terminals) of transistors CTr0 to CTr(m-1). Therefore, the bit line BL coupled to the memory cell that is the target of the operation performed by the memory device 1 is electrically coupled to the global bit line GBL.

The column transfer switch group RTS includes transistors RTr0, RTr1, ... and RTr(n-1) (n is an integer of 1 or greater than 1).

A first terminal of transistor RTr0 is coupled to global word line GWL, and a second terminal of transistor RTr0 is coupled to word line WL0. A first terminal of transistor RTr1 is also coupled to global word line GWL, and a second terminal of transistor RTr1 is coupled to word line WL1. This also applies below, and finally, the first end of transistor RTr(n-1) is also coupled to global word line GWL, and the second end of transistor RTr(n-1) is coupled to word line WL( n-1). In this way, the first terminals of the transistors RTr0 to RTr(n-1) are commonly coupled to the global word line GWL, and the second terminals of the transistors RTr0 to RTr(n-1) are in a one-to-one relationship. Coupled to word lines WL0 to WL(n-1) respectively.

For example, a voltage based on a signal related to word line selection is applied to the gates of transistors RTr0 to RTr(n-1). Therefore, and as determined by the memory device 1. The word line WL coupled to the memory cell of the target operation is electrically coupled to the global word line GWL.

Next, the circuit configuration of the memory cell array MCA will be explained.

The memory cell array MCA includes a plurality of memory cells MC. The coupling relationship of these memory cells MC is as follows. That is, for each combination of a single bit line BL of bit lines BL0 to BL(m-1) and a single word line WL of word lines WL0 to WL(n-1), a single memory cell MC Coupled between bit line BL and word line WL. It should be noted that in the following, the word line WL and the bit line BL coupled to a specific memory cell MC are also referred to as the word line WL and the bit line BL corresponding to the memory cell MC, respectively.

FIG. 4 shows an example of a part of the structure of the memory cell array MCA of the memory device 1 according to the first embodiment.

A plurality of word lines WL are provided in a specific interconnection (or wiring) layer. Each word line WL extends in the first direction D1. The plurality of word lines WL are sequentially arranged adjacent to each other with intervals along the second direction D2. The second direction D2 intersects the first direction D1 and is, for example, orthogonal to the first direction D1.

A plurality of bit lines BL are provided in another interconnection layer. Each bit line BL extends in the second direction D2, for example. For example, the plurality of bit lines BL are sequentially arranged adjacent to each other with a spacing along the first direction D1.

For each combination of a single word line WL and a single bit line BL, a single memory cell MC coupled to the word line WL and the bit line BL is provided between the word line WL and the bit line BL.

The memory cell MC includes MTJ elements stacked along the third direction D3 (in the drawing, the reference symbol MTJ is given) and the switch element S. For example, the third direction D3 intersects the first direction D1 and the second direction D2, and is, for example, orthogonal to the first direction and the second direction. The MTJ element is coupled to, for example, word line WL, and the switching element S is coupled to, for example, bit line BL.

Although FIG. 4 shows an example of a part of the structure of the memory cell array MCA, an interconnection layer in which the word line WL is provided or an interconnection layer in which the bit line BL is provided may be provided on the upper layer. FIG. 4 shows an example in which, regarding the MTJ element and the switching element S included in the memory cell MC, the MTJ element is disposed on the word line WL side, and the switching element S is disposed on the bit line BL side. This embodiment is not limited to the above content. The MTJ element may be disposed on the bit line BL side, and the switching element S may be disposed on the word line WL side.

(4) Memory cells

In the following, the configuration of a specific memory cell of the memory device 1 according to the first embodiment will be explained. In the following, a single memory cell MC will be explained as an example, but the same description holds for each of the other memory cells MC.

FIG. 5 is a cross-sectional view showing an example of the configuration of a specific memory cell MC of the memory device 1 according to the first embodiment.

As already explained with reference to FIG. 4 , the memory cell MC includes an MTJ element as a variable resistance element and a switching element S. For example, the first terminal of the switching element S is coupled to the bit line BL, and the second terminal of the switching element S is coupled to the third terminal of the MTJ element. One end, and the second end of the MTJ element is coupled to word line WL.

The switching element S is, for example, a switching element located between two terminals. When the voltage applied between the two terminals is less than a threshold value, the switching element is in an off state, such as a high resistance state. When the voltage applied between the two terminals is equal to or greater than the threshold value, the switching element is in a conductive state, for example, a low resistance state. Regardless of the polarity of the voltage, the switching element can perform this function.

As the switching element in the present embodiment, a switching element having the following characteristics: the resistance value rapidly decreases at a specific voltage, and therefore, the applied voltage rapidly decreases and the current increases (snap back). It should be noted that the material used for the switching element having such characteristics is appropriately selected and used according to the characteristics of the memory cell. The operation will be explained later.

The MTJ element includes a ferromagnetic body (ferromagnetic layer) SL, a non-magnetic body (non-magnetic layer) TB, and a ferromagnetic body (ferromagnetic layer) RL. The three layers: ferromagnetic SL, non-magnetic TB and ferromagnetic RL are stacked from the first end side toward the second end side of the MTJ element in the order of, for example, ferromagnetic SL, non-magnetic TB and ferromagnetic RL.

The non-magnetic body TB serves, for example, as a tunnel barrier layer. That is, the ferromagnetic body SL, the non-magnetic body TB, and the ferromagnetic body RL form a magnetic tunnel junction. The ferromagnetic RL has a fixed magnetization in a specific direction and serves, for example, as a reference layer. Here, "fixed magnetization" means that the magnetization direction does not change due to a current (spin torque) of a magnitude that switches the magnetization direction of the ferromagnetic body SL. The ferromagnetic SL is a ferromagnetic layer with a variable magnetization direction, and serves as a storage layer. Here, "variable magnetization" means a current whose magnetization direction can switch the magnetization direction of the ferromagnetic body SL due to its magnitude. (spin torque) changes.

The set of ferromagnetic SL, non-magnetic TB and ferromagnetic RL exhibits the TMR effect. The TMR effect refers to the phenomenon in which a structure including two ferromagnets sandwiching an insulator depends on whether the magnetization directions of the two ferromagnets are parallel (P) or antiparallel (AP). and exhibit different resistance values. When the magnetization directions of the two ferromagnets are parallel, the structure exhibits a lower resistance than when the magnetization directions of the two ferromagnets are anti-parallel.

In the case where the magnetization direction of the ferromagnetic body RL is parallel to the magnetization direction of the ferromagnetic body SL, the resistance value of the MTJ element is lower than the resistance value in the case where the two magnetization directions are anti-parallel. That is, the MTJ element is set to the low resistance state LRS. The low resistance state LRS is also called the "parallel (P) state". For example, data "0" is defined as being stored in a memory cell MC that includes an MTJ element in a low resistance state LRS.

In the case where the magnetization direction of the ferromagnetic body RL is anti-parallel to the magnetization direction of the ferromagnetic body SL, the resistance value of the MTJ element is higher than the resistance value in the case where the two magnetization directions are parallel. That is, the MTJ element is set to the high resistance state HRS. The high resistance state HRS is also called the "antiparallel (AP) state". For example, data "1" is defined as being stored in a memory cell MC that includes an MTJ element in a high resistance state HRS.

In the following description, for the purpose of simplifying the description, it is assumed that when the MTJ element is in the low resistance state LRS, the memory cell MC including the MTJ element is also in the low resistance state LRS, and when the MTJ element is in the high resistance state HRS ,include The memory cell MC of the MTJ element is also in the high resistance state HRS.

The MTJ element shown in Figure 5 is only an example, and the MTJ element may include further layers in addition to the layers described above. In addition, the coupling relationship between the MTJ element and the switching element S shown in FIG. 5 is only an example, and this embodiment is not limited thereto. For example, the stacking order of the ferromagnetic body SL, the non-magnetic body TB, and the ferromagnetic body RL of the MTJ element may be reversed from the above-mentioned order. In addition, the order in which the switching element S and the MTJ element are coupled between the bit line BL and the word line WL can be reversed from the above order.

Next, the ferromagnetic body SL, the non-magnetic body TB, and the ferromagnetic body RL will be further explained. The non-magnetic body TB exhibits, for example, insulating properties and contains non-magnetic material. For example, the non-magnetic body TB contains oxygen and magnesium or magnesium oxide (MgO).

The ferromagnetic body SL is electrically conductive and contains ferromagnetic material. For example, the ferromagnet SL includes iron cobalt boron (FeCoB) or iron boride (FeB).

The ferromagnetic RL is electrically conductive and includes a ferromagnetic material having an easy magnetization axis in a direction perpendicular to the interface between the ferromagnetic RL and another layer. For example, the ferromagnetic body RL contains iron cobalt boron (FeCoB) as a ferromagnetic body with perpendicular magnetization. The ferromagnet RL may include at least one of cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd).

The magnetization direction of the ferromagnet RL is fixed and faces the direction on the SL side of the ferromagnet or the opposite direction (in the example shown in Figure 5, it faces the opposite side of the SL side of the ferromagnet).

The magnetization direction of the ferromagnetic body SL can be switched along the easy magnetization axis, and data is written into the memory cell MC by switching the magnetization direction of the ferromagnetic body SL. For this purpose, a spin-injection writing method may be applied to the memory device 1 . In the spin injection writing method, a writing current is applied to the MTJ element, and the magnetization direction of the ferromagnetic body SL is controlled by the writing current. That is, the spin transfer torque (STT) effect generated by the write current is used.

When a write current is applied to the MTJ element in the direction of the arrow A1 shown in FIG. 5, that is, in the direction from the ferromagnetic body SL toward the ferromagnetic RL, the magnetization direction of the ferromagnetic body SL becomes relative to that of the ferromagnetic body RL. The magnetization direction is parallel. When a write current is applied to the MTJ element in the direction of the arrow A2 shown in FIG. 5, that is, in the direction from the ferromagnetic RL toward the ferromagnetic SL, the magnetization direction of the ferromagnetic SL becomes relative to that of the ferromagnetic RL. The magnetization direction is antiparallel.

FIG. 6 shows an example of a graph showing the current-voltage (I-V) characteristics of the switching element S of the memory cell MC. The horizontal axis of the graph represents the voltage VS applied to the switching element S. The vertical axis of the graph represents the current IS flowing through the switching element S. The current IS flowing in a specific direction is defined as a positive current, and the voltage applied to the switching element S so that the current IS flows in the specific direction is defined as a positive voltage.

For example, a case will be described where the voltage applied to the memory cell MC is changed such that the voltage VS gradually increases from zero volts (V).

Current IS continues to increase until voltage VS reaches voltage V1. When the voltage VS reaches the voltage V1, the switching element S changes from the off state to the on state, and the magnitude of the resistance of the MTJ element changes in the resistance of the entire memory cell MC. Have to dominate. Therefore, the magnitude of the voltage applied to the switching element S decreases and, for example, the voltage VS transitions from the voltage V1 to the positive voltage V2. On the other hand, when the switching element transitions to the conductive state, the current IS increases rapidly. The voltage VS and current IS at this time can also be regarded as following the negative resistance area in the graph shown in Figure 6. For example, the sense amplifier SA does not detect the current IS before the rapid increase, but may detect the current IS after the rapid increase.

Subsequently, in the case where the voltage applied to the memory cell MC is changed to lower the voltage VS, when the voltage VS reaches the voltage V2, the switching element S changes from the on state to the off state, and the current IS rapidly decreases. For example, the sense amplifier SA does not detect the current IS after the rapid decrease.

As shown in the graph shown in FIG. 6, when the sign of the voltage VS applied to the switching element S is reversed, the sign of the current IS is reversed. That is, the switching element S has I-V characteristics that are symmetrical to each other in two directions (positive direction and negative direction).

FIG. 7 shows an example of a graph showing the I-V characteristics of the memory cell MC. The horizontal axis of the graph represents voltage VMC, which has the magnitude of the voltage applied to memory cell MC (the potential difference between the corresponding bit line BL and word line WL). The vertical axis of the graph represents the current IMC on a logarithmic scale with the magnitude of the cellular current flowing through the memory cell MC. The portion indicated by the dotted line in the graph shown in FIG. 7 indicates virtual characteristics that do not actually appear.

First, the following description holds for both the case in which the memory cell MC is in the high resistance state HRS and the case in which the memory cell MC is in the low resistance state LRS.

As voltage VMC gradually increases, current IMC continues to increase until voltage VMC reaches voltage VSB (region (a) shown in Figure 7). When voltage VMC is further increased, the function of the graph has a discontinuity at the point where voltage VMC is voltage VSB. That is, when voltage VMC reaches voltage VSB, current IMC increases rapidly. After such a rapid increase in current IMC, current IMC changes continuously with respect to any change in the magnitude of voltage VMC, and the greater the voltage VMC, the greater the current IMC (shown in area (b) in Figure 7). For example, the sense amplifier SA does not detect the current IMC before the rapid increase, but may detect the current IMC after the rapid increase.

Next, a case in which the memory cell MC is in the high resistance state HRS and a case in which the memory cell MC is in the low resistance state LRS will be explained in a comparative manner.

Before the current IMC increases rapidly, the current IMC is substantially the same when the memory cell MC is in the low resistance state LRS and when the memory cell MC is in the high resistance state HRS. This is for the reasons explained below.

The above rapid increase in the current IMC is caused by the switching element S in the memory cell MC transitioning from the off state to the on state and thus becoming conductive. Before the current IMC increases rapidly, the switching element S is in an off state, and therefore the resistance of the switching element S is much greater than that of the MTJ element. Therefore, before the current IMC increases rapidly, the magnitude of the resistance of the switching element S dominates the resistance of the entire memory cell MC, and the situation in which the memory cell MC is in the low resistance state LRS is the same as the situation in which the memory cell MC is in the low resistance state LRS. The resistance of the memory cell MC is substantially the same between the cases where the body cell MC is in the high resistance state HRS.

On the other hand, after the current IMC increases rapidly above, when a specific voltage is applied to the memory cell MC, the current IMC when the MTJ element is in the low resistance state LRS is greater than the current IMC when the MTJ element is in the high resistance state HRS. This is because when the switching element S is in the on state, the resistance of the MTJ element dominates the resistance of the entire memory cell MC.

A case will be explained in which the voltage VMC decreases after the current IMC increases rapidly. As will be explained below, as voltage VMC decreases, the function of the graph has a discontinuity at the point where voltage VMC is a specific voltage.

When the memory cell MC is in the low resistance state LRS, when the voltage VMC reaches the voltage VhldL, the current IMC decreases rapidly. On the other hand, when the memory cell MC is in the high resistance state HRS, when the voltage VMC reaches the voltage VhldH, the current IMC decreases rapidly. Voltages VhldL and VhldH are each less than voltage VSB. Voltage VhldH is greater than voltage VhldL. After such a rapid decrease in current IMC, current IMC changes according to the I-V characteristic on which current IMC was based before the above-mentioned rapid increase in current IMC (region (a) shown in FIG. 7). This means that the switching element S has changed from the on state to the off state. For example, the sense amplifier SA does not detect the current IMC after the rapid decrease.

(5) Circuits related to applying voltage to memory cells

8 illustrates each of the write driver CWD, precharge circuit CPC, sense amplifier SA, write driver RWD, precharge circuit RPC, and read slot RS of the memory device 1 according to the first embodiment. Examples of circuit configurations. The circuit configurations set forth below are examples only, and another circuit configuration achieving equivalent functionality may be used. Set. In the following description, a specific memory cell MC that is the target of a read operation or a write operation is also referred to as a selected memory cell MC.

The write driver CWD includes, for example, a current source CS1, a transistor Tr1, and a transistor Tr2. The transistor Tr1 is, for example, a p-channel MOS transistor.

Voltage VHH is applied to the input terminal of current source CS1, and the output terminal of current source CS1 is coupled to the first terminal of transistor Tr1. Voltage VHH is supplied by, for example, an external power supply.

The second terminal of transistor Tr1 is coupled to global bit line GBL. The control signal S1 is input to the gate of the transistor Tr1. The control signal S1 is supplied by, for example, the sequencer 15 . This also applies to other control signals explained in the following description as input to the gate of a specific transistor Tr.

The first terminal of the transistor Tr2 is coupled to the global bit line GBL, while the second terminal of the transistor Tr2 is, for example, grounded. The control signal S2 is input to the gate of the transistor Tr2. Every component stated as being grounded in this specification need not be grounded, and it is sufficient if, for example, each component is at a low reference potential among several reference potentials used in the memory device 1 .

The precharge circuit CPC includes, for example, a transistor Tr3. Voltage VPRE is applied to a first terminal of transistor Tr3, and a second terminal of transistor Tr3 is coupled to global bit line GBL. The control signal S3 is input to the gate of the transistor Tr3. Voltage VPRE is supplied by, for example, an external power supply or voltage generator 151 .

The sense amplifier SA includes, for example, a transistor Tr4, switches SW1, SW2, and SW3, and an operational amplifier circuit AMP.

For example, voltage VHH is applied to a first terminal of transistor Tr4, and a second terminal of transistor Tr4 is coupled to the first terminal of switch SW1. Voltage VCLMP is applied to the gate of transistor Tr4. For example, the voltage VHH is supplied by an external power supply, and the voltage VCLMP is supplied by the voltage generator 151 . For example, the voltage applied to the bit line BL corresponding to the selected memory cell MC during a read operation is determined by the voltage VHH and the voltage VCLMP.

The second terminal of switch SW1 is coupled to global bit line GBL. The switch SW1 is, for example, a switching element located between two terminals, and can transmit a voltage between the first terminal and the second terminal while the switch SW1 is in a conductive state. The switch SW1 is, for example, a field effect transistor, such as an n-channel MOS transistor. In this specification, explanation will be made assuming that the switch SW1 is an n-channel MOS transistor. Unless otherwise stated, this also applies to other switches SW.

A certain control signal is input to the control gate of the switch SW1 (hereinafter, also referred to as the gate or control terminal). The control signal is supplied by the sequencer 15, for example. This also applies to other control signals explained in the following description as input to the gate of a particular switch SW.

A first terminal of the switch SW2 is coupled to the global bit line GBL, and a second terminal of the switch SW2 is coupled to the non-inverting input terminal of the operational amplifier circuit AMP. A specific control signal is input to the gate of switch SW2. Reference will be made to the reference symbol Vsmpl shown in FIG. 8 in the description of the operation example.

A first terminal of the switch SW3 is coupled to the global bit line GBL, and a second terminal of the switch SW3 is coupled to the inverting input terminal of the operational amplifier circuit AMP. specific control The control signal is input to the gate of switch SW3. In the description of the operation example, reference will be made to the reference symbol Veval shown in FIG. 8 .

The operational amplifier circuit AMP amplifies the voltage applied to the non-inverting input terminal based on the voltage applied to the inverting input terminal, and outputs a signal SADOUT that is a result of the amplification. Reading data is based on signal SADOUT.

The write driver RWD includes, for example, a current source CS2, a transistor Tr5, and a transistor Tr6. The transistor Tr5 is, for example, a p-channel MOS transistor.

For example, the voltage VHH is applied to the input terminal of the current source CS2, and the output terminal of the current source CS2 is coupled to the first terminal of the transistor Tr5. Voltage VHH is supplied by, for example, an external power supply.

The second terminal of the transistor Tr5 is coupled to the global word line GWL. The control signal S4 is input to the gate of the transistor Tr5.

The first terminal of the transistor Tr6 is coupled to the global word line GWL, and the second terminal of the transistor Tr6 is, for example, grounded. The control signal S5 is input to the gate of the transistor Tr6.

The precharge circuit RPC includes, for example, a transistor Tr7. For example, voltage VPRE is applied to a first terminal of transistor Tr7, and a second terminal of transistor Tr7 is coupled to global word line GWL. The control signal S6 is input to the gate of the transistor Tr7. Voltage VPRE is supplied by, for example, an external power supply or voltage generator 151 .

The read slot RS includes, for example, a transistor Tr8. The first terminal of the transistor Tr8 is coupled to the global word line GWL, and the second terminal of the transistor Tr8 is, for example, grounded. The control signal S7 is input to the gate of the transistor Tr8.

[Operation example]

Hereinafter, an operation example in which the memory device 1 according to the first embodiment performs a specific read operation will be explained. The read operation may also be called, for example, a self-reference read operation.

FIG. 9 shows an example of a timing chart illustrating the bit lines BL and words applied to the selected memory cell MC when the memory device 1 according to the first embodiment performs a read operation. Time variation of the voltage of element line WL. The bit line BL and the word line WL mentioned in the description of the operating example are respectively the bit line BL and the word line WL corresponding to the selected memory cell MC. The reading operation set forth below is only an example, and the reading operation according to the present embodiment is not limited thereto.

In the read operation, the first sensing operation, the first writing operation and the second sensing operation are sequentially performed on the selected memory cell MC, and after the second sensing operation, it is determined that the first sensing operation The data stored in the selected memory cell MC at the beginning of the operation. The second write operation may also be performed based on the determination result.

In the following description, where control of the voltage applied to a particular interconnection is stated, the control stated with respect to that interconnection continues unless it is expressly stated that another control is subsequently exercised over that interconnection.

In the following description, the application of the voltage to the word is achieved, for example, by the sequencer 15 controlling the column decoder 13, the write driver RWD, the precharge circuit RPC, the read slot RS and the column transfer switch group RTS. Yuan line WL. Applying the voltage to Bit line BL.

At time T00 before the read operation begins, voltage VPRE is applied to each of bit line BL and word line WL. The application of voltage VPRE is achieved by turning the transistors Tr3 and Tr7 of the precharge circuits CPC and RPC into a conductive state.

First, the control performed in the first sensing operation will be explained.

At time T01, while voltage VPRE is applied to word line WL, the voltage applied to bit line BL is increased from voltage VPRE to voltage VBLP. Voltage VBLP may be applied by turning switch SW1 of sense amplifier SA into a conductive state. The difference between voltage VBLP and voltage VPRE is less than voltage VSB (Figure 7).

After the potential of the bit line BL (hereinafter, also referred to as a voltage) is stabilized due to the application of the voltage VBLP, at time T02 , the switch SW1 of the sense amplifier SA is transitioned to the off state, and the bit line BL in a floating state.

Subsequently, at time T03, while the bit line BL remains in the floating state, the voltage applied to the word line WL is reduced from the voltage VPRE to the voltage VSS. The voltage VSS can be applied by turning the transistor Tr8 of the read slot RS into a conductive state. The voltage VSS is, for example, ground voltage.

When the voltage of word line WL is reduced by the application of voltage VSS, the voltage difference between bit line BL and word line WL exceeds voltage VSB. As mentioned above, when the voltage difference reaches the voltage VSB, the switching element S in the selected memory cell MC changes from the off state to the on state and becomes conductive, and flows through the cells of the selected memory cell MC. The current increases rapidly. The cell current is read via word line WL and The transistor Tr8 of the slot RS flows out from the bit line BL. Therefore, the voltage of bit line BL decreases. In Figure 9, the time when the reduction starts is represented as time T04.

The decrease in the voltage of bit line BL results in a decrease in the voltage difference between bit line BL and word line WL. In the case where the selected memory cell MC is, for example, in the high resistance state HRS, when the voltage difference decreases to reach the voltage VhldH (Fig. 7), the cell current decreases rapidly, and therefore the voltage of the bit line BL stabilizes change. That is, the voltage of the bit line BL is stabilized at a voltage higher than the voltage of the word line WL to which the voltage VSS is applied by the voltage VhldH. In the following, the case where the selected memory cell MC is in the high resistance state HRS at the beginning of the first sensing operation will be explained.

The control performed in the subsequent first write operation will be explained.

At time T11, for example, the write current supplied from the current source CS1 of the write driver CWD is controlled to flow through the bit line BL, the selected memory cell MC, and the word line WL in the order of occurrence. This is achieved when the transistor Tr1 of the write driver CWD transitions to the on state and the transistor Tr2 transitions to the off state, and the transistor Tr6 of the write driver RWD transitions to the on state and the transistor Tr5 transitions to the off state. kind of effect. The write current serves as the write current flowing in the direction A1 of the example shown in FIG. 5, and therefore, the MTJ element transitions to the low resistance state LRS, that is, the selected memory cell MC transitions to the low resistance state LRS. FIG. 9 shows that when the write current flows as described above, the voltage of the bit line BL once becomes the voltage VWT, and the voltage of the word line WL is VSS. For example, the difference between voltage VWT and voltage VSS is greater than voltage VSB. While the writing current flows, the voltage of the bit line BL is shown to be constant in FIG. 9 , but is not necessarily constant.

Subsequently, at time T12, voltage VPRE is applied to each of bit line BL and word line WL. As explained in connection with time T00, the application of voltage VPRE is achieved by precharge circuits CPC and RPC. At this time, the transistor Tr1 of the write driver CWD and the transistor Tr6 of the write driver RWD transition to the off state.

The control performed in the subsequent second sensing operation will be explained.

At time T21, as explained in connection with time T01, while voltage VPRE is applied to word line WL, the voltage applied to bit line BL is increased from voltage VPRE to voltage VBLP.

As explained in connection with time T02, after the voltage of bit line BL stabilizes due to the application of voltage VBLP, bit line BL is in a floating state at time T22.

Subsequently, at time T23, as explained in conjunction with time T03, the voltage applied to word line WL is reduced from voltage VPRE to voltage VSS while bit line BL remains in the floating state.

While the voltage of word line WL decreases due to the application of voltage VSS, the voltage difference between bit line BL and word line WL exceeds voltage VSB. As described above, when the voltage difference reaches the voltage VSB, the voltage of the bit line BL decreases as in the first sensing operation. In Figure 9, the time when the reduction starts is represented as time T24.

The decrease in the voltage of bit line BL results in a decrease in the voltage difference between bit line BL and word line WL. When the voltage difference decreases to reach voltage VhldL (Figure 7), The cell current decreases rapidly, and thus the voltage of bit line BL stabilizes. That is, the voltage of the bit line BL is stabilized at a voltage higher than the voltage of the word line WL to which the voltage VSS is applied by the voltage VhldL.

The control of the voltage of each of the bit line BL and the word line WL has been described above with respect to each of the first sensing operation and the second sensing operation. When the voltage of the bit line BL decreases as described above, between the first sensing operation and the second sensing operation, the voltage of the bit line BL decreases at a rate consistent with the stabilization of the bit line BL after the decrease. The rate of voltage reduction varies. Using this difference between the first sensing operation and the second sensing operation, the data stored in the selected memory cell MC at the beginning of the first sensing operation is determined after the second sensing operation. In the following, said determination of the data will be explained in detail.

FIG. 10 is a diagram for explaining the timing of voltage sampling performed by the sense amplifier SA of the memory device 1 according to the first embodiment in the first sensing operation and the second sensing operation.

FIG. 10 shows a diagram in which the waveforms of the voltages of the bit line BL shown in FIG. 9 in the first sensing operation and the second sensing operation are superimposed. More specifically, the two waveforms are superimposed such that the times T04 and T24 when the bit line BL starts to discharge are at the same position on the horizontal axis. In the example shown in FIG. 10 , the time from time T01 to time T03 is the same as the time from time T21 to time T23 . The time from time T03 to time T04 is substantially equal to the time from time T23 to time T24. In FIG. 10 shown in this manner, the horizontal axis represents the elapsed time from the discharge start time, and the vertical axis represents the time when the bit line BL is in the first sensing operation and The voltage in each of the second sensing operations.

As shown in FIG. 10 , the voltage of bit line BL decreases faster in the case of the second sensing operation than in the case of the first sensing operation. This is because when the selected memory cell MC is in the low resistance state LRS as in the second sensing operation, the cell current flowing through the selected memory cell MC is greater than when the selected memory cell MC is in the first sensing operation. Select the situation when the memory cell MC is in the high resistance state HRS. Furthermore, the voltage of the bit line BL stabilized after the reduction is lower in the case of the second sensing operation than in the case of the first sensing operation. This is because, as explained with reference to FIG. 7 , between the situation in which the selected memory cell MC is in the high resistance state HRS and the situation in which the selected memory cell MC is in the low resistance state LRS, the selected memory cell The I-V characteristics of meta-MC are different.

FIG. 10 further illustrates, by alternating long dashed lines and short dashed lines, a state in which the voltage difference of the bit line BL between the first sensing operation and the second sensing operation is determined by the bit line BL. The discharge start of line BL changes with the elapsed time at the same time point. The changes in the voltage difference explained below are based on, for example, the difference in the voltage drop of the bit line BL as described above.

At the beginning of discharge, the voltages of bit line BL in the first sensing operation and the second sensing operation are equal, and there is no difference between the voltages.

Until the time Δt1 elapses when self-discharge begins, the voltage difference increases as the elapsed time increases.

Then, until time Δt2 elapses, the voltage difference decreases as the elapsed time increases. The elapsed time since the start of discharge is the sum of time △t1 and time △t2 At a time point of , the voltage of bit line BL in the second sensing operation stabilizes.

Then, until time Δt3 further elapses, the voltage difference further decreases as the elapsed time increases. The voltage difference decreases at the same rate as the voltage decrease rate of the bit line BL in the first sensing operation, and a time that is the sum of time Δt1, time Δt2, and time Δt3 elapses since the start of discharge. Stabilization at time point. This is because the voltage of bit line BL in the first sensing operation stabilizes when a time that is the sum of time Δt1, time Δt2, and time Δt3 elapses since the start of discharge. In FIG. 10 , the voltage difference after stabilization is expressed as voltage difference VD1x.

In the first sensing operation, the voltage of the bit line BL is sampled at a time when time Δts has elapsed since the discharge start time T04 (indicated as time T04s in FIG. 10 ). For example, time Δts is greater than or equal to time Δt1 and less than the sum of time Δt1, time Δt2, and time Δt3. FIG. 10 shows a case where time Δts is greater than or equal to time Δt1 but less than the time that is the sum of time Δt1 and time Δt2. For example, under the control of the sequencer 15, the sampling is performed when the switch SW2 of the sense amplifier SA transitions to the on state and the switch SW3 transitions to the off state, and thus the voltage of the bit line BL is applied To the non-inverting input terminal of the operational amplifier circuit AMP. In this specification, the voltage sampled by the first sensing operation is called voltage Vsmpl. In addition, in this specification, sampling the voltage in this manner is also called sensing or detecting.

At the time Δts has elapsed since time T04, the cell current flows through the selected memory cell MC, and therefore the voltage of the bit line BL is unstable. That is, the voltage Vsmpl is sampled while the voltage of the bit line BL is changing.

In the second sensing operation, the voltage of the bit line BL is sampled at a time when the self-discharge start time T24 passes the time Δts (indicated as time T24s in FIG. 10 ). For example, when the switch SW2 of the sense amplifier SA transitions to the off state and the switch SW3 transitions to the on state, the sampling is performed under the control of the sequencer 15, and thus the voltage of the bit line BL is applied to The inverting input terminal of the operational amplifier circuit AMP. In this specification, the voltage sampled by the second sensing operation is called voltage Veval. The voltage Veval is lower than the voltage Vsmpl by a voltage difference VD1. The voltage difference VD1 is greater than the voltage difference VD1x.

In the case where time Δts is greater than or equal to time Δt1 but less than the sum of time Δt1 and time Δt2, when time Δts has elapsed since time T24, the cell current flows through the selected memory Cell MC, and therefore the voltage of bit line BL, is unstable. That is, the voltage Veval is sampled while the voltage of the bit line BL is changing.

The result of amplifying the voltage Vsmpl of the non-inverting input terminal based on the voltage Veval of the inverting input terminal is reflected in the signal SADOUT output from the operational amplifier circuit AMP, and the voltage of the signal SADOUT changes to the high (H) level.

The fact that the voltage of signal SADOUT is at the H level means that the data stored in the selected memory cell MC is different between the beginning of the first sensing operation and the beginning of the second sensing operation. Therefore, for example, the sequencer 15 determines that the data at the beginning of the first sensing operation is different from the data "0" stored during the second sensing operation based on the fact that the voltage of the signal SADOUT is at the H level. "1" is stored in the selected memory cell MC. Therefore, with reference to Figures 9 and 10 In the read operation described, data "1" is read. On the other hand, for example, the sequencer 15 performs a second write that causes the data "1" stored at the beginning of the first sensing operation to be stored again in the selected memory cell MC according to the determination. operate.

In the above, it has been explained that time Δts is, for example, greater than or equal to time Δt1 and less than the sum of time Δt1, time Δt2 and time Δt3. For example, as long as the voltage difference of bit line BL in each of the first sensing operation and the second sensing operation is greater than The voltage difference VD1x, the time △ts can be smaller than the time △t1.

In the above, the situation has been explained in which the selected memory cell MC is in the high resistance state HRS at the beginning of the first sensing operation. The situation in which the selected memory cell MC is in the low resistance state LRS at the beginning of the first sensing operation will also be briefly explained.

In this case, the voltage drop of bit line BL in the first sensing operation is substantially the same as the voltage drop of bit line BL in the second sensing operation. Therefore, the voltage Vsmpl sampled by the first sensing operation is substantially the same as the voltage Veval. Since the voltage Vsmpl is substantially the same as the voltage Veval, and taking into account the offset voltage, the voltage of the signal SADOUT changes to a low (L) level. For example, the sequencer 15 determines that at the beginning of the first sensing operation, the data "0" stored during the second sensing operation is also stored in the selected region based on the fact that the voltage of the signal SADOUT is at the L level. in the memory cell MC. Therefore, data "0" is read.

In the above content, it has been explained that the implementation is used to transfer the selected memory cell The control element MC transitions to the low resistance state LRS as is the case for the first write operation. However, this embodiment is not limited to the above. The techniques disclosed in this specification are also applicable to the situation in which the control for transitioning the selected memory cell MC to the high resistance state HRS is performed as the first write operation.

[Beneficial effect]

In the read operation, the memory device 1 according to the first embodiment sequentially performs the first sensing operation, the first writing operation and the second sensing operation on the selected memory cell MC.

In each of the first sensing operation and the second sensing operation, the memory device 1 performs the following control on the word line WL and the bit line BL corresponding to the selected memory cell MC. First, the memory device 1 stabilizes the voltage of the bit line BL by applying the voltage VBLP, and then transitions the bit line BL into a floating state. Memory device 1 applies voltage VSS to word line WL while keeping bit line BL in a floating state. While the voltage of word line WL decreases due to the application of voltage VSS, the voltage difference between bit line BL and word line WL exceeds voltage VSB. As mentioned above, when the voltage difference reaches the voltage VSB, the switching element S in the selected memory cell MC changes from the off state to the on state and becomes conductive, and flows through the cells of the selected memory cell MC. The current increases rapidly. The cell current flows out from the bit line BL via the word line WL and the transistor Tr8 of the read slot RS. Therefore, the voltage of bit line BL decreases. In this way, the memory device 1 lowers the voltage of the bit line BL in each of the first sensing operation and the second sensing operation.

In such a decrease in the voltage of the bit line BL, the memory in which the selected memory Between the situation in which the body cell MC is in the high resistance state HRS and the situation in which the selected memory cell MC is in the low resistance state LRS, the voltage of the bit line BL decreases at the same rate as the decrease in the voltage of the bit line BL. The rate of decrease of the stabilized voltage afterward varies.

In the first sensing operation, the memory device 1 operates on the voltage Vsmpl of the bit line BL at a time T04 s reached when the time Δts explained with reference to FIG. 10 has elapsed since the time T04 when the discharge of the bit line BL was started. Sampling. In the second sensing operation, the memory device 1 samples the voltage Veval of the bit line BL at a time T24 s reached when time Δts has elapsed since the time T24 when the discharge of the bit line BL started. When the sampling is performed in this manner, the voltage of bit line BL continues to change, at least in the case where the selected memory cell MC is in the high resistance state HRS.

For example, a case will be described where the selected memory cell MC is in the high resistance state HRS at the beginning of the first sensing operation and the selected memory cell MC is in the low resistance state LRS during the second sensing operation. In this case, the difference between the voltage Vsmpl sampled as described above and the voltage Veval is the voltage difference VD1. On the other hand, when the voltage is sampled at a timing when the voltage of the bit line BL stabilizes after being reduced in both the first sensing operation and the second sensing operation (hereinafter, referred to as the case of the comparative example), so The difference between the sampled voltages is the voltage difference VD1x. As described with reference to FIG. 10 , the voltage difference VD1 is greater than the voltage difference VD1x. The memory device 1 determines the data stored in the selected memory cell MC at the beginning of the first sensing operation based on the voltage difference VD1.

As described above, compared to the case of the comparative example, in the case in which the selected memory cell MC is in the high resistance state HRS and in the case in which the selected memory cell MC is in the low resistance state LRS, The memory device 1 can perform read operations based on a larger sensing margin. For example, the memory device 1 can accurately perform a read operation even when there is a reproducibility variation in the voltage of the bit line BL after discharge. Therefore, with the memory device 1 according to the first embodiment, the frequency of erroneous readings can be reduced, and the design of the operational amplifier circuit AMP for performing accurate reading operations can be facilitated.

Furthermore, with the memory device 1, in each of the first sensing operation and the second sensing operation, the time from the start of the discharge of the voltage of the bit line BL to the sampling of the voltage of the bit line BL is relatively long. Short in the case of comparison examples. Therefore, with the memory device 1 according to the first embodiment, the speed of the read operation can be increased.

In addition, by using the memory device 1 according to the first embodiment, the advantageous effects described below can also be obtained. FIG. 11 is a diagram for explaining further advantageous effects obtainable by the memory device 1 according to the first embodiment.

In the first sensing operation in the example shown in FIG. 9 , while the voltage of bit line BL decreases after time T04 , cell current flows from bit line BL to the word cell via selected memory cell MC. Line WL. When the selected memory cell MC is in the high resistance state HRS, the cell current can be used as a write current flowing in the direction A1 of the example shown in Figure 5, and therefore, the MTJ element can be transitioned to the low resistance state LRS , that is, the selected memory cell MC can be transformed into the low resistance state LRS. This means that the data stored in the selected memory cell MC can be used in the first sensing operation is inverted (read disturb). On the other hand, in the second sensing operation of the example shown in Figure 9, such data inversion does not occur. This is because the cell current is controlled to flow through the selected memory cell MC in the same direction during the first writing operation and the second sensing operation.

FIG. 11 is obtained by replacing the waveform of the bit line BL in the first sensing operation in FIG. 10 with the waveform in the case where such data inversion occurs at early timing.

As shown in FIG. 11 , the memory device 1 can perform voltage sampling before the voltage difference of the bit line BL in the first sensing operation and the second sensing operation disappears due to data inversion.

Therefore, even when such data inversion occurs during the first sensing operation, the memory device 1 according to the first embodiment can accurately read the data stored in the selected memory cell at the beginning of the first sensing operation. Information from Yuanzhong.

[Modified form]

Another operation example in which the memory device 1 performs a specific read operation will be explained. Differences from the above operation examples and beneficial effects will be mainly explained.

FIG. 12 shows an example of a timing diagram illustrating the timing diagram applied to the bit line corresponding to the selected memory cell MC when the memory device 1 according to the modification of the first embodiment performs a read operation. Time changes in the voltages of BL and word line WL.

Also in the read operation, the first sensing operation, the first writing operation and the second sensing operation are sequentially performed on the selected memory cell MC, and in the second sensing operation The data stored in the selected memory cell MC at the beginning of the first sensing operation is then determined. The second write operation may also be performed based on the determination result.

At time T30 before the read operation is started, the control described in connection with time T00 shown in FIG. 9 is performed on the bit line BL and the word line WL.

First, the control performed in the first sensing operation will be explained.

In the description up to time T04 with respect to the first sensing operation shown in FIG. 9 , time T01 is replaced by time T31 , time T02 is replaced by time T32 , time T03 is replaced by time T33 , and time T04 is replaced The description for time T34 is established. Time T34 and subsequent times will be described. Similar to the example shown in FIG. 9 , a case will be described in which the selected memory cell MC is in the high resistance state HRS at the beginning of the first sensing operation.

While the voltage drop of bit line BL starting at time T34 continues to occur, voltage VPRE is applied to word line WL at time T35. The application of voltage VPRE is performed by turning the transistor Tr8 of the read slot RS into the off state and turning the transistor Tr7 of the precharge circuit RPC into the on state.

While the voltage of word line WL increases due to the application of voltage VPRE, the voltage difference between bit line BL and word line WL drops below voltage VhldH. As mentioned above, when the voltage difference reaches the voltage VhldH, the switching element S in the selected memory cell MC changes from the on state to the off state, and the cell current flowing through the selected memory cell MC decreases rapidly. . Therefore, no cell current flows through the selected memory cell MC, and the voltage of the bit line BL is maintained.

For the subsequent first write operation, the first write operation shown in Figure 9 In the description, the description that time T11 is replaced by time T41 and time T12 is replaced by time T42 is established.

The control performed in the subsequent second sensing operation will be explained.

In the description up to time T24 with respect to the second sensing operation shown in FIG. 9 , time T21 is replaced by time T51 , time T22 is replaced by time T52 , time T23 is replaced by time T53 , and time T24 is replaced The description for time T54 is established. Time T54 and subsequent times will be described.

As explained in connection with time T35, voltage VPRE is applied to word line WL at time T55 while the decrease in the voltage of bit line BL that began at time T54 continues to occur.

While the voltage of word line WL increases due to the application of voltage VPRE, the voltage difference between bit line BL and word line WL drops below voltage VhldL. As mentioned above, when the voltage difference reaches the voltage VhldL, the switching element S in the selected memory cell MC changes from the on state to the off state, and the cell current flowing through the selected memory cell MC decreases rapidly. . Therefore, no cell current flows through the selected memory cell MC, and the voltage of the bit line BL is maintained.

FIG. 13 is a diagram for explaining the timing of voltage sampling in the first sensing operation and the second sensing operation by the sense amplifier SA of the memory device 1 according to the modification of the first embodiment.

FIG. 13 shows a diagram in which the waveforms of the voltages of the bit line BL shown in FIG. 12 in the first sensing operation and the second sensing operation are superimposed. More specifically, the two waveforms are superimposed so that the time T34 and T54 when the bit line BL starts to discharge are between at the same position on the flat axis. In the example shown in FIG. 13 , the time from time T31 to time T33 is the same as the time from time T51 to time T53 . The time from time T33 to time T34 is substantially equal to the time from time T53 to time T54. In addition, in the example shown in FIG. 13 , the time from time T34 to time T35 is the same as the time from time T54 to time T55 .

Similar to FIG. 10 , FIG. 13 further illustrates the following state by alternating long dotted lines and short dotted lines. In the state, the voltage difference of the bit line BL between the first sensing operation and the second sensing operation is It changes depending on the elapsed time at the time point when the same time has elapsed since the discharge of the bit line BL started.

From when the transistor Tr8 of the read slot RS transitions to the on state (the read slot RS transitions to the on state) and discharge starts to when the transistor Tr8 of the read slot RS transitions to the off state (the read slot RS transitions to the off state) (off state), the voltage difference is the same as in the example shown in Figure 10. When the read slot RS transitions to the off state and the transistor Tr7 of the precharge circuit RPC transitions to the on state, the voltage difference is maintained. This is because the voltage of bit line BL is maintained in each of the first sensing operation and the second sensing operation. In FIG. 13, the voltage difference after holding is expressed as voltage difference VD2x.

In the operation of the example shown in FIG. 12 , at least in the case where the selected memory cell MC is in the high resistance state HRS in the first sensing operation, the voltage difference VD2x is greater than, for example, the voltage in the case of the above-described comparative example. The difference is VD1x. This is because the time Δth from the start of the discharge of the bit line BL until the read slot RS changes to the off state is greater than or equal to the time Δt1, but less than the time Δt1 and the time Δt2. The time between the sum of △t3.

FIG. 13 shows that in the first sensing operation, similar to the example shown in FIG. 10 , the alignment of the bit line at a time when time Δts has elapsed since the discharge start time T34 (denoted as time T34s in FIG. 13 ) The voltage of BL is sampled. In addition, also in the second sensing operation, similar to the example shown in FIG. 10 , the bit line is shown at a time when the self-discharge start time T54 passes the time Δts (expressed as time T54s in FIG. 13 ). The voltage of BL is sampled. FIG. 13 shows an example of a situation in which time Δts is greater than or equal to time Δt1 but smaller than the time that is the sum of time Δt1 and time Δt2 in the range of time Δts explained with reference to FIG. 10 . After sampling for each of the first sensing operation and the second sensing operation, the above-described change of the read slot RS to the off state is performed. 12 and 13 show an example of a case in which time Δth is greater than or equal to time Δts but less than the time that is the sum of time Δt1 and time Δt2. The voltage difference of the bit line BL sampled in each of the first sensing operation and the second sensing operation is the voltage difference VD2. In the case of the comparative example, the voltage difference VD2 is greater than or equal to the voltage difference VD2x and greater than the voltage difference VD1x.

Although the case where time Δth is greater than or equal to time Δts and less than the time that is the sum of time Δt1 and time Δt2 has been explained above, time Δth is not limited to this as long as it is greater than or equal to time Δts. In the case where the time Δth with respect to the second sensing operation is, for example, equal to or greater than the time that is the sum of the time Δt1 and the time Δt2 and is smaller than the time that is the sum of the time Δt1, the time Δt2, and the time Δt3 , unlike the situation explained with respect to time T55 in the example shown in FIG. 12 , the voltage of the bit line BL is stable at the timing when the read slot RS transitions to the off state.

In the above, the case in which time Δts is greater than or equal to time Δt1 but less than the time that is the sum of time Δt1 and time Δt2 has been explained as an example. As long as the time Δts satisfies the conditions explained with reference to Figure 10, the technique disclosed in this modified form is applicable. For example, a case will also be described in which time Δts is greater than or equal to the time that is the sum of time Δt1 and time Δt2 and is smaller than the time that is the sum of time Δt1, time Δt2, and time Δt3. In this case as well, with respect to the second sensing operation, unlike the case explained with respect to time T55 of the example shown in FIG. 12 , the voltage of the bit line BL transitions to the off state at the timing of the read slot RS. is stable.

As described above, while the voltage of the bit line BL decreases, the read slot RS may transition to the off state after sampling the voltage without waiting for the stabilization of the voltage. In the examples shown in FIGS. 12 and 13 , in the first sensing operation and the second sensing operation, the time from the start of discharging of the bit line BL to the transition of the read slot RS to the off state is the same. However, the time from the start of discharge of the bit line BL until the read slot RS transitions to the off state may differ between the first sensing operation and the second sensing operation. Furthermore, in each of the first sensing operation and the second sensing operation, the read slot RS may be transitioned to the off state at the same timing from the start of discharge of the bit line BL, and may be read After the sampling slot RS transitions to the off state, the voltage of the bit line BL is sampled.

As described above, in the modified form of the first embodiment, for example, at least in the case where the selected memory cell MC is in the high resistance state HRS, at the timing when the voltage of the bit line BL decreases, the read Take the slot RS and change it to the off state. Since the read slot RS is turned off at an early stage in this way, the power supply during this period The time for flow to pass through the selected memory cell MC is shortened, and therefore the degradation of the memory cell is suppressed.

With the memory device 1 according to the modified form of the first embodiment, the voltage of the bit line BL is sampled in the first sensing operation and the second sensing operation even after the read slot RS is turned off. The difference in voltage is also expected to increase, but since the discharge of bit line BL is forcibly stopped, the voltage of bit line BL may change reproducibly. However, by performing sampling before turning off the read slot RS in a case where a reproducibility change occurs, the memory device 1 according to the modified form of the first embodiment can suppress the reproducibility change and accurately align the bit lines. The voltage of BL is sampled.

<Second Embodiment>

Hereinafter, the memory device 1a according to the second embodiment will be explained.

The configuration of the memory device 1a according to the second embodiment will be explained mainly with respect to differences from the configuration of the memory device 1 according to the first embodiment.

FIG. 14 is a block diagram showing an example of the configuration of the memory device 1a according to the second embodiment. As an explanation of the configuration of the memory device 1a, the memory system 3 is replaced with the memory system 3a, the memory device 1 is replaced with the memory device 1a, and the sequencer 15 is replaced with the sequencer in the illustration of FIG. The explanation of 15a is established.

It should be noted that, as for the memory device 1a, the description of FIGS. 2 to 8 in which the memory device 1 is replaced with the memory device 1a and the sequencer 15 is replaced with the sequencer 15a holds true. Each of the plurality of memory cells MC of the memory cell array MCA of the memory device 1a is grouped so as to be included in any of the plurality of groups.

The sequencer 15a includes a group determination circuit 152. Based on the address information transmitted from the command/address input circuit 14 to the sequencer 15a, the group determination circuit 152 determines in which of the plurality of groups the memory cell MC targeted by the read operation is included. middle. The sequencer 15a performs timing control in the read operation based on the result of the determination.

FIG. 15 shows examples of layouts of various interconnections that can be used as voltage transfer paths to each memory cell MC of the memory device 1a according to the second embodiment.

In the example shown in FIG. 15 , each of the word lines WL0 to WL(n-1) extends in the first direction D1 in a specific interconnect layer, and the word lines WL start with the word line WL0 , word lines WL1, ... and word lines WL(n-1) are arranged adjacent to each other with intervals along the second direction D2. In the example shown in FIG. 15 , each of the bit lines BL0 to BL(m-1) extends in the second direction D2 in another interconnection layer, and the bit lines BL are BL0, the bit lines BL1, ... and the bit lines BL(m-1) are arranged adjacent to each other with intervals along the first direction D1.

In the example shown in FIG. 15, the global word line GWL is arranged to extend in the second direction D2, and the global bit line GBL is arranged to extend in the first direction D1.

For example, a portion of the global word line GWL coupled to the read slot RS and a portion of the global word line GWL are electrically coupled to each of the word lines WL0 to WL(n-1) via the column transfer switch group RTS. For a part of one, the relationship explained below holds. That is, the distance from the portion coupled to the read slot RS to the portion electrically coupled to each word line WL is expressed by the word line WL0, the word line WL1, ... and the word line The order of WL(n-1) increases.

For example, a portion of the global bit line GBL coupled to the sense amplifier SA and a portion of the global bit line GBL electrically coupled to each of the bit lines BL0 to BL(m-1) via the row transfer switch group CTS As part of one, the relationship explained below holds. That is, the distance from the portion coupled to the sense amplifier SA to the portion electrically coupled to each bit line BL is expressed by the bit line BL0, the bit line BL1, ... and the bit line BL(m-1 ) increases in order.

According to this arrangement of various interconnections, for example, for the path of the self-sense amplifier SA to the read slot RS via each memory cell MC, the relationship set forth below holds. In Figure 15, such a path is represented by a two-dot chain line.

The path associated with the memory cell MC coupled between the bit line BL0 and the word line WL(n-1) (in Figure 15, attached with the reference number MC(n-1,0)) is longer than the path associated with the coupling The path associated with the memory cell MC (in FIG. 15, with the reference number MC(0,0)) between the bit line BL0 and the word line WL0. More specifically, the paths associated with memory cell MC(n-1,0) are longer than those of bit line BL0 coupled to memory cells MC(0,0) and MC(n-1,0) respectively. Paths between portions and portions of global word line GWL are electrically coupled to word lines WL0 and WL(n-1) respectively.

Furthermore, the path associated with the memory cell MC (in FIG. 15, attached with the reference number MC(0,m-1)) coupled between the bit line BL(m-1) and the word line WL0 is longer than Path associated with memory cell MC(0,0). More specifically, with memory The paths associated with cell MC(0,m-1) are longer than the paths between the portions of global bit line GBL electrically coupled to bit lines BL0 and BL(m-1) respectively and the respective couplings of word line WL0 The path between the parts of memory cells MC(0,0) and MC(0,m-1).

As mentioned above, as the word line WL corresponding to the memory cell MC is the word line WL0, the word line WL1, ... and the word line WL(n-1), the self-sense amplifier SA passes through the specific The path from memory cell MC to read slot RS becomes longer. In the following, it will be assumed that the word line WL with a shorter path (eg, word line WL0) is closer to the "near" side, while the word line WL with a longer path (eg, word line WL(n-1)) Give instructions closer to the "far" side.

On the other hand, the path becomes longer as the bit lines BL corresponding to the memory cell MC are bit lines BL0, BL1,... and BL(m-1) . In the following, it will be assumed that the bit line BL with a shorter path (eg, bit line BL0) is closer to the "near" side, while the bit line BL with a longer path (eg, bit line BL(m-1)) Give instructions closer to the "far" side.

FIG. 16 is a diagram for explaining grouping of memory cells MC for timing control performed in a read operation by the memory device 1a according to the second embodiment. The grouping set forth below is only an example, and the grouping according to the present embodiment is not limited thereto.

First, the grouping of word lines WL will be explained.

Each of word lines WL0 to WL(n-1) is included in any of a plurality of word line groups WLG1 to WLG8. Each of the word line groups WLG1 to WLG8 includes, for example, a plurality of word lines WL. Among all word line groups WLG1 to WLG8, the number of word lines WL constituting a single word line group WLG may be the same. It may be different.

Grouping is performed so that the word line group WLGp with a smaller integer p (p is an integer that is 1 or greater than 1 and 8 or less than 8) is configured by the word line WL closer to the "near" side, and has The word line group WLGp with a larger integer p is configured by the word line WL closer to the "far" side.

Next, an example of grouping of bit lines BL will be explained.

Each of the bit lines BL0 to BL(m-1) is included in any one of the plurality of bit line groups BLG1 to BLG8. Each of the bit line groups BLG1 to BLG8 includes, for example, a plurality of bit lines BL. Among all the bit line groups BLG1 to BLG8, the number of bit lines BL constituting a single bit line group BLG may be the same or different.

Grouping is performed so that the bit line group BLGq with a smaller integer q (q is an integer that is 1 or greater than 1 and 8 or less than 8) is configured by the bit line BL closer to the "near" side, and has The bit line group BLGq of the larger integer q is configured by the bit line BL closer to the "far" side.

Next, the grouping of memory cells MC will be explained.

When the word line WL corresponding to a specific memory cell MC is included in the word line group WLGt and the bit line BL corresponding to the memory cell MC is included in the bit line group BLGu, the value ( t+u) is assigned to the memory cell MC. This numerical assignment is performed for every case where t is an integer from 1 to 8 and for every case where u is an integer from 1 to 8. Figure 16 shows the values assigned in this way.

When assigning a value to a specific memory cell MC in this way, for example If 6 or less, include the memory cell MC in the "near" group. A memory cell MC is included in the "middle" group when the value assigned to a particular memory cell MC in this manner is, for example, 7 or greater and 11 or less. When the value assigned to a particular memory cell MC in this manner is, for example, 12 or greater, the memory cell MC is included in the "far" group.

Hereinafter, the difference between the operation of the memory device 1a according to the second embodiment and the operation of the memory device 1 according to the first embodiment will be mainly explained.

For the case where a specific memory cell MC in the "near" group is the selected memory cell MC (hereinafter also referred to as the case "near") and where a specific memory cell MC is in the "far" group is the case of the selected memory cell MC (hereinafter also referred to as the case "far"), an explanation equivalent to the explanation given with reference to FIGS. 9 and 10 holds.

FIG. 17 is a diagram for explaining the timing of voltage sampling performed by the sense amplifier SA of the memory device 1a according to the second embodiment in the first sensing operation and the second sensing operation.

Fig. 17 shows together a diagram equivalent to Fig. 10 in the case "near" and a diagram equivalent to Fig. 10 in the situation "far".

As far as the case "near" is concerned, the time corresponding to time Δt1 in the example shown in FIG. 10 is expressed as time Δt1n, and similarly, the time corresponding to time Δt2 is expressed as time Δt2n, and the time corresponding to time Δt2n is expressed as time Δt2n. The time of time Δt3 is expressed as time Δt3n. In the case of "far", the time corresponding to time Δt1 in the example shown in FIG. 10 is expressed as time Δt1f, and similarly, the time corresponding to time Δt2 is expressed as time time Δt2f, and the time corresponding to time Δt3 is expressed as time Δt3f.

Time △t1f is longer than time △t1n, time △t2f is longer than time △t2n, and time △t3f is longer than time △t3n. This is because, as described with reference to Figure 15, the path from the sense amplifier SA to the read slot RS via the selected memory cell MC is longer in the case "far" than in the case "near", and therefore for The resistor-capacitor (RC) delay in the discharge path of bit line BL is large.

In the case "near", in both the first sensing operation and the second sensing operation, for example, from the start of self-discharge until the time Δt1n has elapsed but has not elapsed is the time Δt1n, the time Δt2n and the time During the period up to the sum of Δt3n, the voltage of the bit line BL is sampled. In the case "near", the time from the start of discharge to the sampling of the voltage of the bit line BL is the same in the first sensing operation and the second sensing operation.

In the case "far", in both the first sensing operation and the second sensing operation, for example, from the start of self-discharge until the time Δt1f has elapsed but the time Δt1f, the time Δt2f and the time Δt have not elapsed During the period up to the sum of t3f, the voltage of the bit line BL is sampled. In the case "far", the time from the start of discharge to the sampling of the voltage of the bit line BL is the same in the first sensing operation and the second sensing operation.

The time from the start of the discharge of the bit line BL to the sampling of the voltage of the bit line BL may differ between the case "near" and the case "far". For example, when the voltage difference of bit line BL between the first sensing operation and the second sensing operation during sampling the voltage of bit line BL is between the case "near" and the case "far" At approximately the same time, the time from the start of the discharge of the bit line BL to the sampling of the voltage of the bit line BL is longer in the case "far" than in the case "near".

For multiple or all memory cells MC of the "near" group, for example, even when any of the memory cells MC is the selected memory cell MC, the value from the bit line BL The time from the start of discharge to the sampling of the voltage of bit line BL is also substantially the same. Likewise for multiple or all memory cells MC of the "far" group, for example, even when any of the memory cells MC is the selected memory cell MC, from the bit line BL The time from the start of the discharge to the sampling of the voltage of the bit line BL is also substantially the same.

For example, such control according to the sampling timing of the group associated with the selected memory cell MC is performed under the control of the sequencer 15a based on the determination result of the group associated with the selected memory cell MC by the group determination circuit 152.

In the above content, the situation in which the specific memory cell MC in the "near" group is the selected memory cell MC and the situation in which the specific memory cell MC in the "far" group is the selected memory cell have been explained Take the case of meta-MC as an example. When the memory cells MC are divided into multiple groups as described with reference to FIG. 16 , timing control similar to the timing control explained above can be performed on any two different groups of memory cells MC.

By utilizing the memory device 1a according to the second embodiment, in addition to the advantageous effects explained in the first embodiment, the advantageous effects explained below can also be obtained.

For example, for each group including the selected memory cells MC, the memory device 1a may set the self-bit in the same manner as explained with reference to FIG. 10 The time from the start of discharge of the bit line BL to the sampling of the voltage of the bit line BL used in the read operation of the example shown in FIG. 9 . For example, in each group, as long as the memory cell MC of the group is the selected memory cell, the difference in the RC delay in the discharge path of the bit line BL explained above is relatively small. That is, the memory device 1 a sets the timing at which the voltage of the bit line BL is sampled at which the sensing margin can be reliably obtained for each group. Therefore, even when the difference in RC delay may increase depending on which memory cell MC of the memory cell array MCA is the selected memory cell MC, the memory device 1a can be based on a larger sensing margin to perform the aforementioned read operations reliably.

Therefore, with the memory device 1a according to the second embodiment, as described in the first embodiment, the frequency of erroneous readings can be reduced, and the design of the operational amplifier circuit AMP for performing accurate reading operations can be facilitated.

<Other embodiments>

In the above example of a read operation, also referred to as a self-referenced read operation, a bit coupled to a selected memory cell is sensed in each of the first sensing operation and the second sensing operation. line voltage, and compares the two sensed voltages to determine the reading. The techniques disclosed in this specification can also be applied to other reading operations. For example, the techniques disclosed in this specification may be applied to read operations in which the value of a specific physical quantity associated with a specific component is sensed when a memory cell is in a high-resistance state and when a memory cell is in a high-resistance state. The value of a physical quantity associated with the component or another component when the cell is in a low-resistance state, and the data stored in the memory cell is determined based on the difference between the two values. The physical quantity may be, for example, voltage or current.

In this specification, "coupling" refers to electrical coupling, and does not exclude, for example, sandwiching another component.

In this specification, the annotations "same", "consistent", "constant", "maintain" and similar annotations are intended to include when performing the techniques described in the embodiments. There are errors within the design range. The same applies when the term "substantial" is used in combination with these notations, such as "substantially the same". Additionally, the notation "applying or supplying a specific voltage" is intended to include both performing control to apply or supply said voltage and actually applying or supplying said voltage. Furthermore, applying or supplying a specific voltage may include applying or supplying a voltage of, for example, 0 volts.

Although specific embodiments have been set forth, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. Indeed, the novel embodiments set forth herein may be implemented in various other forms; in addition, various omissions, substitutions, and changes in form may be made to the embodiments set forth herein without departing from the spirit of the invention. The accompanying patent claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.

HRS: high resistance state

LRS: low resistance state

T03, T04, T04s, T23, T24, T24s, △t1, △t2, △t3, △ts: time

VBLP, Veval, VPRE, Vsmpl: voltage

VD1, VD1x: voltage difference

Claims (14)

A semiconductor memory device includes: a first memory cell including a first variable resistance element and a first switching element; and a control circuit configured to detect a third memory cell related to the first memory cell. a first detection of a first value of a physical quantity, performing a first write for storing first data in the first memory cell, performing detection and the A second detection of a second value of the first physical quantity associated with a first memory cell, and reading a second value associated with the first memory cell based on the first value and the second value. Second information, wherein at least one of the first value and the second value is a value during a change of the first physical quantity associated with the first memory cell. The semiconductor memory device of claim 1, wherein at least one of the first value and the second value is detected while the first physical quantity associated with the first memory cell changes. One. The semiconductor memory device of claim 1, wherein the second data is data stored in the first memory cell when the first detection starts. The semiconductor memory device of claim 1, wherein each of the first value and the second value is a value obtained by changing the first physical quantity from a third value. The semiconductor memory device according to claim 4, wherein The first time from the start of the change of the first physical quantity to the detection of the first value in the first detection is substantially equal to the time from the start of the change of the first physical quantity to the detection of the first value in the first detection. The second time until the second value is detected in the second detection. The semiconductor memory device of claim 1, wherein the first physical quantity is a voltage coupled to a first interconnect of the first memory cell. The semiconductor memory device of claim 6, wherein the control circuit is further configured to: in the first detection, apply a first voltage to the first interconnect, and then switch the first interconnect the first interconnect is in the floating state, and applying a second voltage lower than the first voltage to the second interconnect coupled to the first memory cell while the first interconnect is in the floating state. two voltages to reduce the voltage of the first interconnect, and in the second detection, apply the first voltage to the first interconnect and then convert the first interconnect to the floating state, and applying the second voltage to the second interconnect while the first interconnect is in the floating state to reduce the voltage of the first interconnect, Each of the first value and the second value is a value obtained by reducing the voltage of the first interconnection from the first voltage, and the first value and the At least one of said second values is a value during said decrease in said voltage of said first interconnection. The semiconductor memory device of claim 7, wherein while the voltage of the first interconnection is reduced, the first value is detected and at least one of the second values. The semiconductor memory device of claim 7, wherein a first step from the reduction of the voltage of the first interconnection to detection of the first value in the first detection The time is substantially equal to the second time from the onset of the decrease in the voltage of the first interconnect until the second value is detected in the second detection. The semiconductor memory device of claim 7, wherein when the first variable resistance element is in a low resistance state at the start of the first detection, after the decrease in the first detection The voltage of the stabilized first interconnect is lower than when the first variable resistance element is in a high resistance state. The semiconductor memory device of claim 7, wherein when the first value is a value during the decrease of the voltage of the first interconnection, the control circuit is further configured to During the reduction of the voltage of the first interconnect in the first detection, the second voltage is not applied to the second interconnect, and when the second value is within the first When the value of the voltage of the interconnection decreases during the decrease period, the control circuit is further configured to not supply the voltage to the first interconnection during the decrease period in the second detection. The second interconnect applies the second voltage. The semiconductor memory device of claim 7, further comprising: a second memory cell including a second variable resistance element and a second switching element, wherein the control circuit is further configured to: execute the A voltage is applied to a third probe of a third interconnect coupled to the second memory cell, then transitioning the third interconnect to the floating state, and when the third interconnect is in While in the floating state, the second voltage is applied to the fourth interconnect coupled to the second memory cell to reduce the voltage of the third interconnect, and detects the a third value obtained by reducing the voltage of the third interconnect from the first voltage; performing a second write for storing the first data in the second memory cell; in the After the second writing, a fourth detection of applying the first voltage to the third interconnect is performed, and then the third interconnect is transitioned to a floating state, and after the third interconnect While in the floating state, applying the second voltage to the fourth interconnect to reduce the voltage of the third interconnect and detecting the voltage as the third interconnect a fourth value obtained as a result of the first voltage reduction; and reading third data related to the second memory cell based on the third value and the fourth value, the third at least one of the three values and the fourth value is a value during the reduction of the voltage of the third interconnection, A first time from the decrease in the voltage of the first interconnect until the first value is detected in the first detection is substantially equal to the first time from the first interconnect to the detection of the first value in the first detection. The second time from the beginning of the decrease in the voltage to the detection of the second value in the second detection, from the beginning of the decrease in the voltage of the third interconnection to the second time in the second detection The third time until the third value is detected in the third detection is substantially equal to the time from the decrease in the voltage of the third interconnection to the detection of the third value in the fourth detection. The fourth time until the fourth value, the first memory cell is included in the first group, and when the second memory cell is included in the first group, the first time is substantially is equal to the third time, and the first time is different from the third time when the second memory cell is included in the second group. The semiconductor memory device of claim 12, wherein when the second memory cell is included in the second group, the first time is longer than the third time, and the first interaction The discharge path connected in the first detection is longer than the discharge path of the third interconnection in the third detection. The semiconductor memory device of claim 1, wherein the first variable resistance element is a magnetic tunnel junction element.

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