JP5076182B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device including a resistor memory element that stores data according to a change in resistance value level.

  The nonvolatile semiconductor memory device can hold stored data even when the power supply voltage is cut off, and does not need to supply the power supply voltage in a standby state. For this reason, it is widely used in portable devices that are required to have low power consumption.

  One such nonvolatile semiconductor memory device is an MRAM (Magnetic Random Access Memory) that stores data using the magnetoresistive effect. One of the MRAMs uses a tunnel magnetoresistive element having a magnetic tunnel junction (MTJ) (see, for example, Non-Patent Document 1).

  This MRAM includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a word line, a source line and a digit line provided corresponding to each row, and a bit line provided corresponding to each column. Prepare. Each memory cell includes a tunnel magnetoresistive element and a transistor. One electrode of the tunnel magnetoresistive element is connected to the bit line, the other electrode is connected to the source line through the transistor, and the gate of the transistor is connected to the word line. Each source line is grounded.

During a write operation, a magnetic field application current is supplied to the digit line of the selected row, and a write current having a polarity corresponding to the write data is supplied to the bit line of the selected column, so that the tunnel magnetoresistance of the selected memory cell The element is put into a high resistance state or a low resistance state. During a read operation, the word line of the selected row is set to the selected level, the transistor of each memory cell in that row is turned on, and the memory cell flows out from the bit line of the selected column through the tunnel magnetoresistive element and transistor of the selected memory cell. Current is detected and the stored data is read out.
2004 Symposium on VLSI Circuits Digest of Technical Papers p.450-453 A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture

  In such an MRAM, a driver for supplying a bidirectional write current of several mA to each bit line is provided. This driver includes a P channel MOS transistor and an N channel MOS transistor connected to one end of the bit line, and a P channel MOS transistor and an N channel MOS transistor connected to the other end of the bit line (see FIG. 2). . The gate width of each transistor is at least several tens of times the gate width of the transistor of the memory cell. Therefore, the parasitic capacitance of the four transistors of the driver is added to each bit line, and there is a problem that the read operation is delayed by this parasitic capacitance.

  SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a nonvolatile semiconductor memory device having a fast read operation.

  A nonvolatile semiconductor memory device according to the present invention is provided with a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, and a plurality of columns, respectively. A memory array including a plurality of bit lines and a plurality of source lines provided corresponding to a plurality of columns, respectively. Each memory cell is connected in series with a resistor memory element that stores data by changing the level of the resistance value, and between the corresponding bit line and the source line, and the corresponding word line is set to the selected level. And a transistor which conducts accordingly. The nonvolatile semiconductor memory device further includes a row decoder for setting a word line corresponding to a selected memory cell of a plurality of memory cells to a selection level and conducting a transistor of the selected memory cell, and the selected memory And a read circuit for reading data of a selected memory cell through a source line corresponding to the cell. The read circuit includes a bit line bias circuit that applies a predetermined bias voltage to the bit line corresponding to the selected memory cell, and a clamp circuit that sets the voltage of the source line corresponding to the selected memory cell to the ground voltage. The data of the selected memory cell is read based on the current flowing through the source line corresponding to the selected memory cell.

  In the nonvolatile semiconductor memory device according to the present invention, a word line is provided corresponding to each memory cell row, a bit line and a source line are provided corresponding to each memory cell column, and a source corresponding to the selected memory cell is provided. Read the data of the selected memory cell via the line. Therefore, the reading operation can be speeded up as compared with the conventional case where data is read through a bit line having a large parasitic capacitance.

[Embodiment 1]
FIG. 1 is a block diagram showing an overall configuration of an MRAM according to Embodiment 1 of the present invention. 1, this MRAM includes a memory array 1, a row decoder 2, a column decoder 3, a write / read circuit 4, and a control circuit 5. The memory array 1 is divided into two memory blocks MB0 and MB1.

  As shown in FIG. 2, the memory block MB0 corresponds to a plurality of memory cells MC arranged in a plurality of rows and a plurality of columns, a plurality of word lines WL provided corresponding to the plurality of rows, and a plurality of rows, respectively. A plurality of digit lines DL, a plurality of bit lines BL corresponding to a plurality of columns, and a plurality of pairs of source lines SL0 and SL1 respectively corresponding to a plurality of columns.

  The plurality of word lines WL are previously divided into a plurality of word line groups, and each word line group includes four adjacent word lines WL. The plurality of memory cells MC in each column are divided into a plurality of memory cell groups respectively corresponding to a plurality of word line groups. Each memory cell group includes four adjacent memory cells MC. The source line SL0 is provided corresponding to the first and second memory cells MC of the four memory cells MC in each memory cell group. The source line SL1 is provided corresponding to the third and fourth memory cells MC of the four memory cells MC in each memory cell group.

  Each memory cell MC includes a tunnel magnetoresistive element TMR and an access transistor (N channel MOS transistor) ATR as shown in FIG. Tunneling magneto-resistance element TMR and access transistor ATR are connected in series between corresponding bit line BL and source line SL (SL0 or SL1), and the gate of access transistor ATR is connected to corresponding word line WL. Tunneling magneto-resistance element TMR is an element whose electric resistance value changes according to the logic of stored data.

  That is, as shown in FIG. 4, tunnel magnetoresistive element TMR includes fixed magnetization film FL, tunnel insulating film TB, and free magnetization film VL stacked between electrode EL and bit line BL. Each of the fixed magnetization film FL and the free magnetization film VL is composed of a ferromagnetic film. The magnetization direction of the fixed magnetization film FL is fixed in one direction. The magnetization direction of free magnetic film VL is written in one of one direction and the other direction. When the magnetization directions of the fixed magnetic film FL and the free magnetic film VL are the same, the resistance value of the tunnel magnetoresistive element TMR becomes a relatively high value, and when the magnetization directions of the two are opposite, the tunnel magnetoresistive element TMR The electrical resistance value is relatively low. The two-stage resistance values of tunneling magneto-resistance element TMR are associated with, for example, data “1” and “0”, respectively.

  At the time of data writing, as shown in FIG. 4, word line WL is set to the “L” level of the non-selection level and access transistor ATR is made non-conductive, and writing is performed to each of bit line BL and digit line DL. A current flows. The magnetization direction of free magnetic film VL is determined by the combination of the directions of the write currents flowing through bit line BL and digit line DL.

  FIG. 5 is a diagram showing the relationship between the direction of the data write current and the magnetic field direction during data writing. Referring to FIG. 5, a magnetic field Hx indicated by the horizontal axis indicates a magnetic field H (DL) generated by a data write current flowing through digit line DL. On the other hand, the magnetic field Hy indicated on the vertical axis indicates the magnetic field H (BL) generated by the data write current flowing through the bit line BL.

  The magnetic field direction stored in the free magnetic film VL is newly written only when the sum of the magnetic fields H (DL) and H (BL) reaches a region outside the asteroid characteristic line shown in the drawing. That is, when a magnetic field corresponding to the area inside the asteroid characteristic line is applied, the magnetic field direction stored in the free magnetic film VL is not updated. Therefore, in order to update the storage data of tunneling magneto-resistance element TMR by the write operation, it is necessary to pass a current through both digit line DL and bit line BL. The magnetic field direction once stored in tunneling magneto-resistance element TMR, that is, the stored data is held in a nonvolatile manner until new data writing is executed.

  At the time of data reading, as shown in FIG. 6, the source line SL is set to the ground voltage VSS, the word line WL is set to the “H” level of the selection level, and the access transistor ATR is turned on. A current Is flows through the element TMR, the access transistor ATR, and the source line SL to the line of the ground potential VSS. The value of this current Is changes according to the resistance value of tunneling magneto-resistance element TMR. Therefore, the data stored in tunneling magneto-resistance element TMR can be read by detecting the value of current Is.

  FIG. 7 is a diagram showing a layout of the memory block MB0. FIG. 7 shows a layout of memory cells MC in 4 rows and 2 columns. In FIG. 7, four word lines WL extending in the Y direction in the drawing are formed on the surface of a P-type silicon substrate (not shown). Each word line WL and the surface of the P-type silicon substrate are insulated by a gate oxide film (not shown).

  A total of four rectangular N-type diffusion regions ND of two rows and two columns are formed using the four word lines WL as a mask. Each N-type diffusion region ND is formed between two word lines WL and across both sides. A region between two word lines WL in each N-type diffusion region ND serves as a common source for access transistors ATR of two adjacent memory cells MC, and two regions on both sides of the two word lines WL have two regions. It becomes the drain of the access transistor ATR of the memory cell MC.

  Two pairs of source lines SL0 and SL1 extending in the X direction in the figure are formed above the N-type diffusion region ND of 2 rows and 2 columns. Source line SL0 is formed above one end of N-type diffusion region ND in the corresponding column, and is connected to the center of one end of N-type diffusion region ND in the second row via contact hole CH. . Source line SL1 is formed above the other end of N-type diffusion region ND in the corresponding column, and is connected to the center of the other end of N-type diffusion region ND in the first row via contact hole CH. .

  Four digit lines DL extending in the Y direction in the figure are formed above the two pairs of source lines SL0 and SL1. Each digit line DL is arranged between two word lines WL as viewed from above. A total of eight rectangular electrodes EL in four rows and two columns are formed above the four digit lines DL. Each electrode EL is formed from the corresponding digit line DL over the drain of the corresponding access transistor ATR as viewed from above, and is connected to the drain of the corresponding access transistor ATR via the contact hole CH.

  A tunnel magnetoresistive element TMR is formed on each electrode EL. Each tunnel magnetoresistive element TMR is arranged above the corresponding digit line DL as viewed from above. Two bit lines BL extending in the X direction in the figure are formed on the 4 × 2 tunnel magnetoresistive element TMR. Each bit line BL is connected to four tunneling magneto-resistance elements TMR in the corresponding column.

  Returning to FIG. 2, a plurality of memory cells MC of the memory block MB0 are grouped in advance in groups of four in each row. The sources of the access transistors ATR of the first and second memory cells MC of each memory cell group are connected to the source line SL0, and the sources of the access transistors ATR of the third and fourth memory cells MC are source lines. Connected to SL1.

  Also, each memory cell group in a predetermined column of the plurality of columns of the memory block MB0 is used as a reference memory cell group, the bit line BL in that column is used as a reference bit line RBL, and the source line in that column SL0 and SL1 are used as reference source lines RSL0 and RSL1. The resistance value of the tunnel magnetoresistive element TMR of each of the first and second memory cells MC of the plurality of reference memory cell groups in the column is set to a high level, and each of the third and fourth memory cells MC is set. The resistance value of the tunnel magnetoresistive element TMR is set to a low level. Therefore, the resistance value of the parallel connection body of the tunnel magnetoresistive element TMR of the odd-numbered memory cell MC and the tunnel magnetoresistive element TMR of the even-numbered memory cell MC is lower than the high level resistance value of the tunnel magnetoresistive element TMR. It becomes the average value with the resistance value of the level. This is used for data reading. The memory block MB1 has the same configuration as the memory block MB0.

  Returning to FIG. 1, row decoder 2 selects one of a plurality of digit lines DL in each of memory blocks MB0 and MB1 in accordance with row address signal RA at the time of data writing. In the data read operation, the row decoder 2 selects one of the plurality of word lines WL in each of the memory blocks MB0 and MB1 according to the row address signal RA, and selects the selected word line WL. Is raised to the “H” level of the selection level. At this time, when the odd-numbered word line WL is selected, the row decoder 2 raises the other odd-numbered word line WL in the same word line group to “H” level and selects the even-numbered word line WL. In this case, another even-numbered word line WL in the same word line group is raised to “H” level. When the row decoder 2 selects the odd-numbered word line WL in one of the memory blocks MB0 and MB1, the row decoder 2 selects the even-numbered word line WL in the other memory block.

  Column decoder 5 selects one of a plurality of columns in each of memory blocks MB0 and MB1 in accordance with column address signal CA during data writing. In the data read operation, column decoder 5 selects one of a plurality of columns in each of memory blocks MB0 and MB1 in accordance with column address signal CA, and two source lines SL0, The source line SL0 or SL1 corresponding to the word line WL selected by the row decoder 2 in SL1 is selected. At this time, when the column decoder 5 selects the source lines SL0 and SL1, the column decoder 5 also selects the reference source lines RSL1 and RSL0, respectively.

  Write / read circuit 4 supplies a constant write current to digit line DL selected by row decoder 2 and is selected by column decoder 5 in each of memory blocks MB0 and MB1 during data writing. A write current having a polarity corresponding to the write data signal D0 or D1 is supplied to the bit line BL corresponding to the column, and the data signal is written to the memory cell MC.

  Write / read circuit 4 applies bias voltage VB to each of bit line BL and reference bit line RBL in the column selected by column decoder 5 in each of memory blocks MB0 and MB1 during data reading. At the same time, the source lines SL0 and SL1 and the reference source lines RSL0 and RSL1 are set to the ground voltage VSS. Then, the write / read circuit 4 compares the value of the current flowing through each of the source lines SL0 and SL1 with the average value of the current values flowing through the two reference source lines RSL0 and RSL1, and determines the logic according to the comparison result. Level data signals Q0 and Q1 are output to the outside. The control circuit 7 controls the entire MRAM according to the external command signal CMD.

  More specifically, as shown in FIG. 2, the write / read circuit 4 includes a DL driver 6, BL drivers 10, 13 and a BL bias circuit 16 provided corresponding to each of the memory blocks MB0 and MB1, Column selection gate 18 provided in common to memory blocks MB0 and MB1 and comparison circuits 19 and 20 provided corresponding to memory blocks MB0 and MB1, respectively. In FIG. 2, the illustration of the memory block MB1, the DL driver 6, the BL drivers 10, 13 and the BL bias circuit 16 corresponding to the memory block MB1 is omitted for simplification of the drawing. DL driver 6 includes an N channel MOS transistor 7 provided corresponding to each digit line DL. One end of each digit line DL is connected to a power supply voltage VDD line, and the other end is connected to a ground voltage VSS line via a corresponding N-channel MOS transistor 7. The gate of each N channel MOS transistor 7 receives signal φD.

  When one of the plurality of digit lines DL is selected by the row decoder 2 during data writing, the signal φD corresponding to the digit line DL is set to the activation level “H” level, N channel MOS transistor 7 corresponding to the signal φD is rendered conductive, and a write current flows through selected digit line DL.

  BL driver 10 includes a P channel MOS transistor 11 and an N channel MOS transistor 12 provided corresponding to each of a plurality of bit lines BL and reference bit line RBL. P channel MOS transistor 11 is connected between a line of power supply voltage VDD and one end of corresponding bit line BL or RBL, and its gate receives signal φW1. N-channel MOS transistor 12 is connected between one end of corresponding bit line BL or RBL and the line of ground voltage VSS, and has its gate receiving signal φW1.

  BL driver 13 includes a P channel MOS transistor 14 and an N channel MOS transistor 15 provided corresponding to each of a plurality of bit lines BL and reference bit line RBL. P-channel MOS transistor 14 is connected between a line of power supply voltage VDD and the other end of corresponding bit line BL or RBL, and has its gate receiving signal φW2. N channel MOS transistor 15 is connected between the other end of corresponding bit line BL or RBL and the line of ground voltage VSS, and has its gate receiving signal φW2.

  When data signal D0 is at “H” level during data writing, for example, signals φW1 and φW2 corresponding to bit line BL or RBL of the column selected by column decoder 3 are at “L” level and “H” level, respectively. To the level. As a result, the transistors 11 and 15 corresponding to the bit line BL or RBL become conductive and the transistors 12 and 14 become non-conductive, and the transistor 11, the bit line BL or RBL, and the transistor 15 are connected from the power supply voltage VDD line. Thus, a write current flows through the line of the ground voltage VSS.

  At the time of data writing, if data signal D0 is at “L” level, for example, signals φW1 and φW2 corresponding to bit line BL or RBL in the column selected by column decoder 3 are at “H” level and It is set to “L” level. As a result, the transistors 12 and 14 corresponding to the bit line BL or RBL are turned on and the transistors 11 and 15 are turned off, and the transistor 14, the bit line BL or RBL, and the transistor 12 are connected from the power supply voltage VDD line. Thus, a write current flows through the line of the ground voltage VSS.

  Accordingly, a write current is supplied to one digit line DL by the DL driver 6 and a write current in a direction corresponding to the write data signal D is supplied to one bit line BL or RBL by the BL drivers 10 and 16. Thus, the data signal D can be written to the memory cell MC at the intersection of the digit line DL and the bit line BL or RBL.

  BL bias circuit 16 includes an N-channel MOS transistor 17 provided corresponding to each of the plurality of bit lines BL and reference bit line RBL. The drain of each N channel MOS transistor 17 receives a bias voltage VB, its source is connected to the corresponding bit line BL or RBL, and its gate receives a signal φR.

  When one of a plurality of columns is selected by column decoder 3 at the time of data reading, signal φR corresponding to bit line BL and reference bit line RBL of that column is set to the activation level “H” level. Is done. As a result, N channel MOS transistor 17 corresponding to signal φR is rendered conductive, and bias voltage VB is applied to bit lines BL and RBL corresponding to signal φR.

  The column selection gate 18 connects the source line SL0 or SL1 of the memory block MB0 selected by the column decoder 3 to one input node 19a of the comparison circuit 19 and reads the reference source line RSL1 or RSL0 at the time of data reading. To the other input node 19b. Column select gate 18 connects source line SL0 or SL1 of memory block MB1 selected by column decoder 3 to one input node 20a of comparison circuit 20 and compares reference source line RSL1 or RSL0 during data reading. Connected to the other input node 20b of the circuit 20. The other input nodes 19b and 20b of the comparison circuits 19 and 20 are connected to each other.

  The comparison circuit 19 compares the value of the current flowing through the selected source line SL0 or SL1 with the average value of the current flowing through the reference source lines RSL0 and RSL1, and outputs a data signal Q0 having a logic level according to the comparison result. To do. The comparison circuit 20 compares the value of the current flowing through the selected source line SL0 or SL1 with the average value of the current flowing through the reference source lines RSL0 and RSL1, and outputs a data signal Q1 having a logic level according to the comparison result. To do.

  FIG. 8 is a circuit diagram showing the configuration of the comparison circuits 19 and 20. In FIG. 8, the column selection gate 18 connects the source lines SL0 and SL1 to the one input nodes 19a and 20a of the comparison circuits 19 and 20, respectively, and the reference source lines RSL1 and RSL0 are the other input nodes 19b of the comparison circuits 19 and 20, respectively. , 20b are shown connected. The resistance values of the tunnel magnetoresistive elements TMR corresponding to the reference source lines RSL0 and RSL1 are set to the high level value RH and the low level value RL, respectively, and the resistance values R0, RMR of the tunnel magnetoresistive elements TMR corresponding to the source lines SL0, SL1 are set. Each of R1 is set to a high level value RH or a low level value RL. A bias voltage VB (for example, a voltage of about 0.3 to 2 V) is applied to each of the bit line BL and the reference bit line RBL.

  In FIG. 8, comparison circuit 19 includes P channel MOS transistors 21 and 22, N channel MOS transistors 23 and 24, and differential amplifier 25. Transistors 21 and 23 are connected in series between one input node 19a and a negative voltage VN (for example, -0.7V) line, and transistors 22 and 24 are connected in series between the other input node 19b and a negative voltage VN line. It is connected.

  P-channel MOS transistors 21 and 22 constitute a clamp circuit that fixes the voltages of input nodes 19a and 19b to ground voltage VSS. That is, a predetermined voltage VSAN is applied to the gates of the P channel MOS transistors 21 and 22. The voltage VSAN is set in advance so that the voltages of the input nodes 19a and 19b become the ground voltage VSS. Voltage VSAN is a voltage 0− | Vthp | + α that is slightly larger than the voltage obtained by subtracting the absolute value | Vthp | of the threshold voltage of P channel MOS transistors 21 and 22 from 0V.

  A ground voltage VSS is applied to the gates of the N-channel MOS transistors 23 and 24, and a negative voltage VN is applied to their back gates. Each of N channel MOS transistors 23 and 24 constitutes a load resistance element having a predetermined resistance value. A voltage that is the product of the value of the current flowing through the source line SL 0 and the resistance value of the transistor 23 is generated at the drain of the transistor 23. A voltage that is the product of the average value of the currents flowing through the reference source lines RSL 0 and RSL 1 and the resistance value of the transistor 23 is generated at the drain of the transistor 24.

  The differential amplifier 25 compares the drain voltages of the transistors 23 and 24 and outputs a data signal Q0 having a logic level corresponding to the comparison result. For example, when the resistance value of tunneling magneto-resistance element TMR is high level value RH, the data signal is “H” level (data “1”), and the resistance value of tunneling magneto-resistance element TMR is low level value RL. Are set to the “L” level (data “0”). In this case, the differential amplifier 25 sets the data signal Q0 to “H” level when the drain voltage of the transistor 23 is lower than the drain voltage of the transistor 24, and sets the data signal Q0 to “L” level when it is higher.

  The comparison circuit 20 has the same configuration as the comparison circuit 19. In the comparison circuit 20, a voltage that is the product of the value of the current flowing through the source line SL1 and the resistance value of the transistor 23 is generated at the drain of the transistor 23. A voltage that is the product of the average value of the currents flowing through the reference source lines RSL 0 and RSL 1 and the resistance value of the transistor 23 is generated at the drain of the transistor 24. The differential amplifier 25 compares the drain voltages of the transistors 23 and 24 and outputs a data signal Q1 having a logic level corresponding to the comparison result.

  In the first embodiment, the word line WL is provided in each row, the bit line BL and the source lines SL0 and SL1 are provided in each column, and the storage data of the memory cell MC is read through the source lines SL0 and SL1, so that the parasitic capacitance Compared to the conventional case where the stored data of the memory cell MC is read via the bit line BL having a large length, the data can be read quickly.

  In addition, since each of source lines SL0, SL1, RSL0, and RSL1 is clamped to ground voltage VSS, the voltages of source lines SL0, SL1, RSL0, and RSL1 are increased, the resistance value of access transistor ATR is increased, and the reading speed is increased. It is possible to prevent the decrease.

[Embodiment 2]
FIG. 9 is a circuit diagram showing the main part of the MRAM according to the second embodiment of the present invention, which is compared with FIG. In FIG. 9, the MRAM differs from the MRAM according to the first embodiment in that the comparison circuits 19 and 20 are replaced with comparison circuits 30 and 31, respectively. In FIG. 9, the source lines SL0 and SL1 are connected to one input nodes 30a and 31a of the comparison circuits 30 and 31, respectively, and the reference source lines RSL1 and RSL0 are connected to the other input node 30b of the comparison circuits 30 and 31, respectively. , 31b are shown connected. A bias voltage VB (for example, a voltage of about 0.3 to 2 V) is applied to each of the bit line BL and the reference bit line RBL.

  In FIG. 9, comparison circuit 30 includes P-channel MOS transistors 32 and 33, N-channel MOS transistors 34 to 37, and differential amplifier 38. Transistors 32, 34, and 36 are connected in series between a line of power supply voltage VDD (for example, 1.2V) and a line of negative voltage VN (for example, -0.7V), and transistors 33, 35, and 37 are connected to power supply voltage VDD. And the negative voltage VN line are connected in series. The sources of the transistors 34 and 35 are connected to the input nodes 30a and 30b, respectively.

  A ground voltage VSS is applied to the gates of the P-channel MOS transistors 32 and 33. Each of P channel MOS transistors 32 and 33 constitutes a load resistance element having a predetermined resistance value.

  N-channel MOS transistors 34 and 35 constitute a clamp circuit that fixes the voltage of input nodes 30a and 30b to ground voltage VSS. That is, a predetermined voltage VSAP is applied to the gates of the P channel MOS transistors 34 and 35. The voltage VSAP is set in advance so that the voltages of the input nodes 30a and 30b become the ground voltage VSS. Voltage VSAP is a voltage Vthn-α that is slightly smaller than threshold voltage Vthn of N-channel MOS transistors 34 and 35.

  A ground voltage VSS is applied to the gates of the N-channel MOS transistors 36 and 37, and a negative voltage VN is applied to their back gates. Each of N channel MOS transistors 36 and 37 constitutes a load resistance element having a predetermined resistance value. Since the voltages of input nodes 30a and 30b are fixed to ground voltage VSS, a constant current flows through each of N channel MOS transistors 36 and 37.

A current I ₃₂ = I _C −I _{SL0, which} is the difference between the constant current I _C flowing through the transistor 36 and the current I _SL0 flowing through the source line SL 0, flows through the transistor ₃₂ . When the resistance value of the transistor 32 is R _C , the drain voltage V ₃₂ of the transistor 32 is V ₃₂ = VDD−R _C × I ₃₂ = VDD−R _C × (I _C −I _SL0 ). Further, when the average value of the currents flowing through the reference source lines RSL0 and RSL1 is I _TH , the drain voltage V ₃₃ of the transistor ₃₃ is V ₃₃ = VDD− _RC × (I _C −I _TH ).

The differential amplifier 38 compares the drain voltages V ₃₂ and V ₃₃ of the transistors ₃₂ and ₃₃ , and outputs a data signal Q0 having a logic level corresponding to the comparison result. For example, when the resistance value of tunneling magneto-resistance element TMR is high level value RH, the data signal is “H” level (data “1”), and the resistance value of tunneling magneto-resistance element TMR is low level value RL. Are set to the “L” level (data “0”). In this case, the differential amplifier 38, and a data signal Q0 to the "H" level when the drain voltage V ₃₂ of the transistor 32 is lower than the drain voltage V ₃₃ of the transistor 33, "L" data signal Q0 is higher To level.

The comparison circuit 31 has the same configuration as the comparison circuit 30. In the comparison circuit 31, a current I ₃₂ = I _C −I _{SL1, which} is the difference between the constant current I _C flowing in the transistor 36 and the current I _SL1 flowing in the source line SL 1, flows in the transistor 32. The drain voltage V ₃₂ of the transistor 32 is V ₃₂ = VDD− _RC × (I _C −I _SL1 ). The drain voltage _{V 33} of the transistor 33 _{becomes V 33 = VDD-R C ×} (I C -I TH). The differential amplifier 38 compares the drain voltages V ₃₂ and V ₃₃ of the transistors ₃₂ and ₃₃ , and outputs a data signal Q1 having a logic level corresponding to the comparison result.

  Also in this second embodiment, the same effect as in the first embodiment can be obtained. Also, since only one transistor 36 is connected between the input node (for example, 30a) to be clamped to the ground voltage VSS and the negative voltage VN line, it is between the input node (for example, 19a) and the negative voltage VN line. The absolute value of the negative voltage VN can be made smaller than in the first embodiment in which the two transistors 21 and 23 are connected to each other, and the configuration of the negative voltage generating circuit can be simplified. Further, since the gate voltage VSAP of the transistors 34 and 35 constituting the clamp circuit can be made positive, the gate voltage VSAP of the transistors 34 and 35 is compared with the first embodiment in which the gate voltage VSAN of the transistors 21 and 22 is negative. Can be adjusted easily.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows the whole structure of MRAM by Embodiment 1 of this invention. FIG. 2 is a circuit block diagram showing a configuration of a memory array and a write / read circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing a configuration of a memory cell shown in FIG. 2. FIG. 4 is a diagram for explaining a method of writing data in the memory cell shown in FIG. 3. FIG. 4 is another diagram for explaining a data writing method of the memory cell shown in FIG. 3. FIG. 4 is a diagram for explaining a data reading method of the memory cell shown in FIG. 3. FIG. 3 is a diagram showing a layout of the memory array shown in FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a comparison circuit shown in FIG. 2. It is a circuit diagram which shows the principal part of MRAM by Embodiment 2 of this invention.

Explanation of symbols

  1 memory array, MB memory block, 2 row decoder, 3 column decoder, 4 write / read circuit, 5 control circuit, MC memory cell, WL word line, DL digit line, BL bit line, RBL reference bit line, SL source Line, RSL reference source line, 6 DL driver, 7, 12, 17, 23, 24, 34, 37 N channel MOS transistor, 10, 13 BL driver, 11, 14, 21, 22, 32, 33 P channel MOS transistor , 18 column selection gate, 19, 20, 30, 31 comparison circuit, TMR tunnel magnetoresistive element, ATR access transistor, EL electrode, FL fixed magnetization film, TB tunnel insulation film, VL free magnetization film, NDN type diffusion region, CH contact hole, 25, 38 differential amplifier.

Claims (2)

A plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, a plurality of bit lines provided corresponding to the plurality of columns, respectively, A memory array including a plurality of source lines provided corresponding to a plurality of columns;
Each memory cell is connected in series with a resistor memory element that stores data according to a change in resistance value level, and a corresponding bit line and a source line, and the corresponding word line is set to a selected level. And a transistor that conducts in response to
A row decoder for setting a word line corresponding to the selected memory cell of the plurality of memory cells to a selection level and conducting a transistor of the selected memory cell;
A read circuit for reading data of the selected memory cell via a source line corresponding to the selected memory cell;
The readout circuit includes:
A bit line bias circuit for applying a predetermined bias voltage to the bit line corresponding to the selected memory cell;
A clamp circuit for setting the voltage of the source line corresponding to the selected memory cell to the ground voltage,
Based on the current flowing through the source line corresponding to the selected memory cell, and read out the data of the selected memory cell,
The clamp circuit includes a P-channel MOS transistor having a source connected to a source line corresponding to the selected memory cell and a gate receiving a predetermined voltage,
The readout circuit includes:
A load element having one electrode connected to the drain of the P-channel MOS transistor and the other electrode receiving a predetermined negative voltage;
A non-volatile semiconductor memory device including a comparison circuit that compares a voltage of one electrode of the load element with a predetermined reference voltage and outputs a data signal of a logic level according to the comparison result . A plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, a plurality of bit lines provided corresponding to the plurality of columns, respectively, A memory array including a plurality of source lines provided corresponding to a plurality of columns;
Each memory cell is connected in series with a resistor memory element that stores data according to a change in resistance value level, and a corresponding bit line and a source line, and the corresponding word line is set to a selected level. And a transistor that conducts in response to
A row decoder for setting a word line corresponding to the selected memory cell of the plurality of memory cells to a selection level and conducting a transistor of the selected memory cell;
A read circuit for reading data of the selected memory cell via a source line corresponding to the selected memory cell;
The readout circuit includes:
A bit line bias circuit for applying a predetermined bias voltage to the bit line corresponding to the selected memory cell;
A clamp circuit for setting the voltage of the source line corresponding to the selected memory cell to the ground voltage,
Based on the current flowing in the source line corresponding to the selected memory cell, the data of the selected memory cell is read,
The clamp circuit includes an N-channel MOS transistor having a source connected to a source line corresponding to the selected memory cell and a gate receiving a predetermined voltage.
The readout circuit includes:
A first load element having one electrode connected to the source of the N-channel MOS transistor and the other electrode receiving a predetermined negative voltage;
A second load element having one electrode receiving a power supply voltage and the other electrode connected to the drain of the N-channel MOS transistor;
The second compares the voltage with a predetermined reference voltage of the other electrode of the load element, and a comparator circuit for outputting a logic level of the data signal corresponding to the comparison result, nonvolatile semiconductor memory device.

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