WO2020238288A1 - Substrat matriciel et son procédé de préparation et dispositif d'affichage - Google Patents

Substrat matriciel et son procédé de préparation et dispositif d'affichage Download PDF

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Publication number
WO2020238288A1
WO2020238288A1 PCT/CN2020/075610 CN2020075610W WO2020238288A1 WO 2020238288 A1 WO2020238288 A1 WO 2020238288A1 CN 2020075610 W CN2020075610 W CN 2020075610W WO 2020238288 A1 WO2020238288 A1 WO 2020238288A1
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WIPO (PCT)
Prior art keywords
base substrate
layer
orthographic projection
conductive
gate
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PCT/CN2020/075610
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English (en)
Chinese (zh)
Inventor
黄勇潮
成军
王东方
刘军
张扬
王庆贺
周斌
何敏
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2020238288A1 publication Critical patent/WO2020238288A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diode
  • electroluminescent diodes have the advantages of self-emission and low energy consumption. , Is one of the hot spots in the application research field of electroluminescent display devices.
  • the base substrate includes: a plurality of sub-pixels
  • the semiconductor layer is located on the base substrate, and the semiconductor layer includes an active layer located in each of the sub-pixels; wherein, the active layer includes a channel region and a conductive region;
  • a gate insulating layer located on the side of the semiconductor layer away from the base substrate;
  • the first conductive layer is located on the side of the gate insulating layer away from the base substrate;
  • An interlayer dielectric layer located on the side of the first conductive layer away from the base substrate;
  • the second conductive layer is located on the side of the interlayer dielectric layer away from the base substrate, and the second conductive layer includes: a capacitor electrode located in each of the sub-pixels;
  • the orthographic projection of the capacitor electrode on the base substrate and the conductive area of the active layer on the orthographic projection of the base substrate have a first overlap area, and the orthographic projection has The capacitor electrode in the first overlap area and the conductive area of the active layer form a storage capacitor;
  • the insulating dielectric layer located between the capacitor electrode in the first overlap area and the conductive area of the active layer has a first thickness, and the remaining area
  • the insulating dielectric layer has a second thickness, and the first thickness is smaller than the second thickness.
  • the first conductive layer includes a gate located in each of the sub-pixels; the orthographic projection of the gate insulating layer on the base substrate and the gate located at the The orthographic projection of the base substrate at least partially overlaps; and the orthographic projection of the gate and the gate insulating layer on the base substrate does not overlap with the first overlap region;
  • the orthographic projection of the interlayer dielectric layer on the base substrate covers the base substrate
  • the insulating dielectric layer includes the interlayer dielectric layer.
  • the first conductive layer further includes a plurality of first gate lines and a plurality of second gate lines; wherein, a row of sub-pixels corresponds to one first gate line and one Second grid line
  • the orthographic projection of the capacitor electrode on the base substrate is located where the first gate is on the The orthographic projection of the base substrate and the second gate line are between the orthographic projection of the base substrate.
  • the sub-pixel further includes a driving transistor and an electroluminescent diode;
  • the second conductive layer further includes a first power line;
  • the active layer further includes: a first source region and a first drain region of the driving transistor; wherein the first source region is electrically connected to the first power line, and the first drain The zone is electrically connected to the electroluminescent diode.
  • the first source region is located on the side of the channel region away from the conductive region
  • the first drain region is located on the side of the conductive region away from the conductive region.
  • the orthographic projection of the first source region on the base substrate is close to the orthographic projection of the first gate line on the base substrate relative to the orthographic projection of the first drain region on the base substrate, And the orthographic projection of the first drain region on the base substrate is close to the orthographic projection of the second gate line on the base substrate relative to the orthographic projection of the first source region on the base substrate .
  • the gate of the driving transistor is electrically connected to the capacitor electrode, the first source region serves as the first electrode of the driving transistor, and the first drain region As the second pole of the driving transistor;
  • the second conductive layer further includes: a plurality of data lines and a plurality of detection lines arranged at intervals from the capacitor electrode; wherein, one column of sub-pixels corresponds to one data line;
  • the sub-pixel further includes: a switching transistor and a sensing transistor;
  • the gate of the switching transistor is electrically connected to a first gate line, the first electrode of the switching transistor is electrically connected to the data line, and the second electrode of the switching transistor is electrically connected to the capacitor electrode;
  • the gate of the sensing transistor is electrically connected to a second gate line
  • the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor
  • the second electrode of the sensing transistor is electrically connected to a
  • the detection line is electrically connected.
  • the array substrate further includes:
  • a buffer layer located between the semiconductor layer and the base substrate
  • the light-shielding electrode layer is located between the buffer layer and the base substrate;
  • the light-shielding electrode layer includes a plurality of light-shielding electrodes arranged at intervals; wherein, one of the light-shielding electrodes is provided in one of the sub-pixels;
  • the orthographic projection of the shading electrode on the base substrate covers the orthographic projection of the active layer of the driving transistor on the base substrate.
  • the first thickness E satisfies:
  • the semiconductor layer includes an active layer located in each of the sub-pixels; wherein the active layer includes a channel region and a conductive region;
  • the second conductive layer is formed on the side of the interlayer dielectric layer away from the base substrate; wherein, the second conductive layer includes: capacitor electrodes located in each of the sub-pixels; and in the same sub-pixel ,
  • the orthographic projection of the capacitor electrode on the base substrate and the orthographic projection of the conductive area of the active layer on the base substrate have a first overlap area, and the orthographic projection has a first overlap area.
  • the capacitor electrode and the conductive area of the active layer form a storage capacitor; and, on a plane perpendicular to the base substrate, the capacitor electrode and the active layer located in the first overlapping area
  • the insulating dielectric layer between the layers has a first thickness, and the insulating dielectric layers in the remaining regions have a second thickness;
  • the method further includes: performing a thinning treatment on the insulating dielectric layer located in the first overlap region, so that the first A thickness is smaller than the second thickness.
  • the insulating dielectric layer includes an interlayer dielectric layer.
  • a dry etching process is used to thin the interlayer dielectric layer located in the first overlap region.
  • the method before forming the semiconductor layer on the base substrate, the method further includes:
  • a buffer layer is formed on the side of the light-shielding metal layer away from the base substrate.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned array substrate.
  • FIG. 1 is a schematic top view of the structure of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a circuit structure in a sub-pixel provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of a layout structure in sub-pixels provided by an embodiment of the disclosure.
  • FIG. 4a is a schematic diagram of a layout structure of a semiconductor layer provided by an embodiment of the disclosure.
  • 4b is a schematic diagram of the layout structure of the first conductive layer provided by an embodiment of the disclosure.
  • 4c is a schematic diagram of the layout structure of the second conductive layer provided by an embodiment of the disclosure.
  • 4d is a schematic diagram of the layout structure of a light-shielding metal layer provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic cross-sectional structure view along the BB' direction in FIG. 3 according to an embodiment of the disclosure
  • 6 to 9 are schematic diagrams of the cross-sectional structure of film layer changes along the AA' direction during the preparation process of the array substrate in FIG. 3 provided by the embodiments of the disclosure;
  • Fig. 10 is a flow chart of a preparation method provided by an embodiment of the disclosure.
  • the thickness of the conductive film in the display panel is getting thicker and thicker, and the thickness of the corresponding insulating layer is also increasing. The thicker.
  • the thickness of the insulating layer located between the two electrodes of the storage capacitor in the pixel unit will also increase. According to the formula satisfied by the capacitor, when the facing area is fixed, if the thickness of the insulating layer between the two electrodes of the storage capacitor increases, the capacitance value of the storage capacitor will decrease, resulting in a decrease in transistor efficiency.
  • the embodiments of the present disclosure provide an array substrate, which can increase the capacitance value of the storage capacitor when the facing area is fixed, so that the efficiency of the driving transistor can be effectively improved and the brightness of the pixel can be improved.
  • the array substrate provided by the embodiment of the present disclosure may include: a base substrate 1.
  • the base substrate 1 may be a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited herein.
  • the array substrate may include a display area AA and a frame area surrounding the display area AA1. Elements such as an electrostatic discharge circuit and a gate drive circuit can be arranged in the frame area.
  • the array substrate may not be provided with a frame area, which can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • the display area AA may include a plurality of pixel units PX, for example, a plurality of pixel units PX.
  • At least one pixel unit PX may include a plurality of sub-pixels.
  • each pixel unit may include multiple sub-pixels.
  • each sub-pixel can be provided with an electroluminescent diode and a pixel driving circuit, so that the electroluminescent diode can be driven to emit light through the pixel driving circuit.
  • the electroluminescent diode may include: at least one of OLED, QLED, and Micro LED.
  • the specific implementation of the electroluminescent diode can be set according to the requirements of the actual application environment, which is not limited here.
  • a pixel unit usually includes a plurality of sub-pixels that can respectively display a single color (for example, red, green, or blue), so as to realize different colors by controlling the light-emitting ratio of the sub-pixels of different colors.
  • a single color for example, red, green, or blue
  • the above-mentioned sub-pixels may be set as monochromatic sub-pixels.
  • the pixel unit PX may include: a first color sub-pixel 010, a second color sub-pixel 020, and a third color sub-pixel 030.
  • the first color sub-pixel is configured to emit light of a first color
  • the second color sub-pixel is configured to emit light of a second color
  • the third color sub-pixel is configured to emit light of a third color.
  • the first color, the second color, and the third color can be selected from red, green, and blue.
  • the first color is red
  • the second color is green
  • the third color is blue. Therefore, the pixel unit PX may be an arrangement structure of red, green and blue sub-pixels.
  • the embodiments of the present disclosure include but are not limited thereto, and the aforementioned first color, second color, and third color may also be other colors.
  • the first-color sub-pixels, the second-color sub-pixels, and the third-color sub-pixels are sequentially arranged along the second direction F2 (for example, the direction indicated by the F2 arrow in FIG. 1), and the colors of the sub-pixels in the same column are the same.
  • F2 for example, the direction indicated by the F2 arrow in FIG. 1
  • the embodiments of the present disclosure include but are not limited to this.
  • the pixel driving circuit may include: a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst.
  • the gate of the switching transistor T2 is electrically connected to the first gate line G1
  • the first electrode (for example, the source) of the switching transistor T2 is electrically connected to the data line DA
  • the second electrode (for example, the drain) of the switching transistor T2 is electrically connected to the driving The gate of the transistor T1 is electrically connected.
  • the first electrode (for example, the source) of the driving transistor T1 is electrically connected to the first power line OVDD
  • the second electrode (for example, the drain) of the driving transistor T1 is electrically connected to the anode of the electroluminescent diode L.
  • the cathode is electrically connected to the second power line OVSS.
  • the gate of the sensing transistor T3 is electrically connected to the second gate line G2
  • the first electrode (for example, the source) of the sensing transistor T3 is electrically connected to the second electrode (for example, the drain) of the driving transistor T1
  • the The second electrode (for example, the drain) is electrically connected to the detection line SL.
  • the second electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the first electrode of the storage capacitor Cst is electrically connected to the second electrode (for example, the drain) of the driving transistor T1.
  • the second electrode of the driving transistor T1 is electrically connected to the anode of the electroluminescent diode.
  • the switching transistor T2 is controlled to be turned on by the signal transmitted on the first gate line G1 to write the data voltage transmitted on the data line DA into the gate of the driving transistor T1, and the driving transistor T1 is controlled to generate a working current to drive the electromotive force.
  • the light emitting diode L emits light.
  • the sensing transistor T3 is controlled to be turned on by the signal transmitted on the second gate line G2 to output the operating current generated by the driving transistor T1 to the detection line SL to charge the detection line SL. After that, by detecting the voltage on each detection line SL, and performing compensation calculation based on the detected voltage, the data voltage corresponding to each sub-pixel in the row is obtained for display.
  • the first power line OVDD may transmit a constant first voltage, which is a positive voltage; and the second power line OVSS may transmit a constant second voltage, which is a negative voltage. Or, in some examples, the second power line OVSS may also be grounded.
  • the pixel driving circuit may be a structure including other numbers of transistors and capacitors in addition to the structure shown in FIG. 2, which is not limited in the embodiment of the present disclosure.
  • the array substrate may further include: multiple detection lines SL, multiple data lines (for example, DA-010, DA-020, DA-030), and The first power line OVDD.
  • multiple detection lines SL for example, DA-010, DA-020, DA-030
  • the first power line OVDD exemplary, one column of sub-pixels corresponds to one data line, and the detection line SL is located in the gap between two adjacent pixel unit columns.
  • the detection line SL is located in the gap between two adjacent pixel unit columns.
  • a detection line SL is provided in the gap between the first pixel unit column and the second pixel unit column, and another detection line SL is provided in the gap between the third pixel unit column and the fourth pixel unit column.
  • the multiple data lines may include: data lines DA-010, DA-020, and DA-030.
  • one data line DA-010 corresponds to a column of first color sub-pixels 010
  • one data line DA-010 is electrically connected to the switching transistor T2 in a column of first color sub-pixels 010.
  • One data line DA-020 corresponds to a column of second color sub-pixels 020
  • one data line DA-020 is electrically connected to the switching transistor T2 in a column of second color sub-pixels 020.
  • One data line DA-030 corresponds to a row of third-color sub-pixels 030, and one data line DA-030 is electrically connected to the switching transistor T2 in a row of third-color sub-pixels 030.
  • a data line DA-010 and a data line DA-020 are arranged between a first color sub-pixel and a second color sub-pixel, and a second color sub-pixel and a third color sub-pixel are arranged.
  • a data line DA-030 is set between the color sub-pixels.
  • the data line DA-010 is located between the first color sub-pixel and the data line DA-020.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • Figs. 3 to 5 are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the present disclosure. The positional relationship of the pixel driving circuit on the base substrate 1 will be described below with reference to FIGS. 3 to 5.
  • a semiconductor layer 100 is provided on the base substrate 1.
  • the semiconductor layer 100 may be formed by patterning a semiconductor material.
  • the semiconductor layer 100 may include an active layer located in each sub-pixel.
  • the semiconductor layer 100 may include the active layer 21 of the driving transistor T1, the active layer 22 of the switching transistor T2, and the sensing transistor in the first color sub-pixel 010, the second color sub-pixel 020, and the third color sub-pixel 030.
  • Each active layer 21-23 may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the active layer 21 may further include a conductive area B; wherein the conductive area B may form the first pole of the storage capacitor Cst.
  • the active layer 21 may include: a first source region T1-S, a first drain region T1-D, a channel region A1, and a conductive region B.
  • the first source region T1-S can be used as the first electrode (for example, the source) of the driving transistor, and the first drain region can be used as the second electrode (for example, the drain) of the driving transistor.
  • the embodiments of the present disclosure include but are not limited to this.
  • the active layers 21 to 23 of each transistor are arranged at intervals.
  • the semiconductor layer 100 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source and drain regions may be regions doped with n-type impurities or p-type impurities.
  • the aforementioned conductive area B may be a conductive area formed after ion doping of the semiconductor layer 100.
  • the embodiments of the present disclosure include but are not limited to this.
  • the array substrate may further include a first conductive layer 200 on the side of the semiconductor layer 100 away from the base substrate 1.
  • a gate insulating layer 410 is formed between the aforementioned semiconductor layer 100 and the first conductive layer 200.
  • the first conductive layer 200 is disposed on the gate insulating layer 410 so as to be insulated from the semiconductor layer 100.
  • the first conductive layer 200 may include a plurality of first gate lines G1, a plurality of second gate lines G2, and a plurality of gates 4. Wherein, each sub-pixel is provided with a gate 4, and a row of sub-pixels corresponds to a first gate line G1 and a second gate line G2.
  • first gate line G1 and the second gate line G2 extend along the first direction and are arranged along the second direction.
  • the orthographic projection of the gate 4 on the base substrate 1 is located on the first gate line G1 and the second gate line G1 corresponding to the sub-pixel.
  • the line G2 is between the orthographic projections of the base substrate 1.
  • the orthographic projection of the conductive area B on the base substrate 1 is also located between the orthographic projection of the first gate line G1 and the second gate line G2 corresponding to the sub-pixel on the base substrate 1.
  • the gate of the switching transistor T2 may be the overlapping portion of the first gate line G1 and the semiconductor layer 100
  • the gate of the sensing transistor T3 may be The portion where the second gate line G2 overlaps the semiconductor layer 100.
  • the gate 4 can drive the gate of the transistor T1. It should be noted that the dashed rectangular frames A1, A2, and A3 in FIG. 4a show areas where the first conductive layer 200 and the semiconductor layer 100 overlap.
  • an interlayer dielectric layer 420 is provided on the side of the aforementioned first conductive layer 200 away from the base substrate 1 to protect the aforementioned first conductive layer 200.
  • the array substrate may further include a second conductive layer 300 on the side of the first conductive layer 200 away from the base substrate 1.
  • an interlayer dielectric layer 420 is provided between the first conductive layer 200 and the second conductive layer 300.
  • the second conductive layer 300 may include: a plurality of detection lines SL arranged at intervals, a plurality of data lines DA-010 (of course, the data lines DA-020 and DA-030), a first power line OVDD, a capacitor The electrode 71 and the connecting portions 72 and 73.
  • a capacitor electrode 71 is provided in each sub-pixel, and the capacitor electrode 71 serves as the second pole of the storage capacitor Cst. That is, the gate of the driving transistor is electrically connected to the capacitor electrode 71, and the second electrode of the switching transistor is electrically connected to the capacitor electrode 71.
  • the data lines DA-010, DA-020, and DA-030 can be extended along the first direction F1 and arranged along the second direction F2.
  • the data lines DA-010, DA-020, and DA-030 are respectively electrically connected to the first electrode of the switching transistor through a portion protruding in the second direction F2.
  • a planarization layer is provided on the side of the second conductive layer 300 away from the base substrate 1 to protect the second conductive layer 300 and achieve the planarization effect.
  • the anode of the electroluminescent diode is provided on the side of the planarization layer away from the base substrate 1.
  • a pixel defining layer is provided on the side of the anode away from the base substrate 1; wherein the pixel defining layer has a plurality of light-emitting opening areas, and one anode corresponds to one light-emitting opening area to expose the corresponding anode through the light-emitting opening area.
  • a light-emitting function layer and a cathode are sequentially arranged on the side of the pixel defining layer away from the base substrate 1.
  • the light-emitting functional layer directly contacts the anode through the light-emitting opening area
  • the light-emitting functional layer directly contacts the cathode, so as to drive the light-emitting functional layer to emit light through the signal loaded on the anode and the signal loaded on the cathode.
  • the present disclosure includes but is not limited to this.
  • a hole transport layer and a hole injection layer can also be arranged between the light-emitting functional layer and the anode, and film layers such as an electron transport layer and an electron injection layer can also be arranged between the light-emitting functional layer and the cathode layer.
  • film layers such as an electron transport layer and an electron injection layer can also be arranged between the light-emitting functional layer and the cathode layer.
  • the anode, the light-emitting functional layer, and the cathode can be stacked to form an electroluminescent diode.
  • a gate insulating layer 410 is provided between the semiconductor layer 100 and the first conductive layer 200, and a gate insulating layer 410 is provided between the first conductive layer 200 and the second conductive layer 300.
  • the detection line SL is electrically connected to the source region of the active layer of the sensing transistor T3 through the via 511.
  • One end of the connecting portion 72 is electrically connected to the drain region of the active layer of the sensing transistor T3 through a via 512, and the other end of the connecting portion 72 is electrically connected to the drain region of the active layer of the driving transistor through a via 513.
  • the capacitor electrode 71 is electrically connected to the gate 4 of the driving transistor through the via hole 514, and the capacitor electrode 71 is also electrically connected to the drain region of the active layer of the switching transistor through the via hole 515.
  • the data line DA-010 is electrically connected to the source region of the active layer of the switching transistor through the via 516.
  • One end of the connecting portion 73 is electrically connected to the first power supply line OVDD through the via 517, and the other end of the connecting portion 73 is electrically connected to the source region of the active layer of the driving transistor through the via 518.
  • the anode is electrically connected to the connection portion 72 through a via 519 penetrating the planarization layer.
  • a buffer layer is also provided between the semiconductor layer 100 and the base substrate 1.
  • a light-shielding electrode layer 400 is also provided between the buffer layer and the base substrate 1.
  • the light-shielding electrode layer 400 may include a plurality of light-shielding electrodes 3, and one light-shielding electrode 3 is provided in one sub-pixel.
  • the orthographic projection of the light shielding electrode 3 on the base substrate 1 covers the orthographic projection of the active layer of the driving transistor on the base substrate 1.
  • the present disclosure includes but is not limited to this.
  • each sub-pixel is provided with a capacitor electrode 71, respectively.
  • the orthographic projection of the capacitor electrode 71 on the base substrate 1 and the orthographic projection of the conductive area B of the active layer on the base substrate 1 have a first overlap zone Z, and the orthographic projection has a first overlap.
  • the capacitor electrode 71 of an overlap zone Z and the conductive area B of the active layer form a storage capacitor Cst; wherein, the capacitor electrode 71 located in the first overlap zone Z forms the second electrode of the storage capacitor Cst, which is located in the first
  • the conductive area B of the active layer 21 in an overlap area Z forms the first pole of the storage capacitor Cst.
  • the insulating dielectric layer located between the capacitor electrode 71 in the first overlap zone Z and the conductive zone of the active layer has a first thickness E1, and the insulation of the remaining zone
  • the dielectric layer has a second thickness E2, and the first thickness E1 is smaller than the second thickness E2.
  • the insulating dielectric layer located between the capacitor electrode 71 and the active layer in the first overlap zone Z has a first thickness E1
  • the insulating dielectric layer in the remaining area has a second thickness E2.
  • each sub-pixel is provided with a gate, for example, each sub-pixel is provided with a driving transistor T1.
  • the orthographic projection of the gate insulating layer 410 on the base substrate 1 and the orthographic projection of the gate on the base substrate 1 at least partially overlap.
  • the orthographic projection of the gate insulating layer 410 on the base substrate 1 and the orthographic projection of the gate on the base substrate 1 may overlap, or the orthographic projection of the gate insulating layer 410 on the base substrate 1 covers the gate on the base substrate 1. 1.
  • Orthographic projection Of course, the present disclosure includes but is not limited to this.
  • the orthographic projection of the interlayer dielectric layer 420 on the base substrate 1 covers the base substrate 1;
  • the orthographic projection of the and gate insulating layer 410 on the base substrate 1 does not overlap the first overlap zone Z, so that an interlayer dielectric layer 420 can be provided between the first pole and the second pole of the storage capacitor to make the layer
  • the intermediate dielectric layer 420 insulates the first pole and the second pole of the storage capacitor.
  • the insulating dielectric layer may include the interlayer dielectric layer 420.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the active layer of the driving transistor on the base substrate 1 and the orthographic projection of the gate on the base substrate 1 have a second overlap area, and the second overlap area
  • the active layer in the channel region is a channel region
  • the active layer in the channel region is a semiconductor.
  • other regions in the active layer except the channel region can be set to be conductive.
  • the storage capacitor may include a conductive region B of an active layer, an interlayer dielectric layer 420, and a capacitor electrode 71 stacked in sequence.
  • the active layer and the capacitor electrode 71 in the Z region of the first overlap region have a facing area, thereby forming The capacitance area.
  • the thickness of the interlayer dielectric layer 420 in the Z region of the first overlap region is smaller than the thickness of other regions, the thickness of the interlayer dielectric layer 420 in the capacitor region is thinner than other parts.
  • the thickness of the interlayer dielectric layer 420 in the capacitor area in the present disclosure is thin, so that the area of the capacitor area does not change, and the capacitance of the capacitor area The thickness of the interlayer dielectric layer 420 is reduced and the capacitance is increased, which can effectively improve the efficiency of the driving transistor and increase the brightness of the pixel.
  • the via holes 511 to 516 and 518 may be via holes penetrating the interlayer dielectric layer 420, respectively. It should be noted that the shape and area of these vias can be designed and determined according to actual application requirements, and are not limited here.
  • the capacitor electrode 71 for the capacitor electrode 71, the first gate line G1, and the second gate line G2 corresponding to the same sub-pixel, the capacitor The orthographic projection of the electrode 71 on the base substrate 1 is located between the orthographic projection of the first grid on the base substrate 1 and the orthographic projection of the second grid G2 on the base substrate 1.
  • the present disclosure includes but is not limited to this.
  • the active layer may further include: the first source region T1-S and the first drain region T1- of the driving transistor. D.
  • the first source region is electrically connected to the first power line OVDD through the connection portion 73, and the first drain region is electrically connected to the electroluminescent diode.
  • the present disclosure includes but is not limited to this.
  • the active layer of the driving transistor may include: a first source region T1-S, a first drain region T1-D , The channel area A1 and the conductive area B.
  • the first source region can be located on the side of the channel region away from the conductive region B
  • the first drain region can be located on the side of the conductive region B away from the channel region.
  • the orthographic projection of the first source region T1-S on the base substrate 1 may be located between the channel region A1 and the orthographic projection of the first gate line G1 on the base substrate 1.
  • the orthographic projection of the first drain region T1-D on the base substrate 1 is on the side of the conductive region B away from the channel region A1.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the first source region on the base substrate 1 is opposite to that of the first drain region on the base substrate 1.
  • the projection is close to the orthographic projection of the first gate line G1 on the base substrate 1, and the orthographic projection of the first drain region on the base substrate 1 is closer to the second gate line G2 than the orthographic projection of the first source region on the base substrate 1 Orthographic projection on the base substrate 1.
  • the first thickness E1E can be satisfied: That is, the first thickness E1 can be set at Specifically, the first thickness E1 can be set as In this way, the interlayer dielectric layer 420 between the first electrode and the second electrode of the storage capacitor can not be broken down, and the thickness can be made thinner, which is beneficial to increase the capacitance of the capacitor region. It should be noted that the first thickness E1 can also be set to or Or other thickness values are not limited in this embodiment.
  • the present disclosure also provides a preparation method of the above-mentioned array substrate.
  • the preparation method may include the following steps:
  • a semiconductor layer 100 is formed on the base substrate 1; wherein, the semiconductor layer 100 includes an active layer located in each sub-pixel; wherein, the active layer includes a channel region and a conductive region B;
  • a second conductive layer 300 is formed on the side of the interlayer dielectric layer 420 away from the base substrate 1; wherein, the second conductive layer 300 includes: a capacitor electrode 71 located in each sub-pixel; in the same sub-pixel, the capacitor electrode 71 is located
  • the orthographic projection of the base substrate 1 and the conductive area B of the active layer on the orthographic projection of the base substrate 1 have a first overlap zone Z, and the orthographic projection has the capacitor electrode 71 and the active layer of the first overlap zone Z
  • the method further includes: thinning the insulating dielectric layer located in the first overlap zone Z Process to make the first thickness E1 smaller than the second thickness E2. In this way, when the facing areas of the two electrodes of the storage capacitor remain unchanged, the capacitance value of the storage capacitor can be increased, thereby effectively improving the efficiency of the driving transistor and improving the brightness of the pixel.
  • a semiconductor layer 100 is formed on the base substrate 1.
  • the semiconductor layer 100 may include the active layer 21 of the driving transistor T1 and partially conductive the active layer 21, wherein the conductive area B in the active layer 21 serves as the first electrode of the storage capacitor;
  • a gate insulating layer 410, a gate 4 of the driving transistor T1, and an interlayer dielectric layer 420 are sequentially formed on the side of the semiconductor layer 100 away from the base substrate 1;
  • the interlayer dielectric layer 420 is formed, a portion of the interlayer dielectric layer 420 corresponding to the first pole of the storage capacitor is thinned so that the interlayer dielectric layer 420 and the storage capacitor
  • the first thickness E1 of the corresponding part of the first pole 6 is smaller than the second thickness E2 of the other parts; that is, the interlayer dielectric layer 420 in the Z domain of the first overlap zone is thinned to make the first thickness E1 smaller than The second thickness E2.
  • a dry etching process may be used to thin the interlayer dielectric layer 420 located in the first overlap zone Z.
  • vias 511 to 518 are formed in the interlayer dielectric layer 420 for subsequent electrical connections.
  • the second conductive layer 300 may be formed on the side of the interlayer dielectric layer 420 away from the base substrate 1.
  • the second conductive layer 300 please refer to the above description, which is not repeated here.
  • step S10 it may further include: first forming a light-shielding electrode layer on the base substrate, and then forming a buffer layer on the side of the light-shielding electrode layer away from the base substrate. In this way, a semiconductor layer can be formed on the side of the buffer layer away from the base substrate.
  • embodiments of the present disclosure also provide a display device including the above-mentioned array substrate. Further, the display device may further include an opposite substrate disposed opposite to the array substrate.
  • the principle of solving the problem of the display device is similar to that of the aforementioned array substrate. Therefore, the implementation of the display device can refer to the implementation of the aforementioned array substrate, and the repetitive parts will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • the other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the source of the driving transistor, the switching transistor, and the compensation transistor mentioned in the above embodiments is the input electrode of the electrical signal, and the drain is the output end of the electrical signal.
  • the transistors include P-type and N-type, different types
  • the signal input and output of the source and drain of the transistor will be different, but only the name of the input electrode and output electrode of the electrical signal is different, and the direction of the electrical signal path of the transistor in the circuit is not changed. Therefore, in this embodiment
  • the driving transistors, switching transistors, and compensation transistors are of N-type or P-type.
  • the source and drain electrodes of the source and drain electrodes of the above-mentioned driving transistor, switching transistor, and compensation transistor can be interchanged according to their type. It does not affect the direction of the electrical signal path in the pixel drive circuit.

Abstract

La présente invention concerne un substrat matriciel et son procédé de préparation, ainsi qu'un dispositif d'affichage. Le substrat matriciel comprend : un substrat de base, une couche semi-conductrice, une couche d'isolation de grille, une première couche conductrice, une couche diélectrique intermédiaire et une seconde couche conductrice. La couche semi-conductrice comprend des couches actives situées dans tous les sous-pixels, chaque couche active comprenant une région de canal et une région conductrice. La seconde couche conductrice comprend des électrodes de condensateur situées dans tous les sous-pixels. Dans un même sous-pixel, il existe une première région de chevauchement entre la projection orthographique d'une électrode de condensateur sur le substrat de base et la projection orthographique d'une région conductrice sur le substrat de base, l'électrode de condensateur et la région conductrice dont la projection orthographique a la première région de chevauchement forment un condensateur de stockage. Dans la direction perpendiculaire au plan du substrat de base, une couche diélectrique isolante située dans la première région de chevauchement et entre l'électrode de condensateur et la région conductrice a une première épaisseur, et les couches diélectriques isolantes situées dans d'autres régions ont une seconde épaisseur, la première épaisseur étant inférieure à la seconde épaisseur.
PCT/CN2020/075610 2019-05-27 2020-02-17 Substrat matriciel et son procédé de préparation et dispositif d'affichage WO2020238288A1 (fr)

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