WO2020238288A1

WO2020238288A1 - Array substrate and preparation method therefor, and display device

Info

Publication number: WO2020238288A1
Application number: PCT/CN2020/075610
Authority: WO
Inventors: 黄勇潮; 成军; 王东方; 刘军; 张扬; 王庆贺; 周斌; 何敏
Original assignee: 京东方科技集团股份有限公司; 合肥鑫晟光电科技有限公司
Priority date: 2019-05-27
Filing date: 2020-02-17
Publication date: 2020-12-03
Also published as: CN110164373B; CN110164373A

Abstract

Disclosed by the present disclosure are an array substrate and a preparation method therefor as well as a display device. The array substrate comprises: a base substrate, a semiconductor layer, a gate insulating layer, a first conductive layer, an interlayer dielectric layer, and a second conductive layer. The semiconductor layer comprises active layers located in all sub-pixels, each active layer comprising a channel region and a conductor region. The second conductive layer comprises capacitor electrodes located in all sub-pixels. In a same sub-pixel, there is a first overlap region between the orthographic projection of a capacitor electrode on the base substrate and the orthographic projection of a conductor region on the base substrate, the capacitor electrode and the conductive region whose orthographic projection has the first overlap region form a storage capacitor. In the direction perpendicular to the plane of the base substrate, an insulating dielectric layer located in the first overlap region and between the capacitor electrode and the conductive region has a first thickness, and the insulating dielectric layers in other regions have a second thickness, the first thickness being less than the second thickness.

Description

Array substrate, preparation method thereof, and display device

Cross references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on May 27, 2019, the application number is 201910444513.4, and the application name is "a pixel driving circuit and its preparation method, and OLED display panel". The entire content of the application is approved The reference is incorporated in this application.

Technical field

The present disclosure relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display device.

Background technique

Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED) and other electroluminescent diodes have the advantages of self-emission and low energy consumption. , Is one of the hot spots in the application research field of electroluminescent display devices.

Summary of the invention

The array substrate provided by the embodiment of the present disclosure includes:

The base substrate includes: a plurality of sub-pixels;

The semiconductor layer is located on the base substrate, and the semiconductor layer includes an active layer located in each of the sub-pixels; wherein, the active layer includes a channel region and a conductive region;

A gate insulating layer located on the side of the semiconductor layer away from the base substrate;

The first conductive layer is located on the side of the gate insulating layer away from the base substrate;

An interlayer dielectric layer located on the side of the first conductive layer away from the base substrate;

The second conductive layer is located on the side of the interlayer dielectric layer away from the base substrate, and the second conductive layer includes: a capacitor electrode located in each of the sub-pixels;

In the same sub-pixel, the orthographic projection of the capacitor electrode on the base substrate and the conductive area of the active layer on the orthographic projection of the base substrate have a first overlap area, and the orthographic projection has The capacitor electrode in the first overlap area and the conductive area of the active layer form a storage capacitor;

In the direction perpendicular to the plane where the base substrate is located, the insulating dielectric layer located between the capacitor electrode in the first overlap area and the conductive area of the active layer has a first thickness, and the remaining area The insulating dielectric layer has a second thickness, and the first thickness is smaller than the second thickness.

Optionally, in an embodiment of the present disclosure, the first conductive layer includes a gate located in each of the sub-pixels; the orthographic projection of the gate insulating layer on the base substrate and the gate located at the The orthographic projection of the base substrate at least partially overlaps; and the orthographic projection of the gate and the gate insulating layer on the base substrate does not overlap with the first overlap region;

The orthographic projection of the interlayer dielectric layer on the base substrate covers the base substrate;

The insulating dielectric layer includes the interlayer dielectric layer.

Optionally, in the embodiment of the present disclosure, the first conductive layer further includes a plurality of first gate lines and a plurality of second gate lines; wherein, a row of sub-pixels corresponds to one first gate line and one Second grid line

For the capacitor electrode, the first gate line, and the second gate line corresponding to the same sub-pixel, the orthographic projection of the capacitor electrode on the base substrate is located where the first gate is on the The orthographic projection of the base substrate and the second gate line are between the orthographic projection of the base substrate.

Optionally, in the embodiment of the present disclosure, the sub-pixel further includes a driving transistor and an electroluminescent diode; the second conductive layer further includes a first power line;

The active layer further includes: a first source region and a first drain region of the driving transistor; wherein the first source region is electrically connected to the first power line, and the first drain The zone is electrically connected to the electroluminescent diode.

Optionally, in the embodiment of the present disclosure, the first source region is located on the side of the channel region away from the conductive region, and the first drain region is located on the side of the conductive region away from the conductive region. One side of the channel region; and/or,

The orthographic projection of the first source region on the base substrate is close to the orthographic projection of the first gate line on the base substrate relative to the orthographic projection of the first drain region on the base substrate, And the orthographic projection of the first drain region on the base substrate is close to the orthographic projection of the second gate line on the base substrate relative to the orthographic projection of the first source region on the base substrate .

Optionally, in the embodiment of the present disclosure, the gate of the driving transistor is electrically connected to the capacitor electrode, the first source region serves as the first electrode of the driving transistor, and the first drain region As the second pole of the driving transistor;

The second conductive layer further includes: a plurality of data lines and a plurality of detection lines arranged at intervals from the capacitor electrode; wherein, one column of sub-pixels corresponds to one data line;

The sub-pixel further includes: a switching transistor and a sensing transistor;

The gate of the switching transistor is electrically connected to a first gate line, the first electrode of the switching transistor is electrically connected to the data line, and the second electrode of the switching transistor is electrically connected to the capacitor electrode;

The gate of the sensing transistor is electrically connected to a second gate line, the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sensing transistor is electrically connected to a The detection line is electrically connected.

Optionally, in the embodiment of the present disclosure, the array substrate further includes:

A buffer layer located between the semiconductor layer and the base substrate;

The light-shielding electrode layer is located between the buffer layer and the base substrate;

The light-shielding electrode layer includes a plurality of light-shielding electrodes arranged at intervals; wherein, one of the light-shielding electrodes is provided in one of the sub-pixels;

In the same sub-pixel, the orthographic projection of the shading electrode on the base substrate covers the orthographic projection of the active layer of the driving transistor on the base substrate.

Optionally, in the embodiment of the present disclosure, the first thickness E satisfies:

The manufacturing method of the above-mentioned array substrate provided by the embodiment of the present disclosure includes:

Forming the semiconductor layer on the base substrate; wherein the semiconductor layer includes an active layer located in each of the sub-pixels; wherein the active layer includes a channel region and a conductive region;

Forming the gate insulating layer on the side of the semiconductor layer away from the base substrate;

Forming the first conductive layer on the side of the gate insulating layer away from the base substrate;

Forming the interlayer dielectric layer on the side of the first conductive layer away from the base substrate;

The second conductive layer is formed on the side of the interlayer dielectric layer away from the base substrate; wherein, the second conductive layer includes: capacitor electrodes located in each of the sub-pixels; and in the same sub-pixel , The orthographic projection of the capacitor electrode on the base substrate and the orthographic projection of the conductive area of the active layer on the base substrate have a first overlap area, and the orthographic projection has a first overlap area. The capacitor electrode and the conductive area of the active layer form a storage capacitor; and, on a plane perpendicular to the base substrate, the capacitor electrode and the active layer located in the first overlapping area The insulating dielectric layer between the layers has a first thickness, and the insulating dielectric layers in the remaining regions have a second thickness;

Wherein, after the formation of the interlayer dielectric layer and before the formation of the second conductive layer, the method further includes: performing a thinning treatment on the insulating dielectric layer located in the first overlap region, so that the first A thickness is smaller than the second thickness.

Optionally, in the embodiment of the present disclosure, the insulating dielectric layer includes an interlayer dielectric layer.

Optionally, in the embodiment of the present disclosure, a dry etching process is used to thin the interlayer dielectric layer located in the first overlap region.

Optionally, in the embodiment of the present disclosure, before forming the semiconductor layer on the base substrate, the method further includes:

Forming a light-shielding metal layer on the base substrate;

A buffer layer is formed on the side of the light-shielding metal layer away from the base substrate.

The display device provided by the embodiment of the present disclosure includes the above-mentioned array substrate.

Description of the drawings

FIG. 1 is a schematic top view of the structure of an array substrate provided by an embodiment of the disclosure;

2 is a schematic diagram of a circuit structure in a sub-pixel provided by an embodiment of the disclosure;

3 is a schematic diagram of a layout structure in sub-pixels provided by an embodiment of the disclosure;

4a is a schematic diagram of a layout structure of a semiconductor layer provided by an embodiment of the disclosure;

4b is a schematic diagram of the layout structure of the first conductive layer provided by an embodiment of the disclosure;

4c is a schematic diagram of the layout structure of the second conductive layer provided by an embodiment of the disclosure;

4d is a schematic diagram of the layout structure of a light-shielding metal layer provided by an embodiment of the disclosure;

FIG. 5 is a schematic cross-sectional structure view along the BB' direction in FIG. 3 according to an embodiment of the disclosure;

6 to 9 are schematic diagrams of the cross-sectional structure of film layer changes along the AA' direction during the preparation process of the array substrate in FIG. 3 provided by the embodiments of the disclosure;

Fig. 10 is a flow chart of a preparation method provided by an embodiment of the disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. And in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, and are only intended to illustrate the present disclosure. And the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions.

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present disclosure.

In the thin film transistor (TFT) manufacturing process of the display panel, due to the high-resolution display requirements, the thickness of the conductive film in the display panel is getting thicker and thicker, and the thickness of the corresponding insulating layer is also increasing. The thicker. However, as the thickness of the insulating layer increases, the thickness of the insulating layer located between the two electrodes of the storage capacitor in the pixel unit will also increase. According to the formula satisfied by the capacitor, when the facing area is fixed, if the thickness of the insulating layer between the two electrodes of the storage capacitor increases, the capacitance value of the storage capacitor will decrease, resulting in a decrease in transistor efficiency.

In view of this, the embodiments of the present disclosure provide an array substrate, which can increase the capacitance value of the storage capacitor when the facing area is fixed, so that the efficiency of the driving transistor can be effectively improved and the brightness of the pixel can be improved.

As shown in FIG. 1, the array substrate provided by the embodiment of the present disclosure may include: a base substrate 1. Wherein, the base substrate 1 may be a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited herein. In practical applications, the array substrate may include a display area AA and a frame area surrounding the display area AA1. Elements such as an electrostatic discharge circuit and a gate drive circuit can be arranged in the frame area. Of course, the array substrate may not be provided with a frame area, which can be designed and determined according to the requirements of the actual application environment, and is not limited here.

As shown in FIG. 1, the display area AA may include a plurality of pixel units PX, for example, a plurality of pixel units PX. At least one pixel unit PX may include a plurality of sub-pixels. For example, each pixel unit may include multiple sub-pixels. Among them, each sub-pixel can be provided with an electroluminescent diode and a pixel driving circuit, so that the electroluminescent diode can be driven to emit light through the pixel driving circuit. Exemplarily, the electroluminescent diode may include: at least one of OLED, QLED, and Micro LED. In actual applications, the specific implementation of the electroluminescent diode can be set according to the requirements of the actual application environment, which is not limited here.

Generally in the display field, a pixel unit usually includes a plurality of sub-pixels that can respectively display a single color (for example, red, green, or blue), so as to realize different colors by controlling the light-emitting ratio of the sub-pixels of different colors. Exemplarily, the above-mentioned sub-pixels may be set as monochromatic sub-pixels.

Exemplarily, as shown in FIG. 1, the pixel unit PX may include: a first color sub-pixel 010, a second color sub-pixel 020, and a third color sub-pixel 030. Wherein, the first color sub-pixel is configured to emit light of a first color, the second color sub-pixel is configured to emit light of a second color, and the third color sub-pixel is configured to emit light of a third color. In some examples, the first color, the second color, and the third color can be selected from red, green, and blue. For example, the first color is red, the second color is green, and the third color is blue. Therefore, the pixel unit PX may be an arrangement structure of red, green and blue sub-pixels. Of course, the embodiments of the present disclosure include but are not limited thereto, and the aforementioned first color, second color, and third color may also be other colors.

Exemplarily, the first-color sub-pixels, the second-color sub-pixels, and the third-color sub-pixels are sequentially arranged along the second direction F2 (for example, the direction indicated by the F2 arrow in FIG. 1), and the colors of the sub-pixels in the same column are the same. Of course, the embodiments of the present disclosure include but are not limited to this.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 2, the pixel driving circuit may include: a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst. Wherein, the gate of the switching transistor T2 is electrically connected to the first gate line G1, the first electrode (for example, the source) of the switching transistor T2 is electrically connected to the data line DA, and the second electrode (for example, the drain) of the switching transistor T2 is electrically connected to the driving The gate of the transistor T1 is electrically connected. The first electrode (for example, the source) of the driving transistor T1 is electrically connected to the first power line OVDD, and the second electrode (for example, the drain) of the driving transistor T1 is electrically connected to the anode of the electroluminescent diode L. The cathode is electrically connected to the second power line OVSS. The gate of the sensing transistor T3 is electrically connected to the second gate line G2, the first electrode (for example, the source) of the sensing transistor T3 is electrically connected to the second electrode (for example, the drain) of the driving transistor T1, and the The second electrode (for example, the drain) is electrically connected to the detection line SL. The second electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the first electrode of the storage capacitor Cst is electrically connected to the second electrode (for example, the drain) of the driving transistor T1. The second electrode of the driving transistor T1 is electrically connected to the anode of the electroluminescent diode.

Exemplarily, the switching transistor T2 is controlled to be turned on by the signal transmitted on the first gate line G1 to write the data voltage transmitted on the data line DA into the gate of the driving transistor T1, and the driving transistor T1 is controlled to generate a working current to drive the electromotive force. The light emitting diode L emits light. And the sensing transistor T3 is controlled to be turned on by the signal transmitted on the second gate line G2 to output the operating current generated by the driving transistor T1 to the detection line SL to charge the detection line SL. After that, by detecting the voltage on each detection line SL, and performing compensation calculation based on the detected voltage, the data voltage corresponding to each sub-pixel in the row is obtained for display.

Exemplarily, the first power line OVDD may transmit a constant first voltage, which is a positive voltage; and the second power line OVSS may transmit a constant second voltage, which is a negative voltage. Or, in some examples, the second power line OVSS may also be grounded.

It should be noted that, in the embodiment of the present disclosure, the pixel driving circuit may be a structure including other numbers of transistors and capacitors in addition to the structure shown in FIG. 2, which is not limited in the embodiment of the present disclosure.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 1, the array substrate may further include: multiple detection lines SL, multiple data lines (for example, DA-010, DA-020, DA-030), and The first power line OVDD. Exemplarily, one column of sub-pixels corresponds to one data line, and the detection line SL is located in the gap between two adjacent pixel unit columns. For example, in the direction pointed by the F2 arrow (that is, in the direction from left to right), there may be a first pixel unit column, a second pixel unit column, a third pixel unit column, and a fourth pixel unit column. Wherein, a detection line SL is provided in the gap between the first pixel unit column and the second pixel unit column, and another detection line SL is provided in the gap between the third pixel unit column and the fourth pixel unit column. . The rest of the settings can be deduced by analogy, so I won’t repeat them here.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 1, the multiple data lines may include: data lines DA-010, DA-020, and DA-030. Among them, one data line DA-010 corresponds to a column of first color sub-pixels 010, and one data line DA-010 is electrically connected to the switching transistor T2 in a column of first color sub-pixels 010. One data line DA-020 corresponds to a column of second color sub-pixels 020, and one data line DA-020 is electrically connected to the switching transistor T2 in a column of second color sub-pixels 020. One data line DA-030 corresponds to a row of third-color sub-pixels 030, and one data line DA-030 is electrically connected to the switching transistor T2 in a row of third-color sub-pixels 030. Exemplarily, in the same pixel unit column, a data line DA-010 and a data line DA-020 are arranged between a first color sub-pixel and a second color sub-pixel, and a second color sub-pixel and a third color sub-pixel are arranged. A data line DA-030 is set between the color sub-pixels. And, the data line DA-010 is located between the first color sub-pixel and the data line DA-020. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, which is not limited here.

Taking the first color sub-pixel 010 as an example, the various layers of the pixel driving circuit provided by some embodiments of the present disclosure are described below. As shown in Figs. 3 to 5, Figs. 4a to 4d are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the present disclosure. The positional relationship of the pixel driving circuit on the base substrate 1 will be described below with reference to FIGS. 3 to 5.

Illustratively, in conjunction with FIGS. 3, 4 a and 5 to 9, a semiconductor layer 100 is provided on the base substrate 1. The semiconductor layer 100 may be formed by patterning a semiconductor material. Wherein, the semiconductor layer 100 may include an active layer located in each sub-pixel. For example, the semiconductor layer 100 may include the active layer 21 of the driving transistor T1, the active layer 22 of the switching transistor T2, and the sensing transistor in the first color sub-pixel 010, the second color sub-pixel 020, and the third color sub-pixel 030. The active layer 23 of T3. Each active layer 21-23 may include a source region, a drain region, and a channel region between the source region and the drain region. In addition, the active layer 21 may further include a conductive area B; wherein the conductive area B may form the first pole of the storage capacitor Cst. For example, the active layer 21 may include: a first source region T1-S, a first drain region T1-D, a channel region A1, and a conductive region B. The first source region T1-S can be used as the first electrode (for example, the source) of the driving transistor, and the first drain region can be used as the second electrode (for example, the drain) of the driving transistor. Of course, the embodiments of the present disclosure include but are not limited to this.

Further, the active layers 21 to 23 of each transistor are arranged at intervals. Illustratively, the semiconductor layer 100 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source and drain regions may be regions doped with n-type impurities or p-type impurities. The aforementioned conductive area B may be a conductive area formed after ion doping of the semiconductor layer 100. Of course, the embodiments of the present disclosure include but are not limited to this.

Exemplarily, with reference to FIGS. 3, 4 b, and FIGS. 5 to 9, the array substrate may further include a first conductive layer 200 on the side of the semiconductor layer 100 away from the base substrate 1. A gate insulating layer 410 is formed between the aforementioned semiconductor layer 100 and the first conductive layer 200. Also, the first conductive layer 200 is disposed on the gate insulating layer 410 so as to be insulated from the semiconductor layer 100. Exemplarily, the first conductive layer 200 may include a plurality of first gate lines G1, a plurality of second gate lines G2, and a plurality of gates 4. Wherein, each sub-pixel is provided with a gate 4, and a row of sub-pixels corresponds to a first gate line G1 and a second gate line G2. And, the first gate line G1 and the second gate line G2 extend along the first direction and are arranged along the second direction. For example, for the gate 4, the first gate line G1 and the second gate line G2 corresponding to the same sub-pixel, the orthographic projection of the gate 4 on the base substrate 1 is located on the first gate line G1 and the second gate line G1 corresponding to the sub-pixel. The line G2 is between the orthographic projections of the base substrate 1. Moreover, for a sub-pixel, the orthographic projection of the conductive area B on the base substrate 1 is also located between the orthographic projection of the first gate line G1 and the second gate line G2 corresponding to the sub-pixel on the base substrate 1.

Exemplarily, as shown in FIGS. 3, 4b, and 5-9, the gate of the switching transistor T2 may be the overlapping portion of the first gate line G1 and the semiconductor layer 100, and the gate of the sensing transistor T3 may be The portion where the second gate line G2 overlaps the semiconductor layer 100. Also, the gate 4 can drive the gate of the transistor T1. It should be noted that the dashed rectangular frames A1, A2, and A3 in FIG. 4a show areas where the first conductive layer 200 and the semiconductor layer 100 overlap.

Illustratively, an interlayer dielectric layer 420 is provided on the side of the aforementioned first conductive layer 200 away from the base substrate 1 to protect the aforementioned first conductive layer 200. As shown in FIG. 3, FIG. 4c and FIG. 5 to FIG. 9, the array substrate may further include a second conductive layer 300 on the side of the first conductive layer 200 away from the base substrate 1. In addition, an interlayer dielectric layer 420 is provided between the first conductive layer 200 and the second conductive layer 300. Exemplarily, the second conductive layer 300 may include: a plurality of detection lines SL arranged at intervals, a plurality of data lines DA-010 (of course, the data lines DA-020 and DA-030), a first power line OVDD, a capacitor The electrode 71 and the connecting

portions

72 and 73. A capacitor electrode 71 is provided in each sub-pixel, and the capacitor electrode 71 serves as the second pole of the storage capacitor Cst. That is, the gate of the driving transistor is electrically connected to the capacitor electrode 71, and the second electrode of the switching transistor is electrically connected to the capacitor electrode 71.

Exemplarily, in a specific implementation, in the implementation of the present disclosure, the data lines DA-010, DA-020, and DA-030 can be extended along the first direction F1 and arranged along the second direction F2. In addition, the data lines DA-010, DA-020, and DA-030 are respectively electrically connected to the first electrode of the switching transistor through a portion protruding in the second direction F2.

Exemplarily, in specific implementation, in the implementation of the present disclosure, a planarization layer is provided on the side of the second conductive layer 300 away from the base substrate 1 to protect the second conductive layer 300 and achieve the planarization effect. . The anode of the electroluminescent diode is provided on the side of the planarization layer away from the base substrate 1. A pixel defining layer is provided on the side of the anode away from the base substrate 1; wherein the pixel defining layer has a plurality of light-emitting opening areas, and one anode corresponds to one light-emitting opening area to expose the corresponding anode through the light-emitting opening area. A light-emitting function layer and a cathode are sequentially arranged on the side of the pixel defining layer away from the base substrate 1. Exemplarily, the light-emitting functional layer directly contacts the anode through the light-emitting opening area, and the light-emitting functional layer directly contacts the cathode, so as to drive the light-emitting functional layer to emit light through the signal loaded on the anode and the signal loaded on the cathode. Of course, the present disclosure includes but is not limited to this. For example, a hole transport layer and a hole injection layer can also be arranged between the light-emitting functional layer and the anode, and film layers such as an electron transport layer and an electron injection layer can also be arranged between the light-emitting functional layer and the cathode layer. It should be noted that the anode, the light-emitting functional layer, and the cathode can be stacked to form an electroluminescent diode.

Exemplarily, in specific implementation, as shown in FIGS. 3 to 9, a gate insulating layer 410 is provided between the semiconductor layer 100 and the first conductive layer 200, and a gate insulating layer 410 is provided between the first conductive layer 200 and the second conductive layer 300. There is an interlayer dielectric layer 420. Wherein, the detection line SL is electrically connected to the source region of the active layer of the sensing transistor T3 through the via 511. One end of the connecting portion 72 is electrically connected to the drain region of the active layer of the sensing transistor T3 through a via 512, and the other end of the connecting portion 72 is electrically connected to the drain region of the active layer of the driving transistor through a via 513. The capacitor electrode 71 is electrically connected to the gate 4 of the driving transistor through the via hole 514, and the capacitor electrode 71 is also electrically connected to the drain region of the active layer of the switching transistor through the via hole 515. The data line DA-010 is electrically connected to the source region of the active layer of the switching transistor through the via 516. One end of the connecting portion 73 is electrically connected to the first power supply line OVDD through the via 517, and the other end of the connecting portion 73 is electrically connected to the source region of the active layer of the driving transistor through the via 518. Further, the anode is electrically connected to the connection portion 72 through a via 519 penetrating the planarization layer.

Further, as shown in FIG. 3, FIG. 4d and FIG. 5, a buffer layer is also provided between the semiconductor layer 100 and the base substrate 1. A light-shielding electrode layer 400 is also provided between the buffer layer and the base substrate 1. Wherein, the light-shielding electrode layer 400 may include a plurality of light-shielding electrodes 3, and one light-shielding electrode 3 is provided in one sub-pixel. Illustratively, in the same sub-pixel, the orthographic projection of the light shielding electrode 3 on the base substrate 1 covers the orthographic projection of the active layer of the driving transistor on the base substrate 1. Of course, the present disclosure includes but is not limited to this.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 3, 4a, 4c, 5, and 9, each sub-pixel is provided with a capacitor electrode 71, respectively. Exemplarily, in the same sub-pixel, the orthographic projection of the capacitor electrode 71 on the base substrate 1 and the orthographic projection of the conductive area B of the active layer on the base substrate 1 have a first overlap zone Z, and the orthographic projection has a first overlap. The capacitor electrode 71 of an overlap zone Z and the conductive area B of the active layer form a storage capacitor Cst; wherein, the capacitor electrode 71 located in the first overlap zone Z forms the second electrode of the storage capacitor Cst, which is located in the first The conductive area B of the active layer 21 in an overlap area Z forms the first pole of the storage capacitor Cst.

In addition, in the direction perpendicular to the plane where the base substrate 1 is located, the insulating dielectric layer located between the capacitor electrode 71 in the first overlap zone Z and the conductive zone of the active layer has a first thickness E1, and the insulation of the remaining zone The dielectric layer has a second thickness E2, and the first thickness E1 is smaller than the second thickness E2.

In the above-mentioned array substrate provided by the embodiment of the present disclosure, in a direction perpendicular to the plane of the base substrate 1, the insulating dielectric layer located between the capacitor electrode 71 and the active layer in the first overlap zone Z has a first thickness E1, The insulating dielectric layer in the remaining area has a second thickness E2. By making the first thickness E1 smaller than the second thickness E2, the thickness of the insulating dielectric layer between the two electrodes of the storage capacitor can be made thinner, so that the two The distance between the electrodes is reduced. In this way, when the facing areas of the two electrodes of the storage capacitor remain unchanged, the capacitance value of the storage capacitor can be increased, thereby effectively improving the efficiency of the driving transistor and improving the brightness of the pixel.

In specific implementation, in the embodiments of the present disclosure, as shown in FIG. 3, FIG. 4a, FIG. 4c, and FIG. 5, each sub-pixel is provided with a gate, for example, each sub-pixel is provided with a driving transistor T1. The gate, the gate of the switching transistor T2, and the gate of the sensing transistor T3. In addition, the orthographic projection of the gate insulating layer 410 on the base substrate 1 and the orthographic projection of the gate on the base substrate 1 at least partially overlap. Exemplarily, the orthographic projection of the gate insulating layer 410 on the base substrate 1 and the orthographic projection of the gate on the base substrate 1 may overlap, or the orthographic projection of the gate insulating layer 410 on the base substrate 1 covers the gate on the base substrate 1. 1. Orthographic projection. Of course, the present disclosure includes but is not limited to this.

In specific implementation, in the embodiments of the present disclosure, as shown in FIG. 3, FIG. 4a, FIG. 4c, and FIG. 5, the orthographic projection of the interlayer dielectric layer 420 on the base substrate 1 covers the base substrate 1; The orthographic projection of the and gate insulating layer 410 on the base substrate 1 does not overlap the first overlap zone Z, so that an interlayer dielectric layer 420 can be provided between the first pole and the second pole of the storage capacitor to make the layer The intermediate dielectric layer 420 insulates the first pole and the second pole of the storage capacitor. That is, the insulating dielectric layer may include the interlayer dielectric layer 420. Of course, the present disclosure includes but is not limited to this.

In the above-mentioned array substrate provided by the embodiment of the present disclosure, the orthographic projection of the active layer of the driving transistor on the base substrate 1 and the orthographic projection of the gate on the base substrate 1 have a second overlap area, and the second overlap area The active layer in the channel region is a channel region, and the active layer in the channel region is a semiconductor. And other regions in the active layer except the channel region can be set to be conductive. The storage capacitor may include a conductive region B of an active layer, an interlayer dielectric layer 420, and a capacitor electrode 71 stacked in sequence. The active layer and the capacitor electrode 71 in the Z region of the first overlap region have a facing area, thereby forming The capacitance area. Since the thickness of the interlayer dielectric layer 420 in the Z region of the first overlap region is smaller than the thickness of other regions, the thickness of the interlayer dielectric layer 420 in the capacitor region is thinner than other parts. In this way, compared with the uniform thickness of the interlayer dielectric layer 420 in each region, the thickness of the interlayer dielectric layer 420 in the capacitor area in the present disclosure is thin, so that the area of the capacitor area does not change, and the capacitance of the capacitor area The thickness of the interlayer dielectric layer 420 is reduced and the capacitance is increased, which can effectively improve the efficiency of the driving transistor and increase the brightness of the pixel.

In specific implementation, in the embodiment of the present disclosure, as shown in FIGS. 3 and 5, the via holes 511 to 516 and 518 may be via holes penetrating the interlayer dielectric layer 420, respectively. It should be noted that the shape and area of these vias can be designed and determined according to actual application requirements, and are not limited here.

In specific implementation, in the embodiments of the present disclosure, as shown in FIG. 3, FIG. 4b, FIG. 4c, and FIG. 5, for the capacitor electrode 71, the first gate line G1, and the second gate line G2 corresponding to the same sub-pixel, the capacitor The orthographic projection of the electrode 71 on the base substrate 1 is located between the orthographic projection of the first grid on the base substrate 1 and the orthographic projection of the second grid G2 on the base substrate 1. Of course, the present disclosure includes but is not limited to this.

In specific implementation, in the embodiments of the present disclosure, as shown in FIG. 3, FIG. 4a, and FIG. 5, the active layer may further include: the first source region T1-S and the first drain region T1- of the driving transistor. D. In addition, the first source region is electrically connected to the first power line OVDD through the connection portion 73, and the first drain region is electrically connected to the electroluminescent diode. Of course, the present disclosure includes but is not limited to this.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 3, 4a, and 5, the active layer of the driving transistor may include: a first source region T1-S, a first drain region T1-D , The channel area A1 and the conductive area B. Wherein, the first source region can be located on the side of the channel region away from the conductive region B, and the first drain region can be located on the side of the conductive region B away from the channel region. For example, the orthographic projection of the first source region T1-S on the base substrate 1 may be located between the channel region A1 and the orthographic projection of the first gate line G1 on the base substrate 1. The orthographic projection of the first drain region T1-D on the base substrate 1 is on the side of the conductive region B away from the channel region A1. Of course, the present disclosure includes but is not limited to this.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 3, 4a, and 5, the orthographic projection of the first source region on the base substrate 1 is opposite to that of the first drain region on the base substrate 1. The projection is close to the orthographic projection of the first gate line G1 on the base substrate 1, and the orthographic projection of the first drain region on the base substrate 1 is closer to the second gate line G2 than the orthographic projection of the first source region on the base substrate 1 Orthographic projection on the base substrate 1.

In practical applications, to ensure that the interlayer dielectric layer 420 between the first pole and the second pole of the storage capacitor is not broken down, the interlayer dielectric layer 420 between the first pole and the second pole of the storage capacitor is generally It cannot be too thin. In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 9, the first thickness E1E can be satisfied:

That is, the first thickness E1 can be set at

Specifically, the first thickness E1 can be set as

In this way, the interlayer dielectric layer 420 between the first electrode and the second electrode of the storage capacitor can not be broken down, and the thickness can be made thinner, which is beneficial to increase the capacitance of the capacitor region. It should be noted that the first thickness E1 can also be set to

or

Or other thickness values are not limited in this embodiment.

Based on the same inventive concept, the present disclosure also provides a preparation method of the above-mentioned array substrate. As shown in FIG. 10, the preparation method may include the following steps:

S10. A semiconductor layer 100 is formed on the base substrate 1; wherein, the semiconductor layer 100 includes an active layer located in each sub-pixel; wherein, the active layer includes a channel region and a conductive region B;

S20, forming a gate insulating layer 410 on the side of the semiconductor layer 100 away from the base substrate 1;

S30, forming a first conductive layer 200 on the side of the gate insulating layer 410 away from the base substrate 1;

S40, forming an interlayer dielectric layer 420 on the side of the first conductive layer 200 away from the base substrate 1;

S50: Perform a thinning process on the insulating dielectric layer located in the first overlap zone Z, so that the first thickness E1 is smaller than the second thickness E2;

S60. A second conductive layer 300 is formed on the side of the interlayer dielectric layer 420 away from the base substrate 1; wherein, the second conductive layer 300 includes: a capacitor electrode 71 located in each sub-pixel; in the same sub-pixel, the capacitor electrode 71 is located The orthographic projection of the base substrate 1 and the conductive area B of the active layer on the orthographic projection of the base substrate 1 have a first overlap zone Z, and the orthographic projection has the capacitor electrode 71 and the active layer of the first overlap zone Z The conductorized area B of the forming a storage capacitor; and, on the plane perpendicular to the base substrate 1, the insulating dielectric layer located between the capacitor electrode 71 and the active layer in the first overlap area Z has a first thickness E1, and the rest The insulating dielectric layer of the zone has a second thickness E2.

In the above-mentioned preparation method provided by the embodiment of the present disclosure, after forming the interlayer dielectric layer 420 and before forming the second conductive layer 300, the method further includes: thinning the insulating dielectric layer located in the first overlap zone Z Process to make the first thickness E1 smaller than the second thickness E2. In this way, when the facing areas of the two electrodes of the storage capacitor remain unchanged, the capacitance value of the storage capacitor can be increased, thereby effectively improving the efficiency of the driving transistor and improving the brightness of the pixel.

In specific implementation, referring to FIG. 6 and FIG. 4a, a semiconductor layer 100 is formed on the base substrate 1. Wherein, the semiconductor layer 100 may include the active layer 21 of the driving transistor T1 and partially conductive the active layer 21, wherein the conductive area B in the active layer 21 serves as the first electrode of the storage capacitor;

7 and 4b, a gate insulating layer 410, a gate 4 of the driving transistor T1, and an interlayer dielectric layer 420 are sequentially formed on the side of the semiconductor layer 100 away from the base substrate 1;

In addition, referring to FIG. 8, after the interlayer dielectric layer 420 is formed, a portion of the interlayer dielectric layer 420 corresponding to the first pole of the storage capacitor is thinned so that the interlayer dielectric layer 420 and the storage capacitor The first thickness E1 of the corresponding part of the first pole 6 is smaller than the second thickness E2 of the other parts; that is, the interlayer dielectric layer 420 in the Z domain of the first overlap zone is thinned to make the first thickness E1 smaller than The second thickness E2. Wherein, a dry etching process may be used to thin the interlayer dielectric layer 420 located in the first overlap zone Z. In addition, vias 511 to 518 are formed in the interlayer dielectric layer 420 for subsequent electrical connections.

In addition, referring to FIG. 9 and FIG. 4c, the second conductive layer 300 may be formed on the side of the interlayer dielectric layer 420 away from the base substrate 1. For the second conductive layer 300, please refer to the above description, which is not repeated here.

In a specific implementation, before step S10, it may further include: first forming a light-shielding electrode layer on the base substrate, and then forming a buffer layer on the side of the light-shielding electrode layer away from the base substrate. In this way, a semiconductor layer can be formed on the side of the buffer layer away from the base substrate.

Based on the same inventive concept, embodiments of the present disclosure also provide a display device including the above-mentioned array substrate. Further, the display device may further include an opposite substrate disposed opposite to the array substrate. In addition, the principle of solving the problem of the display device is similar to that of the aforementioned array substrate. Therefore, the implementation of the display device can refer to the implementation of the aforementioned array substrate, and the repetitive parts will not be repeated here.

In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator. The other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.

It should be noted that the source of the driving transistor, the switching transistor, and the compensation transistor mentioned in the above embodiments is the input electrode of the electrical signal, and the drain is the output end of the electrical signal. Among them, the transistors include P-type and N-type, different types The signal input and output of the source and drain of the transistor will be different, but only the name of the input electrode and output electrode of the electrical signal is different, and the direction of the electrical signal path of the transistor in the circuit is not changed. Therefore, in this embodiment The driving transistors, switching transistors, and compensation transistors are of N-type or P-type. The source and drain electrodes of the source and drain electrodes of the above-mentioned driving transistor, switching transistor, and compensation transistor can be interchanged according to their type. It does not affect the direction of the electrical signal path in the pixel drive circuit.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

An array substrate, which includes:

The base substrate includes: a plurality of sub-pixels;

The semiconductor layer is located on the base substrate, and the semiconductor layer includes an active layer located in each of the sub-pixels; wherein, the active layer includes a channel region and a conductive region;

A gate insulating layer located on the side of the semiconductor layer away from the base substrate;

The first conductive layer is located on the side of the gate insulating layer away from the base substrate;

An interlayer dielectric layer located on the side of the first conductive layer away from the base substrate;

The second conductive layer is located on the side of the interlayer dielectric layer away from the base substrate, and the second conductive layer includes: a capacitor electrode located in each of the sub-pixels;

In the same sub-pixel, the orthographic projection of the capacitor electrode on the base substrate and the conductive region of the active layer on the orthographic projection of the base substrate have a first overlap area, and the orthographic projection has The capacitor electrode in the first overlap area and the conductive area of the active layer form a storage capacitor;

In the direction perpendicular to the plane where the base substrate is located, the insulating dielectric layer located between the capacitor electrode in the first overlap area and the conductive area of the active layer has a first thickness, and the remaining area The insulating dielectric layer has a second thickness, and the first thickness is smaller than the second thickness.
8. The array substrate of claim 1, wherein the first conductive layer comprises a gate located in each of the sub-pixels; the orthographic projection of the gate insulating layer on the base substrate is in the same position as the gate. The orthographic projection of the base substrate at least partially overlaps; and the orthographic projection of the gate and the gate insulating layer on the base substrate does not overlap with the first overlap region;

The orthographic projection of the interlayer dielectric layer on the base substrate covers the base substrate;

The insulating dielectric layer includes the interlayer dielectric layer.
The array substrate of claim 2, wherein the first conductive layer further comprises a plurality of first gate lines and a plurality of second gate lines; wherein a row of sub-pixels corresponds to one first gate line and one The second grid line;

For the capacitor electrode, the first gate line, and the second gate line corresponding to the same sub-pixel, the orthographic projection of the capacitor electrode on the base substrate is located on the first gate in the The orthographic projection of the base substrate and the second gate line are between the orthographic projection of the base substrate.
5. The array substrate of claim 3, wherein the sub-pixel further comprises a driving transistor and an electroluminescent diode; the second conductive layer further comprises a first power line;

The active layer further includes: a first source region and a first drain region of the driving transistor; wherein the first source region is electrically connected to the first power line, and the first drain The zone is electrically connected to the electroluminescent diode.
5. The array substrate of claim 4, wherein the first source region is located on a side of the channel region away from the conductive region, and the first drain region is located where the conductive region is away from the conductive region. On one side of the channel region; and/or,

The orthographic projection of the first source region on the base substrate is close to the orthographic projection of the first gate line on the base substrate relative to the orthographic projection of the first drain region on the base substrate, And the orthographic projection of the first drain region on the base substrate is close to the orthographic projection of the second gate line on the base substrate relative to the orthographic projection of the first source region on the base substrate .
5. The array substrate according to claim 4 or 5, wherein the gate of the driving transistor is electrically connected to the capacitor electrode, the first source region serves as the first electrode of the driving transistor, and the first The drain region serves as the second electrode of the driving transistor;

The second conductive layer further includes: a plurality of data lines and a plurality of detection lines arranged at intervals from the capacitor electrode; wherein, one column of sub-pixels corresponds to one data line;

The sub-pixel further includes: a switching transistor and a sensing transistor;

The gate of the switching transistor is electrically connected to a first gate line, the first electrode of the switching transistor is electrically connected to the data line, and the second electrode of the switching transistor is electrically connected to the capacitor electrode;

The gate of the sensing transistor is electrically connected to a second gate line, the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sensing transistor is electrically connected to a The detection line is electrically connected.
8. The array substrate according to any one of claims 1 to 6, wherein the array substrate further comprises:

A buffer layer located between the semiconductor layer and the base substrate;

The light-shielding electrode layer is located between the buffer layer and the base substrate;

The light-shielding electrode layer includes a plurality of light-shielding electrodes arranged at intervals; wherein, one light-shielding electrode is provided in one of the sub-pixels;

In the same sub-pixel, the orthographic projection of the light shielding electrode on the base substrate covers the orthographic projection of the active layer of the driving transistor on the base substrate.
7. The array substrate according to any one of claims 1-7, wherein the first thickness E satisfies:
A method for preparing the array substrate according to any one of claims 1-8, comprising:

Forming the semiconductor layer on the base substrate; wherein the semiconductor layer includes an active layer located in each of the sub-pixels; wherein the active layer includes a channel region and a conductive region;

Forming the gate insulating layer on the side of the semiconductor layer away from the base substrate;

Forming the first conductive layer on the side of the gate insulating layer away from the base substrate;

Forming the interlayer dielectric layer on the side of the first conductive layer away from the base substrate;

The second conductive layer is formed on the side of the interlayer dielectric layer away from the base substrate; wherein, the second conductive layer includes: capacitor electrodes located in each of the sub-pixels; and in the same sub-pixel , The orthographic projection of the capacitor electrode on the base substrate and the orthographic projection of the conductive area of the active layer on the base substrate have a first overlap area, and the orthographic projection has a first overlap area. The capacitor electrode and the conductive area of the active layer form a storage capacitor; and, on a plane perpendicular to the base substrate, the capacitor electrode and the active layer located in the first overlapping area The insulating dielectric layer between the layers has a first thickness, and the insulating dielectric layers in the remaining regions have a second thickness;

Wherein, after the formation of the interlayer dielectric layer and before the formation of the second conductive layer, the method further includes: performing a thinning treatment on the insulating dielectric layer located in the first overlap region, so that the first A thickness is smaller than the second thickness.
9. The manufacturing method of claim 9, wherein the insulating dielectric layer comprises an interlayer dielectric layer.
The manufacturing method according to claim 9 or 10, wherein a dry etching process is used to thin the interlayer dielectric layer located in the first overlap region.
11. The preparation method according to any one of claims 9-11, wherein before forming the semiconductor layer on the base substrate, further comprising:

Forming a light-shielding metal layer on the base substrate;

A buffer layer is formed on the side of the light shielding metal layer away from the base substrate.
A display device comprising the array substrate according to any one of claims 1-8.