WO2020237783A1 - 电平移位电路及时钟讯号电路 - Google Patents

电平移位电路及时钟讯号电路 Download PDF

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Publication number
WO2020237783A1
WO2020237783A1 PCT/CN2019/095270 CN2019095270W WO2020237783A1 WO 2020237783 A1 WO2020237783 A1 WO 2020237783A1 CN 2019095270 W CN2019095270 W CN 2019095270W WO 2020237783 A1 WO2020237783 A1 WO 2020237783A1
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Prior art keywords
unit
level shift
switch
switches
delay
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French (fr)
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傅晓立
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a level shift circuit and a clock signal circuit.
  • AMLCD Active-Matrix Liquid Crystal Display
  • GOA Gate On Array
  • a level shift chip is used to increase the level.
  • the existing level shift chips are 2 in 4 out, 4 in 4 out and 12 in and 12 out.
  • the output terminals of the clock control chip are limited, it is difficult for the level shift circuit to provide more output ports. Even when the output terminal of the clock control chip is sufficient, the use of multiple level shifting chips will take up area and increase the cost.
  • the existing level shift chip is not easy to provide more output ports, is costly, and occupies area.
  • the present disclosure provides a level shift circuit, including a level shift unit, a first delay unit, two first switches, two second switches, four third switches, and four fourth switches. switch.
  • the level shift unit has two input terminals and four output terminals. The two input terminals of the level shift unit are electrically connected to the first switch respectively.
  • the first delay unit has two input terminals and two output terminals. The two output terminals of the first delay unit are respectively electrically connected between the two input terminals and the two first switches of the level shift unit. The two input ends of the first delay unit are respectively electrically connected to the other ends of the two first switches.
  • a second switch is electrically connected between the two output terminals of the first delay unit and the two input terminals of the level shift unit.
  • the first delay unit is used to delay a delay time of one unit.
  • the four output terminals of the level shift unit are electrically connected to the four third switches and the four fourth switches, respectively.
  • control signal of the second switch is delayed by one unit of the delay time from the control signal of the first switch.
  • control signal of the fourth switch is delayed by one unit of the delay time from the control signal of the third switch.
  • the level shift circuit further includes a second delay unit, two fifth switches, and four sixth switches.
  • the second delay unit has two input terminals and two output terminals. The two output terminals of the second delay unit are respectively electrically connected between the two input terminals of the level shift unit and the two first switches. The two input ends of the second delay unit are respectively electrically connected to the other ends of the two first switches.
  • One of the fifth switches is electrically connected between the two output terminals of the second delay unit and the two input terminals of the level shift unit.
  • the second delay unit is used to delay a delay time of two units.
  • the four output terminals of the level shift unit are electrically connected to the four sixth switches respectively.
  • control signal of the fifth switch is delayed by two units of the delay time than the control signal of the first switch.
  • the control signal of the sixth switch is delayed by two units of the delay time from the control signal of the third switch.
  • the level shift unit has four input terminals.
  • the first delay unit has four input terminals and four output terminals.
  • the second delay unit has four input terminals and four output terminals.
  • the present disclosure also provides a clock signal circuit including a clock control unit and a level shift circuit.
  • the clock control unit has two output terminals.
  • the level shift circuit includes a level shift unit, a first delay unit, two first switches, two second switches, four third switches, and four fourth switches.
  • the level shift unit has two input terminals and four output terminals. The two input terminals of the level shift unit are electrically connected to the first switch respectively. The two input terminals of the level shift unit are respectively electrically connected to the two output terminals of the clock control unit.
  • the two first switches are respectively electrically connected between the two output terminals of the clock control unit and the two input terminals of the level shift unit.
  • the first delay unit has two input terminals and two output terminals.
  • the two output terminals of the first delay unit are respectively electrically connected between the two input terminals of the level shift unit and the two first switches.
  • the two input terminals of the first delay unit are respectively electrically connected between the two first switches and the two output terminals of the clock control unit.
  • a second switch is electrically connected between the two output terminals of the first delay unit and the two input terminals of the level shift unit.
  • the first delay unit is used to delay a delay time of one unit, and four output terminals of the level shift unit are electrically connected to the four third switches and the four fourth switches, respectively.
  • control signal of the second switch is delayed by one unit of the delay time from the control signal of the first switch.
  • control signal of the fourth switch is delayed by one unit of the delay time from the control signal of the third switch.
  • the level shift circuit further includes a second delay unit, two fifth switches, and four sixth switches.
  • the second delay unit has two input terminals and two output terminals. The two output terminals of the second delay unit are respectively electrically connected between the two input terminals of the level shift unit and the two first switches. The two input ends of the second delay unit are respectively electrically connected to the other ends of the two first switches.
  • One of the fifth switches is electrically connected between the two output terminals of the second delay unit and the two input terminals of the level shift unit.
  • the second delay unit is used to delay a delay time of two units.
  • the four output terminals of the level shift unit are electrically connected to the four sixth switches respectively.
  • control signal of the fifth switch is delayed by two units of the delay time from the control signal of the first switch.
  • the control signal of the sixth switch is delayed by two units of the delay time from the control signal of the third switch.
  • the level shift unit has four input terminals.
  • the first delay unit has four input terminals and four output terminals.
  • the second delay unit has four input terminals and four output terminals.
  • the level shift circuit and the clock signal circuit of the embodiments of the present disclosure use at least the first delay unit, the two first switches, and two The second switch enables the input port of the level shift circuit to produce a time division multiplexing effect.
  • the output ports of the level shift circuit are multiplexed into more output ports. It has the effect of reducing cost and reducing circuit area.
  • FIG. 1 shows a schematic structural diagram of a clock signal circuit according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a clock signal circuit according to an embodiment of the present disclosure
  • FIG. 3 shows a timing diagram of a clock signal according to an embodiment of the present disclosure
  • FIG. 4 shows a timing diagram of a clock signal according to an embodiment of the present disclosure
  • FIG. 5 shows a timing diagram of a clock signal according to an embodiment of the present disclosure
  • FIG. 6 shows a timing diagram of a clock signal according to an embodiment of the present disclosure.
  • FIG. 7 shows a timing diagram of a clock signal according to an embodiment of the present disclosure.
  • the present disclosure provides a level shift circuit 100, including a level shift unit 110, a first delay unit 121, two first switches SW1, two second switches SW2, four third switches SW3, and four fourth switches SW4.
  • the level shift unit 110 has two input terminals and four output terminals. The two input terminals of the level shift unit 110 are electrically connected to the first switch SW1 respectively.
  • the first delay unit 121 has two input terminals and two output terminals. The two output terminals of the first delay unit 121 are respectively electrically connected between the two input terminals of the level shift unit 110 and the two first switches SW1. The two input ends of the first delay unit 121 are respectively electrically connected to the other ends of the two first switches SW1.
  • the second switch SW2 is electrically connected between the two output terminals of the first delay unit 121 and the two input terminals of the level shift unit 110 respectively.
  • the first delay unit 121 is used to delay the delay time D_1 by one unit.
  • the four output terminals of the level shift unit 110 are electrically connected to the four third switches SW3 and the four fourth switches SW4, respectively.
  • the clock control unit 200 has two output terminals corresponding to the output signals CK1 and CK2, respectively.
  • the first delay unit 121 intercepts and delays the two signals of the clock control unit 200 and then outputs signals CK3 and CK4 corresponding to the two output terminals.
  • the level shift circuit 100 After receiving the signals CK1 to CK4, the level shift circuit 100 performs level boosting and outputs signals CK1' to CK8'.
  • the two first switches SW1 are turned on according to the control signal CT1
  • the two second switches SW2 are turned on according to the control signal CT2.
  • the first switch SW1 and the second switch SW2 are turned on successively to multiplex the two input terminals of the level shift unit 110 in time division.
  • the four third switches SW3 are turned on according to the control signal CT3, and the four fourth switches SW4 are turned on according to the control signal CT4.
  • the third switch SW3 and the fourth switch SW4 are turned on successively to multiplex the four output terminals of the level shift unit 110 in time division.
  • the level shift unit 110 is, for example, a level shift chip (Level Shift IC), which is used to boost a driving signal circuit to supply a gate driver chip (Gate Shift IC) on the display panel 300. drive IC).
  • Level Shift IC level shift chip
  • Gate Shift IC gate driver chip
  • the delay time D_1 of one unit is 4 times the time interval of any two adjacent output signal pulses (CK1' ⁇ CK12') of the level shift unit 110, but the present disclosure is not limited to this.
  • the length of one unit of delay time D_1 can be determined according to the number of output/input ports actually used.
  • the signal ST is a start signal sent by the clock control unit 200. It is used to trigger the level shift unit 110 to generate an output signal according to the input signal.
  • the level shift circuit 100 wherein the control signal CT2 of the second switch SW2 is delayed from the control signal CT1 of the first switch SW1 One unit of the delay time D_1.
  • the control signal CT4 of the fourth switch SW4 is delayed by one unit of the delay time D_1 from the control signal CT3 of the third switch SW3.
  • the level shift circuit 100 wherein the level shift circuit 100 further includes a second delay unit 122, two fifth switches SW5, And four sixth switches SW6.
  • the second delay unit 122 has two input terminals and two output terminals. The two output terminals of the second delay unit 122 are respectively electrically connected between the two input terminals of the level shift unit 110 and the two first switches SW1. The two input ends of the second delay unit 122 are respectively electrically connected to the other ends of the two first switches SW1.
  • a fifth switch SW5 is electrically connected between the two output terminals of the second delay unit 122 and the two input terminals of the level shift unit 110 respectively.
  • the second delay unit 122 is used to delay the delay time D_1 by two units.
  • the four output terminals of the level shift unit 110 are respectively electrically connected to the four sixth switches SW6.
  • the two fifth switches SW5 are turned on according to the control signal CT5.
  • the first switch SW1, the second switch SW2, and the fifth switch SW5 are turned on sequentially to time-division multiplex the two input terminals of the level shift unit 110.
  • the four sixth switches SW6 are turned on according to the control signal CT6.
  • the third switch SW3, the fourth switch SW4, and the sixth switch SW6 are turned on successively to multiplex the four output terminals of the level shift unit 110 in time division.
  • the clock control unit 200 has two output terminals corresponding to the output signals CK1 and CK2, respectively.
  • the first delay unit 121 intercepts and delays the two signals of the clock control unit 200 and then outputs signals CK3 and CK4 corresponding to the two output terminals.
  • the second delay unit 122 intercepts and delays the two signals of the clock control unit 200 and then outputs the signals CK5 and CK6 corresponding to the two output terminals.
  • the level shift circuit 100 After receiving the signals CK1 to CK6, the level shift circuit 100 performs level boosting and outputs signals CK1' to CK12'.
  • the level shift circuit 100 wherein the control signal CT5 of the fifth switch SW5 is delayed from the control signal CT1 of the first switch SW1 The delay time D_1 of two units.
  • the control signal CT6 of the sixth switch SW6 is delayed by two units of the delay time D_1 from the control signal CT3 of the third switch SW3.
  • the level shift circuit 100' wherein the level shift unit 110' has four input terminals.
  • the first delay unit 121' has four input terminals and four output terminals.
  • the second delay unit 122' has four input terminals and four output terminals.
  • the clock control unit 200' has four output terminals corresponding to output signals CK1, CK2, CK3, and CK4, respectively.
  • the first delay unit 121' intercepts and delays the four signals of the clock control unit 200' and outputs signals CK5, CK6, CK7 and CK8 at the four output terminals respectively.
  • the second delay unit 122' intercepts and delays the four signals of the clock control unit 200' and outputs signals CK9, CK10, CK11, and CK12 at the four output terminals.
  • the level shift circuit 100' After receiving the signals CK1 to CK12, the level shift circuit 100' performs level boosting and outputs the signals CK1' to CK12'.
  • the present disclosure also provides a clock signal circuit 1000, including a clock control unit 200 and a level shift circuit 100.
  • the clock control unit 200 has two output terminals.
  • the level shift circuit 100 includes a level shift unit 110, a first delay unit 121, two first switches SW1, two second switches SW2, four third switches SW3, and four fourth switches SW4.
  • the level shift unit 110 has two input terminals and four output terminals. The two input terminals of the level shift unit 110 are electrically connected to the first switch SW1 respectively. The two input terminals of the level shift unit 110 are respectively electrically connected to the two output terminals of the clock control unit 200.
  • the two first switches SW1 are respectively electrically connected between the two output terminals of the clock control unit 200 and the two input terminals of the level shift unit 110.
  • the first delay unit 121 has two input terminals and two output terminals.
  • the two output terminals of the first delay unit 121 are respectively electrically connected between the two input terminals of the level shift unit 110 and the two first switches SW1.
  • the two input terminals of the first delay unit 121 are respectively electrically connected between the two first switches SW1 and the two output terminals of the clock control unit 200.
  • the second switch SW2 is electrically connected between the two output terminals of the first delay unit 121 and the two input terminals of the level shift unit 110 respectively.
  • the first delay unit 121 is used to delay the delay time D_1 by one unit, and the four output terminals of the level shift unit 110 are electrically connected to the four third switches SW3 and the four fourth switches SW4, respectively.
  • the clock control unit 200 has two output terminals corresponding to the output signals CK1 and CK2, respectively.
  • the first delay unit 121 intercepts and delays the two signals of the clock control unit 200 and then outputs signals CK3 and CK4 corresponding to the two output terminals.
  • the level shift circuit 100 After receiving the signals CK1 to CK4, the level shift circuit 100 performs level boosting and outputs the signals CK1' to CK8'.
  • the two first switches SW1 are turned on according to the control signal CT1
  • the two second switches SW2 are turned on according to the control signal CT2.
  • the first switch SW1 and the second switch SW2 are turned on sequentially to time-division multiplex the two input terminals of the level shift unit 110.
  • the four third switches SW3 are turned on according to the control signal CT3, and the four fourth switches SW4 are turned on according to the signal CT4.
  • the third switch SW3 and the fourth switch SW4 are turned on successively to multiplex the four output terminals of the level shift unit 110 in time division.
  • the level shift unit 110 is, for example, a level shift chip (Level Shift IC), which is used to boost a driving signal circuit to supply a gate driver chip (Gate Shift IC) on the display panel 300. drive IC).
  • Level Shift IC level shift chip
  • Gate Shift IC gate driver chip
  • the delay time D_1 of one unit is 4 times the time interval of any two adjacent output signal pulses (CK1' ⁇ CK12') of the level shift unit 110, but the present disclosure is not limited to this.
  • the length of the delay time D_1 of one unit can be determined according to the number of output/input ports actually used.
  • the signal ST is a start signal sent by the clock control unit 200. It is used to trigger the level shift unit 110 to generate an output signal according to the input signal.
  • the clock signal circuit 1000 wherein the control signal CT2 of the second switch SW2 is delayed by one than the control signal CT1 of the first switch SW1 Unit of the delay time D_1.
  • the control signal CT4 of the fourth switch SW4 is delayed by one unit of the delay time D_1 from the control signal CT3 of the third switch SW3.
  • the clock signal circuit 1000 wherein the level shift circuit 100 further includes a second delay unit 122, two fifth switches SW5, and Four sixth switches SW6.
  • the second delay unit 122 has two input terminals and two output terminals. The two output terminals of the second delay unit 122 are respectively electrically connected between the two input terminals of the level shift unit 110 and the two first switches SW1. The two input ends of the second delay unit 122 are respectively electrically connected to the other ends of the two first switches SW1.
  • a fifth switch SW5 is electrically connected between the two output terminals of the second delay unit 122 and the two input terminals of the level shift unit 110 respectively.
  • the second delay unit 122 is used to delay the delay time D_1 by two units.
  • the four output terminals of the level shift unit 110 are respectively electrically connected to the four sixth switches SW6.
  • the two fifth switches SW5 are turned on according to the control signal CT5.
  • the first switch SW1, the second switch SW2, and the fifth switch SW5 are turned on successively to multiplex the two input terminals of the level shift unit 110 in time division.
  • the four sixth switches SW6 are turned on according to the control signal CT6.
  • the third switch SW3, the fourth switch SW4, and the sixth switch SW6 are turned on successively to multiplex the four output terminals of the level shift unit 110 in time division.
  • the clock control unit 200 has two output terminals corresponding to the output signals CK1 and CK2, respectively.
  • the first delay unit 121 intercepts and delays the two signals of the clock control unit 200 and then outputs signals CK3 and CK4 corresponding to the two output terminals.
  • the second delay unit 122 intercepts and delays the two signals of the clock control unit 200 and then outputs the signals CK5 and CK6 corresponding to the two output terminals.
  • the level shift circuit 100 After receiving the signals CK1 to CK6, the level shift circuit 100 performs level boosting and outputs the signals CK1' to CK12'.
  • the clock signal circuit 1000 wherein the control signal CT5 of the fifth switch SW5 is delayed by two times the control signal CT1 of the first switch SW1 Units of the delay time D_1.
  • the control signal CT6 of the sixth switch SW6 is delayed by two units of the delay time D_1 from the control signal CT3 of the third switch SW3.
  • the level shift unit 110' has four input terminals.
  • the first delay unit 121' has four input terminals and four output terminals.
  • the second delay unit 122' has four input terminals and four output terminals.
  • the clock control unit 200' has four output terminals corresponding to output signals CK1, CK2, CK3, and CK4, respectively.
  • the first delay unit 121' intercepts and delays the four signals of the clock control unit 200' and outputs signals CK5, CK6, CK7 and CK8 at the four output terminals respectively.
  • the second delay unit 122' intercepts and delays the four signals of the clock control unit 200' and outputs signals CK9, CK10, CK11, and CK12 at the four output terminals.
  • the level shift circuit 100' After receiving the signals CK1 to CK12, the level shift circuit 100' performs level boosting and outputs the signals CK1' to CK12'.
  • the numbers of the input terminals and the output terminals in all the embodiments of the present disclosure are only examples, and the present disclosure does not limit the number of the input terminals and the output terminals.
  • the first delay unit, the two first switches, and the two second switches are used to make the input of the level shift circuit
  • the port produces the effect of time division multiplexing.
  • the output ports of the level shift circuit are multiplexed into more output ports. It has the effect of reducing cost and reducing circuit area.

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Abstract

本揭示提供一种电平移位电路以及一种时钟讯号电路。所述电平移位电路包括电平移位单元、第一延迟单元、二个第一开关、以及二个第二开关。所述电平移位单元的所述两个输入端分别电连接一个所述第一开关。所述第一延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间。所述第一延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第二开关。所述第一延迟单元用以延迟一个单位的延迟时间。

Description

电平移位电路及时钟讯号电路 技术领域
本揭示涉及显示技术领域，特别涉及一种电平移位电路以及一种时钟讯号电路。
 背景技术
主动矩阵式的液晶显示屏(Active-Matrix Liquid Crystal Display, AMLCD)若采用阵列基板栅驱动技术(Gate On Array, GOA)，则需要在时钟讯号进入栅驱动芯片之前进行电平的提升。
一般采用电平移位芯片来进行电平的提升。现有的电平移位芯片为2进4出，4进4出以及12进12出。在时钟控制芯片的输出端有限的情况下，电平移位电路不易提供更多的输出端口。即使在时钟控制芯片的输出端足够的情况下，使用多个电平移位芯片也会占用面积，提高成本。
 技术问题
现有的电平移位芯片不易提供更多的输出端口、成本高且占用面积。
 技术解决方案
为解决上述技术问题，本揭示提供一种电平移位电路，包括电平移位单元、第一延迟单元、二个第一开关、二个第二开关、四个第三开关、以及四个第四开关。所述电平移位单元具有两个输入端及四个输出端。所述电平移位单元的所述两个输入端分别电连接一个所述第一开关。所述第一延迟单元具有二个输入端及二个输出端。所述第一延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间。所述第一延迟单元的二个所述输入端分别对应电连接至二个所述第一开关的另一端。所述第一延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第二开关。所述第一延迟单元用以延迟一个单位的延迟时间。所述电平移位单元的四个输出端分别电连接四个所述第三开关以及四个所述第四开关。
于本揭示的一实施例的电平移位电路中，其中，所述第二开关的控制信号比所述第一开关的控制信号延迟一个单位的所述延迟时间。所述第四开关的控制信号比所述第三开关的控制信号延迟一个单位的所述延迟时间。
于本揭示的一实施例的电平移位电路中，其中，所述电平移位电路还包括第二延迟单元、二个第五开关、以及四个第六开关。所述第二延迟单元具有二个输入端及二个输出端。所述第二延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间。所述第二延迟单元的二个所述输入端分别对应电连接至二个所述第一开关的另一端。所述第二延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第五开关。所述第二延迟单元用以延迟二个单位的延迟时间。所述电平移位单元的四个输出端分别电连接四个所述第六开关。
于本揭示的一实施例的电平移位电路中，其中，所述第五开关的控制信号比所述第一开关的控制信号延迟二个单位的所述延迟时间。所述第六开关的控制信号比所述第三开关的控制信号延迟二个单位的所述延迟时间。
于本揭示的一实施例的电平移位电路中，其中，所述电平移位单元具有四个输入端。所述第一延迟单元具有四个输入端及四个输出端。所述第二延迟单元具有四个输入端及四个输出端。
本揭示还提供一种时钟讯号电路，包括时钟控制单元以及电平移位电路。所述时钟控制单元具有两个输出端。所述电平移位电路包括电平移位单元、第一延迟单元、二个第一开关、二个第二开关、四个第三开关、以及四个第四开关。所述电平移位单元具有两个输入端及四个输出端。所述电平移位单元的所述两个输入端分别电连接一个所述第一开关。所述电平移位单元的两个所述输入端分别对应电连接至所述时钟控制单元的两个所述输出端。所述两个第一开关分别对应电连接至所述时钟控制单元的两个所述输出端与所述电平移位单元的两个所述输入端之间。所述第一延迟单元具有二个输入端及二个输出端。所述第一延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间。所述第一延迟单元的二个所述输入端分别对应电连接至二个所述第一开关与所述时钟控制单元的两个所述输出端之间。所述第一延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第二开关。所述第一延迟单元用以延迟一个单位的延迟时间，所述电平移位单元的四个输出端分别电连接四个所述第三开关以及四个所述第四开关。
于本揭示的一实施例的时钟讯号电路中，其中，所述第二开关的控制信号比所述第一开关的控制信号延迟一个单位的所述延迟时间。所述第四开关的控制信号比所述第三开关的控制信号延迟一个单位的所述延迟时间。
于本揭示的一实施例的时钟讯号电路中，其中，所述电平移位电路还包括第二延迟单元、二个第五开关、以及四个第六开关。所述第二延迟单元具有二个输入端及二个输出端。所述第二延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间。所述第二延迟单元的二个所述输入端分别对应电连接至二个所述第一开关的另一端。所述第二延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第五开关。所述第二延迟单元用以延迟二个单位的延迟时间。所述电平移位单元的四个输出端分别电连接四个所述第六开关。
于本揭示的一实施例的时钟讯号电路中，其中，所述第五开关的控制信号比所述第一开关的控制信号延迟二个单位的所述延迟时间。所述第六开关的控制信号比所述第三开关的控制信号延迟二个单位的所述延迟时间。
于本揭示的一实施例的时钟讯号电路中，其中，所述电平移位单元具有四个输入端。所述第一延迟单元具有四个输入端及四个输出端。所述第二延迟单元具有四个输入端及四个输出端。
 有益效果
相较于现有技术，为解决上述技术问题，由于本揭示的实施例的电平移位电路以及时钟讯号电路中，使用至少所述第一延迟单元、二个所述第一开关、以及二个所述第二开关以使电平移位电路的输入端口产生分时复用的效果。配合所述第三开关、以及所述第四开关以使电平移位电路的输出端口复用成更多个输出端口。具有降低成本并减小电路面积的效果。
 附图说明
图1显示根据本揭示的一实施例的时钟讯号电路的结构示意图；
图2显示根据本揭示的一实施例的时钟讯号电路的结构示意图；
图3显示根据本揭示的一实施例的时钟讯号的时序示意图；
图4显示根据本揭示的一实施例的时钟讯号的时序示意图；
图5显示根据本揭示的一实施例的时钟讯号的时序示意图；
图6显示根据本揭示的一实施例的时钟讯号的时序示意图；以及
图7显示根据本揭示的一实施例的时钟讯号的时序示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1及图3，本揭示提供一种电平移位电路100，包括电平移位单元110、第一延迟单元121、二个第一开关SW1、二个第二开关SW2、四个第三开关SW3、以及四个第四开关SW4。所述电平移位单元110具有两个输入端及四个输出端。所述电平移位单元110的所述两个输入端分别电连接一个所述第一开关SW1。所述第一延迟单元121具有二个输入端及二个输出端。所述第一延迟单元121的二个所述输出端分别对应电连接至所述电平移位单元110的二个所述输入端与二个所述第一开关SW1之间。所述第一延迟单元121的二个所述输入端分别对应电连接至二个所述第一开关SW1的另一端。所述第一延迟单元121的二个所述输出端与所述电平移位单元110的二个所述输入端之间分别电连接一个所述第二开关SW2。所述第一延迟单元121用以延迟一个单位的延迟时间D_1。所述电平移位单元110的四个输出端分别电连接四个所述第三开关SW3以及四个所述第四开关SW4。
具体的，时钟控制单元200有二个输出端分别对应输出讯号CK1、CK2。所述第一延迟单元121截取时钟控制单元200的二个讯号进行延迟后于二个输出端分别对应输出讯号CK3、及CK4。电平移位电路100接收讯号CK1至CK4后进行电平提升并输出讯号CK1’至CK8’。
参照图4及图5，具体的，二个所述第一开关SW1依据控制讯号CT1而导通、二个所述第二开关SW2依据控制讯号CT2而导通。所述第一开关SW1与所述第二开关SW2先后导通以分时复用所述电平移位单元110的所述两个输入端。四个所述第三开关SW3依据控制讯号CT3而导通、四个所述第四开关SW4依据控制讯号CT4而导通。所述第三开关SW3与所述第四开关SW4先后导通以分时复用所述电平移位单元110的所述四个输出端。
具体的，所述电平移位单元110例如为电平移位芯片(Level Shift IC)，用以将驱动信号的电路升压，以供给显示面板300上的栅驱动芯片(Gate drive IC)。
具体的，一个单位的延迟时间D_1为所述电平移位单元110任两相临输出讯号脉冲(CK1’~CK12’)的时间间隔的4倍，但本揭示不限于此。可依实际使用的输出/输入端口数目来决定一个单位的延迟时间D_1的长度。
具体的，信号ST为时钟控制单元200发送的启始信号。用以触发所述电平移位单元110依据输入信号产生输出信号。
参照图4及图5，于本揭示其中的一实施例中，所述的电平移位电路100，其中，所述第二开关SW2的控制信号CT2比所述第一开关SW1的控制信号CT1延迟一个单位的所述延迟时间D_1。所述第四开关SW4的控制信号CT4比所述第三开关SW3的控制信号CT3延迟一个单位的所述延迟时间D_1。
参照图1及图3，于本揭示其中的一实施例中，所述的电平移位电路100，其中，所述电平移位电路100还包括第二延迟单元122、二个第五开关SW5、以及四个第六开关SW6。所述第二延迟单元122具有二个输入端及二个输出端。所述第二延迟单元122的二个所述输出端分别对应电连接至所述电平移位单元110的二个所述输入端与二个所述第一开关SW1之间。所述第二延迟单元122的二个所述输入端分别对应电连接至二个所述第一开关SW1的另一端。所述第二延迟单元122的二个所述输出端与所述电平移位单元110的二个所述输入端之间分别电连接一个所述第五开关SW5。所述第二延迟单元122用以延迟二个单位的延迟时间D_1。所述电平移位单元110的四个输出端分别电连接四个所述第六开关SW6。
参照图4及图5，具体的，二个所述第五开关SW5依据控制讯号CT5而导通。所述第一开关SW1、所述第二开关SW2与所述第五开关SW5先后导通以分时复用所述电平移位单元110的所述两个输入端。四个所述第六开关SW6依据控制讯号CT6而导通。所述第三开关SW3、所述第四开关SW4与所述第六开关SW6先后导通以分时复用所述电平移位单元110的所述四个输出端。
具体的，时钟控制单元200有二个输出端分别对应输出讯号CK1、CK2。所述第一延迟单元121截取时钟控制单元200的二个讯号进行延迟后于二个输出端分别对应输出讯号CK3、及CK4。所述第二延迟单元122 截取时钟控制单元200的二个讯号进行延迟后于二个输出端对应输出讯号CK5、及CK6。电平移位电路100接收讯号CK1至CK6后进行电平提升并输出讯号CK1’至CK12’。
参照图4及图5，于本揭示其中的一实施例中，所述的电平移位电路100，其中，所述第五开关SW5的控制信号CT5比所述第一开关SW1的控制信号CT1延迟二个单位的所述延迟时间D_1。所述第六开关SW6的控制信号CT6比所述第三开关SW3的控制信号CT3延迟二个单位的所述延迟时间D_1。
参照图2，于本揭示其中的一实施例中，所述的电平移位电路100’，其中，所述电平移位单元110’具有四个输入端。所述第一延迟单元121’具有四个输入端及四个输出端。所述第二延迟单元122’具有四个输入端及四个输出端。
具体的，参照图2、图6及图7，时钟控制单元200’有四个输出端分别对应输出讯号CK1、CK2、CK3及CK4。所述第一延迟单元121’截取时钟控制单元200’的四个讯号进行延迟后于四个输出端分别对应输出讯号CK5、CK6、CK7及CK8。所述第二延迟单元122’截取时钟控制单元200’的四个讯号进行延迟后于四个输出端对应输出讯号CK9、CK10、CK11及CK12。电平移位电路100’接收讯号CK1至CK12后进行电平提升并输出讯号CK1’至CK12’。
参照图1及图3，本揭示还提供一种时钟讯号电路1000，包括时钟控制单元200以及电平移位电路100。所述时钟控制单元200具有两个输出端。所述电平移位电路100包括电平移位单元110、第一延迟单元121、二个第一开关SW1、二个第二开关SW2、四个第三开关SW3、以及四个第四开关SW4。所述电平移位单元110具有两个输入端及四个输出端。所述电平移位单元110的所述两个输入端分别电连接一个所述第一开关SW1。所述电平移位单元110的两个所述输入端分别对应电连接至所述时钟控制单元200的两个所述输出端。所述两个第一开关SW1分别对应电连接至所述时钟控制单元200的两个所述输出端与所述电平移位单元110的两个所述输入端之间。所述第一延迟单元121具有二个输入端及二个输出端。所述第一延迟单元121的二个所述输出端分别对应电连接至所述电平移位单元110的二个所述输入端与二个所述第一开关SW1之间。所述第一延迟单元121的二个所述输入端分别对应电连接至二个所述第一开关SW1与所述时钟控制单元200的两个所述输出端之间。所述第一延迟单元121的二个所述输出端与所述电平移位单元110的二个所述输入端之间分别电连接一个所述第二开关SW2。所述第一延迟单元121用以延迟一个单位的延迟时间D_1，所述电平移位单元110的四个输出端分别电连接四个所述第三开关SW3以及四个所述第四开关SW4。
具体的，时钟控制单元200有二个输出端分别对应输出讯号CK1、CK2。所述第一延迟单元121截取时钟控制单元200的二个讯号进行延迟后于二个输出端分别对应输出讯号CK3、及CK4。电平移位电路100接收讯号CK1至CK4后进行电平提升并输出讯号CK1’至CK8’。
参照图4及图5，具体的，二个所述第一开关SW1依据控制讯号CT1而导通、二个所述第二开关SW2依据控制讯号CT2而导通。所述第一开关SW1与所述第二开关SW2先后导通以分时复用所述电平移位单元110的所述两个输入端。四个所述第三开关SW3依据控制讯号CT3而导通、四个所述第四开关SW4依据讯号CT4而导通。所述第三开关SW3与所述第四开关SW4先后导通以分时复用所述电平移位单元110的所述四个输出端。
具体的，所述电平移位单元110例如为电平移位芯片(Level Shift IC)，用以将驱动信号的电路升压，以供给显示面板300上的栅驱动芯片(Gate drive IC)。
具体的，一个单位的延迟时间D_1为所述电平移位单元110任两相临输出讯号脉冲(CK1’~CK12’)的时间间隔的4倍，但本揭示不限于此。可依实际使用的输出/输入端口数目来决定一个单位的延迟时间D_1的长度。
具体的，信号ST为时钟控制单元200发送的启始信号。用以触发所述电平移位单元110依据输入信号产生输出信号。
参照图4及图5，于本揭示其中的一实施例中，所述的时钟讯号电路1000，其中，所述第二开关SW2的控制信号CT2比所述第一开关SW1的控制信号CT1延迟一个单位的所述延迟时间D_1。所述第四开关SW4的控制信号CT4比所述第三开关SW3的控制信号CT3延迟一个单位的所述延迟时间D_1。
参照图1及图3，于本揭示其中的一实施例中，所述的时钟讯号电路1000，其中，所述电平移位电路100还包括第二延迟单元122、二个第五开关SW5、以及四个第六开关SW6。所述第二延迟单元122具有二个输入端及二个输出端。所述第二延迟单元122的二个所述输出端分别对应电连接至所述电平移位单元110的二个所述输入端与二个所述第一开关SW1之间。所述第二延迟单元122的二个所述输入端分别对应电连接至二个所述第一开关SW1的另一端。所述第二延迟单元122的二个所述输出端与所述电平移位单元110的二个所述输入端之间分别电连接一个所述第五开关SW5。所述第二延迟单元122用以延迟二个单位的延迟时间D_1。所述电平移位单元110的四个输出端分别电连接四个所述第六开关SW6。
参照图4及图5，具体的，二个所述第五开关SW5依据控制讯号CT5而导通。所述第一开关SW1、所述第二开关SW2与所述第五开关SW5先后导通以分时复用所述电平移位单元110的所述两个输入端。四个所述第六开关SW6依据控制讯号CT6而导通。所述第三开关SW3、所述第四开关SW4与所述第六开关SW6先后导通以分时复用所述电平移位单元110的所述四个输出端。
具体的，时钟控制单元200有二个输出端分别对应输出讯号CK1、CK2。所述第一延迟单元121截取时钟控制单元200的二个讯号进行延迟后于二个输出端分别对应输出讯号CK3、及CK4。所述第二延迟单元122 截取时钟控制单元200的二个讯号进行延迟后于二个输出端对应输出讯号CK5、及CK6。电平移位电路100接收讯号CK1至CK6后进行电平提升并输出讯号CK1’至CK12’。
参照图4及图5，于本揭示其中的一实施例中，所述的时钟讯号电路1000，其中，所述第五开关SW5的控制信号CT5比所述第一开关SW1的控制信号CT1延迟二个单位的所述延迟时间D_1。所述第六开关SW6的控制信号CT6比所述第三开关SW3的控制信号CT3延迟二个单位的所述延迟时间D_1。
参照图2，于本揭示其中的一实施例中，所述的时钟讯号电路1000’，其中，所述电平移位单元110’具有四个输入端。所述第一延迟单元121’具有四个输入端及四个输出端。所述第二延迟单元122’具有四个输入端及四个输出端。
具体的，参照图2、图6及图7，时钟控制单元200’有四个输出端分别对应输出讯号CK1、CK2、CK3及CK4。所述第一延迟单元121’截取时钟控制单元200’的四个讯号进行延迟后于四个输出端分别对应输出讯号CK5、CK6、CK7及CK8。所述第二延迟单元122’截取时钟控制单元200’的四个讯号进行延迟后于四个输出端对应输出讯号CK9、CK10、CK11及CK12。电平移位电路100’接收讯号CK1至CK12后进行电平提升并输出讯号CK1’至CK12’。
具体的，本揭示的所有实施例的所述输入端与所述输出端的数目仅为示例，本揭示不限制所述输入端与所述输出端的数目。
由于本揭示的实施例的电平移位电路以及时钟讯号电路中，使用至少所述第一延迟单元、二个所述第一开关、以及二个所述第二开关以使电平移位电路的输入端口产生分时复用的效果。配合所述第三开关、以及所述第四开关以使电平移位电路的输出端口复用成更多个输出端口。具有降低成本并减小电路面积的效果。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (12)

  1. 一种电平移位电路，包括：
    电平移位单元；
    第一延迟单元；
    二个第一开关；
    二个第二开关；
    四个第三开关；以及
    四个第四开关，其中，所述电平移位单元具有两个输入端及四个输出端，所述电平移位单元的所述两个输入端分别电连接一个所述第一开关，所述第一延迟单元具有二个输入端及二个输出端，所述第一延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间，所述第一延迟单元的二个所述输入端分别对应电连接至二个所述第一开关的另一端，所述第一延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第二开关，所述第一延迟单元用以延迟一个单位的延迟时间，所述电平移位单元的四个输出端分别电连接四个所述第三开关以及四个所述第四开关。
  2. 如权利要求1所述的电平移位电路，其中，所述第二开关的控制信号比所述第一开关的控制信号延迟一个单位的所述延迟时间，所述第四开关的控制信号比所述第三开关的控制信号延迟一个单位的所述延迟时间。
  3. 如权利要求1所述的电平移位电路，其中，所述电平移位电路还包括第二延迟单元，二个第五开关以及四个第六开关，其中，所述第二延迟单元具有二个输入端及二个输出端，所述第二延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间，所述第二延迟单元的二个所述输入端分别对应电连接至二个所述第一开关的另一端，所述第二延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第五开关，所述第二延迟单元用以延迟二个单位的延迟时间，所述电平移位单元的四个输出端分别电连接四个所述第六开关。
  4. 如权利要求3所述的电平移位电路，其中，所述第五开关的控制信号比所述第一开关的控制信号延迟二个单位的所述延迟时间，所述第六开关的控制信号比所述第三开关的控制信号延迟二个单位的所述延迟时间。
  5. 如权利要求3所述的电平移位电路，其中，所述电平移位单元具有四个输入端，所述第一延迟单元具有四个输入端及四个输出端，所述第二延迟单元具有四个输入端及四个输出端。
  6. 如权利要求5所述的电平移位电路，其中，所述第一开关的数量为四个、所述第二开关的数量为四个、所述第五开关的数量为四个。
  7. 一种时钟讯号电路，包括：
    时钟控制单元；以及
    电平移位电路，其中，所述时钟控制单元具有两个输出端，所述电平移位电路包括:
    电平移位单元；
    第一延迟单元；
    二个第一开关；
    二个第二开关；
    四个第三开关；以及
    四个第四开关，其中，所述电平移位单元具有两个输入端及四个输出端，所述电平移位单元的所述两个输入端分别电连接一个所述第一开关，所述电平移位单元的两个所述输入端分别对应电连接至所述时钟控制单元的两个所述输出端，所述两个第一开关分别对应电连接至所述时钟控制单元的两个所述输出端与所述电平移位单元的两个所述输入端之间，所述第一延迟单元具有二个输入端及二个输出端，所述第一延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间，所述第一延迟单元的二个所述输入端分别对应电连接至二个所述第一开关与所述时钟控制单元的两个所述输出端之间，所述第一延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第二开关，所述第一延迟单元用以延迟一个单位的延迟时间，所述电平移位单元的四个输出端分别电连接四个所述第三开关以及四个所述第四开关。
  8. 如权利要求7所述的时钟讯号电路，其中，所述第二开关的控制信号比所述第一开关的控制信号延迟一个单位的所述延迟时间，所述第四开关的控制信号比所述第三开关的控制信号延迟一个单位的所述延迟时间。
  9. 如权利要求8所述的时钟讯号电路，其中，所述电平移位电路还包括第二延迟单元，二个第五开关以及四个第六开关，其中，所述第二延迟单元具有二个输入端及二个输出端，所述第二延迟单元的二个所述输出端分别对应电连接至所述电平移位单元的二个所述输入端与二个所述第一开关之间，所述第二延迟单元的二个所述输入端分别对应电连接至二个所述第一开关的另一端，所述第二延迟单元的二个所述输出端与所述电平移位单元的二个所述输入端之间分别电连接一个所述第五开关，所述第二延迟单元用以延迟二个单位的延迟时间，所述电平移位单元的四个输出端分别电连接四个所述第六开关。
  10. 如权利要求9所述的时钟讯号电路，其中，所述第五开关的控制信号比所述第一开关的控制信号延迟二个单位的所述延迟时间，所述第六开关的控制信号比所述第三开关的控制信号延迟二个单位的所述延迟时间。
  11. 如权利要求9所述的时钟讯号电路，其中，所述时钟控制单元具有两个输出端，所述电平移位单元具有四个输入端，所述第一延迟单元具有四个输入端及四个输出端，所述第二延迟单元具有四个输入端及四个输出端。
  12. 如权利要求11所述的时钟讯号电路，其中，所述第一开关的数量为四个、所述第二开关的数量为四个、所述第五开关的数量为四个。
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