WO2020233490A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2020233490A1
WO2020233490A1 PCT/CN2020/090199 CN2020090199W WO2020233490A1 WO 2020233490 A1 WO2020233490 A1 WO 2020233490A1 CN 2020090199 W CN2020090199 W CN 2020090199W WO 2020233490 A1 WO2020233490 A1 WO 2020233490A1
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WIPO (PCT)
Prior art keywords
sub
pixel
switching element
display panel
gate lines
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PCT/CN2020/090199
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English (en)
French (fr)
Inventor
张夺
张英豪
江峰
路永全
张炜檬
张旭茹
张彦杰
王谦
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/270,067 priority Critical patent/US11328648B2/en
Publication of WO2020233490A1 publication Critical patent/WO2020233490A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the embodiment of the present disclosure relates to a display panel and a display device including the display panel.
  • Wearable devices such as smart watches are gradually being favored by consumers.
  • transflective technology smart wearable devices can realize the function of reflection under strong light and transmission under dark light. This reduces the power consumption of the device and improves battery life.
  • the working mode of reflection under strong light improves the appropriability of the wearable device under strong light, thereby improving consumer experience.
  • an embodiment of the present disclosure provides a display panel, including: a plurality of data lines; a plurality of groups of gate lines, wherein each group of gate lines includes at least three gate lines; and a plurality of pixel units, wherein the plurality of pixels
  • the units are arranged in an array, each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes at least two sub-sub-pixels, wherein each row of sub-pixels is configured to be controlled by a corresponding set of gate lines, and each column of sub-pixels is configured So that the at least two sub-sub-pixels receive a data signal from a corresponding data line under the control of each group of gate lines.
  • two sets of gate lines corresponding to two adjacent rows of sub-pixels share one gate line.
  • the plurality of groups of gate lines include an odd array of gate lines corresponding to odd rows of pixel units and an even array of gate lines corresponding to even rows of pixel units, and two adjacent odd arrays of gate lines One gate line is shared, and two adjacent even-group gate lines share one gate line.
  • the display panel further includes a plurality of switching elements, and each switching element of the plurality of switching elements is controlled on and off by a corresponding gate line.
  • each sub-sub-pixel in each sub-pixel is connected to a corresponding one of the data lines through two switches in the plurality of switching elements.
  • each sub pixel includes a first sub sub pixel and a second sub sub pixel
  • each group of gate lines includes a first gate line, a second gate line, and a third gate line
  • Each switching element includes a first switching element, a second switching element, and a third switching element.
  • the first gate line controls the on-off of the first switch
  • the second gate line controls the on-off of the second switch
  • the third gate line controls the On and off of the third switch.
  • the first sub-sub-pixel is connected to the first data line through the first switching element and the second switching element
  • the second sub-sub-pixel is connected to the first data line through the third switching element and the second switching element.
  • the switching element is connected to the first data line.
  • the area ratio of the first sub-sub-pixel and the second sub-sub-pixel is 2:1.
  • each sub-pixel includes a first sub-sub-pixel, a second sub-sub-pixel, and a third sub-sub-pixel
  • each group of gate lines includes a first gate line, a second gate line, and a third gate line.
  • Line, and the plurality of switching elements include a first switching element, a second switching element, a third switching element, a fourth switching element, and a fifth switching element.
  • the first gate line controls the on-off of the first switch and the fourth switch
  • the second gate line controls the on-off of the second switch
  • the first The three gate lines control the on and off of the third switch and the fifth switch.
  • the first sub-sub-pixel is connected to the first data line through the first switching element and the second switching element
  • the second sub-sub-pixel is connected to the first data line through the fifth switching element and the fourth switching element.
  • the switching element is connected to the first data line
  • the third sub-sub-pixel is connected to the first data line through the third switching element and the second switching element.
  • the area ratio of the first sub-sub-pixel, the second sub-sub-pixel, and the third sub-sub-pixel is 4:2:1.
  • the first sub-sub-pixel, the second sub-sub-pixel, and the third sub-sub-pixel of each sub-pixel have the same primary color.
  • the third sub-sub pixel of each sub-pixel is a white sub-sub pixel.
  • the white sub-sub-pixels are total reflection sub-sub-pixels.
  • the switching element is a thin film transistor.
  • an embodiment of the present disclosure also provides a display device including the display panel described above.
  • FIG. 1 is a schematic diagram of a pixel unit of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of wiring used in the pixel unit shown in FIG. 1;
  • FIG. 3 is a timing diagram of signals used to drive the pixel unit shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a pixel unit of a display panel according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of wiring used in the pixel unit shown in FIG. 4.
  • FIG. 6 is a timing diagram of signals used to drive the pixel unit shown in FIG. 4.
  • the driver IC of the wearable device usually can only use the serial peripheral interface (Serial Peripheral Interface, SPI) signal for transmission.
  • SPI Serial Peripheral Interface
  • This signal is high or low, that is, 0 or 1, so it is impossible to directly control the level of the control signal in the data line to achieve different display gray levels.
  • an embodiment of the present disclosure provides a display panel in which a sub-pixel in a pixel unit is divided into two sub-sub-pixels, and the sub-sub-pixels are turned on or off respectively to achieve different display gray levels.
  • Fig. 1 schematically shows a layout of pixel units of a display panel adopting this solution.
  • the display panel may include a plurality of pixel units 100 (only one of which is exemplarily shown in FIG. 1).
  • Each pixel unit 100 may include three sub-pixels, such as a first sub-pixel 110, a second sub-pixel 120, and a third sub-pixel 130.
  • the first sub-pixel 110 is a red sub-pixel
  • the second sub-pixel 120 is a green sub-pixel
  • the third sub-pixel 130 is a blue sub-pixel.
  • each sub-pixel is divided into two sub-sub-pixels.
  • the first sub-pixel 110 includes a first sub-sub-pixel 110a and a second sub-sub-pixel 110b
  • the second sub-pixel 120 includes a first sub-sub-pixel 120a and a second sub-sub-pixel 120b
  • the third sub-pixel 130 includes a first The sub-sub-pixel 130a and the second sub-sub-pixel 130b.
  • the two sub-sub-pixels of each sub-pixel are divided according to a preset area ratio.
  • the area ratio of the first sub-sub pixel and the second sub-sub pixel is 2:1.
  • the area ratio of the first sub sub pixel 110 a to the second sub sub pixel 110 b is 2:1.
  • FIG. 2 schematically shows a wiring diagram for the pixel unit shown in FIG. 1.
  • a plurality of pixel units 100 are arranged in an array.
  • the display panel also includes a plurality of data lines and a plurality of gate lines arranged in a staggered manner.
  • Figure 2 only shows the pixel units of odd rows, z data lines S1, S2, S3...Sz, and odd gate lines G1-0, G1-1, G1-2, G3-0, G3-1, G3- 2...Gn-m.
  • n is a positive odd number greater than 1
  • m is an integer between 0-2.
  • each row of sub-pixels corresponds to a group of gate lines, and each group of gate lines includes three gate lines.
  • the pixel units 100 in the first odd row correspond to the first group of gate lines.
  • the first group of gate lines includes a first gate line G1-0, a second gate line G1-1, and a third gate line G1-2.
  • the pixel units 100 in the second odd row correspond to the third group of gate lines.
  • the third group of gate lines includes a third gate line G3-0, a fourth gate line G3-1, and a fifth gate line G3-2.
  • the pixel units in the even rows and their corresponding groups of gate lines are not shown here, for example, the pixel units in the first even rows and their corresponding second group of gate lines, and the pixel units in the second even rows and their corresponding groups
  • the fourth set of grid lines Two adjacent odd groups of grid lines can share one grid line, and two adjacent even groups of grid lines can share one grid line.
  • G1-2 and G3-0 can be the same grid line
  • G4-0 and G2- 2 can be the same grid line.
  • each of the three sub-pixels is turned on or off to provide different display gray levels.
  • the first sub-sub-pixel 110a is connected to the data line S1 through the first switching element 21 and the second switching element 22, wherein the first gate line G1-0 controls the on and off of the first switching element 21 ,
  • the second gate line G1-1 controls the on and off of the second switching element 22;
  • the second sub-pixel 110b is connected to the data line S1 through the third switching element 23 and the second switching element 22, wherein the third gate line G1-2
  • the third switching element 23 is controlled on and off, and the second gate line G1-1 controls the on and off of the second switching element 22. That is, one sub-sub pixel is jointly controlled by two switching elements.
  • the first sub-sub-pixel 110a is controlled by the combination of the first switching element 21 and the second switching element 22, and the second sub-sub-pixel 110b is controlled by the combination of the second switching element 22 and the third switching element 23.
  • the data lines S1-Sz are used to provide electrical signals for driving the sub-pixels to emit light, such as voltage signals.
  • the gate lines G1-0 to Gn-m are used to control the sub-sub-pixels of each row of sub-pixels according to a certain timing, such as turning on or off the corresponding sub-sub-pixels.
  • the first data line S1 is connected to the first sub-sub-pixel 110a, so that the first sub-sub-pixel 110a Connected.
  • the gate lines G1-1 and G1-2 are at a high level at the same time, the first data line S1 and the second sub-sub-pixel 110b are turned on, so that the second sub-sub-pixel 110b is turned on.
  • the three adjacent grid lines are grouped into one group and scanned group by group to realize the display of the entire display panel.
  • the gate lines G1-0, G1-1, and G1-2 are the first group of gate lines
  • the gate lines G3-0 (G1-2), G3-1, and G3-2 are the second group of gate lines
  • the remaining gate lines Line grouping and so on are scanned.
  • the first group of gate lines G1-0, G1-1, and G1-2 are scanned first to display the pixel units of the first row. That is, the sub-sub-pixels 110a-110b, 120a-120b, 130a-130b of the sub-pixels 110, 120, and 130 in the first row of pixel units are respectively controlled according to the timing signal.
  • the second group of gate lines G2-0, G2-1, and G2-2 are scanned, and the display of the pixel unit of the second row is performed.
  • the third group of gate lines G3-0 (G1-2), G3-1, and G3-2 are scanned to display the pixel units of the third row.
  • the fourth group of gate lines G4-0 (G2-2), G4-1, and G4-2 are scanned to display the pixel units of the fourth row. In this way, scanning is carried out group by group until the last group of raster lines, thereby completing the display of all rows of the display panel, that is, completing the display of one frame of picture.
  • the second group of gate lines G1-1 and G1-2 are scanned to display the sub-sub-pixels 110b, 120b, and 130b.
  • the third group of gate lines G1-2 (G3-0) and G3-1 are scanned to display the third row of sub-sub-pixels.
  • the fourth group of gate lines G3-1 and G3-2 are scanned to display the fourth row of sub-sub-pixels. In this way, scanning is carried out group by group until the last group of raster lines, thereby completing the display of all rows of the display panel, that is, completing the display of one frame of picture.
  • the first sub-pixel 110 there are four different display modes as follows.
  • the first display mode both the first sub-sub-pixel 110a and the second sub-sub-pixel 110b are not turned on, and the gray scale displayed by the first sub-pixel 110 is represented by R21.
  • the second display mode the first sub-sub-pixel 110a is not turned on and the second sub-sub-pixel 110b is turned on. At this time, the gray scale displayed by the first sub-pixel 110 is represented by R22.
  • the third display mode the first sub-sub-pixel 110a is turned on and the second sub-sub-pixel 110b is not turned on. At this time, the gray scale displayed by the first sub-pixel 110 is represented by R23.
  • the fourth display mode the first sub-sub-pixel 110a and the second sub-sub-pixel 110b are both turned on, and the gray scale displayed by the first sub-pixel 110 is represented by R24.
  • R24 the gray scale displayed by the first sub-pixel 110
  • R21-R24 four different display gray scales R21-R24 are realized in each sub-pixel.
  • FIG. 3 schematically shows timing signals for driving the pixel unit shown in FIG. 2.
  • the pixel units of the first odd row are driven; in stages T3 and T4, the first even row (second row) is completed.
  • the sub-pixels of all rows are sequentially driven.
  • the driving method of the pixel units in the first row of the display panel of this embodiment is schematically described below with reference to FIG. 3.
  • the first gate line G1-0 and the second gate line G1-1 are both at high level (that is, both are "1") and the third gate line G1-2 is at low level (that is, "0" ), the first data line S1 is connected to the first sub-sub-pixel 110a.
  • the second gate line G1-1 and the third gate line G1-2 are both at a high level and the first gate line G1-0 is at a low level.
  • the first data line S1 and the second sub-pixel 110b are Between conduction.
  • FIG. 4 schematically shows the layout of pixel units of a display panel according to another embodiment of the present disclosure.
  • the display panel may include a plurality of pixel units 400 (only one of which is schematically shown in FIG. 4), and each pixel unit 400 may include three sub-pixels, namely, a first sub-pixel 410 and a second sub-pixel. 420 and the third sub-pixel 430.
  • the first sub-pixel 410 may be a red sub-pixel
  • the second sub-pixel 420 may be a green sub-pixel
  • the third sub-pixel 430 may be a blue sub-pixel.
  • each sub-pixel can be divided into three sub-sub-pixels.
  • the first sub pixel 410 may include a first sub sub pixel 410 a, a second sub sub pixel 410 b, and a third sub sub pixel 410 c
  • the second sub pixel 420 may include a first sub sub pixel 420 a and a second sub sub pixel 420 b And a third sub-sub pixel 420c
  • the third sub-pixel 430 may include a first sub-sub-pixel 430a, a second sub-sub-pixel 430b, and a third sub-sub-pixel 430c.
  • the three sub-sub-pixels of each sub-pixel can be divided according to a preset area ratio.
  • the area ratio of the first sub-sub-pixel, the second sub-sub-pixel, and the third sub-sub-pixel of each sub-pixel may be 4:2:1.
  • the area ratio of the first sub-sub-pixel 410a, the second sub-sub-pixel 410b, and the third sub-sub-pixel 410c is 4:2:1.
  • FIG. 5 schematically shows a wiring diagram of a pixel unit used in the display panel shown in FIG. 4. Similar to the circuit schematic diagram of the previous embodiment shown in FIG. 2, a plurality of pixel units 400 are arranged in an array, each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes three sub-sub-pixels.
  • the display panel further includes a plurality of data lines and a plurality of groups of gate lines, each group of gate lines includes at least three gate lines, and the data lines S1-Sz and the gate lines G1-0 to Gn-m are alternately arranged. Taking the pixel unit of the display panel shown in FIG.
  • each row of pixel units is configured to be controlled by a corresponding set of gate lines
  • each column of sub-pixels is configured to be connected to a corresponding data line and configured such that Each sub-sub pixel receives a data signal from the data line under the control of each group of gate lines.
  • FIG. 5 only shows z data lines S1, S2, S3...Sz, pixel units in odd rows, and gate lines G1-0, G1-1, G1- included in odd array gate lines corresponding to pixel units in odd rows. 2.
  • G3-0, G3-1, G3-2...Gn-m Here, n is a positive odd number greater than 1, and m is an integer between 0-2.
  • each row of pixel units corresponds to a group of gate lines
  • each group of gate lines includes at least three gate lines.
  • the pixel unit 400 in the first odd-numbered row corresponds to the first group of gate lines.
  • the first group of gate lines includes three gate lines, such as a first gate line G1-0, a second gate line G1-1, and a third gate line G1-2.
  • the pixel units 400 in the second odd row correspond to the third group of gate lines.
  • the third group of gate lines includes three gate lines, such as a third gate line G3-0, a fourth gate line G3-1, and a fifth gate line G3-2.
  • each pixel unit of an even row corresponds to a group of gate lines including at least three gate lines.
  • the pixel units of the even-numbered rows and their corresponding groups of gate lines are not shown here, for example, the pixel units of the first even-numbered row (the second row) and their corresponding second group of gate lines, and the second even-numbered row (the second row).
  • two switching elements jointly control a sub-sub-pixel, and each switching element is turned on and off by a corresponding gate line.
  • the first sub-sub-pixel 410a is controlled by the combination of the first switching element 51 and the second switching element 52
  • the second sub-sub-pixel 410b is controlled by the combination of the fourth switching element 54 and the fifth switching element 55
  • the third sub-sub-pixel 410c is controlled by the combination of the second switching element 52 and the third switching element 53.
  • each column of sub-pixels is connected to a corresponding data line and receives data signals from the corresponding data line; each data line is connected to each sub-sub-pixel of each sub-pixel through a corresponding switching element.
  • the following takes the first sub-pixel 410 of the pixel unit of the first row shown in FIG. 5 as an example for exemplary description.
  • the first sub-pixel 410 may include a first sub-sub-pixel 410a, a second sub-sub-pixel 410b, and a third sub-sub-pixel 410c.
  • the first sub-sub-pixel 410a is connected to the first data line S1 through the first switching element 51 and the second switching element 52.
  • each pixel unit includes three sub-pixels, so each column of pixel units corresponds to three data lines, and each of the three data lines is respectively connected to three columns of sub-pixels in the column of pixel units.
  • the switching elements may be thin film transistors, or any other suitable switching elements.
  • the switching elements 51-55 may be thin film transistors.
  • the first switching element 51 may be a thin film transistor TFT1.
  • the first sub-pixel 410a is connected to one of the source and drain of the thin film transistor TFT1, and the gate of the thin film transistor TFT1 is connected to the first gate line G1-0.
  • the second switching element 52 may be a thin film transistor TFT2, the other of the source and drain of the thin film transistor TFT1 is connected to one of the source and drain of the thin film transistor TFT2, and the gate of the thin film transistor TFT2 is connected to the second The gate line G1-1, the other of the source and drain of the thin film transistor TFT2 is connected to the data line S1.
  • the third switching element 53 may be a thin film transistor TFT3, one of the source and drain of the thin film transistor TFT2 is also connected to one of the source and drain of the thin film transistor TFT3, and the gate of the thin film transistor TFT3 is connected to the third gate.
  • Line G1-1, and the other of the source and drain of the thin film transistor TFT3 is connected to the third sub-sub-pixel 410c.
  • the fourth switching element 54 may be a thin film transistor TFT4, and the fifth switching element 54 may be a thin film transistor TFT5.
  • the second sub-pixel 410b is connected to one of the source and drain of the thin film transistor TFT5, the gate of the thin film transistor TFT5 is connected to the third gate line G1-2, and the other of the source and drain of the thin film transistor TFT5 Connected to one of the source and drain of the thin film transistor TFT4, the gate of the thin film transistor TFT4 is connected to the first gate line G1-0, and the other of the source and drain of the thin film transistor TFT4 is connected to the data line S1.
  • two groups of gate lines corresponding to pixel units (or sub-pixels) in two adjacent odd rows share one gate line
  • two groups of gate lines corresponding to pixel units (or sub-pixels) in two adjacent even rows are shared.
  • the lines share a grid line.
  • multiple pixel units are arranged in an array and are divided into odd-numbered rows of pixel units (or sub-pixels) and even-numbered rows of pixel units (or sub-pixels).
  • the odd-numbered rows of pixel units correspond to odd-numbered gate lines
  • the even-numbered rows of pixel units correspond to even-numbered gate lines. Therefore, two adjacent odd array gate lines share one gate line, and two adjacent even array gate lines share one gate line.
  • the first group of gate lines corresponding to the pixel units 400 in the first odd row (first row) and the third group of gate lines corresponding to the pixel units in the second odd row (third row) share one gate line, that is, the first Three grid lines G1-2 (G3-0).
  • the second group of gate lines corresponding to the pixel units in the first even-numbered row (second row) and the fourth group of gate lines corresponding to the pixel units in the second even-numbered row (fourth row) share one gate line.
  • the display process of the display panel of this embodiment will be schematically described below with reference to FIG. 5.
  • the first group of gate lines G1-0, G1-1, and G1-2 are scanned first to display the sub-sub-pixels of the first row of pixel units. That is, the sub-sub-pixels 410a-410c, 420a-420c, and 430a-430c of the sub-pixels 410, 420, and 430 are respectively controlled according to the time sequence.
  • the second group of gate lines G2-0, G2-1, and G2-2 are scanned to display the sub-sub-pixels of the second row of pixel units.
  • the third group of gate lines G3-0 (G1-2), G3-1, and G3-2 are scanned to display the sub-sub-pixels of the third row of pixel units.
  • the fourth group of gate lines G4-0 (G2-2), G4-1 and G4-2 are scanned to display the sub-sub-pixels of the fourth row of pixel units. In this way, scanning is carried out group by group until the last group of raster lines, so as to complete the display of all rows of the display panel, that is, complete the display of one frame.
  • each row of pixel units is connected to a group of gate lines, and each group of gate lines includes three gate lines.
  • the sub-sub-pixels in each sub-pixel are respectively turned on or off to provide different display gray levels.
  • the embodiment of FIG. 5 controls the on and off of three different sub-sub-pixels without adding data lines and gate lines.
  • the number of controllable sub-sub-pixels is increased without increasing the data lines and gate lines.
  • the number of gate lines is reduced.
  • the first sub-pixel 410 there are 8 different display modes as follows.
  • the first display mode: the first sub-sub-pixel 410a, the second sub-sub-pixel 410b, and the third sub-sub-pixel 410c are all off, and the gray scale displayed by the first sub-pixel 410 is represented by R41.
  • the gray scale displayed by the first sub-pixel 410 is represented by R42.
  • the third display mode the first sub-sub-pixel 410a and the third sub-sub-pixel 410c are not turned on, and the second sub-sub-pixel 410b is turned on.
  • the gray scale displayed by the first sub-pixel 410 is represented by R43. Since the brightness (ie, gray scale) of the sub-pixel display is related to the area of the sub-sub-pixel connected in the sub-pixel, based on the above three display modes, the following five other display gray levels can be obtained.
  • the fourth display mode the first sub-sub-pixel 410a is not turned on, the second sub-sub-pixel 410b and the third sub-sub-pixel 410c are turned on, and the gray scale displayed by the first sub-pixel 410 is represented by R44.
  • the fifth display mode the first sub-sub-pixel 410a is turned on, the second sub-sub-pixel 410b and the third sub-sub-pixel 410c are not turned on, and the gray scale displayed by the first sub-pixel 410 is represented by R45.
  • the sixth display mode the first sub-sub-pixel 410a and the third sub-sub-pixel 410c are turned on, and the second sub-sub-pixel 410b is not turned on. At this time, the gray scale displayed by the first sub-pixel 410 is represented by R46.
  • the seventh display mode the first sub-sub-pixel 410a and the second sub-sub-pixel 410b are turned on, and the third sub-sub-pixel 410c is not turned on.
  • the gray scale displayed by the first sub-pixel 410 is represented by R47.
  • eight different display gray levels R41-R48 are realized in each sub-pixel.
  • the first sub-pixel 410, the second sub-pixel 420, and the third sub-pixel 430 of each pixel unit 400 are red, green, and blue sub-pixels, respectively.
  • FIG. 6 schematically shows a timing diagram of signals used to drive the pixel unit shown in FIG. 5.
  • the timing diagram shown in Figure 6 in the T1, T2, T3 stages, the first row of sub-pixels are driven; in the T4, T5, and T6 stages, the second row of sub-pixels are driven; in T7, T8 , T9 stage, complete the driving of the third row of sub-pixels; and in the T10, T11, T12 stages, complete the driving of the fourth row of sub-pixels.
  • the sub-pixels in all rows are driven.
  • the driving mode of the sub-pixels in the first row is schematically described below in conjunction with FIG. 6, so that those skilled in the art can understand the driving modes of the sub-pixels in other rows.
  • the first gate line G1-0 and the second gate line G1-1 are both at a high level and the third gate line G1-2 is at a low level.
  • the first data line S1 and the first sub-sub-pixel 410a are Between conduction.
  • the second gate line G1-1 and the third gate line G1-2 are both at a high level and the first gate line G1-0 is at a low level.
  • the first data line S1 and the third sub-pixel 410c are Between conduction.
  • the first gate line G1-0 and the third gate line G1-2 are both at a high level and the second gate line G1-1 is at a low level.
  • the first data line S1 and the second sub-pixel 410b are Between conduction.
  • scanning mode of progressive scanning is used as an example to describe this embodiment above, scanning modes such as interlaced scanning are also possible, that is, the scanning of pixel units (or sub-pixels) of odd rows can be the same as those of even rows. The scanning of pixel units (or sub-pixels) is performed separately.
  • the grouping mode of the gate lines connected to each row of pixel units may be different.
  • the pixel unit 400 in the first row corresponds to the first group of gate lines.
  • the first group of gate lines includes three gate lines, such as a first gate line G1-0, a second gate line G1-1, and a third gate line G1-2.
  • the pixel unit 400 in the second row corresponds to the second group of gate lines.
  • the second group of gate lines includes three gate lines, such as a third gate line G2-0, a fourth gate line G2-1, and a fifth gate line G2-2.
  • the gate lines corresponding to the pixel units 400 in other rows (or the sub-pixels included in the pixel units) can be deduced by analogy.
  • the manner in which each sub-pixel (sub-sub-pixel) is connected to the gate line and the data line is similar to the foregoing description of this embodiment, and will not be repeated here.
  • two adjacent sets of gate lines share one gate line, that is, two sets of gate lines corresponding to two adjacent rows of sub-pixels share one gate line, for example, the first set of gate lines and the second set of gate lines
  • the lines share one gate line, that is, the third gate line G1-2 (G2-0).
  • the first group, the second group... to the last group of gate lines can be respectively scanned according to the scanning sequence, so as to complete the display of the first row, the second row... to the last row of pixel units.
  • a RGB three-primary color display system is taken as an example for description.
  • the display panel according to the embodiment of the present disclosure may be used in a display system of more primary colors such as CMYK.
  • circuit connection relationship between the three sub-sub-pixels and the gate line in this embodiment is not limited to the relationship shown in FIGS. 4-6.
  • the positions of the three sub-sub-pixels can be interchanged.
  • the three sub-sub-pixels in each sub-pixel have the same primary color.
  • the first sub pixel 410 is an R sub pixel
  • the second sub pixel 420 is a G sub pixel
  • the third sub pixel 430 is a B sub pixel.
  • the first sub-sub-pixel 410a, the second sub-sub-pixel 410b, and the third sub-sub-pixel 410c of the first sub-pixel 410 are all R sub-sub-pixels; the first sub-sub-pixel 420a of the second sub-pixel 420 , The second sub-sub-pixel 420b and the third sub-sub-pixel 420c are all G sub-sub-pixels; and the first sub-sub-pixel 430a, the second sub-sub-pixel 430b and the third sub-sub-pixel 430c of the third sub-pixel 430 are all B Sub-sub pixel.
  • one of the three sub-sub-pixels in each sub-pixel is a white sub-sub-pixel.
  • the sub-sub-pixel with the smallest area among the three sub-sub-pixels is the white sub-sub-pixel.
  • the third sub-sub-pixel 410c of the first sub-pixel 410, the third sub-sub-pixel 420c of the second sub-pixel 420, and the third sub-sub-pixel 430c of the third sub-pixel 430 are White sub-pixels.
  • the above-mentioned white sub-sub-pixel is a total reflection sub-sub-pixel
  • the other sub-sub-pixels are transmission sub-sub-pixels.
  • the display panel described in the embodiment of the present disclosure may also be applicable to a situation where each row of sub-pixels corresponds to more than three gate lines. In this case, the number of sub-sub-pixels that can be individually controlled will be more than three.
  • the term “on” is not limited to charging or energizing the self-luminous pixel unit. Any means that can make the pixel unit emit light, such as adjusting the direction of the liquid crystal to make the pixel unit emit light, should be included in Within the scope of the term “on”.
  • “off” means the opposite meaning of "on”, that is, the sub-sub-pixels of the pixel unit are changed from a light-emitting state to a non-light-emitting state.
  • the embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, Any product or component with display function such as navigator.
  • the implementation of the display device can refer to the embodiment of the above-mentioned display panel, and the repetition is not repeated here.
  • the display device provided in the embodiments of the present disclosure may further include a source driver, a gate driver, and a timing controller.
  • the output terminal of the source driver is connected to the data line of the display panel and is configured to provide a data signal to the data line; the data signal is input to the sub-pixel or sub-sub-pixel connected to the data line.
  • the gate driver is connected to the gate line of the display panel and is configured to provide a scan signal to the gate line; when the gate line receives the scan signal, the switching element of a certain row of sub-pixels connected to the gate line is turned on, so that Receive data signal.
  • the timing controller is connected to the source driver and the gate driver; the timing controller generates a gate control signal and a source control signal; the source control signal is output to the source driver, and the gate controls The signal is output to the gate driver, thereby controlling the operation of the source driver and the gate driver.
  • Embodiments of the present disclosure provide a display panel and a display device including the display panel.
  • each pixel unit includes a plurality of sub-pixels, each sub-pixel includes at least two sub-sub-pixels, each row of sub-pixels is configured to be controlled by a corresponding set of gate lines, and each column of sub-pixels is configured such that The at least two sub-sub-pixels receive a data signal from a corresponding data line under the control of each group of gate lines.
  • each sub-pixel includes at least three sub-sub-pixels
  • the sub-sub-pixel with the smallest area can be configured as a total reflection sub-sub-pixel (white sub-sub-pixel).
  • the display can be displayed at a low refresh rate. In the mode, the display brightness of the screen is improved, thereby improving the user experience.

Abstract

一种显示面板，包括多条数据线、多组栅线和多个像素单元（100）；每组栅线包括至少三条栅线；多个像素单元（100）呈阵列排布，每个像素单元（100）包括多个亚像素，并且每个亚像素包括至少两个子亚像素；每行亚像素配置成由相应的一组栅线控制，并且每列亚像素配置成使得至少两个子亚像素在各组栅线的控制下从相应的一条数据线接收数据信号。还公开了包括显示面板的显示装置。

Description

显示面板和显示装置 技术领域
本公开的实施例涉及一种显示面板和包括该显示面板的显示装置。
背景技术
诸如智能手表的可穿戴设备正逐步被消费者所青睐。通过使用半透半反技术，智能可穿戴设备可以实现在强光下反射、暗光下透射的功能。这降低了设备的功耗，并且提高了续航时间。此外，在强光下反射的工作模式提高了可穿戴设备在强光下的可适度，由此提高了消费者的体验性。
发明内容
在一方面，本公开实施例提供了一种显示面板，包括：多条数据线；多组栅线，其中每组栅线包括至少三条栅线；以及多个像素单元，其中所述多个像素单元呈阵列排布，每个像素单元包括多个亚像素，并且每个亚像素包括至少两个子亚像素，其中每行亚像素配置成由相应的一组栅线控制，并且每列亚像素配置成使得所述至少两个子亚像素在各组栅线的控制下从相应的一条数据线接收数据信号。
在一个或多个实施例中，与相邻两行亚像素对应的两组栅线共用一条栅线。
在一个或多个实施例中，所述多组栅线包括与奇数行像素单元对应的奇数组栅线以及与偶数行像素单元对应的偶数组栅线，以及其中相邻两个奇数组栅线共用一条栅线，并且相邻两个偶数组栅线共用一条栅线。
在一个或多个实施例中，对于每个亚像素，所述显示面板还包括多个开关元件，所述多个开关元件中的每个开关元件由相应的一条栅线控制通断。
在一个或多个实施例中，每个亚像素中的每个子亚像素通过所述多个开关元件中的两个开关连接到相应的一条数据线。
在一个或多个实施例中，每个亚像素包括第一子亚像素和第二子亚像素，每组栅线包括第一栅线、第二栅线和第三栅线，并且所述多个开关元件包括第一开关元件、第二开关元件和第三开关元件。
在一个或多个实施例中，所述第一栅线控制所述第一开关的通断，所述第二栅线控制所述第二开关的通断，所述第三栅线控制所述第三开关的通断。
在一个或多个实施例中，对于每个亚像素，第一子亚像素通过第一开关元件和第二开关元件连接到第一数据线，第二子亚像素通过第三开关元件和第二开关元件连接到第一数据线。
在一个或多个实施例中，所述第一子亚像素和所述第二子亚像素的面积比例为2:1。
在一个或多个实施例中，每个亚像素包括第一子亚像素、第二子亚像素和第三子亚像素，每组栅线包括第一栅线、第二栅线和第三栅线，并且所述多个开关元件包括第一开关元件、第二开关元件、第三开关元件、第四开关元件和第五开关元件。
在一个或多个实施例中，所述第一栅线控制所述第一开关和所述第四开关的通断，所述第二栅线控制所述第二开关的通断，所述第三栅线控制所述第三开关和所述第五开关的通断。
在一个或多个实施例中，对于每个亚像素，第一子亚像素通过第一开关元件和第二开关元件连接到第一数据线，第二子亚像素通过第五开关元件和第四开关元件连接到第一数据线，并且第三子亚像素通过第三开关元件和第二开关元件连接到第一数据线。
在一个或多个实施例中，第一子亚像素、第二子亚像素和第三子亚像素的面积比例为4:2:1。
在一个或多个实施例中，每个亚像素的第一子亚像素、第二子亚像素和第三子亚像素具有相同的基色。
在一个或多个实施例中，每个亚像素的第三子亚像素为白色子亚像素。
在一个或多个实施例中，所述白色子亚像素为全反射子亚像素。
在一个或多个实施例中，所述开关元件为薄膜晶体管。
在另一方面，本公开实施例还提供了一种显示装置，包括如上所述的显示面板。
附图说明
为了更清楚地说明本公开的实施例或现有技术中的技术方案，下面将对 实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。附图中：
图1是根据本公开一实施例的显示面板的像素单元的示意图；
图2是用于图1所示像素单元的布线示意图；
图3是用于驱动图2所示像素单元的信号的时序图；
图4是根据本公开另一实施例的显示面板的像素单元的示意图；
图5是用于图4所示像素单元的布线示意图；以及
图6是用于驱动图4所示像素单元的信号的时序图。
附图仅是示意性的，且不一定按照比例绘制。贯穿所有附图，相同的附图标记指示相同或相似的部分。
具体实施方式
为使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图对本发明的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅是本发明的一部分示例性实施例，而不是全部的实施例。基于所描述的本发明的示例性实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
受限于尺寸和功耗，可穿戴设备的驱动器集成电路(Driver IC)通常只能选用串行外设接口(Serial Peripheral Interface,SPI)信号来进行传输。这种信号为高电平或低电平，即0或1，因此无法通过直接控制数据线中控制信号的高 低的方式来实现不同显示灰阶。
作为一种解决方案，本公开一实施例提供了一种显示面板，其像素单元中的亚像素被分割为两个子亚像素，并且子亚像素分别被接通或切断以实现不同显示灰阶。图1示意性示出一种采用这种解决方案的显示面板的像素单元的布局。如图1所示，该显示面板可包括多个像素单元100(图1仅示例性示出其中一个)。每个像素单元100可包括三个亚像素，例如第一亚像素110、第二亚像素120和第三亚像素130。以RBG三基色显示系统为例，第一亚像素110为红色亚像素，第二亚像素120为绿色亚像素，并且第三亚像素130为蓝色亚像素。在图1的布局中，每个亚像素被分割为两个子亚像素。例如，第一亚像素110包括第一子亚像素110a和第二子亚像素110b，第二亚像素120包括第一子亚像素120a和第二子亚像素120b，并且第三亚像素130包括第一子亚像素130a和第二子亚像素130b。每个亚像素的两个子亚像素按照预设面积比例分割。通常，第一子亚像素和第二子亚像素的面积比例为2:1。以第一亚像素110为例，第一子亚像素110a与第二子亚像素110b的面积比例为2:1。
图2示意性示出用于图1所示像素单元的布线图。如图2所示，多个像素单元100呈阵列排布。该显示面板还包括交错布置的多条数据线和多条栅线。图2仅仅示出奇数行的像素单元，z条数据线S1、S2、S3…Sz，以及奇数条栅线G1-0、G1-1、G1-2、G3-0、G3-1、G3-2…Gn-m。此处，n为大于1的正奇数，m为0-2之间的整数。
如图2所示，每行亚像素对应一组栅线，每组栅线包括三条栅线。第一奇数行的像素单元100对应第一组栅线。该第一组栅线包括第一栅线G1-0、第二栅线G1-1和第三栅线G1-2。第二奇数行的像素单元100对应第三组栅线。该第三组栅线包括第三栅线G3-0、第四栅线G3-1和第五栅线G3-2。此处未示出偶数行的像素单元及其对应的各组栅线，例如，第一偶数行的像素单元及其对应的第二组栅线，以及第二偶数行的像素单元及其对应的第四组栅线。相邻两个奇数组栅线可以共用一条栅线，并且相邻两个偶数组栅线可以共用一条栅线，例如，G1-2和G3-0可以为同一栅线，G4-0和G2-2可以为同一栅线。
在本实施例中，三个亚像素中的每个子亚像素分别接通或切断以提供不同显示灰阶。以第一亚像素110为例，第一子亚像素110a通过第一开关元件 21和第二开关元件22连接到数据线S1，其中第一栅线G1-0控制第一开关元件21的通断，第二栅线G1-1控制第二开关元件22的通断；第二子亚像素110b通过第三开关元件23和第二开关元件22连接到数据线S1，其中第三栅线G1-2控制第三开关元件23的通断，第二栅线G1-1控制第二开关元件22的通断。即：通过两个开关元件共同控制一个子亚像素。第一子亚像素110a由第一开关元件21和第二开关元件22组合控制，并且第二子亚像素110b由第二开关元件22和第三开关元件23组合控制。数据线S1-Sz用于提供驱动子亚像素发光的电信号，例如电压信号。栅线G1-0至Gn-m用于按照一定时序控制每一行亚像素的子亚像素，例如接通或切断相应的子亚像素。例如，栅线G1-0和G1-1同时为高电平(即均为“1”)时，第一数据线S1与第一子亚像素110a之间导通，使得第一子亚像素110a接通。栅线G1-1和G1-2同时为高电平时，第一数据线S1与第二子亚像素110b之间导通，使得第二子亚像素110b接通。将相邻三条栅线分为一组，逐组进行扫描，来实现整个显示面板的显示。例如，栅线G1-0、G1-1和G1-2为第一组栅线，栅线G3-0(G1-2)、G3-1和G3-2为第二组栅线，并且其余栅线分组以此类推。在显示时，首先扫描第一组栅线G1-0、G1-1和G1-2，进行第一行像素单元的显示。即，按照时序信号分别控制第一行像素单元中的亚像素110、120、130的子亚像素110a-110b、120a-120b、130a-130b。接着，扫描第二组栅线G2-0、G2-1和G2-2，进行第二行像素单元的显示。接着，扫描第三组栅线G3-0(G1-2)、G3-1和G3-2，进行第三行像素单元的显示。再接着，扫描第四组栅线G4-0(G2-2)、G4-1和G4-2，进行第四行像素单元的显示。如此逐组进行扫描，直至最后一组栅线，从而完成显示面板的所有行的显示，即，完成一帧画面的显示。
应当理解，根据本实施例，也可能的是，将相邻两条栅线分为一组，逐组进行扫描，来实现整个显示面板的显示，其中两条栅线中的第二条重复扫描一次。例如，以栅线G1-0和G1-1为第一组进行扫描，以栅线G1-1和G1-2为第二组进行扫描，以栅线G1-2(G3-0)和G3-1为第三组进行扫描，并且其余栅线的分组和扫描以此类推。在这种情况下，在显示时，首先扫描第一组栅线G1-0、G1-1，显示子亚像素110a、120a、130a。接着，扫描第二组栅线G1-1、G1-2，显示子亚像素110b、120b、130b。接着，扫描第三组栅线G1-2(G3-0)、G3-1，进行第三行子亚像素的显示。再接着，扫描第四组栅 线G3-1、G3-2，进行第四行子亚像素的显示。如此逐组进行扫描，直至最后一组栅线，从而完成显示面板的所有行的显示，即，完成一帧画面的显示。
在本实施例中，例如，对于第一亚像素110而言，共有下列四种不同的显示模式。第一种显示模式：第一子亚像素110a和第二子亚像素110b均未接通，此时第一亚像素110显示的灰阶用R21表示。第二种显示模式：第一子亚像素110a未接通并且第二子亚像素110b接通，此时第一亚像素110显示的灰阶用R22表示。第三种显示模式：第一子亚像素110a接通并且第二子亚像素110b未接通，此时第一亚像素110显示的灰阶用R23表示。第四种显示模式：第一子亚像素110a和第二子亚像素110b均接通，此时第一亚像素110显示的灰阶用R24表示。由此，在每个亚像素中实现了四种不同的显示灰阶R21-R24。例如，在RGB显示系统中，每个像素单元100包括R、G、B三个不同的亚像素110、120、130。通过采用上述像素布局，每个像素单元提供4×4×4＝64种颜色的显示。
图3示意性地示出用于驱动图2所示像素单元的时序信号。在图3所示的时序图中，在T1、T2阶段，完成对第一奇数行(第一行)的像素单元的驱动；在T3、T4阶段，完成对第一偶数行(第二行)的像素单元的驱动；在T5、T6阶段，完成对第二奇数行(第三行)亚像素的驱动；并且在T7、T8阶段，完成对第二偶数行(第四行)亚像素的驱动。在后续时间段，依次完成对所有行的亚像素的驱动。
下面结合图3示意性地描述本实施例的显示面板中第一行的像素单元的驱动方式。在T1阶段，第一栅线G1-0和第二栅线G1-1同时为高电平(即均为“1”)并且第三栅线G1-2为低电平(即为“0”)，第一数据线S1与第一子亚像素110a之间导通。在T2阶段，第二栅线G1-1和第三栅线G1-2同时为高电平并且第一栅线G1-0为低电平，第一数据线S1与第二子亚像素110b之间导通。通过设置在T1、T2阶段施加到第一栅线G1-0和第二栅线G1-1上的驱动信号(即高电平或低电平)，在每个亚像素中实现了4种不同的显示灰阶，如上文所述。
图4示意性示出根据本公开另一实施例的显示面板的像素单元的布局。本实施例中，显示面板可包括多个像素单元400(图4中仅示意性示出其中一个)，每个像素单元400可包括三个亚像素，即第一亚像素410、第二亚像素420和第三亚像素430。以RBG三基色显示系统为例，第一亚像素410可为 红色亚像素，第二亚像素420可为绿色亚像素，并且第三亚像素430可为蓝色亚像素。
与图1-图3所示实施例不同的是，在图4的实施例中，每个亚像素可被分割为三个子亚像素。例如，第一亚像素410可包括第一子亚像素410a、第二子亚像素410b和第三子亚像素410c；第二亚像素420可包括第一子亚像素420a、第二子亚像素420b和第三子亚像素420c；并且第三亚像素430可包括第一子亚像素430a、第二子亚像素430b和第三子亚像素430c。
在本实施例中，每个亚像素的三个子亚像素可按照预设面积比例分割。例如，每个亚像素的第一子亚像素、第二子亚像素和第三子亚像素的面积比例可为4:2:1。例如，以图4所示像素单元的第一亚像素410为例，第一子亚像素410a、第二子亚像素410b和第三子亚像素410c的面积比例为4:2:1。
图5示意性示出用于图4所示显示面板的像素单元的布线图。与图2所示前一实施例的电路示意图相似，多个像素单元400呈阵列排布，每个像素单元包括多个亚像素，并且每个亚像素包括三个子亚像素。该显示面板还包括多条数据线和多组栅线，每组栅线包括至少三条栅线，并且数据线S1-Sz与栅线G1-0至Gn-m交错布置。以图4所示显示面板的像素单元为例，每行像素单元(或亚像素)配置成由相应的一组栅线控制，每列亚像素配置成连接到相应的一条数据线并且配置成使得各子亚像素在各组栅线的控制下从该数据线接收数据信号。图5仅仅示出z条数据线S1、S2、S3…Sz，奇数行的像素单元，以及与奇数行像素单元对应的奇数组栅线所包含的栅线G1-0、G1-1、G1-2、G3-0、G3-1、G3-2…Gn-m。此处，n为大于1的正奇数，m为0-2之间的整数。
根据本实施例，每一行的像素单元对应一组栅线，并且每组栅线包括至少三条栅线。例如，第一奇数行的像素单元400(或者该像素单元包括的亚像素)对应第一组栅线。该第一组栅线包括三条栅线，例如第一栅线G1-0、第二栅线G1-1和第三栅线G1-2。第二奇数行的像素单元400对应第三组栅线。该第三组栅线包括三条栅线，例如第三栅线G3-0、第四栅线G3-1和第五栅线G3-2。类似地，每一偶数行的像素单元对应包括至少三条栅线的一组栅线。此处未示出偶数行的像素单元及其对应的各组栅线，例如，第一偶数行(第二行)的像素单元及其对应的第二组栅线，以及第二偶数行(第四行)的像素单元及其对应的第四组栅线。
在本实施例中，两个开关元件共同控制一个子亚像素，每个开关元件由对应的一条栅线控制通断。例如，第一子亚像素410a由第一开关元件51和第二开关元件52组合控制，第二子亚像素410b由第四开关元件54和第五开关元件55组合控制，并且第三子亚像素410c由第二开关元件52和第三开关元件53组合控制。
在本实施例中，每列亚像素连接到相应一条数据线，并且从相应数据线接收数据信号；每条数据线通过相应的开关元件连接到每个亚像素的各个子亚像素。下面以图5所示的第一行像素单元的第一亚像素410为例进行示例性说明。第一亚像素410可包括第一子亚像素410a、第二子亚像素410b和第三子亚像素410c。第一子亚像素410a通过第一开关元件51和第二开关元件52连接到第一数据线S1。第二子亚像素410b通过第五开关元件55和第四开关元件54连接到第一数据线S1。第三子亚像素410c通过第三开关元件53和第二开关元件52连接到第一数据线S1。在本公开实施例中，每个像素单元包括三个亚像素，因此每列像素单元对应三条数据线，这三条数据线中的每一条分别连接到该列像素单元中的三列亚像素。
本实施例的一些示例中，开关元件(例如图2中的开关元件21-23以及图5中的开关元件51-55)可以为薄膜晶体管，或任何其他合适的开关元件。
例如，开关元件51-55可以为薄膜晶体管。第一开关元件51可以为薄膜晶体管TFT1。第一子亚像素410a连接到薄膜晶体管TFT1的源极和漏极中的一个，薄膜晶体管TFT1的栅极连接到第一栅线G1-0。并且第二开关元件52可以为薄膜晶体管TFT2，薄膜晶体管TFT1的源极和漏极中的另一个连接到薄膜晶体管TFT2的源极和漏极中的一个，薄膜晶体管TFT2的栅极连接到第二栅线G1-1，薄膜晶体管TFT2的源极和漏极中的另一个连接到数据线S1。第三开关元件53可以为薄膜晶体管TFT3，薄膜晶体管TFT2的源极和漏极中的一个还连接到薄膜晶体管TFT3的源极和漏极中的一个，薄膜晶体管TFT3的栅极连接到第三栅线G1-1，并且薄膜晶体管TFT3的源极和漏极中的另一个连接到第三子亚像素410c。第四开关元件54可以为薄膜晶体管TFT4，第五开关元件54可以为薄膜晶体管TFT5。第二子亚像素410b连接到薄膜晶体管TFT5的源极和漏极中的一个，薄膜晶体管TFT5的栅极连接到第三栅线G1-2，薄膜晶体管TFT5的源极和漏极中的另一个连接到薄膜晶体管TFT4的源极和漏极中的一个，薄膜晶体管TFT4的栅极连接到第一栅线G1-0，薄 膜晶体管TFT4的源极和漏极中的另一个连接到数据线S1。
本实施例中，相邻两个奇数行的像素单元(或者亚像素)对应的两组栅线共用一条栅线，并且相邻两个偶数行的像素单元(或者亚像素)对应的两组栅线共用一条栅线。以图5所示情形为例，多个像素单元呈阵列排布，并且划分为奇数行像素单元(或者亚像素)和偶数行像素单元(或者亚像素)。奇数行像素单元对应于奇数组栅线，并且偶数行像素单元对应于偶数组栅线。因此，相邻两个奇数组栅线共用一条栅线，并且相邻两个偶数组栅线共用一条栅线。例如，第一奇数行(第一行)的像素单元400对应的第一组栅线和第二奇数行(第三行)的像素单元对应的第三组栅线共用一条栅线，即，第三栅线G1-2(G3-0)。类似地，第一偶数行(第二行)的像素单元对应的第二组栅线和第二偶数行(第四行)的像素单元对应的第四组栅线共用一条栅线。
下面继续参考图5示意性描述本实施例的显示面板的显示过程。在显示时，首先扫描第一组栅线G1-0、G1-1和G1-2，以进行第一行像素单元的子亚像素的显示。即，按照时序分别控制亚像素410、420、430的子亚像素410a-410c、420a-420c、430a-430c。接着，扫描第二组栅线G2-0、G2-1和G2-2，以进行第二行像素单元的子亚像素的显示。接着，扫描第三组栅线G3-0(G1-2)、G3-1和G3-2，进行第三行像素单元的子亚像素的显示。再接着，扫描第四组栅线G4-0(G2-2)、G4-1和G4-2，进行第四行像素单元的子亚像素的显示。如此逐组进行扫描，直至最后一组栅线，从而完成显示面板的所有行的显示，即：完成一帧画面的显示。
在本实施例中，每行像素单元(或亚像素)连接到一组栅线，并且每组栅线包括三条栅线。每个亚像素中的子亚像素分别接通或切断以提供不同显示灰阶。与图2所示实施例相比，图5的实施例在不增加数据线和栅线的情况下控制三种不同子亚像素的接通和切断。通过这种设计，在不增加数据线和栅线情况下增加了可以控制的子亚像素的数量。并且，与常规的每条栅线分别对应控制每个子亚像素的设计相比、减少了栅线的数目。
本实施例中，对于第一亚像素410而言，共有下列8种不同的显示模式。第一种显示模式：第一子亚像素410a、第二子亚像素410b和第三子亚像素410c均未接通，此时第一亚像素410显示的灰阶用R41表示。第二种显示模式：第一子亚像素410a和第二子亚像素410b未接通，第三子亚像素410c接通，此时第一亚像素410显示的灰阶用R42表示。第三种显示模式：第一子 亚像素410a和第三子亚像素410c未接通，第二子亚像素410b接通，此时第一亚像素410显示的灰阶用R43表示。由于亚像素显示的亮暗(即灰阶)与亚像素中接通的子亚像素的面积有关，基于上述三种显示模式，可以得到以下另外五种的显示灰阶。第四种显示模式：第一子亚像素410a未接通，第二子亚像素410b和第三子亚像素410c接通，此时第一亚像素410显示的灰阶用R44表示。第五种显示模式：第一子亚像素410a接通，第二子亚像素410b和第三子亚像素410c未接通，此时第一亚像素410显示的灰阶用R45表示。第六种显示模式：第一子亚像素410a和第三子亚像素410c接通，第二子亚像素410b未接通，此时第一亚像素410显示的灰阶用R46表示。第七种显示模式：第一子亚像素410a和第二子亚像素410b接通，第三子亚像素410c未接通，此时第一亚像素410显示的灰阶用R47表示。第八种显示模式：第一子亚像素410a、第二子亚像素410b和第三子亚像素410c均接通，此时第一亚像素410显示的灰阶用R48表示。由此，在每个亚像素中实现了八种不同的显示灰阶R41-R48。
本实施例中，对于诸如RGB三基色的显示系统，每个像素单元400的第一亚像素410、第二亚像素420和第三亚像素430分别为红色、绿色、蓝色亚像素。这种情况下，可以提供8×8×8＝512种颜色的显示。这提高了所显示的灰阶数量和颜色数量。藉此，显示面板的显示颜色更加丰富，进一步提高了用户的体验效果。
图6示意性地示出用于驱动图5所示像素单元的信号的时序图。在图6所示的时序图中，在T1、T2、T3阶段，完成对第一行亚像素的驱动；在T4、T5、T6阶段，完成对第二行亚像素的驱动；在T7、T8、T9阶段，完成对第三行亚像素的驱动；并且在T10、T11、T12阶段，完成对第四行亚像素的驱动。以此类推，通过对相应栅线施加驱动信号，完成对所有行的亚像素的驱动。
下面结合图6示意性描述第一行亚像素的驱动方式，本领域技术人员由此将可以理解其他各行亚像素的驱动方式。在T1阶段，第一栅线G1-0和第二栅线G1-1同时为高电平并且第三栅线G1-2为低电平，第一数据线S1与第一子亚像素410a之间导通。在T2阶段，第二栅线G1-1和第三栅线G1-2同时为高电平并且第一栅线G1-0为低电平，第一数据线S1与第三子亚像素410c之间导通。在T3阶段，第一栅线G1-0和第三栅线G1-2同时为高电平 并且第二栅线G1-1为低电平，第一数据线S1与第二子亚像素410b之间导通。通过设置在T1、T2、T3阶段施加到栅线G1-0、G1-1和G1-2上的驱动信号(即高电平或低电平)，在每个亚像素中实现了8种不同的显示灰阶，如上文所述。
应当理解，尽管上文以逐行扫描的扫描模式为例描述了本实施例，隔行扫描等扫描模式也是可能的，即，对奇数行的像素单元(或亚像素)的扫描可与偶数行的像素单元(或亚像素)的扫描分开进行。
应当理解，在本实施例的一些示例中，在采用不同的扫描模式的情况下，每行像素单元(或亚像素)所连接的栅线的分组的模式可能是不同的。例如，第一行的像素单元400(或者亚像素单元包括的亚像素)对应第一组栅线。该第一组栅线包括三条栅线，例如第一栅线G1-0、第二栅线G1-1和第三栅线G1-2。第二行的像素单元400(或者该像素单元包括的亚像素)对应第二组栅线。该第二组栅线包括三条栅线，例如第三栅线G2-0、第四栅线G2-1和第五栅线G2-2。其他行的像素单元400(或者该像素单元包括的亚像素)对应的栅线以此类推。各个亚像素(子亚像素)与栅线以及数据线连接的方式与本实施例的前述描述类似，在此不再赘述。在这种情况下，相邻的两组栅线共用一条栅线，即：与相邻两行亚像素对应的两组栅线共用一条栅线，例如，第一组栅线与第二组栅线共用一条栅线，即，第三栅线G1-2(G2-0)。相应地，在显示时，可以按照扫描时序分别扫描第一组、第二组……直至最后一组栅线，从而完成第一行、第二行……直至最后一行像素单元的显示。
在本实施例中，以RGB三基色显示系统为例进行描述。然而，应指出的是，根据本公开的实施例的显示面板可以用于诸如CMYK的更多基色的显示系统。
应注意的是，本实施例中三种子亚像素与栅线的电路连接关系并不限于图4-6中所示的关系。例如，三种子亚像素的位置可以互换。
在本实施例的一些示例中，每个亚像素中的三个子亚像素具有相同的基色。例如，以图5所示像素单元为例，第一亚像素410为R亚像素，第二亚像素420为G亚像素，并且第三亚像素430为B亚像素。这种情况下，第一亚像素410的第一子亚像素410a、第二子亚像素410b和第三子亚像素410c均为R子亚像素；第二亚像素420的第一子亚像素420a、第二子亚像素420b和第三子亚像素420c均为G子亚像素；并且第三亚像素430的第一子亚像 素430a、第二子亚像素430b和第三子亚像素430c均为B子亚像素。
在本实施例的一些示例中，每个亚像素中的三个子亚像素中的一个子亚像素为白色子亚像素。在一些实施例中，三个子亚像素中面积最小的子亚像素为白色子亚像素。例如，在图5所示实施例中，第一亚像素410的第三子亚像素410c，第二亚像素420的第三子亚像素420c，以及第三亚像素430的第三子亚像素430c为白色子亚像素。
在本实施例的一些示例中，在每个亚像素中，上述白色子亚像素为全反射子亚像素，并且其它子亚像素为透射子亚像素。当显示面板在例如1HZ的低刷新率下操作时，后置的背光被切断，显示面板的透射部分(即每个亚像素中除白色子亚像素之外的其它子亚像素)无显示。此时，由于存在外部环境光，显示面板的反射部分(即全反射子亚像素)可以通过反射环境光的反射进行显示。藉此，当显示面板在低刷新率下工作时，反射率提高，进而使得显示面板在低刷新率时的显示亮度提高。
本公开的实施例中描述的显示面板还可以适用于每行亚像素分别对应多于三条栅线的情形。在这种情况下，可以单独控制的子亚像素的数量将多于三个。
在本公开的实施例中，术语“接通”不限于对自发光的像素单元进行充电或通电，任何能够使像素单元发光的手段，例如通过调整液晶的方向使像素单元发光，都应该包括在术语“接通”的范围内。相应地，“切断”则表示与“接通”相反的含义，即：使像素单元的子亚像素由发光的状态转变为不发光的状态。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
应当理解的是，除了在上述各实施例中描述的显示面板之外，本公开实施例提供的该显示装置还可以包括源极驱动器、栅极驱动器和时序控制器。例如，该源极驱动器的输出端连接到显示面板的数据线，并且配置成提供数据信号到数据线；该数据信号被输入到与数据线连接的亚像素或者子亚像素。例如，该栅极驱动器连接到显示面板的栅线，并且配置成提供扫描信号到栅线；当栅线接收到扫描信号后，与栅线连接的某一行亚像素的开关元件接通， 从而可以接收数据信号。例如，该时序控制器连接到该源极驱动器和该栅极驱动器；该时序控制器生成栅极控制信号和源极控制信号；该源极控制信号输出到该源极驱动器，并且该栅极控制信号输出到该栅极驱动器，由此控制该源极驱动器和该栅极驱动器的工作。
本公开的实施例提供了一种显示面板以及包括该显示面板的显示装置。根据本公开的技术方案，每个像素单元包括多个亚像素，每个亚像素包括至少两个子亚像素，每行亚像素配置成由相应的一组栅线控制，每列亚像素配置成使得所述至少两个子亚像素在各组栅线的控制下从相应的一条数据线接收数据信号。藉此，在与每条栅线分别对应控制每个子亚像素的常规设计相比减少了栅线的数目的情况下、增加了显示面板的显示的灰阶和颜色数量。此外，当每个亚像素包括至少三个子亚像素时，面积最小的一个子亚像素可配置成全反射子亚像素(白色子亚像素)，通过全反射子亚像素的设计，在低刷新率显示模式下提高了屏幕的显示亮度，从而提高了用户的体验。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2019年5月17日递交的中国专利申请第201910412211.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种显示面板，包括：
    多条数据线；
    多组栅线，其中每组栅线包括至少三条栅线；以及
    多个像素单元，其中所述多个像素单元呈阵列排布，每个像素单元包括多个亚像素，并且每个亚像素包括至少两个子亚像素，
    其中每行亚像素配置成由相应的一组栅线控制，并且每列亚像素配置成使得所述至少两个子亚像素在各组栅线的控制下从相应的一条数据线接收数据信号。
  2. 根据权利要求1所述的显示面板，其中，与相邻两行亚像素对应的两组栅线共用一条栅线。
  3. 根据权利要求1所述的显示面板，其中，所述多组栅线包括与奇数行像素单元对应的奇数组栅线以及与偶数行像素单元对应的偶数组栅线，以及
    其中相邻两个奇数组栅线共用一条栅线，并且相邻两个偶数组栅线共用一条栅线。
  4. 根据前述权利要求1-3中的任意一项所述的显示面板，其中，对于每个亚像素，所述显示面板还包括多个开关元件，所述多个开关元件中的每个开关元件由相应的一条栅线控制通断。
  5. 根据权利要求4所述的显示面板，其中，每个亚像素中的每个子亚像素通过所述多个开关元件中的两个开关连接到相应的一条数据线。
  6. 根据权利要求5所述的显示面板，其中，每个亚像素包括第一子亚像素和第二子亚像素；每组栅线包括第一栅线、第二栅线和第三栅线；并且所述多个开关元件包括第一开关元件、第二开关元件、第三开关元件。
  7. 根据权利要求6所述的显示面板，其中，所述第一栅线控制所述第一 开关的通断，所述第二栅线控制所述第二开关的通断，所述第三栅线控制所述第三开关的通断。
  8. 根据权利要求6所述的显示面板，其中，对于每个亚像素，第一子亚像素通过第一开关元件和第二开关元件连接到第一数据线，第二子亚像素通过第三开关元件和第二开关元件连接到第一数据线。
  9. 根据前述权利要求6-8中的任意一项所述的显示面板，其中，所述第一子亚像素和所述第二子亚像素的面积比例为2:1。
  10. 根据权利要求5所述的显示面板，其中，每个亚像素包括第一子亚像素、第二子亚像素和第三子亚像素；每组栅线包括第一栅线、第二栅线和第三栅线；并且所述多个开关元件包括第一开关元件、第二开关元件、第三开关元件、第四开关元件和第五开关元件。
  11. 根据权利要求10所述的显示面板，其中，所述第一栅线控制所述第一开关和所述第四开关的通断，所述第二栅线控制所述第二开关的通断，所述第三栅线控制所述第三开关和所述第五开关的通断。
  12. 根据权利要求10所述的显示面板，其中，对于每个亚像素，第一子亚像素通过第一开关元件和第二开关元件连接到第一数据线，第二子亚像素通过第五开关元件和第四开关元件连接到第一数据线，并且第三子亚像素通过第三开关元件和第二开关元件连接到第一数据线。
  13. 根据前述权利要求10-12中的任意一项所述的显示面板，其中第一子亚像素、第二子亚像素和第三子亚像素的面积比例为4:2:1。
  14. 根据权利要求10-13中的任意一项所述的显示面板，其中每个亚像素的第一子亚像素、第二子亚像素和第三子亚像素具有相同的基色。
  15. 根据权利要求10-13中的任意一项所述的显示面板，其中每个亚像 素的第三子亚像素为白色子亚像素。
  16. 根据权利要求15所述的显示面板，其中所述白色子亚像素为全反射子亚像素。
  17. 根据权利要求4所述的显示面板，其中所述开关元件为薄膜晶体管。
  18. 一种显示装置，包括根据权利要求1-17中的任意一项所述的显示面板。
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