WO2020225896A1 - Circuit redresseur, circuit de synthèse d'alimentation électrique cc et circuit redresseur pleine onde - Google Patents

Circuit redresseur, circuit de synthèse d'alimentation électrique cc et circuit redresseur pleine onde Download PDF

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Publication number
WO2020225896A1
WO2020225896A1 PCT/JP2019/018513 JP2019018513W WO2020225896A1 WO 2020225896 A1 WO2020225896 A1 WO 2020225896A1 JP 2019018513 W JP2019018513 W JP 2019018513W WO 2020225896 A1 WO2020225896 A1 WO 2020225896A1
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Prior art keywords
terminal
transistor element
rectifier circuit
resistor
channel mosfet
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PCT/JP2019/018513
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English (en)
Japanese (ja)
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中田　和宏
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三菱電機株式会社
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Priority to PCT/JP2019/018513 priority Critical patent/WO2020225896A1/fr
Priority to DE112019007166.1T priority patent/DE112019007166T5/de
Priority to JP2021513493A priority patent/JP6896203B2/ja
Publication of WO2020225896A1 publication Critical patent/WO2020225896A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

Definitions

  • the present invention relates to a rectifier circuit, a DC power supply synthesis circuit, and a full-wave rectifier circuit.
  • each DC power supply should prevent current from flowing back from one of the multiple DC power supplies to another.
  • a reverse current blocking circuit using a MOSFET Metal-Oxide-Semiconductor Field-Effective Transistor is connected between the DC power supply and the load (see, for example, Patent Document 1).
  • the reverse current blocking circuit described in Patent Document 1 has a bipolar transistor for turning off the MOSFET when a reverse current is generated.
  • This reverse current blocking circuit has a problem that the reverse current cannot be blocked unless the potential difference between the input and output is constantly equal to or higher than the voltage between the base and emitter of the bipolar transistor (usually about 0.7 V).
  • the present invention has been made to solve the above-mentioned problems, and prevents reverse current even when the potential difference between input and output is extremely low (for example, 200 mV) as compared with the conventional case (for example, 0.7 V).
  • the purpose is.
  • the rectifying circuit according to the present invention includes a P-channel MOSFET element, a first PNP bipolar transistor element, a second PNP bipolar transistor element, a third transistor element and a fourth transistor element having opposite polarities, a first resistor, and the like. It includes a second resistor, a third resistor, a fourth resistor, an input terminal, and an output terminal, and the connection point between the drain terminal of the P-channel MOSFET element and one terminal of the first resistor is the input terminal.
  • the first PNP bipolar transistor element constitutes an equivalent diode element, the anode terminal of the equivalent diode element and the other terminal of the first resistor are connected, and the cathode terminal of the equivalent diode element and the base of the second PNP bipolar transistor element.
  • the terminal and one terminal of the second resistor are connected, the connection point between the other terminal of the second resistor, one terminal of the third resistor and the first terminal of the third transistor element is connected to the ground, and the third terminal is connected.
  • the other terminal of the resistor, the collector terminal of the second PNP bipolar transistor element, the third terminal of the third transistor element, the third terminal of the fourth transistor element, and one terminal of the fourth resistor are connected to form the third transistor element.
  • the second terminal, the second terminal of the fourth transistor element, the other terminal of the fourth resistor, and the gate terminal of the P channel MOSFET element are connected, and the emitter terminal of the second PNP bipolar transistor element and the source terminal of the P channel MOSFET element
  • the connection point of the fourth transistor element with the first terminal is connected to the output terminal.
  • reverse current can be blocked even when the potential difference between input and output is extremely low as compared with the conventional case.
  • FIG. 2A and 2B are diagrams showing an example of a PNP transistor Q1 configured as an equivalent diode element. It is a figure explaining the operation of the rectifier circuit IDP when the output potential rises by an external factor in Embodiment 1.
  • FIG. It is a figure explaining the gate capacitance of P channel MOSFET QMp. It is a figure which shows the modification of the current boost circuit in Embodiment 1.
  • FIG. It is a circuit diagram which shows the structural example of the rectifier circuit IDN which concerns on Embodiment 2.
  • FIG. 7A and 7B are diagrams showing an example of an NPN transistor Q11 configured as an equivalent diode element.
  • FIG. 2 is a diagram illustrating the operation of the rectifier circuit IDN when the output potential rises due to an external factor in the second embodiment. It is a figure explaining the gate capacitance of the N channel MOSFET QMn. It is a figure which shows the modification of the current boost circuit in Embodiment 2.
  • FIG. It is a figure which shows the circuit example of the power source Vcc in Embodiment 2.
  • FIG. It is a circuit diagram which shows the structural example of the rectifier circuit IDN which concerns on Embodiment 4.
  • FIG. 5 is a diagram illustrating the operation of the rectifier circuit IDN when the Zener diode DZ is present in the fourth embodiment. It is a circuit diagram which shows the structural example of the DC power source synthesis circuit 1 which concerns on Embodiment 5. It is a circuit diagram which shows the structural example of the full-wave rectifier circuit 2 which concerns on Embodiment 6. It is a circuit diagram which shows the structural example of the full-wave rectifier circuit 3 which concerns on Embodiment 7.
  • FIG. 1 is a circuit diagram showing a configuration example of a rectifier circuit IDP according to the first embodiment.
  • the rectifying circuit IDP includes a P-channel MOSFET QMp, a PNP transistor Q1, a PNP transistor Q2, a PNP transistor Q3, an NPN transistor Q4, a resistor R1, a resistor R2, a resistor R3, and a resistor R4.
  • the rectifier circuit IDP uses the P-channel MOSFET QMp to prevent the backflow of current from the output terminal Vout to the input terminal Vi.
  • This P-channel MOSFET QMp is an enhancement type P-channel MOSFET element.
  • the ground GND is a potential lower than the potential of the input terminal Vi by at least the gate-source potential Vth at which the P-channel MOSFET QMp can be turned on. That is, the magnitude relationship of the potential is GND ⁇ Vi + Vth.
  • the PNP transistor Q1 corresponds to the first PNP bipolar transistor element
  • the PNP transistor Q2 corresponds to the second PNP bipolar transistor element.
  • the PNP transistor Q1 and the PNP transistor Q2 detect the potential difference between the input terminal Vi and the output terminal Vout of the rectifier circuit IDP.
  • the PNP transistor Q3 is a PNP bipolar transistor element corresponding to the third transistor element.
  • the NPN transistor Q4 is an NPN bipolar transistor element corresponding to a fourth transistor element having a polarity opposite to that of the third transistor. Further, in the PNP transistor Q3 and the NPN transistor Q4, the collector terminal corresponds to the first terminal, the emitter terminal corresponds to the second terminal, and the base terminal corresponds to the third terminal.
  • the PNP transistor Q3 and the NPN transistor Q4 are current boost circuits for charging and discharging the gate of the P-channel MOSFET QMp. In the steady state, no current flows between the collector-emitter of the PNP transistor Q3 and between the collector-emitter of the NPN transistor Q4.
  • connection point between the drain terminal of the P channel MOSFET QMp and one terminal of the resistor R1 is connected to the input terminal Vi.
  • the base terminal and the collector terminal of the PNP transistor Q1 are short-circuited, and the PNP transistor Q1 is configured as an equivalent diode element.
  • 2A and 2B are diagrams showing an example of a PNP transistor Q1 configured as an equivalent diode element.
  • the emitter terminal corresponds to the anode terminal (A) of the equivalent diode element
  • the connection point between the base terminal and the collector terminal is the cathode terminal of the equivalent diode element.
  • the emitter terminal of the PNP transistor Q1 is connected to the other terminal of the resistor R1.
  • the connection point between the base terminal and the collector terminal of the PNP transistor Q1 is connected to the base terminal of the PNP transistor Q2 and one terminal of the resistor R2.
  • the collector terminal of the PNP transistor Q1 corresponds to the anode terminal (A) of the equivalent diode element, and the other terminal of the resistor R1 is connected to this collector terminal.
  • the base terminal of the PNP transistor Q2 corresponds to the cathode terminal (K) of the equivalent diode element, and the base terminal of the PNP transistor Q2 and one terminal of the resistor R2 are connected to this base terminal.
  • the emitter terminal of the PNP transistor Q1 is opened.
  • connection point between the other terminal of the resistor R2, the one terminal of the resistor R3, and the collector terminal of the PNP transistor Q3 is connected to the ground GND.
  • the other terminal of the resistor R3, the collector terminal of the PNP transistor Q2, the base terminal of the PNP transistor Q3, the base terminal of the NPN transistor Q4, and one terminal of the resistor R4 are connected.
  • the emitter terminal of the PNP transistor Q3, the emitter terminal of the NPN transistor Q4, the other terminal of the resistor R4, and the gate terminal of the P channel MOSFET QMp are connected.
  • the connection points between the emitter terminal of the PNP transistor Q2, the source terminal of the P channel MOSFET QMp, and the collector terminal of the NPN transistor Q4 are connected to the output terminal Vout.
  • the steady state of the rectifier circuit IDP will be described.
  • the difference [delta]> 0 the base-emitter voltage of the base-emitter voltage and the PNP transistor Q2 of the PNP transistor Q1, the emitter and the base of the PNP transistor Q1 Let the inter-voltage be V BE + ⁇ . Further, the DC leakage current at the gate of the P-channel MOSFET QMp, the base current of the PNP transistor Q1 and the base current of the PNP transistor Q2 are ignored. Further, the resistance value of the resistor R2 is set to a positive value.
  • the forward voltage Vf is virtually negative.
  • the current constantly flows back from the output terminal Vout to the input terminal Vi until the voltage of the output terminal Vout is higher than that of the input terminal Vi by
  • the difference ⁇ ⁇ 0 may occur due to individual variation and the ambient temperature difference between the PNP transistor Q1 and the PNP transistor Q2.
  • the resistance value of the resistor R1 is made larger than "0" to make the equation (3) a positive value, or the method of FIG. 2B is used instead of FIG. 2A as the connection method of the PNP transistor Q1 to make the difference ⁇ . Secure> 0 to prevent backflow.
  • the voltage between the anode terminal (A) and the cathode terminal (K) has a base current of 1 / HFE of the collector current, so that the PNP transistor Q2 has a voltage of 1 / HFE. It is the same as the base-emitter voltage V BE . HFE is the current amplification factor.
  • the PNP transistor Q1 is connected as shown in FIG. 2B, the total current flows between the collector bases and the voltage drop becomes large. Therefore, the voltage between the anode terminal (A) and the cathode terminal (K) is larger than that in the case of FIG. 2A. That is, ⁇ > 0.
  • the withstand voltage between the collector bases is higher than the withstand voltage between the emitter bases, so that the connection method of FIG. 2B has high resistance to a power surge or the like that may be superimposed on the input terminal Vi.
  • FIG. 3 is a diagram illustrating the operation of the rectifier circuit IDP when the output potential rises due to an external factor in the first embodiment.
  • the output terminal Vout is forced from the outside (Vi).
  • the load current when a voltage E1 higher than ⁇ Vf) is applied and the time change of the gate potential of the P-channel MOSFET QMp will be described.
  • the external factor will be an external power supply connected to the output terminal Vout.
  • FIG. 4 is a diagram for explaining the gate capacitance of the P-channel MOSFET QMp.
  • Capacitances Cgd, Cgs, and Cds exist between the drain, gate, and source terminals of the P-channel MOSFET QMp.
  • the gate capacitance Ciss of the P-channel MOSFET QMp is (Cgd + Cgs).
  • the gate potential of the P-channel MOSFET QMp cannot be raised immediately.
  • the PNP transistor Q2 is turned on, the point P side potential becomes higher than the base-emitter voltage V BE fraction of the NPN transistor Q4 from the gate potential of the P-channel MOSFETQMp, i.e., potential difference between both ends of the resistor R4 is of the NPN transistor Q4 base
  • the NPN transistor Q4 is turned on.
  • the NPN transistor Q4 constituting the current boost circuit can be turned on at time t0 to rapidly discharge the charge at the gate of the P-channel MOSFET QMp. As the charge on the gate of the P-channel MOSFET QMp is discharged, the potential of the gate rises.
  • the period from time t0 to time t1 in FIG. 3 is a discharge boost period by the current boost circuit.
  • the gate potential when the P-channel MOSFET QMp is turned off is V1.
  • the period from time t1 to time t2 in FIG. 3 is a non-boost period.
  • PNP transistor Q2 is turned off, P point side potential, becomes the base-emitter voltage V BE fraction lower of the PNP transistor Q3 than the gate potential of the P-channel MOSFETQMp, that is, between the base and the emitter of the potential difference across the resistor R4 is PNP transistor Q3
  • V BE base-emitter voltage
  • the PNP transistor Q3 constituting the current boost circuit can be turned on at time t4 to rapidly charge the gate capacitance of the P-channel MOSFET QMp. As the charge on the gate of the P-channel MOSFET QMp is charged, the potential of the gate decreases.
  • the period from time t4 to time t5 in FIG. 3 is a charging boost period by the current boost circuit.
  • the potential difference between both ends of the resistor R4 is the base-emitter than the voltage V BE of the PNP transistor Q3, the PNP transistor Q3 is turned off.
  • the resistor R3 and the resistor R4 slowly charge the gate capacitance of the P-channel MOSFET QMp, and when the gate potential of the P-channel MOSFET QMp reaches V0 at time t6, the P-channel MOSFET QMp is completely turned on.
  • the period from time t5 to time t6 in FIG. 3 is a non-boost period.
  • the time required for the recovery of the load current is the period Tc from time t4 to time t6 when the current boost circuit is present, whereas it is longer than the time t4 to time t7 when the current boost circuit is not present. It becomes Td for a long period of time, and it takes a longer time for the P-channel MOSFET QMp to be completely turned on, so that the loss in the rectifier circuit IDP increases.
  • the rectifier circuit IDP is used for a load having an extremely small current consumption and the current consumption of the rectifier circuit IDP itself needs to be reduced, it is not possible to use a resistor R2 having a very low resistance value.
  • the current boost circuit is effective.
  • a load with very low current consumption is, for example, a microcontroller during sleep or suspend.
  • the resistance value of the resistor R2 is high, the base current of the PNP transistor Q2 is limited, and the collector current obtained by multiplying the current amplification factor of the PNP transistor Q2 is also limited.
  • the voltage E1 when the voltage E1 is applied to the output terminal Vout, it takes time if the gate terminal of the P channel MOSFET QMp is short-circuited to the source terminal by the PNP transistor Q2 and the charge of the gate is discharged only by the PNP transistor Q2.
  • the collector current of the PNP transistor Q2 is supplied as the base current of the NPN transistor Q4, so that the current of the current amplification factor of the NPN transistor Q4 is doubled between the collector and emitter of the NPN transistor Q4. Can be shed. Therefore, the charge at the gate of the P-channel MOSFET QMp can be quickly discharged to turn off the P-channel MOSFET QMp, and the current backflow period can be shortened.
  • the resistor R3 when the rectifier circuit IDP is used for a load having an extremely small current consumption and the current consumption of the rectifier circuit IDP itself needs to be reduced, the resistor R3 also has a resistance value that is too low. Cannot be used. Therefore, after the voltage E1 is removed from the output terminal Vout, it takes time to charge the gate of the P-channel MOSFET QMp with only the resistor R3.
  • the current boost circuit when the current boost circuit exists, the current flowing through the resistor R3 is supplied as the base current of the PNP transistor Q3, so that the current of the current amplification factor of the PNP transistor Q3 is doubled between the collector and the emitter of the PNP transistor Q3. Can be shed. Therefore, the gate capacitance of the P-channel MOSFET QMp can be quickly charged to turn on the P-channel MOSFET QMp, and the time for recovering the load current output from the output terminal Vout can be shortened.
  • the rectifying circuit IDP includes a P-channel MOSFET QMp, a PNP transistor Q1, a PNP transistor Q2, a PNP transistor Q3 and an NPN transistor Q4 having opposite polarities, and a resistor R1. It includes a resistor R2, a resistor R3, a resistor R4, an input terminal Vi, and an output terminal Vout.
  • the rectifier circuit IDP sets the potential difference between the input terminal Vi and the output terminal Vout to a value (for example, 200 mV) extremely lower than the forward voltage (about 0.4 V to 0.7 V) of the diode element. it can.
  • the rectifier circuit IPD does not have a boost circuit by the PNP transistor Q3 and the NPN transistor Q4 when some electromotive force is connected to the output terminal Vout side and the potential of the output terminal Vout becomes higher than the potential of the input terminal Vi. Compared with the case, the reverse current can be blocked more quickly. Further, the rectifier circuit IPD can quickly start supplying power to the load after the electromotive force is removed.
  • FIG. 5 is a diagram showing a modified example of the current boost circuit according to the first embodiment.
  • a P-channel MOSFET Q3p is used as the third transistor element instead of the PNP transistor Q3.
  • an N-channel MOSFET Q4n is used instead of the NPN transistor Q4.
  • the drain terminal corresponds to the first terminal
  • the source terminal corresponds to the second terminal
  • the gate terminal corresponds to the third terminal.
  • the N-channel MOSFET Q4n is turned on.
  • the gate terminal and the source terminal of the P-channel MOSFET QMp are short-circuited.
  • the P channel MOSFET Q3p is turned on.
  • the P-channel MOSFET Q3p is turned on, the gate terminal of the P-channel MOSFET QMp and the ground GND are short-circuited.
  • the current boost circuit is composed of the P-channel MOSFET Q3p and the N-channel MOSFET Q4n, it operates in the same manner as when it is composed of the PNP transistor Q3 and the NPN transistor Q4. Further, when the current boost circuit is composed of the P-channel MOSFET Q3p and the N-channel MOSFET Q4n having a low on-resistance, the transient response time of the P-channel MOSFET QMp may be further shortened.
  • FIG. 6 is a circuit diagram showing a configuration example of the rectifier circuit IDN according to the second embodiment.
  • the rectifying circuit IDN includes an N-channel MOSFET QMn, an NPN transistor Q11, an NPN transistor Q12, an NPN transistor Q13, a PNP transistor Q14, a resistor R1, a resistor R2, a resistor R3, and a resistor R4.
  • the rectifier circuit IDN uses an N-channel MOSFET QMn to prevent backflow of current from the output terminal Vout to the input terminal Vi.
  • This N-channel MOSFET QMn is an enhancement type N-channel MOSFET element.
  • the power supply Vcc has a potential higher than the potential of the input terminal Vi by at least the gate-source potential Vth at which the N-channel MOSFET QMn can be turned on. That is, the magnitude relationship of the potential is Vcc> Vi + Vth.
  • the NPN transistor Q11 corresponds to the first NPN bipolar transistor element
  • the NPN transistor Q12 corresponds to the second NPN bipolar transistor element.
  • the NPN transistor Q11 and the NPN transistor Q12 detect the potential difference between the input terminal Vi and the output terminal Vout of the rectifier circuit IDN.
  • the NPN transistor Q13 is an NPN bipolar transistor element corresponding to the third transistor element.
  • the PNP transistor Q14 is a PNP bipolar transistor element corresponding to a fourth transistor element having a polarity opposite to that of the third transistor element. Further, in the NPN transistor Q13 and the PNP transistor Q14, the collector terminal corresponds to the first terminal, the emitter terminal corresponds to the second terminal, and the base terminal corresponds to the third terminal.
  • the NPN transistor Q13 and the PNP transistor Q14 are current boost circuits for charging and discharging the gate of the N-channel MOSFET QMn. In the steady state, no current flows between the collector-emitter of the NPN transistor Q13 and between the collector-emitter of the PNP transistor Q14.
  • connection point between the source terminal of the N-channel MOSFET QMn and the emitter terminal of the NPN transistor Q12 is connected to the input terminal Vi.
  • FIGS. 6 and 7A are diagrams showing an example of an NPN transistor Q11 configured as an equivalent diode element.
  • the emitter terminal corresponds to the cathode terminal (K) of the equivalent diode element
  • the connection point between the base terminal and the collector terminal is the anode terminal of the equivalent diode element.
  • the emitter terminal of the NPN transistor Q11 is connected to one terminal of the resistor R1.
  • the connection point between the base terminal and the collector terminal of the NPN transistor Q11 is connected to the base terminal of the NPN transistor Q12 and one terminal of the resistor R2.
  • the collector terminal of the NPN transistor Q11 corresponds to the cathode terminal (K) of the equivalent diode element, and one terminal of the resistor R1 is connected to this collector terminal.
  • the base terminal of the NPN transistor Q11 corresponds to the anode terminal (A) of the equivalent diode element, and the base terminal of the NPN transistor Q12 and one terminal of the resistor R2 are connected to this base terminal.
  • the emitter terminal of the NPN transistor Q11 is opened.
  • connection point between the other terminal of the resistor R2, the one terminal of the resistor R3, and the collector terminal of the NPN transistor Q13 is connected to the power supply Vcc having a potential higher than the input voltage of the input terminal Vi. ..
  • the other terminal of the resistor R3, the collector terminal of the NPN transistor Q12, the base terminal of the NPN transistor Q13, the base terminal of the PNP transistor Q14, and one terminal of the resistor R4 are connected.
  • the emitter terminal of the NPN transistor Q13, the emitter terminal of the PNP transistor Q14, the other terminal of the resistor R4, and the gate terminal of the N-channel MOSFET QMn are connected.
  • the connection point between the drain terminal of the N-channel MOSFET QMn and the other terminal of the resistor R1 is connected to the output terminal Vout.
  • the steady state of the rectifier circuit IDN will be described.
  • the base-emitter voltage of the base-emitter voltage V BE, the base-emitter voltage and the NPN transistor Q12 of NPN transistor Q11 of NPN transistor Q12, the emitter and the base of the NPN transistor Q11 Let the inter-voltage be V BE + ⁇ . Further, the DC leakage current at the gate of the N-channel MOSFET QMn, the base current of the NPN transistor Q11, and the base current of the NPN transistor Q12 are ignored.
  • the potential of the power supply Vcc is higher than the potential of the input terminal Vi.
  • the resistance value of the resistor R2 is set to a positive value.
  • the potential of the output terminal Vout and the potential difference (that is, forward voltage) Vf between the input terminal Vi and the output terminal Vout are set. The following equations (4) and (5) are established.
  • the resistance value of the resistor R1 is made larger than "0" to make the equation (6) a positive value, or the method of FIG. 7B is used instead of FIG. 7A as the connection method of the NPN transistor Q11, and the difference ⁇ Secure> 0 to prevent backflow.
  • the voltage between the anode terminal (A) and the cathode terminal (K) has a base current of 1 / HFE of the collector current, so that the NPN transistor Q12 has a voltage of 1 / HFE. It is the same as the base-emitter voltage V BE .
  • the NPN transistor Q11 is connected as shown in FIG. 7B, the total current flows between the collector bases and the voltage drop becomes large. Therefore, the voltage between the anode terminal (A) and the cathode terminal (K) is larger than that in the case of FIG. 7A. That is, ⁇ > 0.
  • FIG. 8 is a diagram illustrating the operation of the rectifier circuit IDN when the output potential rises due to an external factor in the second embodiment.
  • the output terminal Vout is forcibly (Vi).
  • the load current when a voltage E1 higher than ⁇ Vf) is applied and the time change of the gate potential of the N-channel MOSFET QMn will be described.
  • the external factor will be an external power supply connected to the output terminal Vout.
  • FIG. 9 is a diagram illustrating the gate capacitance of the N-channel MOSFET QMn. Capacitances Cgd, Cgs, and Cds exist between the drain, gate, and source terminals of the N-channel MOSFET QMn. The gate capacitance Ciss of the N-channel MOSFET QMn is (Cgd + Cgs).
  • the collector terminal and the base terminal of the NPN transistor Q11 are short-circuited, so that the voltage between the connection points of the collector terminal and the base terminal and the emitter terminal is constant.
  • the voltage E1 is applied to the output terminal Vout, the base potential of the NPN transistor Q12 rises, so that the NPN transistor Q12 becomes more conductive and the collector terminal of the NPN transistor Q12 and the other terminal of the resistor R3 are connected. Attempts are made to lower the potential at point P (see FIG. 6), which is the point. However, as shown in FIG.
  • the gate potential of the N-channel MOSFET QMn cannot be lowered immediately.
  • N-channel MOSFETQMn N-channel MOSFETQMn is turned, P point side potential becomes lower than the base-emitter voltage V BE amount of PNP transistor Q14 than the gate potential of the N-channel MOSFETQMn, i.e., the base potential difference between both ends of the resistor R4 is of the PNP transistor Q14
  • the PNP transistor Q14 is turned on.
  • the PNP transistor Q14 constituting the current boost circuit can be turned on at time t0 to rapidly discharge the charge at the gate of the N-channel MOSFET QMn. As the charge on the gate of the N-channel MOSFET QMn is discharged, the potential of the gate decreases.
  • the period from time t0 to time t1 in FIG. 8 is a discharge boost period by the current boost circuit.
  • the potential difference between both ends of the resistor R4 is the base-emitter than the voltage V BE of the PNP transistor Q14, PNP transistor Q14 is turned off.
  • the charge at the gate of the N-channel MOSFET QMn is slowly discharged via the resistor R4, and the N-channel MOSFET QMn is turned off at time t2.
  • the gate potential when the N-channel MOSFET QMn is turned off is V1.
  • the period from time t1 to time t2 in FIG. 8 is a non-boost period.
  • NPN transistor Q12 is turned off, P point side potential and the gate potential of the N-channel MOSFETQMn higher base-emitter voltage V BE fraction of the NPN transistor Q13, that is, between the base and the emitter of the potential difference across the resistor R4 is NPN transistor Q13
  • V BE base-emitter voltage
  • the NPN transistor Q13 constituting the current boost circuit can rapidly charge the gate capacitance of the N-channel MOSFET QMn by turning on at time t4. As the charge on the gate of the N-channel MOSFET QMn is charged, the potential of the gate rises.
  • the period from time t4 to time t5 in FIG. 8 is a charging boost period by the current boost circuit.
  • the potential difference between both ends of the resistor R4 is the base-emitter than the voltage V BE of the NPN transistor Q13, NPN transistor Q13 is turned off.
  • the resistor R3 and the resistor R4 slowly charge the gate charge of the N-channel MOSFET QMn, and when the gate potential of the N-channel MOSFET QMn reaches V0 at time t6, the N-channel MOSFET QMn is completely turned on. ..
  • the period from time t5 to time t6 in FIG. 8 is a non-boost period.
  • the time required for the recovery of the load current is the period Tc from time t4 to time t6 when the current boost circuit is present, whereas it is longer than the time t4 to time t7 when the current boost circuit is not present. It becomes Td for a long period of time, and it takes a longer time for the N-channel MOSFET QMn to be completely turned on, so that the loss in the rectifier circuit IDN increases.
  • the current boost circuit is effective as described in the first embodiment. is there.
  • the rectifying circuit IDN includes an N-channel MOSFET QMn, an NPN transistor Q11, an NPN transistor Q12, an NPN transistor Q13 and a PNP transistor Q14 having opposite polarities, and a resistor R1. It includes a resistor R2, a resistor R3, a resistor R4, an input terminal Vi, and an output terminal Vout.
  • the rectifier circuit IDN can set the potential difference between the input terminal Vi and the output terminal Vout to a value (for example, 200 mV) extremely lower than the forward voltage (0.4 V to 0.7 V) of the diode element. ..
  • the rectifier circuit IDN does not have a boost circuit by the NPN transistor Q13 and the PNP transistor Q14 when some electromotive force is connected to the output terminal Vout side and the potential of the output terminal Vout becomes higher than the potential of the input terminal Vi. Compared with the case, the reverse current can be blocked more quickly. Further, the rectifier circuit IDN can quickly start supplying power to the load after the electromotive force is removed.
  • FIG. 10 is a diagram showing a modified example of the current boost circuit according to the second embodiment.
  • an N-channel MOSFET Q13n is used as the third transistor element instead of the NPN transistor Q13.
  • a P-channel MOSFET Q14p is used instead of the PNP transistor Q14.
  • the drain terminal corresponds to the first terminal
  • the source terminal corresponds to the second terminal
  • the gate terminal corresponds to the third terminal.
  • the N-channel MOSFET Q13n is turned on.
  • the gate terminal of the N-channel MOSFET QMn and the power supply Vcc are short-circuited.
  • the P point potential is lower than the source potential of the P channel MOSFET Q14p by the threshold potential between the gate and source, the P channel MOSFET Q14p is turned on.
  • the P-channel MOSFET Q14p is turned on, the gate terminal and the source terminal of the N-channel MOSFET QMn are short-circuited.
  • the current boost circuit is composed of the N-channel MOSFET Q13n and the P-channel MOSFET Q14p, it operates in the same manner as when it is composed of the NPN transistor Q13 and the PNP transistor Q14. Further, when the current boost circuit is composed of the N-channel MOSFET Q13n having a low on-resistance and the P-channel MOSFET Q14p, there is a possibility that the transient response time of the N-channel MOSFET QMn can be further shortened.
  • FIG. 11 is a diagram showing a circuit example of the power supply Vcc according to the second embodiment.
  • the booster circuit is composed of a switch unit SW that performs a switching operation, a capacitor C11, a capacitor C12, a diode D11, and a diode D12.
  • the capacitor C11 corresponds to the first capacitor
  • the capacitor C12 corresponds to the second capacitor.
  • the diode D11 corresponds to the first diode element
  • the diode D12 corresponds to the second diode element.
  • the forward voltage of the diode D11 and the diode D12 is both Vf.
  • the output terminal Vout of the rectifier circuit IDN is connected to the input side of the switch unit SW, the anode terminal of the diode D11, and one terminal of the capacitor C12.
  • the output side of the switch unit SW and one terminal of the capacitor C11 are connected.
  • the other terminal of the capacitor C11, the cathode terminal of the diode D11, and the anode terminal of the diode D12 are connected.
  • the connection point between the other terminal of the capacitor C11, the cathode terminal of the diode D11, and the anode terminal of the diode D12 is defined as the Q point.
  • the connection point between the cathode terminal of the diode D12 and the other terminal of the capacitor C12 is connected to the connection point between the other terminal of the resistor R2, one terminal of the resistor R3, and the collector terminal of the NPN transistor Q13.
  • the switch unit SW is a circuit such as a DC-DC converter that generates a square wave whose duty fluctuates at a value other than 0% and 100%.
  • the switch unit SW is connected to the output terminal Vout and performs a switching operation between the potential of the output terminal Vout and the potential of the ground GND.
  • the capacitor C11 is charged with the potential of (Vout-Vf) via the diode D11 and smoothed to the DC potential of (Vout-Vf).
  • the booster circuit shown in FIG. 11 is an example of the power supply Vcc, and the power supply Vcc is not limited to this booster circuit.
  • FIG. 12 is a circuit diagram showing a configuration example of the rectifier circuit IDP according to the third embodiment.
  • the rectifier circuit IDP according to the third embodiment has a configuration in which a Zener diode DZ is added to the rectifier circuit IDP of the first embodiment shown in FIG.
  • the same or corresponding parts as those in FIGS. 1 to 5 are designated by the same reference numerals, and the description thereof will be omitted.
  • the anode terminal of the Zener diode DZ is connected to the base terminal of the NPN transistor Q4, and the cathode terminal of the Zener diode DZ is connected to the output terminal Vout.
  • the zener diode DZ limits the gate-source voltage V GS of the P-channel MOSFETQMp.
  • the Zener voltage of the Zener diode DZ is directed to an output current load of the output terminal Vout side requires that P-channel MOSFETQMp is only the on-resistance of the gate-source voltage V GS than can be secured can flow sufficiently.
  • the gate potential of the P-channel MOSFET QMp drops only to the potential obtained by subtracting the Zener voltage from the potential of the output terminal Vout (that is, the potential on the source side), so that the P-channel MOSFET QMp approaches the saturated state more than necessary. Can be prevented. Further, since the amount of charge to be changed in the gate capacitance, that is, the fluctuation range of the gate potential can be suppressed in the transient state of the P channel MOSFET QMp, the P channel with respect to the potential increase of the output terminal Vout exceeding the potential of the input terminal Vi. The transient response of the MOSFET QMp is improved. This situation is shown in FIG.
  • FIG. 13 is a diagram illustrating the operation of the rectifier circuit IDP when the Zener diode DZ is present in the third embodiment.
  • the output terminal is output from the outside.
  • the load current when a voltage E1 higher than (Vi-Vf) is forcibly applied to Vout, and the time change of the gate potential of the P-channel MOSFET QMp will be described.
  • the gate potential and load current of the P-channel MOSFET QMp in the presence of the Zener diode DZ are shown by solid lines.
  • the gate potential and load current of the P-channel MOSFET QMp in the absence of the Zener diode DZ are indicated by alternate long and short dash lines.
  • the gate potential of the P-channel MOSFET QMp is V0.
  • the Zener diode DZ raises the gate potential from V0 to V0 DZ (> V0) and a sufficient load current can be secured even if the saturation degree of the P channel MOSFET QMp is relaxed, the gate potential is raised from V0 to V0 DZ .
  • the current backflow period from the output terminal Vout to the input terminal Vi can be shortened. That is, the current backflow period in the absence of the Zener diode DZ is from time t0 to time t2, but the current backflow period in the presence of the Zener diode DZ is from time t0 to time t8 ( ⁇ t2). ..
  • the time for recovering the load current that is, the time from time t4 to time t6 does not change depending on the presence or absence of the Zener diode DZ.
  • the rectifier circuit IDP includes a Zener diode DZ in which the cathode terminal is connected to the output terminal Vout and the anode terminal is connected to the base terminal of the NPN transistor Q4.
  • FIG. 14 is a circuit diagram showing a configuration example of the rectifier circuit IDN according to the fourth embodiment.
  • the rectifier circuit IDN according to the fourth embodiment has a configuration in which a Zener diode DZ is added to the rectifier circuit IDN of the second embodiment shown in FIG.
  • the same or corresponding parts as those in FIGS. 6 to 11 are designated by the same reference numerals, and the description thereof will be omitted.
  • the anode terminal of the Zener diode DZ is connected to the input terminal Vi, and the cathode terminal of the Zener diode DZ is connected to the base terminal of the PNP transistor Q14.
  • the zener diode DZ limits the gate-source voltage V GS of the N-channel MOSFETQMn.
  • the Zener voltage of the Zener diode DZ is directed to an output current load of the output terminal Vout side requires that the N channel MOSFETQMn is only the on-resistance of the gate-source voltage V GS than can be secured can flow sufficiently.
  • the gate potential of the N-channel MOSFET QMn rises only from the potential of the input terminal Vi (that is, the potential on the source side) to the potential to which the Zener voltage is applied, so that the N-channel MOSFET QMn becomes saturated more than necessary. Can be prevented. Further, since the amount of charge to be changed in the gate capacitance, that is, the fluctuation range of the gate potential can be suppressed in the transient state of the N channel MOSFET QMn, the N channel with respect to the potential increase of the output terminal Vout exceeding the potential of the input terminal Vi. The transient response of the MOSFET QMn is improved. This situation is shown in FIG.
  • FIG. 15 is a diagram illustrating the operation of the rectifier circuit IDN when the Zener diode DZ is present in the fourth embodiment.
  • the output terminal is output from the outside.
  • the load current when a voltage E1 higher than (Vi-Vf) is forcibly applied to Vout, and the time change of the gate potential of the N-channel MOSFET QMn will be described.
  • the gate potential and load current of the N-channel MOSFET QMn in the presence of the Zener diode DZ are shown by solid lines.
  • the gate potential and load current of the N-channel MOSFET QMn in the absence of the Zener diode DZ are indicated by alternate long and short dash lines.
  • the gate potential of the N-channel MOSFET QMn is V0.
  • the Zener diode DZ lowers the gate potential from V0 to V0 DZ ( ⁇ V0) and a sufficient load current can be secured even if the saturation degree of the N-channel MOSFET QMn is relaxed, the gate potential is lowered from V0 to V0 DZ .
  • the current backflow period from the output terminal Vout to the input terminal Vi can be shortened. That is, the current backflow period in the absence of the Zener diode DZ is from time t0 to time t2, but the current backflow period in the presence of the Zener diode DZ is from time t0 to time t8 ( ⁇ t2). ..
  • the time for recovering the load current that is, the time from time t4 to time t6 does not change depending on the presence or absence of the Zener diode DZ.
  • the rectifier circuit IDN includes a Zener diode DZ in which the anode terminal is connected to the input terminal Vi and the cathode terminal is connected to the base terminal of the PNP transistor Q14.
  • FIG. 16 is a circuit diagram showing a configuration example of the DC power supply synthesis circuit 1 according to the fifth embodiment.
  • the same or corresponding parts as those in FIGS. 1 to 15 are designated by the same reference numerals, and the description thereof will be omitted.
  • the DC power supply synthesis circuit 1 has a configuration in which n rectifier circuits ID1 to IDn (n is an arbitrary integer) and m ordinary diodes D1 to Dm (m is an arbitrary integer) are combined.
  • the rectifier circuits ID1 to IDn are the rectifier circuit IDP according to the first embodiment, the rectifier circuit IDN according to the second embodiment, the rectifier circuit IDP according to the third embodiment, or the rectifier circuit IDN according to the fourth embodiment, respectively. It is either.
  • the rectifier circuits ID1 to IDn are ideal diode circuits having a smaller forward voltage than the ordinary diodes D1 to Dm.
  • the rectifier circuits ID1 to IDn will be referred to as "low voltage drop rectifier circuits ID1 to IDn".
  • the low voltage drop rectifier circuits ID1 to IDn may include a rectifier circuit IDP and a rectifier circuit IDN.
  • the rectifier circuit IDP corresponds to the first rectifier circuit
  • the rectifier circuit IDN corresponds to the second rectifier circuit.
  • the reference potential Vref is for supplying the drive current of the low voltage drop rectifier circuits ID1 to IDn.
  • the reference potential Vref of the rectifier circuit IDP is a ground GND having a potential lower than the potential of the input terminal Vi by at least the potential between the gate and source at which the P channel MOSFET QMp can be turned on.
  • the reference potential Vref of the rectifier circuit IDN is a power supply Vcc having a potential higher than the potential of the input terminal Vi by at least the potential between the gate and source at which the N-channel MOSFET QMn can be turned on.
  • DC power supplies Ei1 to Eim are connected to the anode terminals of the diodes D1 to Dm. All the cathode terminals of the diodes D1 to Dm and all the output terminals Vout of the low voltage drop rectifier circuits ID1 to IDn are connected. V0 is the output voltage of the DC power supply synthesis circuit 1.
  • the DC power supply synthesis circuit 1 includes DC power supplies Ei1 to Eim, Vi1 to Vin, low voltage drop rectifier circuits ID1 to IDn, and diodes D1 to Dm.
  • Ei1 to Eim are connected to the anode terminals of the diodes D1 to Dm, respectively.
  • the DC power supplies Vi1 to Vin are connected to the input terminals Vi of the low voltage drop rectifier circuits ID1 to IDn, respectively.
  • the cathode terminals of the diodes D1 to Dm and the output terminals Vout of the low voltage drop rectifier circuits ID1 to IDn are connected to each other.
  • the normal diodes D1 to Dm are connected to the DC power supplies Ei1 to Eim having a high power supply voltage and a small current consumption, and the ideal diode circuit is used for the DC power supplies Vi1 to Vin having a low power supply voltage and a large current consumption.
  • the DC power supply synthesis circuit 1 is configured to use at least one diode D1 in addition to at least one of the rectifier circuit IDP and the rectifier circuit IDN, but the rectifier circuit IDP or the rectifier circuit IDN It may be configured to use at least one of them.
  • FIG. 17 is a circuit diagram showing a configuration example of the full-wave rectifier circuit 2 according to the sixth embodiment.
  • the same or corresponding parts as those in FIGS. 1 to 15 are designated by the same reference numerals, and the description thereof will be omitted.
  • the full-wave rectifier circuit 2 is a bridge-type full-wave rectifier circuit that full-wave rectifies the AC voltage output by the transformer Tr.
  • the transformer Tr includes a primary winding, a secondary winding, and a center tap provided on the secondary winding.
  • the full-wave rectifier circuit 2 uses the center tap as a reference potential, and performs full-wave rectification using the rectifier circuits IDP1 and IDP2 on the positive potential side and the rectifier circuits IDN1 and IDN2 on the negative potential side.
  • the rectifier circuits IDP1 and IDP2 are the rectifier circuit IDP according to the first embodiment or the rectifier circuit IDP according to the third embodiment, respectively.
  • the rectifier circuits IDN1 and IDN2 are the rectifier circuit IDN according to the second embodiment or the rectifier circuit IDN according to the fourth embodiment, respectively.
  • the rectifier circuits IDP1, IDP2, IDN1 and IDN2 are ideal diode circuits having a small forward voltage. Loads Za, Zb, and Zc are connected to the output side of the full-wave rectifier circuit 2 via capacitors C1 and C2 for AC ripple smoothing.
  • the input terminal Vi of the rectifier circuit IDP1 and the output terminal Vout of the rectifier circuit IDN2 are connected to one output side of the secondary winding.
  • the input terminal Vi of the rectifier circuit IDP2 and the output terminal Vout of the rectifier circuit IDN1 are connected to the other output side of the secondary winding.
  • the connection point between the output terminal Vout of the rectifier circuit IDP1, the output terminal Vout of the rectifier circuit IDP2, and one terminal of the capacitor C1 is an output terminal of a positive power supply.
  • + V1 is the output potential of the positive power supply with respect to the reference potential of the center tap.
  • connection point between the input terminal Vi of the rectifier circuit IDN1, the input terminal Vi of the rectifier circuit IDN2, and one terminal of the capacitor C2 is an output terminal of a negative power supply.
  • -V1 is the output potential of the negative power supply with respect to the reference potential of the center tap.
  • the ground GND of the rectifier circuit IDP1, the ground GND of the rectifier circuit IDP2, the power supply Vcc of the rectifier circuit IDN1, the power supply Vcc of the rectifier circuit IDN2, the other terminal of the capacitor C1, and the other terminal of the capacitor C2 are center tapped. It is connected.
  • the full-wave rectifier circuit 2 is a bridge-type full-wave rectifier circuit composed of four rectifier circuits IDP1, IDP2, IDN1, and IDN2, and is a transformer having a center tap. Full-wave rectification of the AC voltage output by the device Tr. Since this full-wave rectifier circuit 2 is composed of rectifier circuits IDP1, IDP2, IDN1 and IDN2, which are ideal diode circuits having a small forward voltage, it is compared with a bridge-type full-wave rectifier circuit using a normal diode element. It is possible to suppress the power loss.
  • FIG. 18 is a circuit diagram showing a configuration example of the full-wave rectifier circuit 3 according to the seventh embodiment.
  • the same or corresponding parts as those in FIGS. 1 to 15 are designated by the same reference numerals, and the description thereof will be omitted.
  • the full-wave rectifier circuit 3 is a bridge-type full-wave rectifier circuit that full-wave rectifies the three-phase AC voltage output by the three-phase AC power generation circuit 4.
  • the three-phase AC power generation circuit 4 includes a three-phase sinusoidal AC power supply Eu, Ev, Ew and a neutral point Vn to which the sinusoidal AC power supply Eu, Ev, Ew is connected.
  • the sinusoidal AC power supply Ev has a phase angle 2 ⁇ / 3 behind that of the sinusoidal AC power supply Eu.
  • the sinusoidal AC power supply Ew has a phase angle 2 ⁇ / 3 behind the sinusoidal AC power supply Ev.
  • the full-wave rectifier circuit 3 uses the neutral point Vn as a reference potential, and uses the rectifier circuits IDP3, IDP4, IDP5 on the positive potential side and the rectifier circuits IDN3, IDN4, IDN5 on the negative potential side for each phase. Perform full-wave rectification.
  • the rectifier circuits IDP3, IDP4, and IDP5 are the rectifier circuit IDP according to the first embodiment or the rectifier circuit IDP according to the third embodiment, respectively.
  • the rectifier circuits IDN3, IDN4, and IDN5 are the rectifier circuit IDN according to the second embodiment or the rectifier circuit IDN according to the fourth embodiment, respectively.
  • the rectifier circuits IDP3, IDP4, IDP5, IDN3, IDN4, IDN5 are ideal diode circuits having a small forward voltage.
  • a load Zd is connected to the output side of the full-wave rectifier circuit 3 via a capacitor C3 for smoothing AC ripple.
  • the input terminal Vi of the rectifier circuit IDP3 and the output terminal Vout of the rectifier circuit IDN3 are connected to the output side of the sinusoidal AC power supply Eu of the three-phase AC power generation circuit 4.
  • the input terminal Vi of the rectifier circuit IDP4 and the output terminal Vout of the rectifier circuit IDN4 are connected to the output side of the sinusoidal AC power supply Ew.
  • the input terminal Vi of the rectifier circuit IDP5 and the output terminal Vout of the rectifier circuit IDN5 are connected to the output side of the sinusoidal AC power supply Ev.
  • Each ground GND of the rectifier circuits IDP3, IDP4 and IDP5 and each power supply Vcc of the rectifier circuits IDN3, IDN4 and IDN5 are connected to the neutral point Vn.
  • connection point between each output terminal Vout of the rectifier circuits IDP3, IDP4, and IDP5 on the positive potential side and one terminal of the capacitor C3 becomes an output terminal of the positive power supply.
  • connection point between each input terminal Vi of the rectifier circuits IDN3, IDN4, and IDN5 on the negative potential side and the other terminal of the capacitor C3 becomes an output terminal of a negative power supply.
  • V2 is the output potential applied to the load Zd.
  • the full-wave rectifier circuit 3 is a bridge-type full-wave rectifier circuit composed of six rectifier circuits IDP3, IDP4, IDP5, IDN3, IDN4, IDN5.
  • the three-phase AC voltage output by the three-phase AC power generation circuit 4 having the sex point Vn is full-wave rectified. Since this full-wave rectifier circuit 3 is composed of rectifier circuits IDP3, IDP4, IDP5, IDN3, IDN4, IDN5, which are ideal diode circuits having a small forward voltage, a bridge-type full-wave rectifier circuit using a normal diode element is used. Power loss can be suppressed as compared with a rectifier circuit.
  • the full-wave rectifier circuit 3 is configured to perform full-wave rectification of the three-phase AC voltage, but the n-phase (n ⁇ 4) AC voltage is full-wave rectified. It may be configured.
  • the present invention allows any combination of embodiments, modifications of any component of each embodiment, or omission of any component of each embodiment within the scope of the invention.
  • the rectifier circuit according to the present invention has an extremely small potential difference between input and output and has high responsiveness, and is therefore suitable for a power supply synthesis circuit and a rectifier circuit that require low loss and high-speed response.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Power Conversion In General (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Selon la présente invention, une borne d'entrée (Vi) et une borne de sortie (Vout) sont connectées à la borne de drain d'un MOSFET à canal P (QMp) et la borne de source de celui-ci, respectivement, et le courant inverse provenant de la borne de sortie (Vout) vers la borne d'entrée (Vi) est empêché par la désactivation du MOSFET à canal P (QMp). Un transistor PNP (Q1) et un transistor PNP (Q2) détectent le courant inverse et éteignent le MOSFET à canal P (QMp). Un transistor PNP (Q3) et un transistor NPN (Q4) constituent un circuit d'amplification de courant pour charger et décharger la grille du MOSFET à canal P (QMp) et améliore la réactivité transitoire du MOSFET à canal P (QMp).
PCT/JP2019/018513 2019-05-09 2019-05-09 Circuit redresseur, circuit de synthèse d'alimentation électrique cc et circuit redresseur pleine onde WO2020225896A1 (fr)

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PCT/JP2019/018513 WO2020225896A1 (fr) 2019-05-09 2019-05-09 Circuit redresseur, circuit de synthèse d'alimentation électrique cc et circuit redresseur pleine onde
DE112019007166.1T DE112019007166T5 (de) 2019-05-09 2019-05-09 Gleichrichterschaltung, Gleichspannungsversorgungskombinationsschaltung und Vollwellengleichrichterschaltung
JP2021513493A JP6896203B2 (ja) 2019-05-09 2019-05-09 整流回路、直流電源合成回路、及び全波整流回路

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728903A (en) * 1986-05-02 1988-03-01 Reiffin Martin G Class A high-fidelity amplifier
JP2001230260A (ja) * 2000-02-14 2001-08-24 Nec Corp 半導体装置及び半導体装置の製造方法
US20050253642A1 (en) * 2004-05-14 2005-11-17 Quanta Computer Inc. One way conductor
US20090285001A1 (en) * 2008-05-16 2009-11-19 Zong Bo Hu Control circuits and methods for controlling switching devices
WO2015170479A1 (fr) * 2014-05-09 2015-11-12 パナソニックＩｐマネジメント株式会社 Circuit redresseur, redresseur et dispositif d'alimentation électrique sans fil en étant équipé

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0755025B2 (ja) 1985-07-09 1995-06-07 沖電気工業株式会社 直流電源合成回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728903A (en) * 1986-05-02 1988-03-01 Reiffin Martin G Class A high-fidelity amplifier
JP2001230260A (ja) * 2000-02-14 2001-08-24 Nec Corp 半導体装置及び半導体装置の製造方法
US20050253642A1 (en) * 2004-05-14 2005-11-17 Quanta Computer Inc. One way conductor
US20090285001A1 (en) * 2008-05-16 2009-11-19 Zong Bo Hu Control circuits and methods for controlling switching devices
WO2015170479A1 (fr) * 2014-05-09 2015-11-12 パナソニックＩｐマネジメント株式会社 Circuit redresseur, redresseur et dispositif d'alimentation électrique sans fil en étant équipé

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