WO2020224289A1 - 基于衬底增强型的比较器及电子设备 - Google Patents

基于衬底增强型的比较器及电子设备 Download PDF

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WO2020224289A1
WO2020224289A1 PCT/CN2020/070588 CN2020070588W WO2020224289A1 WO 2020224289 A1 WO2020224289 A1 WO 2020224289A1 CN 2020070588 W CN2020070588 W CN 2020070588W WO 2020224289 A1 WO2020224289 A1 WO 2020224289A1
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Prior art keywords
substrate
latch
transistor
cross
capacitor
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PCT/CN2020/070588
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English (en)
French (fr)
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李婷
黄正波
张勇
倪亚波
王健安
陈光炳
付东兵
徐梓丞
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中国电子科技集团公司第二十四研究所
重庆吉芯科技有限公司
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Priority to US17/609,415 priority Critical patent/US11664794B2/en
Publication of WO2020224289A1 publication Critical patent/WO2020224289A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Definitions

  • the invention relates to the technical field of analog-digital hybrid integrated circuits, in particular to a substrate-enhanced comparator and electronic equipment.
  • Comparator is an important component of many integrated circuits (IC), such as analog-to-digital converter (ADC), transconductance amplifier (OTA), voltage reference (VR) and clock data recovery circuit (CDR).
  • ADC analog-to-digital converter
  • OTA transconductance amplifier
  • VR voltage reference
  • CDR clock data recovery circuit
  • the purpose of the present invention is to provide a substrate-enhanced comparator and electronic device for solving the limitation of the latch speed due to the power supply voltage and process characteristic frequency in the prior art.
  • the limitation of this makes the comparator unable to achieve high-speed problems under low-voltage conditions.
  • the present invention provides a substrate-enhanced comparator, including:
  • the cross-coupled latch is used to connect the input signal to the gate of the cross-coupled MOS transistor to form the first input terminal of the latch;
  • An output buffer connected to the cross-coupling latch, for amplifying the output signal of the latch
  • An AC coupler connected to the output buffer, for receiving and amplifying the latch output signal, and coupling the output signal to the cross-coupled latch MOS tube substrate to form the second input of the latch end;
  • the cross-coupled latch is also used for output signal regeneration latching of the input signal sampled at the first input terminal and the input signal sampled at the second input terminal.
  • Another object of the present invention is to provide an electronic device including the aforementioned substrate-enhanced comparator.
  • the substrate-enhanced comparator and electronic device of the present invention have the following beneficial effects:
  • the present invention additionally introduces the substrate input in the cross-coupling structure of the traditional latch, as the second input terminal of the latch, not only introduces the body transconductance of the cross-coupled MOS transistor into the input node, but also enhances the positive feedback capability, Speed up the latch.
  • the substrate-enhanced latching technology can effectively improve the latching speed of the latch in the metastable state, breaking through the bottleneck of the traditional latching regeneration speed, which is limited by the characteristic frequency of the process and the power supply voltage. It can also be realized under the advanced low-voltage process Design of high-speed latch.
  • Figure 1 shows a schematic diagram of the principle of a substrate-enhanced comparator provided by the present invention
  • FIG. 2 shows a schematic diagram of the principle of an embodiment of a substrate-enhanced comparator provided by the present invention
  • Figure 3 shows a circuit diagram of a substrate-enhanced comparator provided by the present invention
  • FIG. 4 shows a timing diagram of a substrate-enhanced comparator based on FIG. 3 provided by the present invention.
  • the present invention provides a schematic diagram of the principle of a substrate-enhanced comparator, including:
  • the cross-coupled latch 1 is used to connect the input signal to the gate of the cross-coupled MOS transistor to form the first input terminal of the latch;
  • the output buffer 2 is connected to the cross-coupling latch and is used to amplify the output signal of the latch;
  • the AC coupler 3 connected to the output buffer, is used to receive and amplify the output signal of the latch, and couple the output signal to the cross-coupled latch MOS tube substrate to form the second part of the latch Input
  • the cross-coupling latch is also used for output signal regeneration latching of the input signal sampled at the first input terminal and the input signal sampled at the second input terminal;
  • the MOS tube substrate in the cross-coupled latch is fabricated by a deep well process, and is used to isolate the substrate of the MOS tube, and isolate the substrate from the outside to reduce the coupling noise of the substrate and prevent crosstalk or mutual influence.
  • the output buffer amplifies the output signal in the same direction or in the reverse direction to ensure that the substrate on the same side of the cross-coupled latch MOS tube and the input signal phase of the gate of the corresponding MOS tube are the same, for example, the transistor P2 It is the same side as the transistor N3, and the transistor P3 and the transistor N4 are the other same side, that is, the input signal phase of the substrate of the transistor P2 and its gate is the same, and the input signal phase of the substrate of the transistor N3 and its gate is the same. can.
  • the cross-coupled latch in the reset and latch stages of the cross-coupled latch, its corresponding output node and input node are at the same position; when the cross-coupled latch is in the sampling stage, the input node receives the input signal ; When the cross-coupled latch is in the latching stage, the output node performs positive feedback output signal regeneration.
  • the latch as the core unit of the traditional comparator, uses positive feedback to regeneratively latch the metastable signal.
  • almost all latches are designed with cross-coupled inverters. This structure The latching speed is limited by the characteristic frequency of the process, and with the development of advanced process technology, the power supply voltage of the semiconductor chip is getting lower and lower, and the latching speed of the traditional latch is severely restricted.
  • the substrate input is additionally introduced into the cross-coupling structure of the traditional latch as the second input terminal of the latch, which not only introduces the bulk transconductance of the cross-coupled MOS transistor into the input node, but also enhances Positive feedback ability to speed up the latch.
  • FIG. 2 is a schematic diagram of the principle of an embodiment of a substrate-enhanced comparator provided by the present invention.
  • the substrate-enhanced comparator includes:
  • the substrate common mode resetter 4 is respectively connected to the cross-coupled latch and the AC coupler, and is used to perform common mode reset on the AC coupler and the cross-coupled MOS tube substrate during the reset phase.
  • the substrate common-mode resetter resets the output node of the latch and the AC-coupled MOS tube substrate in the reset stage, and the corresponding reset voltage is connected to different AC couplings according to the respective transconductances of the NMOS tube and the PMOS tube
  • the reset voltage of the corresponding MOS transistor does not cause the PN junction of the corresponding MOS transistor to conduct a forward conduction. The lower the reset voltage corresponding to the PMOS transistor, the better, and the higher the reset voltage corresponding to the NMOS transistor, the better.
  • the present invention additionally introduces the substrate input in the cross-coupling structure of the traditional latch, as the second input terminal of the latch, not only the body transconductance of the cross-coupled MOS tube is introduced into the input node, but also the positive feedback capability is enhanced; Introduce the common mode signal in the substrate of the cross-coupled MOS tube to lower the threshold of the cross-coupled MOS tube, thereby increasing the effective transconductance and speeding up the latch.
  • the substrate-enhanced latching technology of the present invention can effectively improve the latching speed of the metastable state of the latch, breaking through the bottleneck limitation of the traditional latching regeneration speed that is limited by the process characteristic frequency and the power supply voltage, and it can also be used under the advanced low-voltage process. Realize the design of high-speed latch.
  • the transistors P1, P2, P3, N 1, N2, N3, and N4 in Fig. 2 constitute a traditional cross-coupled latch LatchT; transistors P4 ⁇ N5 And P5 ⁇ N6 constitute the push-pull amplifier as the output buffer Buffer (first output buffer 21 and second output buffer 21); transistors N7 ⁇ N9 and N8 ⁇ N10 constitute the substrate common mode resetter SUBR (first substrate The bottom common mode resetter 41 and the second substrate common mode resetter 42); capacitors C1, C2, C3, and C4 form an AC coupler ACC (the first AC coupler 31 and the second AC coupler 32).
  • the AC-coupled latch includes transistors P1, P2, P3, N1, N2, N3, and N4, the gate of the transistor P1 is connected to the first clock signal, and the source of the transistor P1 is connected to the power supply voltage,
  • the drain of the transistor P1 is the source of the transistors P2 and P3;
  • the first input signal is connected by the drain of the transistor P2, the gate of the transistor P3, the first input signal, the drains of the transistors N2, N3, and the transistor
  • the gate of N4 is connected together to form an output node;
  • the second input signal is connected by the gate of the transistor P2, the drain of the transistor P3, the source of the transistor N2, the gate of the transistor N3 and the drain of the transistor N4.
  • the gate of the transistor N1 is connected to the second clock signal
  • the gate of the transistor N2 is connected to the third clock signal
  • the drain of the transistor N2 is connected to the sources of the transistors N3 and N4, respectively
  • the source of the transistor N1 is grounded
  • the MOS tube substrate of the transistor P2 and N3 are interconnected to form a cross-coupled latch MOS tube substrate
  • the transistor P3 and the MOS tube substrate of N4 are interconnected
  • the other side substrate of the cross-coupled latch MOS tube is formed.
  • the output buffer 2 includes a first output buffer 21 composed of transistors P4 and N5 and a second output buffer 22 composed of transistors P5 and N6.
  • the gates of the transistors P4 and N5 in the first output buffer 21 are The source of the transistor P4 is connected to the power supply voltage, the source of the transistor N5 is grounded, and the drains of the transistors P4 and N5 are interconnected as an amplifier of the first output buffer 21.
  • the output terminal; the gates of the transistors P5 and N6 in the second output buffer 22 are connected to the other output terminal of the AC-coupled latch, the source of the transistor P5 is connected to the power supply voltage, the source of the transistor N6 is grounded, so The drains of the transistors P5 and N6 are interconnected as the amplified output end of the second output buffer 22.
  • the substrate common mode resetter 4 includes a first substrate common mode resetter 41 composed of transistors N7 and N9 and a second substrate common mode resetter 42 composed of transistors N8 and N10; the first substrate
  • the gates of the transistors N7 and N9 in the common mode resetter 41 are connected to the third clock signal, the drain of the transistor N7 is connected to an output terminal of the AC coupling latch, and the source of the transistor N9 is connected to the common mode level,
  • the source of the transistor N7 and the drain of the transistor N9 serve as the two output terminals of the first substrate common mode resetter 41; the gates of the transistors N8 and N10 in the second substrate common mode resetter 42 are connected
  • the drain of the transistor N8 is connected to the other output terminal of the AC-coupled latch
  • the source of the transistor N10 is connected to the common mode level
  • the source of the transistor N8 and the transistor N10 are The drains serve as two output terminals of the second substrate common mode resetter 42.
  • the AC coupler 3 includes a first AC coupler 31 composed of a first capacitor and a third capacitor, and a second AC coupler 32 composed of a second capacitor and a fourth capacitor; and when the comparator has no substrate common mode reset
  • the connection method of AC coupler is as follows:
  • the upper board of the first capacitor C1 and the third capacitor C3 is connected to the output terminal of the first output buffer 21, and the lower board of the first capacitor C1 is connected to a substrate on one side of the cross-coupling latch MOS tube.
  • the lower board of the three capacitor C3 is connected to the other substrate on the side of the cross-coupling latch MOS tube; the upper board of the second capacitor C2 and the fourth capacitor C4 is connected to the output terminal of the second output buffer, and the second
  • the lower board of the capacitor C2 is connected to a substrate on the other side of the cross-coupling latch MOS tube, and the lower board of the fourth capacitor C4 is connected to the other substrate on the other side of the cross-coupling latch MOS tube.
  • the upper board of the first capacitor and the third capacitor is connected to the output terminal of the first output buffer and an output terminal of the first substrate common mode resetter, and the lower board of the first capacitor is connected to the first substrate common mode resetter
  • the other output terminal of the cross-coupling latch MOS tube, a substrate on one side of the MOS tube, the lower board of the third capacitor is connected to the other output terminal of the common mode resetter of the first substrate, the cross-coupling latch Another substrate on one side of the MOS tube;
  • the upper board of the second capacitor and the fourth capacitor is connected to the output terminal of the second output buffer and an output terminal of the common mode resetter of the second substrate, and the lower stage of the second capacitor
  • the board is connected to the other output terminal of the second substrate common mode resetter, a substrate on the other side of the cross-coupling latch MOS tube, and the lower board of the fourth capacitor is connected to the second substrate common mode resetter.
  • the first capacitor C1 and the second capacitor C2 have the same capacitance value and provide reset voltages to the transistors P2 and P3 respectively, and the third capacitor C3 and the second capacitor C4 have the same capacitance value and provide the reset voltages to the transistors N3 and N4 respectively.
  • FIG. 4 it is a timing diagram of the preferred embodiment shown in FIG. 3.
  • the substrate common mode resetter SUBR switches N2, N7, N8, N9, and N10 are turned on ,
  • the latch output nodes VP and VN are short-circuited, the upper plates of the AC coupling capacitors C1 and C2 are reset to the latch output common mode, and the lower plates are connected to the common mode level Vbcm.
  • the latch When the first clock signal CLKSP1 is high and the second clock signal CLKSP2 is low, the latch enters the sampling phase, the switches P1, N1, N2, N7, N8, N9, and N10 are all disconnected, and the latch
  • the output nodes VP and VN receive the input signal and first act on the gates of the cross-coupling transistors P2, P3, N3 and N4 to form the first input terminal of the latch; the output node voltage of the latch acts on the AC through the buffer
  • the upper plates of the coupling capacitors C1, C2, C3 and C4 then act on the substrates of the cross-coupling transistors P2, P3, N3 and N4 to form the second input terminal of the latch.
  • the transistors P1 and N1 are turned on, the latch enters the latching phase, and the output nodes VP and VN are used as the first input to sample
  • the input signal and the input signal sampled at the second input terminal formed by the substrate of the cross-coupled transistors P2, P3, N3 and N4 are output signal regeneration latch.
  • the first clock signal CLKSP1 and the second clock signal CLKSP2 are clock signals of equal magnitude and opposite phases.
  • the cross-coupled transistors P2, P3, N3, and N4 are used as the second input terminal, the bulk transconductance is increased on the basis of the traditional latch, which effectively accelerates the latch regeneration speed;
  • the AC coupling capacitors C1, C2, C3, and C4 are connected to the bottom plate of the reset level Vbcm during the reset phase, the threshold voltages of the cross-coupling transistors P2, P3, N3, and N4 are reduced during the sampling and latching process, and further Increase the metastable effective transconductance of the latch to improve the latch speed.
  • the present invention also provides an electronic device including the above-mentioned substrate-enhanced comparator.
  • the electronic device may be a circuit, an analog-to-digital converter, an analog-to-digital conversion system, and the like.
  • the circuit includes the aforementioned substrate-enhanced comparator.
  • the analog-to-digital converter includes: a sampling capacitor array, a dynamic comparator, and a primary and secondary approximation logic circuit.
  • the sampling capacitor array is used to sample an analog input signal and compare the sampled signal input After being processed by a comparator, the input is successively approximated to the logic circuit, and a digital signal is output.
  • the comparator is the substrate-enhanced comparator described in any of the above embodiments.
  • the analog-to-digital conversion system includes: an analog-to-digital converter, a digital processing and storage module circuit, and a switch array circuit.
  • the switch array circuit is used to control the analog-to-digital converter through on-off to input an analog signal
  • the analog-to-digital converter includes a sampling capacitor array, a comparator, and a primary and secondary approximation logic circuit.
  • the sampling capacitor array is used to sample an analog input signal, and the sampled signal
  • the input comparator is processed by the comparator, the input is successively approximated to the logic circuit, and the digital signal is output.
  • the comparator is the substrate-enhanced comparator described in any of the above embodiments.
  • the present invention additionally introduces the substrate input into the cross-coupling structure of the traditional latch, as the second input terminal of the latch, not only the body transconductance of the cross-coupled MOS tube is introduced into the input node, but also Enhance the positive feedback capability; and introduce a common mode signal into the substrate of the cross-coupled MOS tube to reduce the threshold of the cross-coupled MOS tube, thereby increasing the effective transconductance and speeding up the latch.
  • the substrate-enhanced latching technology can effectively improve the latching speed of the latch in the metastable state, breaking through the bottleneck of the traditional latching regeneration speed, which is limited by the characteristic frequency of the process and the power supply voltage. It can also be realized under the advanced low-voltage process Design of high-speed latch. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial value.

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  • Nonlinear Science (AREA)
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Abstract

一种基于衬底增强型的比较器及电子设备，该比较器包括：交叉耦合锁存器（1），用于将输入信号连接至交叉耦合MOS管的栅极形成锁存器的第一输入端；输出缓冲器（2），连接于交叉耦合锁存器（1），用于放大锁存器的输出信号；交流耦合器（3），连接于输出缓冲器（2），用于接收并放大锁存器输出信号，将输出信号耦合至交叉耦合锁存器（1）MOS管衬底形成锁存器的第二输入端；交叉耦合锁存器（1），还用于将第一输入端采样的输入信号与第二输入端采样的输入信号进行输出信号再生锁存。本方案在传统锁存器的交叉耦合结构中额外引入衬底输入，作为锁存器的第二输入端，不仅将交叉耦合MOS管的体跨导引入输入结点，而且增强正反馈能力，加快锁存器速度。

Description

基于衬底增强型的比较器及电子设备 技术领域
本发明涉及模数混合集成电路技术领域，特别是涉及一种基于衬底增强型的比较器及电子设备。
背景技术
比较器(Comparator)是诸多集成电路(IC)的重要组成模块，比如模数转换器(ADC)、跨导放大器(OTA)、电压基准源(VR)和时钟数据恢复电路(CDR)，通过检测差分输入电压产生对应输出，显示幅度较大的输入电压信息。在现代通信系统中，伴随着便携设备对更轻重量和更小尺寸的不断需求，迫切需要一种低压高速的比较器结构。
然而，随着先进CMOS工艺尺寸的缩小(已到40nm和28nm，甚至更小)，核心电路的电源电压也跟着降低，但MOS管的阈值电压却不能以相同的比例降低，这限制了比较器的共模输入范围；更重要的是，受到电源电压与工艺特征频率的限制，电源电压越低，比较器中的锁存器的速度越慢，根本无法在低压条件下(即，电源电压低于1.2V可视为低压)保持比较器高速工作。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于衬底增强型的比较器及电子设备，用于解决现有技术中锁存器速度因受限电源电压与工艺特征频率的限制，导致比较器无法在低压状况下实现高速问题。
为实现上述目的及其他相关目的，本发明提供一种基于衬底增强型的比较器，包括：
交叉耦合锁存器，用于将输入信号连接至交叉耦合MOS管的栅极形成锁存器的第一输入端；
输出缓冲器，连接于所述交叉耦合锁存器，用于放大锁存器的输出信号；
交流耦合器，连接于所述输出缓冲器，用于接收并放大的锁存器输出信号，将所述输出信号耦合至所述交叉耦合锁存器MOS管衬底形成锁存器的第二输入端；
所述交叉耦合锁存器，还用于将所述第一输入端采样的输入信号与第二输入端采样的输入信号进行输出信号再生锁存。
于本发明的另一目的在于提供一种电子设备，包括上述的基于衬底增强型的比较器。
如上所述，本发明的基于衬底增强型的比较器及电子设备，具有以下有益效果：
本发明在传统锁存器的交叉耦合结构中额外引入衬底输入，作为锁存器的第二输入端，不仅将交叉耦合MOS管的体跨导引入输入结点，而且增强正反馈能力，加快锁存器速度。
通过衬底增强锁存技术能够有效提高锁存器亚稳态锁存速度，突破传统锁存器锁存再生速度受限于工艺特征频率和电源电压的瓶颈限制，在先进低压工艺下也能实现高速锁存器的设计。
附图说明
图1显示为本发明提供的一种基于衬底增强型的比较器原理示意图；
图2显示为本发明提供的一种基于衬底增强型的比较器一实施例原理示意图；
图3显示为本发明提供的一种基于衬底增强型的比较器电路图；
图4显示为本发明提供的基于图3的一种基于衬底增强型的比较器时序图。
元件标号说明：
1   交叉耦合锁存器
2   输出缓冲器
3   交流耦合器
4   衬底共模复位器
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图1，本发明提供一种基于衬底增强型的比较器原理示意图，包括：
交叉耦合锁存器1，用于将输入信号连接至交叉耦合MOS管的栅极形成锁存器的第一输入端；
输出缓冲器2，连接于所述交叉耦合锁存器，用于放大锁存器的输出信号；
交流耦合器3，连接于所述输出缓冲器，用于接收并放大的锁存器输出信号，将所述输出信号耦合至所述交叉耦合锁存器MOS管衬底形成锁存器的第二输入端；
所述交叉耦合锁存器，还用于将所述第一输入端采样的输入信号与第二输入端采样的输入信号进行输出信号再生锁存；
其中，所述交叉耦合锁存器中MOS管衬底采用深阱工艺制作而成，用于隔离MOS管的衬底，与外界隔离使其衬底耦合噪声更小，防止串扰或相互影响。其中，所述输出缓冲器同向放大或反向放大输出信号，确保所述交叉耦合锁存器MOS管同侧的衬底与其对应该MOS管的栅极的输入信号相位相同，例如，晶体管P2与晶体管N3为同侧，晶体管P3与晶体管N4为另一同侧，即，晶体管P2衬底与其栅极的输入信号相位相同，晶体管N3衬底与其栅极的输入信号相位相同，其它参照上述描述即可。
具体地，所述交叉耦合锁存器在复位和锁存阶段，其对应的输出结点与输入结点为同一位置；当所述交叉耦合锁存器为采样阶段，该输入结点接收输入信号；当所述交叉耦合锁存器为锁存阶段，该输出结点进行正反馈输出信号再生。
在本实施例中，锁存器作为传统比较器的核心单元，采用正反馈对亚稳态信号进行再生锁存，而当前几乎所有锁存器都是采用交叉耦合反相器进行设计，该结构锁存速度受到工艺特征频率的限制，而且随着先进工艺技术的发展，半导体芯片电源电压越来越低，传统锁存器锁存速度受到严重限制。
而本实施例中，在传统锁存器的交叉耦合结构中额外引入衬底输入，作为锁存器的第二输入端，不仅将交叉耦合MOS管的体跨导引入输入结点，而且增强正反馈能力，加快锁存器速度。
在上述实施例中，请参照图2，为本发明提供的一种基于衬底增强型的比较器一实施例原理示意图，所述基于衬底增强型的比较器包括：
衬底共模复位器4，分别连接于所述交叉耦合锁存器、交流耦合器，用于复位阶段时对所述交流耦合器与交叉耦合MOS管衬底进行共模复位。
所述衬底共模复位器在复位阶段对锁存器的输出结点与交流耦合MOS管衬底进行复位，其对应的复位电压根据NMOS管与PMOS管各自的跨导分别连接不同的交流耦合器进行复位，其中，只要复位电压不使得对应的MOS管的PN结正向导通即可，PMOS管对应的复位电压越低越好，NMOS管对应的复位电压越高越好。
本发明在传统锁存器的交叉耦合结构中额外引入衬底输入，作为锁存器第二输入端，不仅将交叉耦合MOS管的体跨导引入输入结点，而且增强正反馈能力；而且在交叉耦合MOS 管的衬底引入共模信号，降低交叉耦合MOS管阈值，从而增加有效跨导，加快锁存器速度。
本发明衬底增强锁存技术能够有效提高锁存器亚稳态锁存速度，突破传统锁存器锁存再生速度受限于工艺特征频率和电源电压的瓶颈限制，在先进低压工艺下也能实现高速锁存器的设计。
如图3所示，为如图2本发明的优选实施例示例图，图2中晶体管P1、P2、P3、N 1、N2、N3和N4构成传统交叉耦合锁存器LatchT；晶体管P4\N5和P5\N6构成的推挽放大器作为输出缓冲器Buffer(第一输出缓冲器21与第二输出缓冲器21)；晶体管N7\N9和N8\N10构成衬底共模复位器SUBR(第一衬底共模复位器41与第二衬底共模复位器42)；电容C1、C2、C3与C4构成交流耦合器ACC(第一交流耦合器31与第二交流耦合器32)。
具体地，所述交流耦合锁存器包括晶体管P1、P2、P3、N1、N2、N3和N4，所述晶体管P1的栅极连接第一时钟信号，所述晶体管P1的源极连接电源电压，所述晶体管P1的漏极分别晶体管P2、P3的源极；第一输入信号连接由所述晶体管P2的漏极、晶体管P3的栅极、第一输入信号、晶体管N2、N3的漏极和晶体管N4的栅极共同连接构成的一输出结点；第二输入信号连接由所述晶体管P2的删极、晶体管P3的漏极、晶体管N2的源极、晶体管N3的栅极极和晶体管N4的漏极共同构成的二输出结点；所述晶体管N1的栅极连接第二时钟信号，所述晶体管N2的栅极连接第三时钟信号，所述晶体管N2的漏极分别连接晶体管N3、N4的源极，所述晶体管N1的源极接地；所述晶体管P2与N3的MOS管衬底互连构成交叉耦合锁存器MOS管一侧衬底；所述晶体管P3与N4的MOS管衬底互连构成交叉耦合锁存器MOS管另一侧衬底。
所述输出缓冲器2包括由晶体管P4与N5构成的第一输出缓冲器21和由晶体管P5与N6构成的第二输出缓冲器22，所述第一输出缓冲器21中晶体管P4与N5的栅极连接交流耦合锁存器的一输出端，所述晶体管P4源极接电源电压，所述晶体管N5源极接地，所述晶体管P4与N5的漏极互连作为第一输出缓冲器21的放大输出端；所述第二输出缓冲器22中晶体管P5与N6的栅极连接交流耦合锁存器的另一输出端，所述晶体管P5源极接电源电压，所述晶体管N6源极接地，所述晶体管P5与N6的漏极互连作为第二输出缓冲器22的放大输出端。
所述衬底共模复位器4包括由晶体管N7与N9构成的第一衬底共模复位器41和由晶体管N8与N10构成的第二衬底共模复位器42；所述第一衬底共模复位器41中晶体管N7、N9的栅极连接第三时钟信号，所述晶体管N7的漏极连接交流耦合锁存器的一输出端，所述晶体管N9的源极连接共模电平，所述晶体管N7的源、所述晶体管N9的漏极作为第一衬底共 模复位器41的两个输出端；所述第二衬底共模复位器42中晶体管N8、N10的栅极连接第三时钟信号，所述晶体管N8的漏极连接交流耦合锁存器的另一输出端，所述晶体管N10的源极连接共模电平，所述晶体管N8的源极、所述晶体管N10的漏极作为第二衬底共模复位器42的两个输出端。
所述交流耦合器3包括由第一电容与第三电容构成的第一交流耦合器31、由第二电容与第四电容构成第二交流耦合器32；而当比较器没有衬底共模复位器，交流耦合器的连接方式如下：
所述第一电容C1与第三电容C3的上级板连接第一输出缓冲器21的输出端，第一电容C1的下级板连接所述交叉耦合锁存器MOS管一侧的一个衬底，第三电容C3的下级板连接所述交叉耦合锁存器MOS管一侧的另一个衬底；所述第二电容C2、第四电容C4的上级板连接第二输出缓冲器的输出端，第二电容C2的下级板连接所述交叉耦合锁存器MOS管另一侧的一个衬底，第四电容C4的下级板连接所述交叉耦合锁存器MOS管另一侧的另一个衬底。而当比较器有衬底共模复位器，交流耦合器的连接方式如下：
所述第一电容、第三电容的上级板连接第一输出缓冲器的输出端与第一衬底共模复位器的一输出端，第一电容的下级板连接第一衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管一侧的一个衬底，第三电容的下级板连接第一衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管一侧的另一个衬底；所述第二电容、第四电容的上级板连接第二输出缓冲器的输出端与第二衬底共模复位器的一输出端，第二电容的下级板连接第二衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管另一侧的一个衬底，第四电容的下级板连接第二衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管另一侧的另一个衬底。
其中，第一电容C1与第二电容C2容值相同，分别对晶体管P2、P3提供复位电压，第三电容C3与第二电容C4容值相同，分别对晶体管N3、N4提供复位电压。
如图4所示，为如图3所示优选实施例时序关系图，当第三时钟信号CLKrst为高电平时，衬底共模复位器SUBR开关管N2、N7、N8、N9和N10导通，锁存器输出结点VP和VN短接，交流耦合电容C1和C2上极板被复位到锁存器输出共模，下极板与共模电平Vbcm连接。
当第一时钟信号CLKSP1为高电平且第二时钟信号CLKSP2为低电平时，锁存器进入采样相位，开关管P1、N1、N2、N7、N8、N9和N10都断开，锁存器输出结点VP和VN接收输入信号，首先作用于交叉耦合晶体管P2、P3、N3和N4的栅极，形成锁存器第一输入端；锁存器输出结点电压通过缓冲器Buffer作用于交流耦合电容C1、C2、C3和C4上极板，进 而作用于交叉耦合晶体管P2、P3、N3和N4的衬底，形成锁存器第二输入端。
当第一时钟信号CLKSP1为低电平且第二时钟信号CLKSP2为高电平时，晶体管P1和N1导通，锁存器进入锁存相位，根据输出结点VP、VN作为第一输入端采样到的输入信号和交叉耦合晶体管P2、P3、N3和N4的衬底形成的第二输入端采样到的输入信号进行输出信号再生锁存。
其中，第一时钟信号CLKSP1与第二时钟信号CLKSP2大小相等、相位相反的时钟信号。
锁存过程中，一方面由于采用了将交叉耦合晶体管P2、P3、N3和N4用作第二输入端，在传统锁存器的基础上增加了体跨导，有效加快锁存再生速度；另一方面由于在复位阶段将交流耦合电容C1、C2、C3和C4下极板接入复位电平Vbcm，使得在采样和锁存过程中交叉耦合晶体管P2、P3、N3和N4阈值电压降低，进一步增加锁存器亚稳态有效跨导，提高锁存速度。
本发明还提供了一种电子设备，包括上述的衬底增强型的比较器，该电子设备可为一种电路、模数转换器、模数转换系统等。
在本实施例中，所述电路包括上述衬底增强型的比较器。
在本实施例中，所述模数转换器包括：采样电容阵列、动态比较器以及主次逼近逻辑电路，所述采样电容阵列用于对模拟输入信号进行采样，并将采样后的信号输入比较器，经过比较器处理后，输入逐次逼近逻辑电路，输出数字信号，所述比较器为上述任意一个实施例中所述的衬底增强型的比较器。
在本实施例中，所述模数转换系统包括：模数转换器、数字处理及存储模块电路以及开关阵列电路，开关阵列电路用于通过通断对模数转换器进行控制，以输入模拟信号以及模数转换器的直流失调校准，所述模数转换器包括采样电容阵列、比较器以及主次逼近逻辑电路，所述采样电容阵列用于对模拟输入信号进行采样，并将采样后的信号输入比较器，经过比较器处理后，输入逐次逼近逻辑电路，输出数字信号，所述比较器为上述任一实施例中所述的衬底增强型的比较器。
综上所述，本发明在传统锁存器的交叉耦合结构中额外引入衬底输入，作为锁存器的第二输入端，不仅将交叉耦合MOS管的体跨导引入输入结点，而且增强正反馈能力；而且在交叉耦合MOS管的衬底引入共模信号，降低交叉耦合MOS管阈值，从而增加有效跨导，加快锁存器速度。通过衬底增强锁存技术能够有效提高锁存器亚稳态锁存速度，突破传统锁存器锁存再生速度受限于工艺特征频率和电源电压的瓶颈限制，在先进低压工艺下也能实现高速锁存器的设计。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (12)

  1. 一种基于衬底增强型的比较器，其特征在于，包括：
    交叉耦合锁存器，用于将输入信号连接至交叉耦合MOS管的栅极形成锁存器的第一输入端；
    输出缓冲器，连接于所述交叉耦合锁存器，用于放大锁存器的输出信号；
    交流耦合器，连接于所述输出缓冲器，用于接收并放大的锁存器输出信号，将所述输出信号耦合至所述交叉耦合锁存器MOS管衬底形成锁存器的第二输入端；
    所述交叉耦合锁存器，还用于将所述第一输入端采样的输入信号与第二输入端采样的输入信号进行输出信号再生锁存。
  2. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述交叉耦合锁存器中MOS管衬底采用深阱工艺制作而成。
  3. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述交叉耦合锁存器在复位和锁存阶段，其对应的输出结点与输入结点为同一位置；当所述交叉耦合锁存器为采样阶段，该输入结点接收输入信号；当所述交叉耦合锁存器为锁存阶段，该输出结点进行正反馈输出信号再生。
  4. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述输出缓冲器同向放大或反向放大输出信号，确保所述交叉耦合锁存器MOS管同侧的衬底与其对应该MOS管的栅极的输入信号相位相同。
  5. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，还包括：衬底共模复位器，分别连接于所述交叉耦合锁存器、交流耦合器，用于复位阶段时对所述交流耦合器与交叉耦合MOS管衬底进行共模复位。
  6. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述衬底共模复位器在复位阶段对锁存器的输出结点与交流耦合MOS管衬底进行复位，其对应的复位电压根据NMOS管与PMOS管各自的跨导分别连接不同的交流耦合器进行复位。
  7. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述交流耦合锁存器包括晶体管P1、P2、P3、N1、N2、N3和N4，所述晶体管P1的栅极连接第一时钟信号，所 述晶体管P1的源极连接电源电压，所述晶体管P1的漏极分别晶体管P2、P3的源极；第一输入信号连接由所述晶体管P2的漏极、晶体管P3的栅极、第一输入信号、晶体管N2、N3的漏极和晶体管N4的栅极共同连接构成的一输出结点；第二输入信号连接由所述晶体管P2的删极、晶体管P3的漏极、晶体管N2的源极、晶体管N3的栅极极和晶体管N4的漏极共同构成的二输出结点；所述晶体管N1的栅极连接第二时钟信号，所述晶体管N2的栅极连接第三时钟信号，所述晶体管N2的漏极分别连接晶体管N3、N4的源极，所述晶体管N1的源极接地；所述晶体管P2与N3的MOS管衬底互连构成交叉耦合锁存器MOS管一侧衬底；所述晶体管P3与N4的MOS管衬底互连构成交叉耦合锁存器MOS管另一侧衬底。
  8. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述输出缓冲器包括由晶体管P4与N5构成的第一输出缓冲器和由晶体管P5与N6构成的第二输出缓冲器，所述第一输出缓冲器中晶体管P4与N5的栅极连接交流耦合锁存器的一输出端，所述晶体管P4源极接电源电压，所述晶体管N5源极接地，所述晶体管P4与N5的漏极互连作为第一输出缓冲器的放大输出端；所述第二输出缓冲器中晶体管P5与N6的栅极连接交流耦合锁存器的另一输出端，所述晶体管P5源极接电源电压，所述晶体管N6源极接地，所述晶体管P5与N6的漏极互连作为第二输出缓冲器的放大输出端。
  9. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述交流耦合器包括由第一电容与第三电容构成的第一交流耦合器、由第二电容与第四电容构成第二交流耦合器；所述第一电容与第三电容的上级板连接第一输出缓冲器的输出端，第一电容的下级板连接所述交叉耦合锁存器MOS管一侧的一个衬底，第三电容的下级板连接所述交叉耦合锁存器MOS管一侧的另一个衬底；所述第二电容、第四电容的上级板连接第二输出缓冲器的输出端，第二电容的下级板连接所述交叉耦合锁存器MOS管另一侧的一个衬底，第四电容的下级板连接所述交叉耦合锁存器MOS管另一侧的另一个衬底。
  10. 根据权利要求1所述的基于衬底增强型的比较器，其特征在于，所述衬底共模复位器包括由晶体管N7与N9构成的第一衬底共模复位器和由晶体管N8与N10构成的第二衬底共模复位器；所述第一衬底共模复位器中晶体管N7、N9的栅极连接第三时钟信号，所述晶体管N7的漏极连接交流耦合锁存器的一输出端，所述晶体管N9的源极连接共模电平，所述晶体管N7的源、所述晶体管N9的漏极作为第一衬底共模复位器的两输 出端；所述第二衬底共模复位器中晶体管N8、N10的栅极连接第三时钟信号，所述晶体管N8的漏极连接交流耦合锁存器的另一输出端，所述晶体管N10的源极连接共模电平，所述晶体管N8的源极、所述晶体管N10的漏极作为第二衬底共模复位器的两输出端。
  11. 根据权利要求10所述的基于衬底增强型的比较器，其特征在于，所述交流耦合器包括由第一电容与第三电容构成的第一交流耦合器、由第二电容与第四电容构成第二交流耦合器；所述第一电容、第三电容的上级板连接第一输出缓冲器的输出端与第一衬底共模复位器的一输出端，第一电容的下级板连接第一衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管一侧的一个衬底，第三电容的下级板连接第一衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管一侧的另一个衬底；所述第二电容、第四电容的上级板连接第二输出缓冲器的输出端与第二衬底共模复位器的一输出端，第二电容的下级板连接第二衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管另一侧的一个衬底，第四电容的下级板连接第二衬底共模复位器的另一输出端、所述交叉耦合锁存器MOS管另一侧的另一个衬底。
  12. 一种电子设备，其特征在于：所述电子设备包括权利要求1-11中任一项所述的比较器。
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