WO2020217850A1 - Condensateur - Google Patents

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Publication number
WO2020217850A1
WO2020217850A1 PCT/JP2020/013998 JP2020013998W WO2020217850A1 WO 2020217850 A1 WO2020217850 A1 WO 2020217850A1 JP 2020013998 W JP2020013998 W JP 2020013998W WO 2020217850 A1 WO2020217850 A1 WO 2020217850A1
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WO
WIPO (PCT)
Prior art keywords
conductive layer
capacitor
normal direction
electrode
continuous groove
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Application number
PCT/JP2020/013998
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English (en)
Japanese (ja)
Inventor
青路 日▲高▼
斉 松野
俊輔 安部
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株式会社村田製作所
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Publication of WO2020217850A1 publication Critical patent/WO2020217850A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 

Definitions

  • the present invention relates to a capacitor.
  • Patent Document 1 As a prior art document that discloses the configuration of a capacitor, there is US Patent Application Publication No. 2017/0104057 (Patent Document 1).
  • the capacitor described in Patent Document 1 has a trench extending from the upper surface of the substrate to the inside of the substrate, and has a first layered electrode, a first electrically insulating layer arranged on the first layered electrode, and a first layer. It includes a second layer electrode arranged on one electrically insulating layer, and a plurality of contact pads electrically connected to each of the first layer electrode and the second layer electrode. A plurality of columnar portions are distributed in the trench.
  • a continuous groove is formed in an annular shape around the first contact pad between the first contact pad and the second contact pad when viewed from the normal direction of the substrate. .. Further, a columnar portion that is a part of the substrate is located inside the continuous groove. Therefore, the power supply path between the inner peripheral side and the outer peripheral side of the annular continuous groove is long.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a capacitor capable of suppressing a decrease in capacitance when connected to a high-frequency circuit.
  • the capacitor based on the present invention includes a substrate, a first conductive layer, a first dielectric layer, a second conductive layer, a first electrode, and a second electrode.
  • the substrate includes a first main surface and a second main surface. The second main surface is located on the opposite side of the first main surface.
  • the first conductive layer is laminated above the first main surface so as to be located along the first main surface.
  • the first dielectric layer is laminated on the upper side or the lower side of the first conductive layer.
  • the second conductive layer is laminated so as to face the first conductive layer with the first dielectric layer interposed therebetween.
  • the first electrode is connected to the first conductive layer.
  • the second electrode is connected to the second conductive layer.
  • At least one continuous groove formed continuously is formed on the first main surface when viewed from the normal direction of the second main surface. Inside the at least one continuous groove, at least one columnar portion that is a part of the substrate is located. Each of the first conductive layer, the first dielectric layer, and the second conductive layer is located along the inner surface of at least one continuous groove and the outer surface of at least one columnar portion. Seen from the normal direction, at least one continuous groove is located on a virtual ring surrounding a first contact region in which the first electrode and the first conductive layer are in contact with each other. The second contact region where the second electrode and the second conductive layer are in contact with each other when viewed from the normal direction is located outside the virtual ring. When viewed from the normal direction, an open portion where the at least one continuous groove is not located is provided in a part of the virtual ring.
  • FIG. 1 It is a top view which shows the structure of the capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which saw the capacitor shown in FIG. 1 from the direction of the arrow of line II-II. It is sectional drawing which saw the capacitor shown in FIG. 1 from the direction of the arrow of line III-III. It is a partial cross-sectional view of the capacitor shown in FIG. 1 as seen from the direction of the arrow along line IV-IV. It is a top view which shows the structure of the capacitor which concerns on 1st modification of Embodiment 1 of this invention. It is a partially enlarged view of the substrate in the region VI of the capacitor shown in FIG.
  • FIG. 5 is a cross-sectional view of the capacitor shown in FIG. 10 as viewed from the direction of the arrow along the XI-XI line. It is a top view which shows only the outer shape of each of a continuous groove and a columnar part in the capacitor which concerns on Embodiment 4 of this invention.
  • FIG. 1 is a plan view showing a configuration of a capacitor according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the capacitor shown in FIG. 1 as viewed from the direction of the arrow on line II-II.
  • FIG. 3 is a cross-sectional view of the capacitor shown in FIG. 1 as viewed from the direction of the arrow along line III-III.
  • FIG. 4 is a partial cross-sectional view of the capacitor shown in FIG. 1 as viewed from the direction of the arrow along the IV-IV line.
  • a plurality of other layers described later are not shown.
  • the capacitor 100 includes the substrate 110, the first conductive layer 120, the first dielectric layer 125, the second conductive layer 130, and the first. It includes an electrode 150 and a second electrode 160.
  • the substrate 110 includes a first main surface 111 and a second main surface 112.
  • the second main surface 112 is located on the opposite side of the first main surface 111.
  • the substrate 110 is made of, for example, silicon.
  • the first conductive layer 120 is laminated above the first main surface 111 so as to be located along the first main surface 111. In the present embodiment, the first conductive layer 120 is laminated on the first main surface 111.
  • the first dielectric layer 125 is laminated on the upper side or the lower side of the first conductive layer 120. In the present embodiment, the first dielectric layer 125 is laminated on the upper side of the first conductive layer 120.
  • the second conductive layer 130 is laminated so as to face the first conductive layer 120 with the first dielectric layer 125 interposed therebetween.
  • the second conductive layer 130 is laminated on the upper side of the first dielectric layer 125.
  • the capacitor 100 according to this embodiment further includes a second dielectric layer 135.
  • the second dielectric layer 135 is laminated on the upper side of the second conductive layer 130.
  • the capacitor 100 according to this embodiment further includes a third conductive layer 140.
  • the third conductive layer 140 is laminated on the upper side of the second dielectric layer 135.
  • Each of the first conductive layer 120, the second conductive layer 130, and the third conductive layer 140 may be made of the same material as each other, or may be made of different materials from each other.
  • the first conductive layer 120 is composed of, for example, an n-type semiconductor, and is specifically an n ++ layer.
  • Each of the second conductive layer 130 and the third conductive layer 140 is made of, for example, polycrystalline silicon.
  • the first conductive layer 120 is formed by implanting impurities such as phosphorus (P) into a substrate 110 made of silicon by an ion implantation method.
  • each of the second conductive layer 130 and the third conductive layer 140 is laminated by a chemical vapor deposition (CVD) method or the like.
  • CVD chemical vapor deposition
  • Each of the first dielectric layer 125 and the second dielectric layer 135 may be made of the same material as each other, or may be made of different materials from each other.
  • Each of the first dielectric layer 125 and the second dielectric layer 135 is composed of, for example, a laminated structure of a silicon oxide film and a silicon nitride film. Specifically, the laminated structure, SiN X layer between two SiO 2 layers are constructed by position.
  • Each of the first dielectric layer 125 and the second dielectric layer 135 is laminated by, for example, a plasma CVD method.
  • the first electrode 150 is connected to the first conductive layer 120.
  • the first electrode 150 is laminated on the first conductive layer 120.
  • the first electrode 150 is positioned so as to be separated from the other conductive layers laminated above the first conductive layer 120.
  • the first electrode 150 is positioned so as to be separated from each of the second conductive layer 130 and the third conductive layer 140.
  • the first electrode 150 has a polygonal outer shape when viewed from the normal direction of the second main surface 112, and specifically, has an octagonal outer shape. ..
  • the outer shape of the first electrode 150 is not limited to the above shape.
  • the second electrode 160 is connected to the second conductive layer 130.
  • the second electrode 160 is laminated on the second conductive layer 130.
  • the second electrode 160 is located so as to be separated from the other conductive layers laminated above the second conductive layer 130. Specifically, the second electrode 160 is positioned so as to be separated from each of the third conductive layer 140.
  • the second electrode 160 has a polygonal outer shape when viewed from the normal direction of the second main surface 112, and specifically, has a hexagonal outer shape. ..
  • the outer shape of the second electrode 160 is not limited to the above shape.
  • the capacitor 100 according to the present embodiment further includes a third electrode 170.
  • the third electrode 170 is laminated on the third conductive layer 140.
  • the third electrode 170 has a polygonal outer shape when viewed from the normal direction of the second main surface 112, and specifically, has a rectangular outer shape. ..
  • the outer shape of the third electrode 170 is not limited to the above shape.
  • Each of the first electrode 150, the second electrode 160, and the third electrode 170 may be made of the same material as each other, or may be made of different materials from each other.
  • each of the first electrode 150, the second electrode 160, and the third electrode 170 is a thin film, and is made of, for example, aluminum.
  • Each of the first electrode 150, the second electrode 160, and the third electrode 170 is provided by, for example, a sputtering method.
  • At least one continuous groove 113 formed continuously is formed on the first main surface 111 when viewed from the normal direction of the second main surface 112.
  • a plurality of continuous grooves 113 may be formed so as to be separated from each other.
  • four continuous grooves 113 are formed so as to be separated from each other.
  • the groove width is substantially constant in the extending direction of the continuous groove 113.
  • the continuous groove 113 is formed by etching the substrate 110.
  • At least one columnar portion 115 which is a part of the substrate 110, is located inside at least one continuous groove 113.
  • a plurality of columnar portions 115 arranged apart from each other are located as at least one columnar portion 115 inside each of the at least one continuous groove 113. There is.
  • each of the first conductive layer 120, the first dielectric layer 125, the second conductive layer 130, the second dielectric layer 135, and the third conductive layer 140 is the inner surface of at least one continuous groove 113. It is located along the outer surface 116 of 114 and at least one column 115. As a result, the facing area between the first conductive layer 120 and the second conductive layer 130 and the facing area between the second conductive layer 130 and the third conductive layer 140 can be increased.
  • each of the plurality of columnar portions 115 has three extending portions extending in the radial direction about the center of the columnar portion 115. .. When viewed from the normal direction, each of the three extending portions is located so as to be evenly spaced from each other in the circumferential direction centered on the center of the columnar portion 115.
  • each of the extending portions of the plurality of columnar portions 115 faces between the extending portions of the adjacent columnar portions 115 that are closest to each other. It is extended.
  • the columnar portions 115 can be densely arranged, and each of the facing area between the first conductive layer 120 and the second conductive layer 130 and the facing area between the second conductive layer 130 and the third conductive layer 140. Can be increased.
  • the groove width of the continuous groove 113 located between the columnar portions 115 adjacent to each other is substantially the same as the groove width of the other portion of the continuous groove 113.
  • the outer shape of the columnar portion 115 when viewed from the above normal direction is not limited to the outer shape formed by the three extending portions.
  • the outer shape of the columnar portion 115 when viewed from the normal direction may be a circular shape or a polygonal shape such as a hexagonal shape.
  • the columnar portion 115 is formed as a part of the substrate 110 that has not been etched when viewed from the normal direction when the continuous groove 113 is formed by etching the substrate 110. That is, the upper surface portion of the outer surface 116 of the columnar portion 115 is located on the same plane as the first main surface outside the continuous groove 113.
  • At least one continuous groove 113 when viewed from the normal direction surrounds a first contact region R1 in which the first electrode 150 and the first conductive layer 120 are in contact with each other. It is located on the virtual ring C. Seen from the normal direction, the inner peripheral edge of the virtual ring is in contact with at least a part of the continuous groove 113. When a plurality of continuous grooves 113 are formed as the continuous grooves 113 apart from each other, the inner peripheral edge of the virtual ring is formed on at least a part of each of the plurality of continuous grooves 113 when viewed from the normal direction. I'm in contact. Seen from the normal direction, the outer peripheral edge of the virtual ring is in contact with a part of the continuous groove 113.
  • the outer peripheral edge of the virtual ring is formed on at least a part of each of the plurality of continuous grooves 113 when viewed from the normal direction. I'm in contact.
  • the second contact region R2 in which the second electrode 160 and the second conductive layer 130 are in contact with each other when viewed from the normal direction is located outside the virtual ring C.
  • four second contact regions R2 are arranged outside the virtual ring C.
  • an open portion 117 in which at least one continuous groove 113 is not located is provided in a part of the virtual ring C when viewed from the normal direction.
  • a plurality of open portions 117 are provided on the virtual ring C when viewed from the normal direction.
  • the four open portions 117 are provided. Is provided.
  • the second contact region R2 is located at a position different from that on the straight line connecting the first contact region R1 and the open portion 117 when viewed from the normal direction.
  • the capacitor 100 further includes a first extraction electrode 180A and a second extraction electrode 180B.
  • the first extraction electrode 180A is located above each of the first electrode 150 and the third electrode 170, in a direction parallel to the second main surface 112. It extends in one direction. As shown in FIG. 2, the first extraction electrode 180A has a plurality of connecting portions extending downward so as to correspond to each of the first electrode 150 and the third electrode 170. The first extraction electrode 180A is connected to each of the first electrode 150 and the third electrode 170 at each of the plurality of connection portions. That is, the first conductive layer 120 connected to the first electrode 150 and the third conductive layer 140 connected to the third electrode 170 are configured to have the same potential.
  • Each of the first drawer electrode 180A and the second drawer electrode 180B may be made of the same material as each other, or may be made of different materials from each other.
  • Each of the first extraction electrode 180A and the second extraction electrode 180B is composed of, for example, an Al—Si—Cu-based alloy composed of aluminum, silicon, and copper.
  • Each of the first extraction electrode 180A and the second extraction electrode 180B is provided by, for example, a sputtering method or the like.
  • the capacitor 100 further includes a plurality of other layers 190.
  • the other plurality of layers 190 include a protective layer 191 and a first external dielectric layer 192, a second external dielectric layer 193, and a third external dielectric layer 194.
  • the first external dielectric layer 192 is located at least between each of the first extraction electrode 180A and the second extraction electrode 180B and the protective layer 191 in the above normal direction.
  • the second external dielectric layer 193 is laminated on at least above each of the first extraction electrode 180A and the second extraction electrode 180B in the above normal direction.
  • the protective layer 191 and the first external dielectric layer 192, the second external dielectric layer 193, and the third external dielectric layer 194 are made of an insulating material, and the types of the materials are particularly limited. Not done.
  • Each of the protective layer 191 and the first external dielectric layer 192, the second external dielectric layer 193, and the third external dielectric layer 194 are made of, for example, silicon dioxide (SiO 2 ) or the like.
  • each of the first conductive layer 120, the first dielectric layer 125, and the second conductive layer 130 has an inner surface 114 of at least one continuous groove 113 and It is located along the outer surface 116 of at least one columnar portion 115. Seen from the normal direction, at least one continuous groove 113 is located on the virtual ring C surrounding the first contact region R1 in which the first electrode 150 and the first conductive layer 120 are in contact with each other.
  • the second contact region R2 in which the second electrode 160 and the second conductive layer 130 are in contact with each other when viewed from the normal direction is located outside the virtual ring C.
  • an open portion 117 in which at least one continuous groove 113 is not located is provided on a part of the virtual ring C.
  • the above-mentioned open portion 117 allows the first conductive layer 120 to be planar from the first contact region R1 located on the inner peripheral side of the virtual ring C to the outer peripheral side region of the virtual ring C.
  • a power supply path is secured that passes only through the portion stacked on the floor.
  • a power feeding path passing through only the flatly stacked portion of the second conductive layer 130. Is secured.
  • the capacitor 100 is connected to the high frequency circuit, the electric charges from the first electrode 150 and the electric charges from the second electrode 160 can be easily applied to the outer peripheral side and the inner peripheral side of the virtual ring C, respectively. Will be sent to. As a result, it is possible to suppress a decrease in the capacitance of the capacitor 100.
  • a plurality of columnar portions 115 arranged apart from each other are located as at least one columnar portion 115 inside each of the at least one continuous groove 113. There is.
  • the facing area between the first conductive layer 120 and the second conductive layer 130 can be increased, so that the capacitance of the capacitor 100 can be increased.
  • a plurality of open portions 117 are provided on the virtual ring C when viewed from the normal direction.
  • FIG. 5 is a plan view showing the configuration of the capacitor according to the first modification of the first embodiment of the present invention.
  • FIG. 6 is a partially enlarged view of the substrate in the region VI of the capacitor shown in FIG.
  • two open portions 117a are provided on the virtual ring C when viewed from the normal direction.
  • each of the inner surface 114a of the continuous groove 113a and the outer surface 116a of the columnar portion 115a of the capacitor 100a according to the first modification of the first embodiment of the present invention is the capacitor 100 according to the first embodiment of the present invention. It has an area-increased portion 118 whose area is increased with respect to each of the inner surface 114 of the continuous groove 113 and the outer surface 116 of the columnar portion 115. In the present modification, the area-increasing portion 118 is larger than the area-decreasing portion 119 in which the area is reduced with respect to the inner surface 114 and the outer surface 116 in the first embodiment of the present invention. Therefore, when the capacitor 100a is connected to a low-frequency circuit, the capacitor 100a according to the first modification of the first embodiment of the present invention has a capacitance with respect to the capacitor 100 according to the first embodiment of the present invention. Becomes larger.
  • FIG. 7 is a plan view showing the configuration of the capacitor according to the second modification of the first embodiment of the present invention.
  • FIG. 8 is a partially enlarged view of the substrate in the capacitor region VIII shown in FIG. 7.
  • At least one columnar portion 115b is formed inside each of the at least one continuous groove 113b. Only one columnar portion 115b is located.
  • the number of open portions 117 can be increased by reducing the area per continuous groove 113 when viewed from the normal direction. As a result, it is possible to further increase the number of feeding paths that pass through only the flatly stacked portions of each of the first conductive layer 120 and the second conductive layer 130.
  • each of the inner surface 114b of the continuous groove 113b of the capacitor 100b and the outer surface 116b of the columnar portion 115b according to the second modification of the first embodiment of the present invention relates to the first embodiment of the present invention. It has an area-increasing portion 118 whose area is increased with respect to each of the inner surface 114 of the continuous groove 113 of the capacitor 100 and the outer surface 116 of the columnar portion 115.
  • the area-increasing portion 118 is smaller than the area-decreasing portion 119 in which the area is reduced with respect to the inner surface 114 and the outer surface 116 in the first embodiment of the present invention. Therefore, when the capacitor 100a is connected to a low-frequency circuit, the capacitor 100a according to the second modification of the first embodiment of the present invention is electrostatically charged with respect to the capacitor 100 according to the first embodiment of the present invention. The capacity becomes smaller.
  • the capacitor 100b according to the second modification of the first embodiment of the present invention has eight open portions 117b.
  • the capacitor 100b according to the present modification can increase the capacitance with respect to the capacitor 100 according to the first embodiment of the present invention.
  • the capacitor according to the second embodiment of the present invention is mainly different from the capacitor 100a according to the first modification of the first embodiment of the present invention in that it includes a plurality of first electrodes. Therefore, the description of the same configuration as that of the capacitor according to the first modification of the first embodiment of the present invention will not be repeated.
  • FIG. 9 is a plan view showing the configuration of the capacitor according to the second embodiment of the present invention.
  • the capacitor 200 according to the second embodiment of the present invention includes a plurality of first electrodes 150 and a plurality of second electrodes 160.
  • Each of the plurality of second electrodes 160 is located so as to correspond to each of the plurality of first electrodes 150.
  • each of the plurality of first electrodes 150 and the plurality of second electrodes 160 are arranged in a staggered pattern when viewed from the normal direction.
  • At least one continuous groove 113 is located on each of the virtual rings C of the above.
  • the second electrode 160 corresponding to each of the plurality of first electrodes 150 and the plurality of second contact regions R2 in which the second conductive layer 130 is in contact with each other correspond to each other. It is located outside the plurality of virtual rings C.
  • an opening portion 117a is provided in a part of each of the plurality of virtual rings C.
  • the capacitor 200 includes the plurality of first electrodes 150 and the plurality of second electrodes 160, the opening portion 117a corresponding to each of the plurality of first electrodes 150 is provided. As a result, a power feeding path is secured in each of the first conductive layer 120 and the second conductive layer 130 so as to pass only through the flatly laminated portions. As a result, it is possible to suppress a decrease in the capacitance of the capacitor 200.
  • the capacitor according to the third embodiment of the present invention is mainly characterized in that the upper layer of the first conductive layer and the second conductive layer is separated when viewed from the normal direction. It is different from the capacitor 200 according to the second embodiment. Therefore, the description of the configuration similar to that of the capacitor according to the second embodiment of the present invention will not be repeated.
  • FIG. 10 is a plan view showing the configuration of the capacitor according to the third embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of the capacitor shown in FIG. 10 as viewed from the direction of the arrow along the XI-XI line.
  • the capacitor 300 As shown in FIG. 10, in the capacitor 300 according to the third embodiment of the present invention, four open rings C are formed on a plurality of virtual rings C corresponding to each of the plurality of first electrodes 150 when viewed from the normal direction. A portion 117 is provided.
  • the second electrode 160 located closest to each of the plurality of first electrodes 150 when viewed from the normal direction is different for each first electrode 150. It is arranged like this.
  • the upper layer of the first conductive layer 120 and the second conductive layer 130 is viewed from the normal direction. Sometimes, they are separated further outside the second electrode 160 corresponding to each of the plurality of first electrodes 150 so as to correspond one-to-one with each of the plurality of first electrodes 150.
  • the capacitor 300 can include a plurality of layers located above the first conductive layer 120 and the second conductive layer 130. That is, the capacitor 300 can be used as a multi-terminal capacitor in which each of the plurality of layers is provided as a plurality of terminals having different potentials from each other.
  • the capacitor 300 can be incorporated into a power distribution network (PDN: Power Distribution Network) of a digital IC.
  • PDN Power Distribution Network
  • the second conductive layer 130 since the second conductive layer 130 is separated, a plurality of second conductive layers 130 are formed. Further, in the present embodiment, the first dielectric layer 125, the second dielectric layer 135, the third conductive layer 140, the first extraction electrode 180A and the second extraction electrode 180B are also second conductive in the above normal direction. It is separated at the same position as the separation position 395 of the layer 130. Of the separation positions 395, between each of the plurality of first dielectric layers 125, between each of the plurality of second conductive layers 130, between each of the plurality of second dielectric layers 135, and a plurality of third conductive layers. A protective layer 191 is located between each of the layers 140. Of the above separation positions, the second external dielectric layer 193 is located between each of the plurality of first extraction electrodes 180A and the plurality of second extraction electrodes 180B.
  • the capacitor according to the fourth embodiment of the present invention differs from the capacitor 200 according to the second embodiment only in the outer shape of the continuous groove and the columnar portion in the substrate 110 when viewed from the normal direction. Therefore, the description of the configuration similar to that of the capacitor according to the second embodiment of the present invention will not be repeated.
  • FIG. 12 is a plan view showing only the outer shapes of the continuous groove and the columnar portion in the capacitor according to the fourth embodiment of the present invention. As shown in FIG. 12, in the fourth embodiment of the present invention, each of the plurality of columnar portions 415 when viewed from the normal direction has a rectangular outer shape.
  • FIG. 13 is a plan view showing only the outer shapes of the continuous groove and the columnar portion in the capacitor according to the comparative example.
  • the capacitor 900 according to the comparative example is different from the configuration of the capacitor 400 according to the fourth embodiment of the present invention mainly in that the opening portion is not provided.
  • the depth of each of the continuous groove 413 of the capacitor 400 according to the fourth embodiment of the present invention and the continuous groove 913 of the capacitor 900 according to the comparative example was 55 ⁇ m.
  • FIG. 14 is a graph showing changes in capacitance depending on the frequency of the connected power supply for each of the capacitor according to the fourth embodiment of the present invention and the capacitor according to the comparative example.
  • the capacitor 400 having the open portion 417 has an open portion.
  • the capacitance is larger than that of the non-capacitor 900.
  • FIG. 15 is a diagram showing an example of the electric field strength distribution on the inner surface of the continuous groove when a high frequency power supply is connected to the capacitor according to the comparative example.
  • the frequency of the high frequency power supply was set to 1 GHz.
  • the inner surface 914 on the first contact region R1 side of the continuous groove 913 and the inner surface 914 on the side opposite to the first contact region R1 side are electrolyzed.
  • the difference in strength is large. That is, in the capacitor 900 having no open portion, either the inner surface 914 on the first contact region R1 side or the inner surface 914 on the opposite side of the first contact region R1 side of the continuous groove 913 when connected to the high frequency power supply. It can be seen that the charges are unevenly distributed in.
  • FIG. 16 is a diagram showing an example of the electrolytic intensity distribution on the inner surface of the continuous groove when a high frequency power supply is connected to the capacitor according to the fourth embodiment of the present invention.
  • the phase of the high frequency power supply in the electric field strength distribution shown in FIG. 15 and the phase of the high frequency power supply in the electric field strength distribution shown in FIG. 16 are the same as each other.
  • the frequency of the high frequency power supply was set to 1 GHz.
  • the capacitor 400 according to the fourth embodiment of the present invention is in first contact with the inner surface 414 on the first contact region R1 side of the continuous groove 413 as compared with the capacitor 900 according to the comparative example.
  • the difference in electric field strength from the inner surface 414 on the side opposite to the region R1 side is reduced.
  • the electric charge supplied from the first contact region R1 and the second contact region R2 by the opening portion 417 is the outer circumference of the virtual ring in which the continuous groove 413 is located. It becomes easy to supply to each of the side and the inner peripheral side. As a result, it is possible to suppress a decrease in the capacitance of the capacitor 400.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Selon l'invention, une première couche conductrice (120), une première couche diélectrique (125) et des secondes couches conductrices (130) sont individuellement positionnées de façon à se trouver le long de la surface interne (114) d'au moins une rainure continue (113) et de la surface externe (116) d'au moins une partie en colonne (115). Observée dans la direction normale, ladite rainure continue (113) est positionnée sur un anneau virtuel (C) entourant une première région de contact (R1) au niveau de laquelle une première électrode (150) et la première couche conductrice (120) sont en contact l'une avec l'autre. Observées dans la direction normale, des secondes régions de contact (R2), au niveau desquelles des secondes électrodes (160) et les secondes couches conductrices (130) sont respectivement en contact les unes avec les autres, sont positionnées à l'extérieur de l'anneau virtuel (C). Observées dans la direction normale, des parties ouvertes (117) au niveau desquelles ladite rainure continue (113) n'est pas positionnée sont ménagées sur des parties de l'anneau virtuel (C).
PCT/JP2020/013998 2019-04-24 2020-03-27 Condensateur WO2020217850A1 (fr)

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US20170104057A1 (en) * 2015-10-08 2017-04-13 Ipdia Capacitor 3d-cell and 3d-capacitor structure
WO2018054828A1 (fr) * 2016-09-20 2018-03-29 Murata Integrated Passive Solutions Structure de condensateur 3d
WO2019002931A1 (fr) * 2017-06-30 2019-01-03 Murata Manufacturing Co., Ltd. Structure de filtre lc distribuée
WO2019058922A1 (fr) * 2017-09-19 2019-03-28 株式会社村田製作所 Condensateur

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