WO2020211142A1 - 显示面板、芯片及柔性电路板 - Google Patents

显示面板、芯片及柔性电路板 Download PDF

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Publication number
WO2020211142A1
WO2020211142A1 PCT/CN2019/087583 CN2019087583W WO2020211142A1 WO 2020211142 A1 WO2020211142 A1 WO 2020211142A1 CN 2019087583 W CN2019087583 W CN 2019087583W WO 2020211142 A1 WO2020211142 A1 WO 2020211142A1
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WO
WIPO (PCT)
Prior art keywords
line
display panel
circuit board
flexible circuit
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/087583
Other languages
English (en)
French (fr)
Inventor
邹恭华
卢宇程
杨翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/625,814 priority Critical patent/US11537182B2/en
Publication of WO2020211142A1 publication Critical patent/WO2020211142A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for supporting printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13456—Cell terminals located on one side of the display only
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • the invention relates to the field of display technology, in particular to a display panel, a chip and a flexible circuit board.
  • Traditional COG modules are generally provided with conductive pads for electrical connection with the pins of the chip, and these conductive pads are electrically connected with the traces.
  • the conductive pads far from the end of the chip need to be connected to longer traces.
  • the longer the trace the greater the impedance. At this time, the trace transmitted The greater the attenuation of the signal.
  • the purpose of the present invention is to provide a display panel, a chip and a flexible circuit board, which can reduce the impedance of part of the signal transmission line.
  • a display panel comprising: a panel main body including a display area and a peripheral area located on at least one side of the display area; at least two signal transmission lines, the signal transmission lines being arranged in all At the peripheral area, the signal transmission line includes a line input terminal for binding with a flexible circuit board to be arranged at the peripheral area, a signal transmission line, and a signal transmission line for binding with a chip to be arranged at the peripheral area.
  • the two ends of the signal transmission line are electrically connected to the line input terminal and the line output terminal; wherein at least two of the line output terminals are arranged in a two-dimensional array.
  • At least two of the line output terminals include a first sub-combination and a second sub-combination, the line output terminals in the first sub-combination are arranged along a first direction, and the lines in the second sub-combination The output terminals are arranged along the second direction.
  • the first direction and the second direction are both the same direction; wherein, the first direction is a direction parallel to or perpendicular to a straight line corresponding to the edge of the peripheral area.
  • the line output terminals in the first sub-combination and the line output terminals in the second sub-combination are arranged side by side; and the line output terminals in the first sub-combination and the second sub-combination are arranged in parallel.
  • At least a part of the signal transmission line electrically connected to the line output terminals in the combination is located between the line output terminals in the first sub-combination and the line output terminals in the second sub-combination arranged side by side.
  • the line output terminals in the first sub-combination and the line output terminals in the second sub-combination are alternately arranged; the line output terminals in the second sub-combination are electrically connected At least a part of the signal transmission line is located between two adjacent line output terminals in the first sub-assembly.
  • the first direction and the second direction intersect; wherein a straight line corresponding to the first direction and the edge of the peripheral area has a first included angle, and the second direction is The straight line corresponding to the edge of the peripheral area has a second included angle.
  • At least two line output terminals in the first sub-assembly are arranged in a ladder shape; at least two line output terminals in the second sub-assembly are arranged in a ladder shape.
  • a combination of line input terminals including at least two line input terminals is disposed on a line output terminal including at least two line output terminals At least one side of the combination.
  • At least two of the line input terminals are arranged in a one-dimensional array; the arrangement direction of at least two of the line input terminals is parallel to a straight line corresponding to the edge of the peripheral area.
  • At least two of the line input terminals are arranged in a one-dimensional array; the arrangement direction of at least two of the line input terminals and a straight line corresponding to the edge of the peripheral area have a third angle.
  • the display panel further includes the chip, the chip is disposed at the peripheral area of the panel main body, the chip includes: a chip main body, the chip main body is elongated; At least two input pins, at least two of the input pins are arranged in a two-dimensional array; the input pins are bound to the line output terminals.
  • the display panel further includes a flexible circuit board, the end of the flexible circuit board is arranged at the peripheral area of the panel main body, and the flexible circuit board includes: a flexible circuit board main body; at least Two output pads, at least two output pads are exposed on the surface of the flexible circuit board main body, at least two of the output pads are arranged in a one-dimensional linear array; the output pads are bound to the line input terminals.
  • a chip suitable for the above-mentioned display panel comprising: a chip body, the chip body is elongated; at least two input pins, at least two of the input pins are arranged in a two-dimensional array; The input pin is used for binding with the line output terminal.
  • a combination of input pins including at least two input pins is arranged at a position close to the end of the chip main body.
  • the arrangement of at least two of the input pins is the same as the arrangement of at least two of the line output terminals, and the relative positions of the two input pins on the surface of the chip body are the same as those of the two The relative positions of the line output terminals in the peripheral area correspond.
  • a flexible circuit board suitable for the above display panel comprising: a flexible circuit board main body; at least two output pads, at least two of the output pads are arranged in a one-dimensional linear array; the output pads are used for To be bound to the line input terminal.
  • an output pad combination including at least two output pads is arranged at a position close to the end of the flexible circuit board main body.
  • the arrangement form of at least two output pads is the same as the arrangement form of at least two line input terminals, and the relative positions of the two output pads on the surface of the flexible circuit board body The relative positions of the line input terminals in the peripheral area correspond.
  • At least two of the output pads are arranged along the edge line of the end of the flexible circuit board body, and one edge of the output pad is flush with the edge of the end of the flexible circuit board body.
  • the length of the signal transmission line electrically connected to some of the line output terminals can be reduced, that is, the above technical solution is shortened.
  • the wiring distance between a part of the line output terminal and the line input terminal is reduced, therefore, the length of the signal transmission line is shortened, the impedance of the signal transmission line is reduced, and power loss and signal attenuation are reduced.
  • FIG. 1 is a schematic diagram of the first embodiment of the display panel of the present invention.
  • FIG. 2 is a schematic diagram of area A in the display panel shown in FIG. 1.
  • 3 to 5 are schematic diagrams of other three arrangements of line input terminals in the area A shown in FIG. 2.
  • FIG. 6 is a schematic diagram of area A in the second embodiment of the display panel of the present invention.
  • FIG. 7 is a schematic diagram of area A in the third embodiment of the display panel of the present invention.
  • the display panel of the present invention may be a TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display panel), OLED (Organic Light Emitting Diode, organic light emitting diode display panel) etc.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display panel
  • OLED Organic Light Emitting Diode, organic light emitting diode display panel
  • FIG. 1 is a schematic diagram of a first embodiment of the display panel of the present invention
  • FIG. 2 is a schematic diagram of area A in the display panel shown in FIG. 1
  • FIGS. 3 to 5 are shown in FIG. A schematic diagram of the other three arrangements of line input terminals 1041 in area A.
  • the display panel of this embodiment includes a panel main body 101 and at least two signal transmission lines.
  • the panel body 101 may be, for example, a COG (Chip On Glass) module.
  • the panel main body 101 includes a display area 1011 and a peripheral area 1012 located on at least one side of the display area 1011.
  • the peripheral area 1012 is located on one side of a short side of the display area 1011.
  • the signal transmission line is arranged at the peripheral area 1012, and the signal transmission line includes a line input terminal 1041, a signal transmission line 106, and a cable for binding with the flexible circuit board 103 to be arranged at the peripheral area 1012.
  • the signal transmission line includes a line input terminal 1041, a signal transmission line 106, and a cable for binding with the flexible circuit board 103 to be arranged at the peripheral area 1012.
  • both ends of the signal transmission line 106 are electrically connected to the line input terminal 1041 and the line output terminal 1053.
  • At least two of the signal transmission lines 106 are arranged in parallel.
  • the line output terminals 1053 are arranged in a two-dimensional array.
  • the two-dimensional array includes a linear arrangement or a nonlinear arrangement in a two-dimensional coordinate system.
  • the first sub-combination 1051 and the second sub-combination 1052 in at least two of the line output terminals 1053 are arranged side by side, or staggered, or crossed.
  • the signal transmission line is used to receive a signal from the flexible circuit board 103 through the line input terminal 1041 and is used to output the signal to the chip 102 through the line output terminal 1053.
  • At least a part of the line input terminal 1041 and at least a part of the line output terminal 1053 are exposed on the surface of the panel body 101.
  • At least two of the line output terminals 1053 include a first sub-combination 1051 and a second sub-combination 1052.
  • the line output terminals 1053 in the first sub-combination 1051 are arranged along the first direction 201, and the second sub-combination 1052
  • the line output terminals 1053 are arranged along the second direction 202.
  • the first direction 201 and the second direction 202 are both the same direction.
  • the first direction 201 is a direction parallel to the straight line corresponding to the edge of the peripheral area 1012, or the first direction 201 is a direction perpendicular to the straight line corresponding to the edge of the peripheral area 1012.
  • the line output terminal 1053 in the first sub-combination 1051 and the line output terminal 1053 in the second sub-combination 1052 are arranged side by side.
  • At least a part of the signal transmission line 106 electrically connected to the line output terminal 1053 in the first sub-combination 1051 and the line output terminal 1053 in the second sub-combination 1052 is located in the first sub-combination arranged in parallel Between the line output terminal 1053 in 1051 and the line output terminal 1053 in the second sub-combination 1052.
  • the line input terminal assembly 104 including at least two line input terminals 1041 is arranged in the line output terminal assembly 1053 including at least two line output terminals 1053 On at least one side.
  • At least two of the line input terminals 1041 are arranged in a one-dimensional array.
  • the arrangement direction of at least two of the line input terminals 1041 is parallel to the line corresponding to the edge of the peripheral area 1012, as shown in FIG. 2.
  • the line corresponding to the arrangement direction of at least two of the line input terminals 1041 and the edge of the peripheral area 1012 has a third included angle, as shown in FIG. 3, FIG. 4, and FIG. 5, which is beneficial to shorten the line input terminal
  • the wiring distance between 1041 and the line output terminal 1053 that is, shorten the length of the signal transmission line 106, so the impedance of the signal transmission line 106 can be reduced, thereby reducing power loss and signal attenuation.
  • At least two line input terminals 1041 are arranged in a stepped shape.
  • the display panel further includes the chip 102, the chip 102 is disposed at the peripheral area 1012 of the panel body 101, and the chip 102 includes a chip body and at least two input pins.
  • the chip main body has a long strip shape, and the chip main body is arranged at a position close to the edge of the peripheral area 1012 (ie, a position far away from the display area 1011).
  • the input pins are arranged on a surface (for example, the bottom surface) of the chip main body, and at least two of the input pins are arranged in a two-dimensional array.
  • the arrangement form of at least two of the input pins is the same as the arrangement form of at least two of the line output terminals 1053, and the relative positions of the two input pins on the surface of the chip main body and the two line output terminals 1053 It corresponds to the relative position of the peripheral area 1012.
  • the input pin combination including at least two input pins is disposed at a position close to the end of the chip main body, that is, the input pin is disposed on the edge of one end of the elongated chip main body.
  • the input pin is bound to the line output terminal 1053.
  • the input pin is used to receive the signal provided by the signal transmission line from the line output terminal 1053 and provide the signal to the chip main body.
  • the display panel further includes a flexible circuit board 103, the end of the flexible circuit board 103 is disposed at the peripheral area 1012 of the panel main body 101, and the flexible circuit board 103 includes a flexible circuit board main body and at least two outputs. pad.
  • At least two output pads are exposed on the surface of the flexible circuit board main body, and at least two of the output pads are arranged in a one-dimensional linear array.
  • the arrangement of at least two of the output pads is the same as the arrangement of at least two of the line input terminals 1041, and the relative positions of the two output pads on the surface of the flexible circuit board body and the two line input terminals 1041 It corresponds to the relative position of the peripheral area 1012.
  • the output pad is bound to the line input terminal 1041.
  • the output pad is used to output the signal provided by the flexible circuit board 103 to the line input terminal 1041.
  • the output pad assembly including at least two output pads is arranged at a position close to the end of the flexible circuit board main body. At least two of the output pads are arranged along the edge line of the end of the flexible circuit board main body, and one edge of the output pad is flush with the edge of the end of the flexible circuit board main body.
  • the edge line of the end of the flexible circuit board body is parallel to the straight line corresponding to the edge of the peripheral area 1012 (as shown in FIG. 2); or the edge line of the end of the flexible circuit board body and the periphery
  • the straight line corresponding to the edge of the area 1012 has a fourth included angle (as shown in FIG. 3, FIG. 4, and FIG. 5), wherein the edge line of the end of the flexible circuit board body faces the line output terminal 1053 or back The line output terminal 1053.
  • the arrangement direction of at least two output pads is parallel to the line corresponding to the edge of the peripheral area 1012, as shown in FIG. 2.
  • the straight line corresponding to the arrangement direction of at least two output pads and the edge of the peripheral area 1012 has a fourth included angle, as shown in FIG. 3, FIG. 4, and FIG. 5, which is beneficial to shorten the line input terminals 1041 and 1041.
  • the wiring distance between the line output terminals 1053, that is, the length of the signal transmission line 106 is shortened, so the impedance of the signal transmission line 106 can be reduced, thereby reducing power loss and signal attenuation.
  • the display panel further includes at least two data lines and at least two data signal input terminals, the data lines are electrically connected to the data signal input terminals, and the data lines are also located in the display area 1011 with the panel body 101
  • the pixel units within are electrically connected.
  • the data signal input terminal is used for binding with the chip 102 to be arranged at the peripheral area 1012.
  • At least two of the data signal input terminals are arranged in a one-dimensional array along a direction parallel to the straight line corresponding to the edge of the peripheral area 1012.
  • the data signal input terminal is located at
  • FIG. 6 is a schematic diagram of the area A in the second embodiment of the display panel of the present invention. This embodiment is similar to the above-mentioned first embodiment, except for the following:
  • the line output terminal 1053 in the first sub-combination 1051 and the line output terminal 1053 in the second sub-combination 1052 are arranged in parallel.
  • the line output terminals 1053 in the first sub-combination 1051 and the line output terminals 1053 in the second sub-combination 1052 are arranged alternately, that is, the line output terminals in the second sub-combination 1052
  • the position of the terminal 1053 corresponds to the position of the gap between the two line output terminals 1053 in the first sub-assembly 1051, and the signal transmission line 106 connected to the line output terminal 1053 in the second sub-assembly 1052 passes through The gap between the two line output terminals 1053 in the first sub-assembly 1051.
  • At least a part of the signal transmission line 106 that is electrically connected to the line output terminal 1053 in the second sub-assembly 1052 is located between two adjacent line output terminals 1053 in the first sub-assembly 1051.
  • FIG. 7 is a schematic diagram of area A in the third embodiment of the display panel of the present invention. This embodiment is similar to the above-mentioned first or second embodiment, except for the following:
  • the first direction 201 and the second direction 202 are the same.
  • the first direction 201 and the second direction 202 intersect.
  • the line corresponding to the first direction 201 and the edge of the peripheral region 1012 has a first included angle
  • the line corresponding to the second direction 202 and the edge of the peripheral region 1012 has a second included angle. That is, the arrangement direction of the line output terminals 1053 in the first sub-combination 1051 and the arrangement direction of the line output terminals 1053 in the second sub-combination 1052 are not parallel.
  • At least two line output terminals 1053 in the first sub-combination 1051 are arranged in a ladder shape; and/or at least two line output terminals 1053 in the second sub-combination 1052 are arranged in a ladder shape.
  • the length of the signal transmission line 106 electrically connected to part of the line output terminals 1053 can be reduced, that is, the above
  • the technical solution shortens part of the wiring distance between the line output terminal 1053 and the line input terminal 1041, therefore, shortens the length of the signal transmission line 106, reduces the impedance of the signal transmission line 106, and thereby reduces the power Consumption loss and signal attenuation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板、芯片及柔性电路板。显示面板包括面板主体（101）和至少两信号传输线路（106），信号传输线路（106）包括用于与待设置于外围区（1012）处的柔性电路板（103）绑定的线路输入端子（1041）、信号传输线（106）和用于与待设置于外围区（1012）处的芯片（102）绑定的线路输出端子（1053）；至少两线路输出端子（1053）以二维阵列的形式排列。能降低部分信号传输线的阻抗。

Description

显示面板、芯片及柔性电路板 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板、芯片及柔性电路板。
 背景技术
传统的COG模组一般设置有用于与芯片的管脚电性连接的导电垫，这些导电垫与走线电性连接。
在实践中，发明人发现现有技术至少存在以下问题：
随着导电垫（芯片的管脚）的数量增多，远离芯片的末端处的导电垫需要连接更长的走线，走线的长度越大，其阻抗也越大，此时，走线所传输的信号的衰减也越大。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种显示面板、芯片及柔性电路板，其能降低部分信号传输线的阻抗。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种显示面板，所述显示面板包括：一面板主体，所述面板主体包括显示区和位于所述显示区的至少一侧的外围区；至少两信号传输线路，所述信号传输线路设置于所述外围区处，所述信号传输线路包括用于与待设置于所述外围区处的柔性电路板绑定的线路输入端子、信号传输线和用于与待设置于所述外围区处的芯片绑定的线路输出端子，所述信号传输线的两端电性连接所述线路输入端子和所述线路输出端子；其中，至少两所述线路输出端子以二维阵列的形式排列。
在上述显示面板中，至少两所述线路输出端子包括第一子组合和第二子组合，所述第一子组合中的线路输出端子沿第一方向排列，所述第二子组合中的线路输出端子沿第二方向排列。
在上述显示面板中，所述第一方向和所述第二方向均为相同的方向；其中，所述第一方向为平行于或者垂直于所述外围区的边缘所对应的直线的方向。
在上述显示面板中，所述第一子组合中的线路输出端子和所述第二子组合中的线路输出端子并列排列；与所述第一子组合中的线路输出端子和所述第二子组合中的线路输出端子电性连接的所述信号传输线的至少一部分位于并列排列的所述第一子组合中的线路输出端子和所述第二子组合中的线路输出端子之间。
在上述显示面板中，所述第一子组合中的线路输出端子与所述第二子组合中的线路输出端子交错排列；与所述第二子组合中的线路输出端子电性连接的所述信号传输线的至少一部分位于所述第一子组合中的相邻两线路输出端子之间。
在上述显示面板中，所述第一方向和所述第二方向相交；其中，所述第一方向与所述外围区的边缘所对应的直线具有第一夹角，所述第二方向与所述外围区的边缘所对应的直线具有第二夹角。
在上述显示面板中，所述第一子组合中的至少两线路输出端子排列成阶梯状；所述第二子组合中的至少两线路输出端子排列成阶梯状。
在上述显示面板中，在平行于所述外围区的边缘所对应的直线的方向上，包括至少两所述线路输入端子的线路输入端子组合设置于包括至少两所述线路输出端子的线路输出端子组合的至少一侧。
在上述显示面板中，至少两所述线路输入端子以一维阵列的形式排列；至少两所述线路输入端子的排列方向平行于所述外围区的边缘所对应的直线。
在上述显示面板中，至少两所述线路输入端子以一维阵列的形式排列；至少两所述线路输入端子的排列方向与所述外围区的边缘所对应的直线具有第三夹角。
在上述显示面板中，在至少两所述线路输入端子的排列方向与所述外围区的边缘所对应的直线具有第三夹角的情况下，至少两所述线路输入端子排列成阶梯状。
在上述显示面板中，所述显示面板还包括所述芯片，所述芯片设置于所述面板主体的所述外围区处，所述芯片包括：一芯片主体，所述芯片主体为长条状；至少两输入管脚，至少两所述输入管脚以二维阵列的形式排列；所述输入管脚与所述线路输出端子绑定。
在上述显示面板中，所述显示面板还包括柔性电路板，所述柔性电路板的末端设置于所述面板主体的所述外围区处，所述柔性电路板包括：一柔性电路板主体；至少两输出垫，至少两输出垫露出于所述柔性电路板主体的表面，至少两所述输出垫以一维线性阵列的形式排列；所述输出垫与所述线路输入端子绑定。
一种适用于上述显示面板的芯片，所述芯片包括：一芯片主体，所述芯片主体为长条状；至少两输入管脚，至少两所述输入管脚以二维阵列的形式排列；所述输入管脚用于与所述线路输出端子绑定。
在上述芯片中，包括至少两输入管脚的输入管脚组合设置于靠近所述芯片主体的末端的位置。
在上述芯片中，至少两所述输入管脚的排列形式与至少两所述线路输出端子的排列形式相同，并且，两所述输入管脚在所述芯片主体的表面的相对位置与两所述线路输出端子在所述外围区的相对位置对应。
一种适用于上述显示面板的柔性电路板，所述柔性电路板包括：一柔性电路板主体；至少两输出垫，至少两所述输出垫以一维线性阵列的形式排列；所述输出垫用于与所述线路输入端子绑定。
在上述柔性电路板中，包括至少两输出垫的输出垫组合设置于靠近所述柔性电路板主体的末端的位置。
在上述柔性电路板中，至少两所述输出垫的排列形式与至少两所述线路输入端子的排列形式相同，并且，两所述输出垫在所述柔性电路板主体的表面的相对位置与两所述线路输入端子在所述外围区的相对位置对应。
在上述柔性电路板中，至少两所述输出垫沿所述柔性电路板主体的末端的边缘线排列，所述输出垫的一边缘与所述柔性电路板主体的末端的边缘齐平。
 有益效果
在上述技术方案中，由于至少两所述线路输出端子以二维阵列的形式排列，因此，与部分所述线路输出端子电性连接的信号传输线的长度将可以得到缩减，即，上述技术方案缩短了部分所述线路输出端子与所述线路输入端子之间的布线距离，因此，缩短了所述信号传输线的长度，减小了所述信号传输线的阻抗，进而降低功耗损失和信号衰减。
 附图说明
图1为本发明的显示面板的第一实施例的示意图。
图2为图1所示的显示面板中的区域A的示意图。
图3至图5为图2所示的区域A中线路输入端子的其它三种排列方式的示意图。
图6为本发明的显示面板的第二实施例中的区域A的示意图。
图7为本发明的显示面板的第三实施例中的区域A的示意图。
 本发明的实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）、OLED（Organic Light Emitting Diode，有机发光二极管显示面板）等。
参考图1至图5，图1为本发明的显示面板的第一实施例的示意图，图2为图1所示的显示面板中的区域A的示意图，图3至图5为图2所示的区域A中线路输入端子1041的其它三种排列方式的示意图。
本实施例的显示面板包括一面板主体101和至少两信号传输线路。其中，所述面板主体101可例如为COG（Chip On Glass）模组。
所述面板主体101包括显示区1011和位于所述显示区1011的至少一侧的外围区1012，例如，所述外围区1012位于所述显示区1011的短边的一侧。
所述信号传输线路设置于所述外围区1012处，所述信号传输线路包括用于与待设置于所述外围区1012处的柔性电路板103绑定的线路输入端子1041、信号传输线106和用于与待设置于所述外围区1012处的芯片102绑定的线路输出端子1053，所述信号传输线106的两端电性连接所述线路输入端子1041和所述线路输出端子1053。至少两所述信号传输线106并列设置。
其中，至少两所述线路输出端子1053以二维阵列的形式排列。所述二维阵列包括二维坐标系中的线性排列或非线性排列。例如，至少两所述线路输出端子1053中的第一子组合1051和第二子组合1052并列排列，或者交错排列，或者交叉排列。
所述信号传输线路用于通过所述线路输入端子1041从所述柔性电路板103接收信号，并用于通过所述线路输出端子1053向所述芯片102输出所述信号。
所述线路输入端子1041的至少一部分和所述线路输出端子1053的至少一部分均露出于所述面板主体101的表面。
至少两所述线路输出端子1053包括第一子组合1051和第二子组合1052，所述第一子组合1051中的线路输出端子1053沿第一方向201排列，所述第二子组合1052中的线路输出端子1053沿第二方向202排列。
在本实施例中，所述第一方向201和所述第二方向202均为相同的方向。
其中，所述第一方向201为平行于所述外围区1012的边缘所对应的直线的方向，或者，所述第一方向201为垂直于所述外围区1012的边缘所对应的直线的方向。
所述第一子组合1051中的线路输出端子1053和所述第二子组合1052中的线路输出端子1053并列排列。
与所述第一子组合1051中的线路输出端子1053和所述第二子组合1052中的线路输出端子1053电性连接的所述信号传输线106的至少一部分位于并列排列的所述第一子组合1051中的线路输出端子1053和所述第二子组合1052中的线路输出端子1053之间。
在平行于所述外围区1012的边缘所对应的直线的方向上，包括至少两所述线路输入端子1041的线路输入端子组合104设置于包括至少两所述线路输出端子1053的线路输出端子1053组合的至少一侧。
至少两所述线路输入端子1041以一维阵列的形式排列。
至少两所述线路输入端子1041的排列方向平行于所述外围区1012的边缘所对应的直线，如图2所示。或者，至少两所述线路输入端子1041的排列方向与所述外围区1012的边缘所对应的直线具有第三夹角，如图3、图4、图5所示，这样有利于缩短线路输入端子1041和线路输出端子1053之间的布线距离，即，缩短所述信号传输线106的长度，因此可以减小所述信号传输线106的阻抗，进而降低功耗损失和信号衰减。
在至少两所述线路输入端子1041的排列方向与所述外围区1012的边缘所对应的直线具有第三夹角的情况下，至少两所述线路输入端子1041排列成阶梯状。
所述显示面板还包括所述芯片102，所述芯片102设置于所述面板主体101的所述外围区1012处，所述芯片102包括一芯片主体和至少两输入管脚。
所述芯片主体为长条状，所述芯片主体设置在靠近所述外围区1012的边缘的位置（即，远离所述显示区1011的位置）。
所述输入管脚设置于所述芯片主体的一表面（例如，底面），至少两所述输入管脚以二维阵列的形式排列。至少两所述输入管脚的排列形式与至少两所述线路输出端子1053的排列形式相同，并且，两所述输入管脚在所述芯片主体的表面的相对位置与两所述线路输出端子1053在所述外围区1012的相对位置对应。进一步地，包括至少两输入管脚的输入管脚组合设置于靠近所述芯片主体的末端的位置，即，所述输入管脚设置于长条状的所述芯片主体的一末端的边缘部。
所述输入管脚与所述线路输出端子1053绑定。所述输入管脚用于从所述线路输出端子1053接收所述信号传输线路提供的所述信号，并将所述信号提供给所述芯片主体。
所述显示面板还包括柔性电路板103，所述柔性电路板103的末端设置于所述面板主体101的所述外围区1012处，所述柔性电路板103包括一柔性电路板主体和至少两输出垫。
至少两输出垫露出于所述柔性电路板主体的表面，至少两所述输出垫以一维线性阵列的形式排列。至少两所述输出垫的排列形式与至少两所述线路输入端子1041的排列形式相同，并且，两所述输出垫在所述柔性电路板主体的表面的相对位置与两所述线路输入端子1041在所述外围区1012的相对位置对应。
所述输出垫与所述线路输入端子1041绑定。所述输出垫用于向所述线路输入端子1041输出所述柔性电路板103所提供的信号。
包括至少两输出垫的输出垫组合设置于靠近所述柔性电路板主体的末端的位置。至少两所述输出垫沿所述柔性电路板主体的末端的边缘线排列，所述输出垫的一边缘与所述柔性电路板主体的末端的边缘齐平。其中，所述柔性电路板主体的末端的边缘线平行于所述外围区1012的边缘所对应的直线（如图2所示）；或者所述柔性电路板主体的末端的边缘线与所述外围区1012的边缘所对应的直线具有第四夹角（如图3、图4、图5所示），其中，所述柔性电路板主体的末端的边缘线朝向所述线路输出端子1053或背向所述线路输出端子1053。
至少两所述输出垫的排列方向平行于所述外围区1012的边缘所对应的直线，如图2所示。或者，至少两所述输出垫的排列方向与所述外围区1012的边缘所对应的直线具有第四夹角，如图3、图4、图5所示，这样有利于缩短线路输入端子1041和线路输出端子1053之间的布线距离，即，缩短所述信号传输线106的长度，因此可以减小所述信号传输线106的阻抗，进而降低功耗损失和信号衰减。
所述显示面板还包括至少两数据线和至少两数据信号输入端子，所述数据线与所述数据信号输入端子电性连接，所述数据线还与所述面板主体101位于所述显示区1011内的像素单元电性连接。
所述数据信号输入端子用于与待设置于所述外围区1012处的所述芯片102绑定。
至少两所述数据信号输入端子沿平行于所述外围区1012的边缘所对应的直线的方向以一维阵列的形式排列。所述数据信号输入端子位于
参考图6，图6为本发明的显示面板的第二实施例中的区域A的示意图。本实施例与上述第一实施例相似，不同之处在于：
在上述第一实施例中，所述第一子组合1051中的线路输出端子1053与所述第二子组合1052中的线路输出端子1053并列排列。
而在本实施例中，所述第一子组合1051中的线路输出端子1053与所述第二子组合1052中的线路输出端子1053交错排列，即，所述第二子组合1052中的线路输出端子1053所处的位置对应于所述第一子组合1051中的两线路输出端子1053之间的间隙的位置，与所述第二子组合1052中的线路输出端子1053连接的信号传输线106穿过所述第一子组合1051中的两线路输出端子1053之间的间隙。与所述第二子组合1052中的线路输出端子1053电性连接的所述信号传输线106的至少一部分位于所述第一子组合1051中的相邻两线路输出端子1053之间。
参考图7，图7为本发明的显示面板的第三实施例中的区域A的示意图。本实施例与上述第一实施例或第二实施例相似，不同之处在于：
在上述第一实施例或第二实施例中，所述第一方向201和所述第二方向202相同。
而在本实施例中，所述第一方向201和所述第二方向202相交。所述第一方向201与所述外围区1012的边缘所对应的直线具有第一夹角，所述第二方向202与所述外围区1012的边缘所对应的直线具有第二夹角。即，所述第一子组合1051中的线路输出端子1053的排列方向和所述第二子组合1052中的线路输出端子1053的排列方向不平行。
所述第一子组合1051中的至少两线路输出端子1053排列成阶梯状；和/或所述第二子组合1052中的至少两线路输出端子1053排列成阶梯状。
在上述技术方案中，由于至少两所述线路输出端子1053以二维阵列的形式排列，因此，与部分所述线路输出端子1053电性连接的信号传输线106的长度将可以得到缩减，即，上述技术方案缩短了部分所述线路输出端子1053与所述线路输入端子1041之间的布线距离，因此，缩短了所述信号传输线106的长度，减小了所述信号传输线106的阻抗，进而降低功耗损失和信号衰减。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    一面板主体，所述面板主体包括显示区和位于所述显示区的至少一侧的外围区；
    至少两信号传输线路，所述信号传输线路设置于所述外围区处，所述信号传输线路包括用于与待设置于所述外围区处的柔性电路板绑定的线路输入端子、信号传输线和用于与待设置于所述外围区处的芯片绑定的线路输出端子，所述信号传输线的两端电性连接所述线路输入端子和所述线路输出端子；
    其中，至少两所述线路输出端子以二维阵列的形式排列。
  2. 根据权利要求1所述的显示面板，其中，至少两所述线路输出端子包括第一子组合和第二子组合，所述第一子组合中的线路输出端子沿第一方向排列，所述第二子组合中的线路输出端子沿第二方向排列。
  3. 根据权利要求2所述的显示面板，其中，所述第一方向和所述第二方向均为相同的方向；
    其中，所述第一方向为平行于或者垂直于所述外围区的边缘所对应的直线的方向。
  4. 根据权利要求3所述的显示面板，其中，所述第一子组合中的线路输出端子和所述第二子组合中的线路输出端子并列排列；
    与所述第一子组合中的线路输出端子和所述第二子组合中的线路输出端子电性连接的所述信号传输线的至少一部分位于并列排列的所述第一子组合中的线路输出端子和所述第二子组合中的线路输出端子之间。
  5. 根据权利要求3所述的显示面板，其中，所述第一子组合中的线路输出端子与所述第二子组合中的线路输出端子交错排列；
    与所述第二子组合中的线路输出端子电性连接的所述信号传输线的至少一部分位于所述第一子组合中的相邻两线路输出端子之间。
  6. 根据权利要求2所述的显示面板，其中，所述第一方向和所述第二方向相交；
    其中，所述第一方向与所述外围区的边缘所对应的直线具有第一夹角，所述第二方向与所述外围区的边缘所对应的直线具有第二夹角。
  7. 根据权利要求6所述的显示面板，其中，所述第一子组合中的至少两线路输出端子排列成阶梯状；
    所述第二子组合中的至少两线路输出端子排列成阶梯状。
  8. 根据权利要求1所述的显示面板，其中，在平行于所述外围区的边缘所对应的直线的方向上，包括至少两所述线路输入端子的线路输入端子组合设置于包括至少两所述线路输出端子的线路输出端子组合的至少一侧。
  9. 根据权利要求1所述的显示面板，其中，至少两所述线路输入端子以一维阵列的形式排列；
    至少两所述线路输入端子的排列方向平行于所述外围区的边缘所对应的直线。
  10. 根据权利要求1所述的显示面板，其中，至少两所述线路输入端子以一维阵列的形式排列；
    至少两所述线路输入端子的排列方向与所述外围区的边缘所对应的直线具有第三夹角。
  11. 根据权利要求10所述的显示面板，其中，至少两所述线路输入端子排列成阶梯状。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括所述芯片，所述芯片设置于所述面板主体的所述外围区处，所述芯片包括：
    一芯片主体，所述芯片主体为长条状；
    至少两输入管脚，至少两所述输入管脚以二维阵列的形式排列；
    所述输入管脚与所述线路输出端子绑定。
  13. 根据权利要求1所述的显示面板，其中，所述显示面板还包括柔性电路板，所述柔性电路板的末端设置于所述面板主体的所述外围区处，所述柔性电路板包括：
    一柔性电路板主体；
    至少两输出垫，至少两输出垫露出于所述柔性电路板主体的表面，至少两所述输出垫以一维线性阵列的形式排列；
    所述输出垫与所述线路输入端子绑定。
  14. 一种适用于如权利要求1所述的显示面板的芯片，其中，所述芯片包括：
    一芯片主体，所述芯片主体为长条状；
    至少两输入管脚，至少两所述输入管脚以二维阵列的形式排列；
    所述输入管脚用于与所述线路输出端子绑定。
  15. 根据权利要求14所述的芯片，其中，包括至少两输入管脚的输入管脚组合设置于靠近所述芯片主体的末端的位置。
  16. 根据权利要求14所述的芯片，其中，至少两所述输入管脚的排列形式与至少两所述线路输出端子的排列形式相同，并且，两所述输入管脚在所述芯片主体的表面的相对位置与两所述线路输出端子在所述外围区的相对位置对应。
  17. 一种适用于如权利要求1所述的显示面板的柔性电路板，其中，所述柔性电路板包括：
    一柔性电路板主体；
    至少两输出垫，至少两所述输出垫以一维线性阵列的形式排列；
    所述输出垫用于与所述线路输入端子绑定。
  18. 根据权利要求17所述的柔性电路板，其中，包括至少两输出垫的输出垫组合设置于靠近所述柔性电路板主体的末端的位置。
  19. 根据权利要求17所述的柔性电路板，其中，至少两所述输出垫的排列形式与至少两所述线路输入端子的排列形式相同，并且，两所述输出垫在所述柔性电路板主体的表面的相对位置与两所述线路输入端子在所述外围区的相对位置对应。
  20. 根据权利要求17所述的柔性电路板，其中，至少两所述输出垫沿所述柔性电路板主体的末端的边缘线排列，所述输出垫的一边缘与所述柔性电路板主体的末端的边缘齐平。
PCT/CN2019/087583 2019-04-15 2019-05-20 显示面板、芯片及柔性电路板 Ceased WO2020211142A1 (zh)

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