WO2020206740A1 - 显示面板和电子设备 - Google Patents

显示面板和电子设备 Download PDF

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Publication number
WO2020206740A1
WO2020206740A1 PCT/CN2019/084040 CN2019084040W WO2020206740A1 WO 2020206740 A1 WO2020206740 A1 WO 2020206740A1 CN 2019084040 W CN2019084040 W CN 2019084040W WO 2020206740 A1 WO2020206740 A1 WO 2020206740A1
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Prior art keywords
metal layer
layer
gate metal
thin film
gate
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PCT/CN2019/084040
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English (en)
French (fr)
Inventor
曾维静
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020206740A1 publication Critical patent/WO2020206740A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present invention relates to the field of electronic display, in particular to a display panel and electronic equipment.
  • the thin film transistor layer of the display panel usually adopts a top-gate thin film transistor to reduce the load of the signal line.
  • the present invention provides a display panel and an electronic device, which can effectively reduce the resistance of signal lines in the display panel.
  • the present invention provides a display panel, which includes:
  • a thin film transistor layer, the thin film transistor layer is located on the substrate;
  • a light-emitting structure the light-emitting structure is located on the thin film transistor layer; wherein,
  • the thin film transistor layer includes a plurality of thin film transistors, and the thin film transistors include:
  • a buffer layer, the buffer layer is located on the substrate
  • a first gate metal layer and a second gate metal layer, the first gate metal layer and the second gate metal layer are located on the buffer layer;
  • a gate dielectric layer covering the first gate metal layer and the second gate metal layer;
  • the active region is located on the gate dielectric layer, the active region includes a channel region and source and drain regions on both sides of the channel region, the channel region is located on the Immediately above the first gate metal layer;
  • An interlayer dielectric layer covering the active area
  • a source region metal layer, the source region metal layer is located on the interlayer dielectric layer and is electrically connected to the source region through a through hole;
  • a drain region metal layer, the drain region metal layer is located on the interlayer dielectric layer, and is electrically connected to the drain region and the second gate metal layer through a through hole;
  • the planarization layer covers the source metal layer, the drain metal layer and the interlayer dielectric layer.
  • the first gate metal layer and the second gate metal layer are light-shielding metal layers.
  • the light-emitting structure includes a light-emitting material layer, and the projection of the light-emitting material layer on the substrate does not overlap with the first gate metal layer and the second gate metal layer.
  • the first gate metal layer and the second gate metal layer are electrically insulated.
  • the projection of the first gate metal layer on the buffer layer covers the projection of the channel region on the buffer layer.
  • the length of the first gate metal layer along the channel direction is greater than the length of the channel region along the channel direction, and the first gate metal layer covers the channel region. Adjacent part of the source and drain regions.
  • the plurality of thin film transistors are distributed in an array, including at least one row of thin film transistors arranged in a first direction and at least one column of thin film transistors arranged in a second direction; wherein,
  • the second gate metal layers in the multiple thin film transistors in the same row are electrically connected, and the second gate metal layers in the multiple thin film transistors in the same column are electrically insulated.
  • the surface of the light shielding metal layer adjacent to the substrate has a uniformly distributed diffuse reflection structure.
  • the surface of the light shielding metal layer adjacent to the substrate has a uniformly undulating wavy structure.
  • the present invention also provides an electronic device, which includes a display panel, and the display panel includes:
  • a thin film transistor layer, the thin film transistor layer is located on the substrate;
  • a light-emitting structure the light-emitting structure is located on the thin film transistor layer; wherein,
  • the thin film transistor layer includes a plurality of thin film transistors, and the thin film transistors include:
  • a buffer layer, the buffer layer is located on the substrate
  • a first gate metal layer and a second gate metal layer, the first gate metal layer and the second gate metal layer are located on the buffer layer;
  • a gate dielectric layer covering the first gate metal layer and the second gate metal layer;
  • the active region is located on the gate dielectric layer, the active region includes a channel region and source and drain regions on both sides of the channel region, the channel region is located on the Immediately above the first gate metal layer;
  • An interlayer dielectric layer covering the active area
  • a source region metal layer, the source region metal layer is located on the interlayer dielectric layer and is electrically connected to the source region through a through hole;
  • a drain region metal layer, the drain region metal layer is located on the interlayer dielectric layer, and is electrically connected to the drain region and the second gate metal layer through a through hole;
  • the planarization layer covers the source metal layer, the drain metal layer and the interlayer dielectric layer.
  • the first gate metal layer and the second gate metal layer are light-shielding metal layers.
  • the light-emitting structure includes a light-emitting material layer, and the projection of the light-emitting material layer on the substrate does not overlap with the first gate metal layer and the second gate metal layer.
  • the first gate metal layer and the second gate metal layer are electrically insulated.
  • the projection of the first gate metal layer on the buffer layer covers the projection of the channel region on the buffer layer.
  • the length of the first gate metal layer along the channel direction is greater than the length of the channel region along the channel direction, and the first gate metal layer covers the channel region. Adjacent part of the source and drain regions.
  • the plurality of thin film transistors are distributed in an array, including at least one row of thin film transistors arranged in a first direction and at least one column of thin film transistors arranged in a second direction; wherein,
  • the second gate metal layers in the multiple thin film transistors in the same row are electrically connected, and the second gate metal layers in the multiple thin film transistors in the same column are electrically insulated.
  • the surface of the light shielding metal layer adjacent to the substrate has a uniformly distributed diffuse reflection structure.
  • the surface of the light shielding metal layer adjacent to the substrate has a uniformly undulating wavy structure.
  • a first gate metal layer and a second gate metal layer are arranged in the buffer layer of the back-gate thin film transistor, and the second gate metal layer is connected to the drain wiring layer through a through hole,
  • the area of the metal trace is effectively increased, and the resistance of the signal line is reduced, thereby effectively avoiding the voltage drop on the signal line.
  • the first gate metal layer and the second gate metal layer are light-shielding metal layers to prevent external light from entering the active area, thereby avoiding threshold voltage drift.
  • FIG. 1 is a schematic cross-sectional view of a display panel in the prior art
  • FIG. 2 is a schematic cross-sectional view of a display panel in a specific embodiment of the present invention.
  • FIG. 3 is a top view of partial wiring of the display panel in a specific embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view of a display panel in the prior art.
  • the display panel includes a substrate 112, a thin film transistor layer, and a light emitting structure.
  • the thin film transistor layer is located on the substrate 112 and includes a plurality of thin film transistors.
  • Each of the thin film transistors includes: a buffer layer 116 on the substrate 112; an active region on the buffer layer 116, and the active region includes a channel region 120 and The source region 122 and the drain region 124 located on both sides of the channel region 120; the gate dielectric layer 130, the gate dielectric layer 130 covers the active region; the gate metal layer 140, the gate metal layer 140 covers the gate dielectric layer 130 located above the active region; an interlayer dielectric layer 150, which covers the gate metal layer 140; a source and drain metal layer, where the source and drain metal layer is located On the interlayer dielectric layer 150; a planarization layer 170, the planarization layer 170 covers the source and drain metal layers and the interlayer dielectric layer 150.
  • the light emitting structure is located on the thin film transistor layer.
  • the light emitting structure includes an anode 182, a pixel defining layer 190, a light emitting material layer 184, and a cathode 186.
  • the anode 182 is located on the planarization layer 170 and is electrically connected to the source/drain metal layer 160 through through holes; the pixel definition layer 190 is located on the planarization layer 172 and has the anode exposed.
  • the luminescent material layer 184 is located on the anode 182; the cathode 186 covers the luminescent material layer 184.
  • FIG. 2 is a schematic cross-sectional view of a display panel in a specific embodiment of the present invention
  • FIG. 3 is a top view of partial wiring of the display panel in a specific embodiment of the present invention.
  • the display panel is an organic light emitting diode (OLED) display panel.
  • OLED organic light emitting diode
  • the display panel may also be a liquid crystal display panel or other types of display panels.
  • the display panel includes a substrate 112, a thin film transistor layer, and a light emitting structure.
  • the substrate 112 may be a rigid substrate or a flexible substrate.
  • the rigid substrate includes glass, metal, etc.
  • the flexible substrate may be various polymers, such as polyimide.
  • the thin film transistor layer is located on the substrate 112 and includes a plurality of thin film transistors.
  • the thin film transistors include a buffer layer 116, an active region, a gate dielectric layer 130, a first gate metal layer 140, and a second gate.
  • first gate metal layer 140 and the second gate metal layer 142 are electrically insulated.
  • the projection of the first gate metal layer 140 on the buffer layer covers the projection of the channel region 120 on the buffer layer.
  • the projection of the second gate metal layer 142 on the buffer layer 116 covers the projection of the drain metal layer 162 on the buffer layer 116.
  • the shape and area of the second gate metal layer 142 are the same as the drain metal layer 162.
  • This arrangement has two advantages. On the one hand, since the second gate metal layer 142 and the drain metal layer 162 have the same shape, they can be formed by the same mask, thereby reducing production costs. On the other hand, the positions and shapes of the second gate metal layer 142 and the drain region metal layer 162 are corresponding, and the projections of the two on the buffer layer 116 overlap to realize the electrical connection between the two through holes The position can be set arbitrarily according to the actual situation, which is convenient for process realization.
  • the first gate metal layer 140 and the second gate metal layer 142 are light-shielding metal layers.
  • the light-shielding metal layer can effectively prevent external light from entering the active area, and effectively inhibit the electronic transition in the active area.
  • the light-shielding metal layer can greatly enhance the stability of the thin film transistor.
  • the surfaces of the first gate metal layer 140 and the second gate metal layer 142 adjacent to the substrate 112 have uniformly distributed diffuse reflection structures, and the diffuse reflection structures may be granular frosted surfaces.
  • the surface of the light shielding metal layer adjacent to the substrate 112 has a uniformly undulating wavy structure.
  • the diffuse reflection structure and the wave-shaped structure can diverge and absorb light, and further enhance the light shielding effect of the first gate metal layer 140 and the second gate metal layer 142.
  • the buffer layer 116 is located on the substrate 112.
  • the buffer layer 116 is a semiconductor oxide or nitride, such as silicon oxide, silicon nitride, and the like.
  • the gate metal layer 130 covers the first gate metal layer 140 and the second gate metal layer 142.
  • the gate dielectric layer 130 covers the first gate metal layer 140 and the second gate metal layer 142 and the buffer layer 116. The overall coverage can save the mask for forming the gate dielectric layer, thereby saving cost.
  • the active region includes a channel region 120 and a source region 122 and a drain region 124 located on both sides of the channel region 120.
  • the projection of the first gate metal layer 140 on the buffer layer covers the projection of the channel region 120 on the buffer layer. In other embodiments, the projection of the first gate metal layer 140 on the buffer layer covers the projection of the channel region 120 on the buffer layer.
  • the projected area of the first gate metal layer 140 on the buffer layer is larger than the projected area of the channel region 120 on the buffer layer, that is, the first gate metal layer 140 is on the buffer layer.
  • the projection on the buffer layer also covers a part of the boundary between the source region 122 and the channel region 120 and a part of the boundary between the drain region 124 and the channel region 120. Such an arrangement can enhance the gate control and well suppress the short channel effect.
  • the source region metal layer 164 is located on the interlayer dielectric layer 150 and is electrically connected to the source region 122 through via holes.
  • the drain region metal layer 162 is located on the interlayer dielectric layer 150 and is electrically connected to the drain region 124 and the second gate metal layer 142 through a through hole.
  • FIG. 3 is a top view of a partial wiring of a display panel in a specific embodiment of the present invention.
  • the area A where the second gate metal layer 142 is located in FIG. 2 is a corresponding cross-sectional view of the area A in FIG. 3.
  • the plurality of thin film transistors are distributed in an array, including at least one row of thin film transistors arranged in a first direction and at least one column of thin film transistors arranged in a second direction.
  • the second gate metal layer 142 in the plurality of thin film transistors in the same row is electrically connected, and the second gate metal layer 142 in the plurality of thin film transistors in the same column is electrically insulated.
  • planarization layer 170 covers the source metal layer 164, the drain metal layer 162, and the interlayer dielectric layer 150.
  • the light emitting structure is located on the thin film transistor layer.
  • the light emitting structure includes an anode 182, a pixel defining layer 190, a light emitting material layer 184, and a cathode 186.
  • the anode 182 is located on the planarization layer 170 and is electrically connected to the source/drain metal layer 160 through through holes; the pixel definition layer 190 is located on the planarization layer 172 and has the anode exposed.
  • the luminescent material layer 184 is located on the anode 182; the cathode 186 covers the luminescent material layer 184.
  • the projection of the luminescent material layer on the substrate 112 is similar to the first gate metal layer 140 and the second gate metal layer. 142 does not overlap.
  • the present invention also provides an electronic device, which includes the display panel as described above.
  • a first gate metal layer and a second gate metal layer are arranged in the buffer layer of the back-gate thin film transistor, and the second gate metal layer is connected to the drain wiring layer through a through hole,
  • the area of the metal trace is effectively increased, and the resistance of the signal line is reduced, thereby effectively avoiding the voltage drop on the signal line.
  • the first gate metal layer and the second gate metal layer are light-shielding metal layers to prevent external light from entering the active area, thereby avoiding threshold voltage drift.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板和电子设备。所述显示面板包括多个薄膜晶体管，所述薄膜晶体管包括：有源区、栅极介质层（130）、第一栅极金属层（140）、第二栅极金属层（142）、层间介质层（150）、源区金属层（164）和漏区金属层（162）。所述有源区包括沟道区（120）、源区（122）和漏区（124）；所述源区金属层（164）位于所述层间介质层（150）上，并且通过通孔与所述源区（122）电连接，所述漏区金属层（162）位于所述层间介质层（150）上，并且通过通孔与所述漏区（124）和所述第二栅极金属层（142）电连接。

Description

显示面板和电子设备 技术领域
本发明涉及电子显示领域，尤其涉及一种显示面板和电子设备。
 背景技术
为了减小电容耦合的对系统阻抗的影响，显示面板的薄膜晶体管层通常采用顶栅型薄膜晶体管，以减小信号线的负载。
 技术问题
对于大尺寸或超大尺寸的显示器，信号线的电阻变的无法忽略。该电阻会消耗电源电压，导致显示面板的亮度不均。因此，有必要提出一种能够消除信号线压降的薄膜晶体管结构。
 技术解决方案
本发明提供一种显示面板和电子设备，能够有效的降低显示面板中的信号线的电阻。
为解决上述问题，本发明提供了一种显示面板，其包括：
基板；
薄膜晶体管层，所述薄膜晶体管层位于所述基板上；
发光结构，所述发光结构位于所述薄膜晶体管层上；其中，
所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管包括：
缓冲层，所述缓冲层位于所述基板上；
第一栅极金属层和第二栅极金属层，所述第一栅极金属层和第二栅极金属层位于所述缓冲层上；
栅极介质层，所述栅极介质层覆盖所述第一栅极金属层和第二栅极金属层；
有源区，所述有源区位于所述栅极介质层上，所述有源区包括沟道区和位于所述沟道区两侧的源区和漏区，所述沟道区位于所述第一栅极金属层正上方；
层间介质层，所述层间介质层覆盖所述有源区；
源区金属层，所述源区金属层位于所述层间介质层上，并且通过通孔与所述源区电连接；
漏区金属层，所述漏区金属层位于所述层间介质层上，并且通过通孔与所述漏区和所述第二栅极金属层电连接；
平坦化层，所述平坦化层覆盖所述源区金属层、漏区金属层和层间介质层。
根据本发明的其中一个方面，所述第一栅极金属层和第二栅极金属层为遮光金属层。
根据本发明的其中一个方面，所述发光结构包括发光材料层，所述发光材料层在所述基板上的投影与所述第一栅极金属层和第二栅极金属层不重合。
根据本发明的其中一个方面，所述第一栅极金属层和第二栅极金属层之间电绝缘。
根据本发明的其中一个方面，所述第一栅极金属层在所述缓冲层上的投影覆盖所述沟道区在所述缓冲层上的投影。
根据本发明的其中一个方面，所述第一栅极金属层沿沟道方向的长度大于所述沟道区沿沟道方向的长度，所述第一栅极金属层覆盖所述沟道区相邻的部分源区和漏区。
根据本发明的其中一个方面，所述多个薄膜晶体管呈阵列状分布，包括沿第一方向排列的至少一行薄膜晶体管和沿第二方向排列的至少一列薄膜晶体管；其中，
同一行的多个薄膜晶体管中的第二栅极金属层电连接，同一列中的多个薄膜晶体管中的第二栅极金属层电绝缘。
根据本发明的其中一个方面，所述遮光金属层与所述基板相邻的表面具有均匀分布的漫反射结构。
根据本发明的其中一个方面，所述遮光金属层与所述基板相邻的表面具有均匀起伏的波浪形结构。
相应的，本发明还提供了一种电子设备，其包括显示面板，所述显示面板包括：
基板；
薄膜晶体管层，所述薄膜晶体管层位于所述基板上；
发光结构，所述发光结构位于所述薄膜晶体管层上；其中，
所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管包括：
缓冲层，所述缓冲层位于所述基板上；
第一栅极金属层和第二栅极金属层，所述第一栅极金属层和第二栅极金属层位于所述缓冲层上；
栅极介质层，所述栅极介质层覆盖所述第一栅极金属层和第二栅极金属层；
有源区，所述有源区位于所述栅极介质层上，所述有源区包括沟道区和位于所述沟道区两侧的源区和漏区，所述沟道区位于所述第一栅极金属层正上方；
层间介质层，所述层间介质层覆盖所述有源区；
源区金属层，所述源区金属层位于所述层间介质层上，并且通过通孔与所述源区电连接；
漏区金属层，所述漏区金属层位于所述层间介质层上，并且通过通孔与所述漏区和所述第二栅极金属层电连接；
平坦化层，所述平坦化层覆盖所述源区金属层、漏区金属层和层间介质层。
根据本发明的其中一个方面，所述第一栅极金属层和第二栅极金属层为遮光金属层。
根据本发明的其中一个方面，所述发光结构包括发光材料层，所述发光材料层在所述基板上的投影与所述第一栅极金属层和第二栅极金属层不重合。
根据本发明的其中一个方面，所述第一栅极金属层和第二栅极金属层之间电绝缘。
根据本发明的其中一个方面，所述第一栅极金属层在所述缓冲层上的投影覆盖所述沟道区在所述缓冲层上的投影。
根据本发明的其中一个方面，所述第一栅极金属层沿沟道方向的长度大于所述沟道区沿沟道方向的长度，所述第一栅极金属层覆盖所述沟道区相邻的部分源区和漏区。
根据本发明的其中一个方面，所述多个薄膜晶体管呈阵列状分布，包括沿第一方向排列的至少一行薄膜晶体管和沿第二方向排列的至少一列薄膜晶体管；其中，
同一行的多个薄膜晶体管中的第二栅极金属层电连接，同一列中的多个薄膜晶体管中的第二栅极金属层电绝缘。
根据本发明的其中一个方面，所述遮光金属层与所述基板相邻的表面具有均匀分布的漫反射结构。
根据本发明的其中一个方面，所述遮光金属层与所述基板相邻的表面具有均匀起伏的波浪形结构。
 有益效果
本发明在背栅型薄膜晶体管中的缓冲层中设置了第一栅极金属层和第二栅极金属层，所述第二栅极金属层通过通孔与所述漏区走线层相连，有效的增大了金属走线的面积，减小了信号线的电阻，从而有效的避免了信号线上的压降。同时，所述第一栅极金属层和第二栅极金属层为遮光金属层，避免外界光线射入有源区，从而避免阈值电压漂移。
 附图说明
图1为现有技术中的显示面板的示意性剖面图；
图2为本发明的一个具体实施例中的显示面板的示意性剖面图；
图3为本发明的一个具体实施例中的显示面板的局部走线的俯视图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
首先对现有技术进行简要说明。参见图1，图1为现有技术中的显示面板的示意性剖面图。所述显示面板包括：基板112、薄膜晶体管层和发光结构。
所述薄膜晶体管层位于所述基板112上，包括多个薄膜晶体管。每一个所述薄膜晶体管包括：缓冲层116，所述缓冲层116位于所述基板112上；有源区，所述有源区位于缓冲层116上，所述有源区包括沟道区120和位于所述沟道区120两侧的源区122和漏区124；栅极介质层130，所述栅极介质层130覆盖所述有源区；栅极金属层140，所述栅极金属层140覆盖位于所述有源区上方的栅极介质层130；层间介质层150，所述层间介质层150覆盖所述栅极金属层140；源漏金属层，所述源漏金属层位于所述层间介质层150上；平坦化层170，所述平坦化层170覆盖所述源漏金属层和层间介质层150。
所述发光结构位于所述薄膜晶体管层上。所述发光结构包括阳极182、像素定义层190、发光材料层184和阴极186。
所述阳极182位于所述平坦化层170上，并通过通孔与所述源漏金属层160电连接；所述像素定义层190位于所述平坦化层172上，并具有暴露出所述阳极182的通孔；所述发光材料层184位于所述阳极182上；所述阴极186覆盖所述发光材料层184。
参见图1，在现有技术中，对于大尺寸或超大尺寸的显示器，源漏金属层的电阻变的无法忽略。该电阻会消耗电源电压，导致显示面板的亮度不均。
针对上述问题，本发明提供一种显示面板和电子设备，能够有效的降低显示面板中的信号线的电阻。参见图2和图3，图2为本发明的一个具体实施例中的显示面板的示意性剖面图，图3为本发明的一个具体实施例中的显示面板的局部走线的俯视图。
在本实施例中，所述显示面板为有机发光二极管（organiclightemittingdiode, OLED）显示面板。在本发明的其他实施例中，所述显示面板也可以是液晶显示面板或其他类型的显示面板。
参见图2，所述显示面板包括：基板112、薄膜晶体管层和发光结构。
所述基板112可以是刚性基板或柔性基板。刚性基板包括玻璃、金属等，柔性基板可以是各种聚合物，例如聚酰亚胺。
所述薄膜晶体管层位于所述基板112上，包括多个薄膜晶体管，所述薄膜晶体管包括：缓冲层116、有源区、栅极介质层130、第一栅极金属层140、第二栅极金属层142、层间介质层150、源区金属层164、漏区金属层162、平坦化层170。
在本实施例中，所述第一栅极金属层140和第二栅极金属层142之间电绝缘。
所述第一栅极金属层140在所述缓冲层上的投影覆盖所述沟道区120在所述缓冲层上的投影。
所述第二栅极金属层142在所述缓冲层116上的投影覆盖所述漏区金属层162在所述缓冲层116上的投影。优选的，所述第二栅极金属层142的形状和面积与所述漏区金属层162相同。这样设置有两个好处，一方面，由于所述第二栅极金属层142和所述漏区金属层162具有相同的形状，则二者可以通过同一块掩膜版形成，从而降低生产成本。另一方面，所述第二栅极金属层142和所述漏区金属层162的位置和形状对应，二者在所述缓冲层116上的投影重合，实现二者之间电连接的通孔位置可以根据实际任意设置，便于工艺实现。
在本实施例中，所述第一栅极金属层140和第二栅极金属层142为遮光金属层。遮光金属层能够有效的避免外界的光线进入有源区，有效的抑制了有源区的电子跃迁。对于非晶硅薄膜晶体管，遮光金属层能够极大地增强薄膜晶体管的稳定性。
优选的，所述第一栅极金属层140和第二栅极金属层142与所述基板112相邻的表面具有均匀分布的漫反射结构，漫反射结构可以是颗粒状的磨砂表面。在其他实施例中，优选的，所述遮光金属层与所述基板112相邻的表面具有均匀起伏的波浪形结构。所述漫反射结构和波浪形结构能够对光线进行发散和吸收，进一步增强第一栅极金属层140和第二栅极金属层142的遮光效果。
在本实施例中，所述缓冲层116位于所述基板112上。所述缓冲层116为半导体氧化物或氮化物，例如氧化硅、氮化硅等。
在本实施例中，所述栅极金属层130覆盖位于所述第一栅极金属层140和第二栅极金属层142。优选的，所述栅极介质层130覆盖所述第一栅极金属层140和第二栅极金属层142和所述缓冲层116。整体覆盖能够节省形成栅介质层的掩膜版，从而节约成本。
所述有源区包括沟道区120和位于所述沟道区120两侧的源区122和漏区124。所述第一栅极金属层140在所述缓冲层上的投影覆盖所述沟道区120在所述缓冲层上的投影。在其他实施例中，所述第一栅极金属层140在所述缓冲层上的投影覆盖所述沟道区120在所述缓冲层上的投影。优选的，所述第一栅极金属层140在所述缓冲层上的投影面积大于所述沟道区120在所述缓冲层上的投影面积，即所述第一栅极金属层140在所述缓冲层上的投影还覆盖所述源区122与沟道区120相邻的部分边界和漏区124与沟道区120相邻的部分边界。这样的设置能够增强栅控，很好的抑制短沟道效应。
在本实施例中，如图2所示，所述源区金属层164位于所述层间介质层150上，并且通过通孔与所述源区122电连接。所述漏区金属层162位于所述层间介质层150上，并且通过通孔与所述漏区124和所述第二栅极金属层142电连接。
参见图3，图3为本发明的一个具体实施例中的显示面板的局部走线的俯视图。图2中所述第二栅极金属层142所在的A区域为图3中的A区域的对应剖面图。在本实施例中，所述多个薄膜晶体管呈阵列状分布，包括沿第一方向排列的至少一行薄膜晶体管和沿第二方向排列的至少一列薄膜晶体管。同一行的多个薄膜晶体管中的第二栅极金属层142电连接，同一列中的多个薄膜晶体管中的第二栅极金属层142电绝缘。
在本实施例中，所述平坦化层170覆盖所述源区金属层164、漏区金属层162和层间介质层150。
在本实施例中，所述发光结构位于所述薄膜晶体管层上。所述发光结构包括阳极182、像素定义层190、发光材料层184和阴极186。所述阳极182位于所述平坦化层170上，并通过通孔与所述源漏金属层160电连接；所述像素定义层190位于所述平坦化层172上，并具有暴露出所述阳极182的通孔；所述发光材料层184位于所述阳极182上；所述阴极186覆盖所述发光材料层184。
在本实施例中，为了避免金属走线影响所述显示面板的发光效果，所述发光材料层在所述基板112上的投影与所述第一栅极金属层140和第二栅极金属层142不重合。
相应的，本发明还提供了一种电子设备，其包括如前所述的显示面板。
本发明在背栅型薄膜晶体管中的缓冲层中设置了第一栅极金属层和第二栅极金属层，所述第二栅极金属层通过通孔与所述漏区走线层相连，有效的增大了金属走线的面积，减小了信号线的电阻，从而有效的避免了信号线上的压降。同时，所述第一栅极金属层和第二栅极金属层为遮光金属层，避免外界光线射入有源区，从而避免阈值电压漂移。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种显示面板，其中，所述显示面板包括：
    基板；
    薄膜晶体管层，所述薄膜晶体管层位于所述基板上；
    发光结构，所述发光结构位于所述薄膜晶体管层上；其中，
    所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管包括：
    缓冲层，所述缓冲层位于所述基板上；
    第一栅极金属层和第二栅极金属层，所述第一栅极金属层和第二栅极金属层位于所述缓冲层上；
    栅极介质层，所述栅极介质层覆盖所述第一栅极金属层和第二栅极金属层；
    有源区，所述有源区位于所述栅极介质层上，所述有源区包括沟道区和位于所述沟道区两侧的源区和漏区，所述沟道区位于所述第一栅极金属层正上方；
    层间介质层，所述层间介质层覆盖所述有源区；
    源区金属层，所述源区金属层位于所述层间介质层上，并且通过通孔与所述源区电连接；
    漏区金属层，所述漏区金属层位于所述层间介质层上，并且通过通孔与所述漏区和所述第二栅极金属层电连接；
    平坦化层，所述平坦化层覆盖所述源区金属层、漏区金属层和层间介质层。
  2. 根据权利要求1所述的显示面板，其中，所述第一栅极金属层和第二栅极金属层为遮光金属层。
  3. 根据权利要求2所述的显示面板，其中，所述发光结构包括发光材料层，所述发光材料层在所述基板上的投影与所述第一栅极金属层和第二栅极金属层不重合。
  4. 根据权利要求1所述的显示面板，其中，所述第一栅极金属层和第二栅极金属层之间电绝缘。
  5. 根据权利要求1所述的显示面板，其中，所述第一栅极金属层在所述缓冲层上的投影覆盖所述沟道区在所述缓冲层上的投影。
  6. 根据权利要求5所述的显示面板，其中，所述第一栅极金属层沿沟道方向的长度大于所述沟道区沿沟道方向的长度，所述第一栅极金属层覆盖所述沟道区相邻的部分源区和漏区。
  7. 根据权利要求1所述的显示面板，其中，所述多个薄膜晶体管呈阵列状分布，包括沿第一方向排列的至少一行薄膜晶体管和沿第二方向排列的至少一列薄膜晶体管；其中，
    同一行的多个薄膜晶体管中的第二栅极金属层电连接，同一列中的多个薄膜晶体管中的第二栅极金属层电绝缘。
  8. 根据权利要求2所述的显示面板，其中，所述遮光金属层与所述基板相邻的表面具有均匀分布的漫反射结构。
  9. 根据权利要求8所述的显示面板，其中，所述遮光金属层与所述基板相邻的表面具有均匀起伏的波浪形结构。
  10. 一种电子设备，其中，所述电子设备包括显示面板，所述显示面板包括：
    基板；
    薄膜晶体管层，所述薄膜晶体管层位于所述基板上；
    发光结构，所述发光结构位于所述薄膜晶体管层上；其中，
    所述薄膜晶体管层包括多个薄膜晶体管，所述薄膜晶体管包括：
    缓冲层，所述缓冲层位于所述基板上；
    第一栅极金属层和第二栅极金属层，所述第一栅极金属层和第二栅极金属层位于所述缓冲层上；
    栅极介质层，所述栅极介质层覆盖所述第一栅极金属层和第二栅极金属层；
    有源区，所述有源区位于所述栅极介质层上，所述有源区包括沟道区和位于所述沟道区两侧的源区和漏区，所述沟道区位于所述第一栅极金属层正上方；
    层间介质层，所述层间介质层覆盖所述有源区；
    源区金属层，所述源区金属层位于所述层间介质层上，并且通过通孔与所述源区电连接；
    漏区金属层，所述漏区金属层位于所述层间介质层上，并且通过通孔与所述漏区和所述第二栅极金属层电连接；
    平坦化层，所述平坦化层覆盖所述源区金属层、漏区金属层和层间介质层。
  11. 根据权利要求10所述的电子设备，其中，所述第一栅极金属层和第二栅极金属层为遮光金属层。
  12. 根据权利要求11所述的电子设备，其中，所述发光结构包括发光材料层，所述发光材料层在所述基板上的投影与所述第一栅极金属层和第二栅极金属层不重合。
  13. 根据权利要求10所述的电子设备，其中，所述第一栅极金属层和第二栅极金属层之间电绝缘。
  14. 根据权利要求10所述的电子设备，其中，所述第一栅极金属层在所述缓冲层上的投影覆盖所述沟道区在所述缓冲层上的投影。
  15. 根据权利要求14所述的电子设备，其中，所述第一栅极金属层沿沟道方向的长度大于所述沟道区沿沟道方向的长度，所述第一栅极金属层覆盖所述沟道区相邻的部分源区和漏区。
  16. 根据权利要求10所述的电子设备，其中，所述多个薄膜晶体管呈阵列状分布，包括沿第一方向排列的至少一行薄膜晶体管和沿第二方向排列的至少一列薄膜晶体管；其中，
    同一行的多个薄膜晶体管中的第二栅极金属层电连接，同一列中的多个薄膜晶体管中的第二栅极金属层电绝缘。
  17. 根据权利要求11所述的电子设备，其中，所述遮光金属层与所述基板相邻的表面具有均匀分布的漫反射结构。
  18. 根据权利要求17所述的电子设备，其中，所述遮光金属层与所述基板相邻的表面具有均匀起伏的波浪形结构。
PCT/CN2019/084040 2019-04-08 2019-04-24 显示面板和电子设备 Ceased WO2020206740A1 (zh)

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