WO2020206591A1

WO2020206591A1 - Chip test indenter and chip test device

Info

Publication number: WO2020206591A1
Application number: PCT/CN2019/081758
Authority: WO
Inventors: 王攀; 段源鸿; 王华杲
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2019-04-08
Filing date: 2019-04-08
Publication date: 2020-10-15
Also published as: CN211348543U

Abstract

A chip test indenter (1) and a chip test device, wherein the chip test indenter (1) comprises an indenter body (11), an adapter plate (12), a socket (13) and an adsorption structure (14); wherein the adapter plate (12) is embedded into the indenter body (11), and the adapter plate (12) is provided with a first electrical connection point (121) and a second electrical connection point (122), wherein the first electrical connection point (121) is electrically connected to the second electrical connection point (122); the bottom of the socket (13) is embedded into the indenter body (11), one end of the adsorption structure (14) is arranged outside the indenter body (11), and the other end of the adsorption structure (14) passes through the bottom of the socket (13); when a chip (3) to be tested is adsorbed into the socket (13) by the adsorption structure (14), the first electrical connection point (121) and a PAD surface (31) of the chip (3) to be tested form an electrical connection, and the second electrical connection point (122) and a test circuit board (2) form an electrical connection, so as to test the chip (3) to be tested. The chip test indenter (1) can simultaneously complete the test on the PAD surface (31) and a non-PAD surface (32).

Description

Chip testing indenter and chip testing device

Technical field

This application relates to the testing field, and in particular to a chip testing indenter and a chip testing device.

Background technique

A chip is a silicon chip containing an integrated circuit, which is small in size and is often an important part of a computer or other electronic equipment. With the development of technology, the function of the chip becomes more and more powerful, and the complexity becomes higher and higher. However, in order to ensure the reliability of the factory chip, it needs to be tested until it is qualified.

Different types of chips have different requirements for testing. For example, for a chip with a PAD surface and a non-PAD surface, when testing it, some only need to test the PAD surface, and some need to test both the PAD surface and the non-PAD surface, such as photoelectric As an example, for example, in addition to testing the PAD surface, it is also necessary to test the photosensitive element or light-emitting element on the non-PAD surface.

In the existing technical solution, since the requirement for testing the non-PAD surface is not taken into consideration, it is impossible to directly use the existing test solution to test the non-PAD surface of the chip. Therefore, there is an urgent need for a technical solution that can simultaneously perform batch testing on the PAD surface and the non-PAD surface of the chip.

Summary of the invention

The purpose of this application is to provide a chip test indenter and a chip test device to solve the problems in the prior art.

In the first aspect, an embodiment of the present application provides a chip test indenter, including an indenter body, an adapter plate, a socket, and a suction structure; the adapter plate is embedded in the indenter body, and the adapter plate is provided There are a first electrical connection point and a second electrical connection point, the first electrical connection point is electrically connected to the second electrical connection point; the bottom of the socket is embedded in the indenter body; one end of the adsorption structure is set on the Outside the indenter body, the other end of the suction structure passes through the bottom of the socket; when the chip under test is sucked into the socket by the suction structure, the first electrical connection point and the chip under test are The PAD surface forms an electrical connection, and the second electrical connection point forms an electrical connection with the test circuit board to test the chip under test.

Optionally, in any embodiment of the present application, the indenter body has a first accommodating space and a second accommodating space, and the second accommodating space is disposed in the first accommodating space, The first accommodating space has a first tooling surface, the first tooling surface is provided with the adapter plate, the second accommodating space has a second tooling surface, and the second tooling surface is provided with The socket.

Optionally, in any embodiment of the present application, the bottom of the socket is disposed on the second tooling surface, and the groove of the socket faces the test circuit board.

Optionally, in any embodiment of the present application, the adsorption structure passes through the indenter body, the adapter plate and the socket in sequence to adsorb the chip under test into the socket.

Optionally, in any embodiment of the present application, the distance between the second electrical connection point and the geometric center of the adapter plate is greater than the distance between the first electrical connection point and the geometric center of the adapter plate.

Optionally, in any embodiment of the present application, it further includes a first connector, one end of which is connected to the first electrical connection point, and the other end passes through the bottom of the socket to be able to connect to the Pins on the PAD surface of the chip to be tested so that the first electrical connection point is electrically connected to the PAD surface of the chip to be tested through the first connector.

In a second aspect, an embodiment of the present application provides a chip testing device, which includes a test circuit board and the indenter described in the foregoing embodiment.

Optionally, in any embodiment of the present application, it further includes a second connector, one end of which is connected to the second electrical connection point, and the other end is connected to the third electrical connection point on the test circuit board, so that The second electrical connection point forms an electrical connection with the test circuit board through a second connector.

Optionally, in any embodiment of the present application, it further includes: a test base, the test base is arranged between the indenter and the test circuit board, and is used to protect the test circuit board.

Optionally, in any embodiment of the present application, it further includes: an optical test module, the optical test module is arranged toward the non-PAD surface of the chip to be tested, and is used to perform an optical test on the chip to be tested.

Optionally, in any embodiment of the present application, the optical test module includes: an optical channel, the optical channel is arranged on the test base, and the arrangement position of the optical channel corresponds to the non-PAD surface of the chip under test .

Optionally, in any embodiment of the present application, the optical test module includes: a light source whose position corresponds to the non-PAD surface of the chip to be tested and is used to construct a light environment required by the test chip.

Optionally, in any embodiment of the present application, the light source is arranged under the test circuit board or in the light channel.

Optionally, in any embodiment of the present application, the optical test module further includes: a light tube, the light tube is disposed under the test circuit board, and is used to adjust the light source.

Optionally, in any embodiment of the present application, the optical test module further includes: an optical path adjusting component, which is arranged in the optical channel.

It can be seen from the above solution that the chip test indenter provided by this application includes an indenter body, an adapter plate, a socket, and an adsorption structure; the adapter plate is embedded in the indenter body, and the adapter plate is provided with a first An electrical connection point and a second electrical connection point, the first electrical connection point is electrically connected to the second electrical connection point; the bottom of the socket is embedded in the indenter body, and one end of the adsorption structure is arranged on the indenter Outside the body, the other end of the suction structure passes through the bottom of the socket; when the chip under test is sucked into the socket by the suction structure, the first electrical connection point is formed with the PAD surface of the chip under test Electrical connection, forming an electrical connection between the chip test indenter and the test circuit board through the second electrical connection point to form a chip testing device to test the chip under test. With the chip testing device, in addition to the test based on the PAD surface, the test on the non-PAD surface can also be completed.

Description of the drawings

In order to more clearly describe the technical solutions in the present application or the prior art, the following briefly introduces the drawings needed in the embodiments. Obviously, the drawings in the following description are only some of the records in this application. For those of ordinary skill in the art, other drawings can be obtained from these drawings.

FIG. 1A is a schematic structural diagram of a chip test indenter according to Embodiment 1 of the application.

FIG. 1B is a schematic diagram of the structure of the chip test indenter according to the first embodiment of the application.

FIG. 1C is a schematic diagram of the structure of the chip test indenter according to the first embodiment of the application.

FIG. 2 is a schematic diagram of the structure of the chip testing device according to the second embodiment of the application.

FIG. 3 is a schematic diagram of the structure of the chip testing device according to the third embodiment of the application.

detailed description

Of course, implementing any technical solution of the embodiments of the present application does not necessarily need to achieve all the above advantages at the same time.

In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the description The embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art should fall within the protection scope of the embodiments of the present application.

In the embodiment of the present application, when the chip to be tested is tested, the PAD surface of the chip to be tested is sucked by the adsorption structure, so that the chip to be tested is adsorbed into the socket, so that the pins on the PAD surface of the chip to be tested and the first The electrical connection points are connected, so that the chip under test and the adapter board are electrically connected; then the pressure head is pressed down to the test circuit board, and the second electrical connection point forms an electrical connection with the test circuit board to form a complete electrical circuit, The PAD surface of the chip to be tested can be tested; if there is a need to test the non-PAD surface of the chip to be tested, the test conditions can be set at the position facing the non-PAD surface of the chip to be tested, such as a pressure test module or an optical test module, etc. , And connect the test circuit board to the test machine to complete the test of the PAD surface and the non-PAD surface of the chip under test at the same time, thereby completing the performance or function test of the chip under test.

The specific implementation of the embodiments of the present application will be further described below in conjunction with the drawings of the embodiments of the present application.

FIG. 1A is a schematic structural diagram of a chip test indenter according to Embodiment 1 of the application. Fig. 1B is a schematic diagram of the structure of the chip test indenter according to the first embodiment of the application. FIG. 1C is a schematic diagram of the structure of the chip test indenter according to the first embodiment of the application. In FIG. 1A, the chip test indenter 1 does not show the adapter plate 12, socket 13 and the adsorption structure 14 in FIG. 1C to show the indenter body 11 more clearly. In FIG. 1B, the chip test indenter 1 is shown in FIG. 1A. On the basis, the adapter plate 12 is added but the socket 13 and the suction structure 14 are not shown to clearly show the positional relationship between the adapter plate 12 and the indenter body 11; the chip test indenter 1 in Figure 1C is based on Figure 1B The socket 13 and the suction structure 14 are added to clearly show the positional relationship between the socket 13 and the adapter plate 12, the indenter body 11, and the relationship between the suction structure 14 and the adapter plate 12, the indenter body 11, and the chip 3 to be tested. Positional relationship.

As shown in FIG. 1A, the chip test indenter 1 includes an indenter body 11. In this embodiment, the shape of the cross section of the indenter 1 is not limited. For the convenience of production and use, it is preferably set to be square. Of course, it can also be set to other shapes, such as circular, etc. Other components such as test circuit board 2. The cross-sectional shape (shown in FIG. 2 for details) can be adapted to the cross-sectional shape of the indenter 1 to complete the test of the chip 3 to be tested.

1A specifically, in this embodiment, the indenter body 11 has a first accommodating space 111 and a second accommodating space 112, and the second accommodating space 112 is disposed in the first accommodating space 111 The first accommodating space 111 has a first tooling surface 1111, the first tooling surface 1111 is provided with the adapter plate 12 shown in FIG. 1B, and the second accommodating space 112 has a second tooling surface 1121. , The second tooling surface 1121 is provided with a socket 13 shown in FIG. 1C.

Further, referring to FIG. 1B in detail, the adapter plate 12 is embedded in the first accommodating space 111 of the indenter body 11 and located outside the second accommodating space 112 and arranged on the first tooling surface 1111 , And the adapter board 12 is provided with a first electrical connection point 121 and a second electrical connection point 122, the first electrical connection point 121 and the second electrical connection point 122 are electrically connected to form an electrical connection path for easy handling Test chip 3 for testing. As shown in FIG. 1B, the adapter plate 12 completely covers the first tooling surface 1111, but the adapter plate 12 may not completely cover the first tooling surface 1111 if the test can be satisfied.

Still further, the bottom of the socket 13 is embedded in the indenter body 11, one end of the suction structure 14 is arranged outside the indenter body 11, and the other end of the suction structure 14 passes through the socket 13 Bottom; specifically, as shown in FIG. 1C, the bottom of the socket 13 is set on the second tooling surface 1121 shown in FIG. 1A, so that the groove of the socket 13 faces the test circuit board 2, matching The suction structure 14 passes through the indenter body 11, the adapter plate 12, and the socket 13 in sequence, and sucks the chip 3 under test into the groove of the socket 13; the chip under test 3 is When the adsorption structure 14 is adsorbed into the socket 13, the first electrical connection point 121 is electrically connected to the PAD surface 31 of the chip under test 3, that is, the integrated surface of the input and output pins after the chip is packaged, so The second electrical connection point 122 is electrically connected with the test circuit board 2 to test the chip 3 under test.

Specifically, when the adsorption structure 14 sucks the PAD surface 31 of the chip under test 3 into the socket 13, the non-PAD surface 32 of the chip under test 3 can face the test circuit board 2. When there is a test requirement on the non-PAD surface 32 of the chip 3 to be tested, a corresponding test environment is set in the space between the indenter 1 and the test circuit board 2, with the cooperation of the socket 13 and the adapter board 12, thereby completing The PAD surface 31 and the non-PAD surface 32 of the chip 3 to be tested are tested.

In this embodiment, when the adsorption structure 14 sucks the chip 3 to be tested into the socket 13, the groove on the socket 13 can accommodate the chip 3 to be tested on the one hand, and can also serve as a limit. The function of the position makes the position of the test chip 3 more stable, avoiding secondary damage to the test chip 3 by sliding the test chip 3 left and right, which affects the pass rate of the test chip 3; and the socket 13 realizes the test chip 3 3 The electrical connection with the adapter board 12 can ensure that the electrical connection between the two through the first electrical connection point 121 is more sufficient, and the test process can be carried out smoothly.

In a specific implementation scenario, for the simple structure of the test device, the suction structure 14 is configured as a vacuum suction nozzle. Correspondingly, the vacuum suction nozzle is set at the geometric center of the indenter 1 to suck the smooth part of the PAD surface 31 of the chip 3 to be tested to ensure that no other parts on the chip 3 to be tested block the formation of a vacuum environment. It can be set in other suitable positions according to different smooth positions of different chips 3 under test.

In a specific implementation scenario, the chip testing device further includes a first connector 4, and the first electrical connection point 121 is electrically connected to the PAD surface 31 of the chip under test 3 through the first connector 4 . Specifically, in order to simplify the structure of the chip testing device and save costs, the first connector 4 is preferably a spring probe, one end is connected to the first electrical connection point 121, and the other end passes through the bottom of the socket 13 to be able to connect The pins on the PAD surface 31 of the chip under test 3 of the socket 13 are sucked. To this end, the length of the first connecting member 4 can be adapted to the distance between the first electrical connection point 121 and the chip 3 to be tested that is adsorbed to the socket 13, so as to ensure that the adapter plate 12 A stable electrical connection is formed with the chip 3 under test.

FIG. 2 is a schematic diagram of the structure of the chip testing device according to the second embodiment of the application. As shown in FIG. 2, the chip testing device includes a test circuit board 2 and the indenter 1 as described in the above embodiment. In a specific implementation scenario, as described above, the adapter board 12 is provided with a first electrical connection point 121 and a second electrical connection point 122. Therefore, in order to ensure that the chip 3 to be tested is set in the socket 13 On the one hand, it can form an electrical connection with the adapter board 12, and at the same time, ensure that the adapter board 12 can form an electrical connection with the test circuit board 2. Preferably, the second electrical connection point 122 is away from the geometric center of the adapter board 12. The distance is greater than the distance between the first electrical connection point 121 and the geometric center of the adapter plate 12. Specifically, as shown in FIG. 1C, the size of the socket 13 is adapted to the size of the chip under test 3, and is generally small. Therefore, when the chip under test 3 enters the socket 13, the first electrical connection The point 121 can be electrically connected to the PAD surface 31 of the chip under test 3, because the distance between the second electrical connection point 122 and the geometric center of the adapter board 12 is greater than the distance between the first electrical connection point 121 and the rotation The distance between the geometric center of the connection board 12, therefore, the adapter board 12 and the test circuit board 2 can be electrically connected through the second electrical connection point 122 to form a complete test path.

In a specific implementation scenario, the chip testing device further includes a second connector 5, and the second electrical connection point 122 forms an electrical connection with the test circuit board 2 through the second connector 5. Specifically, in order to simplify the structure of the chip testing device and save costs, the second connector 5 is also preferably a spring probe, one end is connected to the second electrical connection point 122, and the other end is connected to the test circuit board 2 The third electrical connection point 21. To this end, the length of the second connection member 5 can be adapted to the distance between the second electrical connection point 122 and the third electrical connection point 21 on the test circuit board 2 to ensure that the rotation A stable electrical connection is formed between the connecting board 12 and the test circuit board 2.

It should be noted that the first connecting member 4 and the second connecting member 5 can also be configured in other structures, such as flat cables.

In a specific implementation scenario, the chip testing device further includes a test base 6 which is arranged between the indenter 1 and the test circuit board 2 for protecting the test circuit board 2. Specifically, by setting the test base 6 so that the test circuit board 2 is not damaged when the indenter 1 is pressed down in the direction shown by the arrow in FIG. 1C, and can also use the indenter The interaction force between 1 and the test base 6 enables the chip 3 to be tested to fully enter the socket 13 and form an effective electrical connection with the first connector 4.

In this embodiment, when testing the chip 3 to be tested, the PAD surface 31 of the chip to be tested 3 is sucked by the adsorption structure 14 so that the chip to be tested 3 is sucked into the socket 13 so that the PAD surface 31 of the chip to be tested 3 The pin is connected to the first electrical connection point 121, so that the chip under test 3 and the adapter board 12 are electrically connected; then the indenter 1 is pressed down to the test circuit board 2 in the direction shown by the arrow in FIG. 1C , The second electrical connection point 122 forms an electrical connection with the test circuit board 2 to form a complete electrical circuit, and the PAD surface 31 of the test chip 3 can be tested; if there is a non-PAD surface 32 of the test chip 3 For testing requirements, test conditions can be set at the position facing the non-PAD surface 32 of the chip 3 to be tested, for example, a pressure test module or an optical test module, etc., and the test circuit board 2 is connected to the test machine to complete the treatment at the same time. The PAD surface 31 and the non-PAD surface 32 of the test chip 3 are tested.

FIG. 3 is a schematic diagram of the structure of the chip testing device according to the third embodiment of the application. This embodiment specifically takes an optoelectronic chip as an example, and uses the chip testing device to test the PAD surface 31 and the non-PAD surface 32 of the chip 3 to be tested. As shown in FIG. 3, the difference from the embodiment in FIG. 2 is that the chip testing device further includes an optical testing module 7, and the optical testing module 7 is arranged toward the non-PAD surface 31 of the chip to be tested 3 for alignment The chip 3 to be tested is tested for optical performance. The position where the optical test module 7 is set corresponds to the non-PAD surface 32 of the chip 3 to be tested. When there are photosensitive elements and/or light-emitting elements in the chip 3 to be tested, the size of the optical test module 7 is suitable for the size of the photosensitive surface and/or the size of the light-emitting surface of the chip 3 to be tested, so as to avoid blocking the chip 3 to be tested. The photosensitive surface and/or the luminous surface will affect the test results.

In this embodiment, the non-PAD surface 32 of the chip under test 3 faces the test circuit board 2. In order to perform an optical performance test on the non-PAD surface 32 of the chip under test 3, the optical test module 7 It is arranged on the side facing the non-PAD surface 32 of the chip 3 under test.

In a specific implementation scenario, the optical test module 7 includes an optical channel 71 which is arranged on the test base 6 and whose position is set corresponding to the non-PAD surface 32 of the chip 3 under test. Specifically, when the light-emitting performance test is performed on a photoelectric chip with a light-emitting device mounted on the non-PAD surface 32, the light channel 71 is preferably configured as a groove structure for placing standard photosensitive elements and testing the light-emitting of the chip 3 under test. performance. The size of the light channel 71 is suitable for the size of the light-emitting area of the chip 3 to be tested to complete the light-emitting performance test of the chip 3 to be tested.

Preferably, the cross-sectional area of the light channel 71 is smaller than the cross-sectional area of the chip 3 to be tested, when the indenter 1 is pressed down onto the test base 6 in the direction shown by the arrow in FIG. 2 At this time, the chip under test 3 does not enter the optical channel 71, but contacts the surface of the test base 6, and the interaction force between the indenter 1 and the test base 6 makes the chip under test The pins of the PAD surface 31 of 3 are in full contact with the first connector 4 to ensure that the chip under test 3 and the adapter board 12 form a stable electrical connection.

It should be noted that, in this embodiment, the depth of the light channel 71 is not limited, and the light-emitting performance of the chip 3 to be tested shall prevail. In a specific implementation scenario, the light channel 71 may also be set to penetrate the test base 6 and the test circuit board 2, and a standard photosensitive member is set at an appropriate position to test the luminous performance of the chip 3 to be tested. In order to save cost, the optical channel 71 is preferably configured as a through hole.

In a specific implementation scenario, the optical test module 7 may also include a light source 72 whose position corresponds to the non-PAD surface 32 of the chip 3 under test, and is used to construct the light environment required for testing the chip 3 under test, namely The photosensitive performance of the chip 3 to be tested is tested, for example, a photosensitive performance test is performed on a photoelectric chip with a photosensitive device mounted on the non-PAD surface 32. Specifically, the indenter 1 is pressed down in the direction indicated by the arrow in FIG. 2 and then the light source 72 is used to illuminate the chip 3 under test to test the photosensitive performance. In order to save costs, the light source 72 is preferably an LED lamp whose light intensity can be adjusted adaptively according to test requirements.

It should be noted that, in this embodiment, the depth of the optical channel 71 is not limited, and the sensitivity of the chip 3 to be tested shall prevail. In a specific implementation scenario, the light channel 71 may also be set to penetrate the test base 6 and the test circuit board 2, and then the light source 72 may be set under the test circuit board 2 or the light At a suitable position in the channel 71, the photosensitive performance of the chip 3 to be tested is tested.

In a specific implementation scenario, the optical test module 7 may further include a light tube 73 disposed under the test circuit board 2 for adjusting the light source 72. When the light source 72 is arranged under the test circuit board 2, the light tube 73 is also arranged under the test circuit board 2; preferably, the structure of the light tube 73 is fixed to the test circuit board by screws 2 on; Alternatively, the light tube 73 can also be in the light channel 71.

In a specific implementation scenario, when the optical performance test is performed on a photoelectric chip with light-emitting elements and photosensitive elements mounted on the non-PAD surface 32, the light channel 71 also includes a light path adjusting component 74 for adjusting the test The light path of the light emitting element of the chip 3 or the light path of the light source 72 emitting light, and the specific position of the light path adjusting component 74 is set according to the requirements of testing the chip 3 under test. In order to facilitate the testing requirements of different types of chips 3 to be tested, the optical path adjusting component 74 is preferably configured as a detachable type, installed on the chip testing device when needed, and removed when not needed.

It should be noted that the installation position of the light path adjustment component 74 is not limited, it can be installed in the light channel 71, or above the light source 72 in the light tube 73, as long as it can be treated The light path of the light emitting element of the test chip 3 or the light path of the light source 72 may be adjusted.

When testing the chip 3 under test, if the light source 72 is not turned on, the light path adjusting component 74 reflects the light emitted by the light emitting element of the chip under test 3 to the photosensitive element of the chip under test 3. If the chip 3 can be used normally, it means that there is no problem with the photosensitive element and the light-emitting element of the chip 3 to be tested. If the chip 3 to be tested cannot be used normally during the test, the light path adjusting component 74 can be disassembled, and then a standard photosensitive element is set at a suitable position in the light channel 71 or the light tube 73, and the light emitting element of the chip 3 to be tested Perform a test; if the light-emitting element has no problem after the test, turn on the light source 72 and test the photosensitive element of the chip 3 to be tested. If the photosensitive element has no problem after the test, the inside of the chip 3 to be tested can be explained The circuit has malfunctioned.

It should be noted that the test sequence of the photosensitive element and the light-emitting element is not limited, and the photosensitive element can be tested first, and then the light-emitting element. If the chip 3 under test cannot be used normally during the test without turning on the light source 72, it means that there is a problem with the photosensitive element or light emitting element of the chip under test 3, and both elements need to be tested.

In a specific implementation scenario, in order to facilitate testing of the chip 3 under test, the light path adjusting component 74 is not always disassembled to save time. Preferably, the light path adjusting component 74 is set as a reflective lens, which can reflect the chip under test. 3 The light emitted by the self-luminous element can pass through the light emitted by the light source 72.

The expressions "first", "second", "the first" or "the second" used in various embodiments of the present application can modify various components regardless of order and/or importance , But these expressions do not limit the corresponding components. The above expressions are only used for the purpose of distinguishing elements from other elements. For example, the first user equipment and the second user equipment represent different user equipment, although both are user equipment. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

Although the preferences of this application have been described, those skilled in the art can make additional changes and modifications to these once they learn the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including all changes and modifications that are preferred and fall within the scope of this application. Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application also intends to include these modifications and variations.

Claims

A chip test indenter, which is characterized by comprising an indenter body, an adapter plate, a socket, and an adsorption structure; the adapter plate is embedded in the indenter body, and the adapter plate is provided with a first electrical connection Point and a second electrical connection point, the first electrical connection point is electrically connected to the second electrical connection point; the bottom of the socket is embedded in the indenter body; one end of the adsorption structure is arranged outside the indenter body , The other end of the adsorption structure passes through the bottom of the socket; when the chip to be tested is adsorbed into the socket by the adsorption structure, the first electrical connection point is electrically connected to the PAD surface of the chip to be tested , The second electrical connection point is electrically connected with the test circuit board to test the chip under test.
The indenter according to claim 1, wherein the indenter body has a first accommodating space and a second accommodating space, and the second accommodating space is provided in the first accommodating space, The first accommodating space has a first tooling surface, the first tooling surface is provided with the adapter plate, the second accommodating space has a second tooling surface, and the second tooling surface is provided with The socket.
The indenter according to claim 2, wherein the bottom of the socket is arranged on the second tooling surface, and the groove of the socket faces the test circuit board.
The indenter according to claim 1, wherein the suction structure passes through the indenter body, the adapter plate and the socket in order to suck the chip under test into the socket.
The indenter according to claim 1, wherein the distance between the second electrical connection point and the geometric center of the adapter plate is greater than the distance between the first electrical connection point and the geometric center of the adapter plate.
The indenter according to claim 1, further comprising a first connector, one end of which is connected to the first electrical connection point, and the other end passes through the bottom of the socket to be able to connect to the Pins on the PAD surface of the chip to be tested so that the first electrical connection point is electrically connected to the PAD surface of the chip to be tested through the first connector.
A chip test device, characterized by comprising a test circuit board and the chip test indenter according to any one of claims 1-6.
8. The device according to claim 7, further comprising a second connector, one end of which is connected to the second electrical connection point, and the other end of which is connected to the third electrical connection point on the test circuit board, so that all The second electrical connection point is electrically connected to the test circuit board through a second connector.
8. The device according to claim 7, further comprising: a test base, the test base is arranged between the indenter and the test circuit board for protecting the test circuit board.
The device according to claim 9, further comprising: an optical test module, the optical test module is arranged toward the non-PAD surface of the chip under test, and is used to perform an optical test on the chip under test.
The device according to claim 10, wherein the optical test module comprises: an optical channel, the optical channel is arranged on the test base, and the arrangement position of the optical channel corresponds to the non-PAD surface of the chip under test.
The device according to claim 10, wherein the optical test module comprises: a light source whose position corresponds to the non-PAD surface of the chip to be tested, and is used to construct a light environment required by the test chip.
The device according to claim 12, wherein the light source is arranged under the test circuit board or in the light channel.
The device according to claim 12, wherein the optical test module further comprises: a light tube, the light tube is arranged under the test circuit board for adjusting the light source.
The device according to claim 11, wherein the optical test module further comprises: an optical path adjusting component, which is arranged in the optical channel.