WO2020199534A1 - 显示装置及其显示面板、显示面板的像素驱动电路 - Google Patents

显示装置及其显示面板、显示面板的像素驱动电路 Download PDF

Info

Publication number
WO2020199534A1
WO2020199534A1 PCT/CN2019/107913 CN2019107913W WO2020199534A1 WO 2020199534 A1 WO2020199534 A1 WO 2020199534A1 CN 2019107913 W CN2019107913 W CN 2019107913W WO 2020199534 A1 WO2020199534 A1 WO 2020199534A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
pixel
driving
sub
ratio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/107913
Other languages
English (en)
French (fr)
Inventor
沈志华
张露
吴剑龙
胡思明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
Original Assignee
Kunshan Govisionox Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Publication of WO2020199534A1 publication Critical patent/WO2020199534A1/zh
Priority to US17/320,990 priority Critical patent/US11355051B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays

Definitions

  • This application relates to the technical field of display devices, and in particular to a display device, a display panel thereof, and a pixel drive circuit of the display panel.
  • the purpose of this application is to provide a full-screen display device and its display panel and a pixel drive circuit for the display panel.
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are not the same transistor, by changing the width-to-length ratio of the driving transistor in the pixel driving circuit of each sub-pixel, So that: under the same gray scale, the aspect ratio of the driving transistor of each sub-pixel of the same color is proportional to the driving current;
  • the width-to-length ratio and storage of the driving transistor in the pixel driving circuit of each sub-pixel are changed.
  • the size of the capacitor is such that: under the same gray scale, the charging saturation of the storage capacitor of each sub-pixel of the same color is the same, and the aspect ratio of the driving transistor and the size of the storage capacitor of each sub-pixel of the same color are proportional to the driving current.
  • the charging saturation is the difference between the actual charged voltage and the theoretical shock voltage of the storage capacitor at the end of the charging phase.
  • the advantage is: through the product structure setting, the same data voltage can be applied to each sub-pixel of the same color, and the driving current flowing through the sub-pixels of the same color can achieve a display effect with consistent brightness; avoiding the Gamma adjustment process at different moments and different pixels. A large number of calculations that can make the brightness of the data voltage consistent, reduce the driving capability requirements of the driver chip.
  • the pixel driving circuit in which the sampling transistor and the driving transistor are not short-circuited as diodes in any working stage, it can be a 2T1C or 3T1C structure. Compared with 2T1C, 3T1C adds a light-emitting transistor between the driving transistor and the sub-pixel.
  • the pixel driving circuit has a 4T1C, 4T2C, 5T1C, 6T1C, or 7T1C structure.
  • the pixel driving circuit has a 6T1C or 7T1C structure, and the theoretical shock voltage of the storage capacitor at the end of the charging phase is the difference between the data signal voltage and the threshold voltage of the driving transistor.
  • the display panel includes a transparent display area
  • the pixel driving circuit is a pixel driving circuit of each first OLED sub-pixel in the transparent display area.
  • this solution changes the width-to-length ratio of the drive transistor in the pixel drive circuit of each first OLED sub-pixel, so that: ,
  • the aspect ratio of the driving transistors of the first OLED sub-pixels of the same color is proportional to the driving current; the brightness of the transparent display area can be consistent, while avoiding a large number of calculations in the Gamma adjustment process.
  • this solution changes the driving in the pixel driving circuit of each first OLED sub-pixel.
  • the transistor width-to-length ratio makes: under the same gray scale, the width-to-length ratio of the driving transistors of the first OLED sub-pixels of the same color is proportional to the driving current; the brightness of the transparent display area can be consistent, and the Gamma adjustment process is avoided. A lot of calculations.
  • this solution changes the driving transistor in the pixel driving circuit of each first OLED sub-pixel
  • the aspect ratio and the size of the storage capacitor are such that under the same gray scale, the storage capacitors of the first OLED sub-pixels of the same color have the same charging saturation, the width-to-length ratio of the driving transistors of the first OLED sub-pixels of the same color, and the size of the storage capacitor Both are directly proportional to the driving current, which can achieve the same brightness of the transparent display area, while avoiding a lot of calculations in the Gamma adjustment process.
  • the display panel includes a transparent display area and a non-transparent display area
  • the pixel driving circuit is each first OLED sub-pixel in the transparent display area and each second OLED sub-pixel in the non-transparent display area ⁇ Pixel drive circuit.
  • the ratio of the width-to-length ratio of the driving transistor of each first OLED sub-pixel of the same color to the driving current is equal to the ratio of the second The ratio of the width-to-length ratio of the driving transistors of the OLED sub-pixels of the same color to the driving current;
  • the ratio of the aspect ratio of the driving transistor to the driving current is equal to the ratio of the aspect ratio of the driving transistor of each second OLED sub-pixel of the same color to the driving current;
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, the charging saturation of the storage capacitor of each first OLED sub-pixel of the same color
  • the charging saturation of the storage capacitor of each second OLED same-color sub-pixel is the same, and the ratio of the width-to-length ratio of the driving transistor of each first OLED same-color sub-pixel to the driving current is equal to the width and length of each second OLED same-color sub-pixel.
  • Ratio to the ratio of the driving current the ratio of the size of the storage capacitor of each first OLED same-color sub-pixel to the drive current is equal to the ratio of the size of the storage capacitor of each second OLED same-color sub-pixel to the drive current.
  • the solution realizes that the same data voltage is applied to the sub-pixels of the same color in the transparent display area and the non-transparent display area, and the driving current flowing through the sub-pixels of the same color can achieve a display effect with consistent brightness and improve the uniformity of the entire screen.
  • the former scheme has low requirements on the driving capability of the driving chip, while the latter scheme has a lower driving capability
  • the aspect ratio and capacitance setting are more flexible.
  • the pixel density of the transparent display area is less than the pixel density of the non-transparent display area. Reducing the pixel density of the transparent display area can simplify the film structure of the pixels and the driving circuit, and reduce the diffraction problem under the light transmission function.
  • the display panel includes a transparent display area, a non-transparent display area, and a transition area between the transparent display area and the non-transparent display area, and the pixel driving circuit is the transparent display area. Pixel driving circuit of each first OLED sub-pixel in the area, each second OLED sub-pixel in the non-transparent display area, and each third OLED sub-pixel in the transition area;
  • the ratio of the width-to-length ratio of the driving transistor of each first OLED sub-pixel of the same color to the driving current is equal to each third
  • the ratio of the width-to-length ratio of the driving transistors of the same-color OLED sub-pixels to the driving current is not equal to the ratio of the width-to-length ratio of the driving transistors of the second OLED sub-pixels of the same color to the driving current; or under the same gray scale, each first OLED
  • the ratio of the aspect ratio of the driving transistor of the same color sub-pixel to the driving current is equal to the ratio of the aspect ratio of the driving transistor of each second OLED same-color sub-pixel to the driving current, and is equal to the width of the driving transistor of each third OLED same-color sub-pixel The ratio of length ratio to driving current;
  • the ratio of the aspect ratio of the driving transistor to the driving current is equal to the ratio of the aspect ratio of the driving transistor of each third OLED sub-pixel of the same color to the ratio of the driving current, and is not equal to the aspect ratio of the driving transistor of each second OLED sub-pixel of the same color.
  • the ratio of driving current; or under the same gray scale, the ratio of the aspect ratio of the driving transistor of each first OLED sub-pixel of the same color to the driving current is equal to the ratio of the aspect ratio of the driving transistor of each second OLED sub-pixel of the same color to the driving current , And equal to the ratio of the aspect ratio of the driving transistor of each third OLED sub-pixel of the same color to the ratio of the driving current;
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, the charging saturation of the storage capacitor of each first OLED sub-pixel of the same color
  • the charging saturation of the storage capacitors of the same color sub-pixels of each third OLED is the same, and the charging saturation of the storage capacitors of the same color sub-pixels of each second OLED is different, and the width-to-length ratio of the driving transistors of each first OLED same-color sub-pixel is
  • the ratio of the driving current is equal to the ratio of the aspect ratio of the driving transistor of each third OLED sub-pixel of the same color to the ratio of the driving current, and is not equal to the ratio of the aspect ratio of the driving transistor of each second OLED sub-pixel of the same color to the ratio of the driving current.
  • the ratio of the storage capacitance of an OLED same-color sub-pixel to the driving current is equal to the ratio of the storage capacitance of each third OLED same-color sub-pixel to the driving current, and is not equal to the storage capacitance of each second OLED same-color sub-pixel.
  • Ratio of driving current; or under the same gray scale the charging saturation of the storage capacitor of each first OLED sub-pixel of the same color, the charging saturation of the storage capacitor of each second OLED sub-pixel of the same color, and the storage of each third OLED sub-pixel of the same color
  • the charging saturation of the capacitor is the same.
  • the ratio of the aspect ratio of the driving transistor of each first OLED sub-pixel of the same color to the driving current is equal to the ratio of the aspect ratio of the driving transistor of each second OLED sub-pixel of the same color to the driving current, and is equal to The ratio of the width-to-length ratio of the driving transistors of the third OLED sub-pixels of the same color to the driving current, and the ratio of the size of the storage capacitor of each first OLED sub-pixel of the same color to the driving current is equal to the size of the storage capacitor of each third OLED sub-pixel of the same color
  • the ratio of the driving current is equal to the ratio of the size of the storage capacitor of each second OLED sub-pixel of the same color to the ratio of the driving current.
  • This solution realizes that the same data voltage is applied to the sub-pixels of the same color in the transparent display area and the transition area, and the driving current flowing through the sub-pixels of the same color can achieve a display effect with consistent brightness, and improve the display uniformity of the transparent display area and the transition area.
  • the aspect ratio and capacitance setting of the driving transistors in the transparent display area and the transition zone do not have to consider the aspect ratio and capacitance setting of the driving transistors in the non-transparent display area, so the respective settings are more flexible.
  • the ratio of the aspect ratio of the driving transistor of each first OLED sub-pixel of the same color to the driving current is equal to the ratio of the driving current
  • the ratio of the width-to-length ratio of the driving transistors of the second OLED sub-pixels of the same color to the driving current is equal to the ratio of the width-to-length ratio of the driving transistors of the third OLED sub-pixels of the same color to the driving current;
  • the ratio of the aspect ratio of the driving transistor to the driving current is equal to the ratio of the aspect ratio of the driving transistor of each second OLED sub-pixel of the same color to the driving current, and is equal to the aspect ratio of the driving transistor of each third OLED sub-pixel of the same color and driving Current ratio
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, the storage of the same color sub-pixels of each first OLED under the same gray scale
  • the charging saturation of the capacitor, the charging saturation of the storage capacitor of each second OLED same-color sub-pixel, and the charging saturation of the storage capacitor of each third OLED same-color sub-pixel are the same, and the width and length of the driving transistor of each first OLED same-color sub-pixel
  • the ratio of the ratio to the driving current is equal to the ratio of the aspect ratio of the driving transistor of each second OLED subpixel of the same color to the ratio of the driving current, and is equal to the ratio of the aspect ratio of the driving transistor of each third OLED subpixel of the same color to the ratio of the driving current.
  • the ratio of the storage capacitance of the first OLED same-color sub-pixel to the driving current is equal to the ratio of the storage capacitance of each third OLED same-color sub-pixel to the driving current, and is equal to the storage capacitance of each second OLED same-color sub-pixel and The ratio of driving current.
  • This solution realizes that the same data voltage is applied to the sub-pixels of the same color in the transparent display area, the transition area, and the non-transparent display area.
  • the driving current flowing through the sub-pixels of the same color can achieve the display effect of consistent brightness and improve the uniformity of the entire screen. .
  • each first OLED sub-pixel includes at least: a light-transmitting anode, an OLED light-emitting material layer on the light-transmitting anode, and a light-transmitting cathode on the OLED light-emitting material layer; each When a driving voltage is applied between the light-transmitting anode and the light-transmitting cathode of the first OLED sub-pixel, the first OLED sub-pixel performs a display function; there is no application between the light-transmitting anode and the light-transmitting cathode of each first OLED sub-pixel When driving voltage, the first OLED sub-pixel performs a light transmission function;
  • Each first OLED sub-pixel is driven by PM; the transparent display area has multiple rows of light-transmitting anodes and multiple columns of light-transmitting cathodes, or multiple rows of light-transmitting anodes and multiple rows of light-transmitting cathodes; each row/column of light-transmitting anodes The longer the length of, the greater the width-to-length ratio of the driving transistor in the corresponding pixel driving circuit.
  • the column-distributed transparent anode can omit the pattern between rows and the row-distributed transparent anode can omit the column and column compared with the array-type block-shaped transparent anode.
  • the above two structures both simplify the pattern in the plane direction, and can alleviate the problem of light diffraction in the up and down direction, so the light sensor under the transparent display area has a good imaging effect.
  • each row/column light-transmitting anode the larger the driving current is required; and the longer the light-transmitting anode corresponds to the larger the aspect ratio of the driving transistor in the pixel driving circuit, the greater the driving current provided.
  • each first OLED sub-pixel is driven by PM or AM;
  • the transparent display area has one row and several columns of light-transmitting anodes, or one column and several rows of light-transmitting anodes, and the light-transmitting cathodes are surface electrodes; each row/column The longer the length of the light-transmitting anode, the greater the width-to-length ratio of the driving transistor in the corresponding pixel driving circuit.
  • the transparent display area is in the shape of a drop, rectangular, circular, oval or bangs.
  • the length of the drop-shaped, round, oval, or bangs-shaped part of the row anode is shorter than the length of the remaining part of the row anode. Therefore, the width and length of the driving transistor in the driving circuit corresponding to the shorter anode is shorter; the width and length of the driving transistor in the driving circuit corresponding to the longer anode is longer.
  • the source and drain of each transistor on the path through which the driving current flows are electrically connected to the metal interconnection pattern by a plurality of conductive plugs.
  • the plurality of conductive plugs can reduce the resistance between the source and drain and the metal interconnection pattern, thereby reducing the power consumption of the conductive plug.
  • the width-to-length ratio of each transistor on the path through which the driving current flows is in the range of 1:1-10:1.
  • the larger the aspect ratio is set the more the resistance of the transistor itself can be reduced, and the power consumption of the transistor can also be reduced.
  • FIG. 1 is a top view of a display panel in an embodiment of the present application
  • FIG. 2 is a circuit diagram of another pixel driving circuit of the display panel in an embodiment of the present application.
  • FIG. 3 is a circuit diagram and a corresponding working timing diagram of still another pixel driving circuit of a display panel in an embodiment of the present application;
  • FIG. 4 is a circuit diagram and a corresponding working timing diagram of another pixel driving circuit of the display panel in an embodiment of the present application;
  • Figure 5 is a cross-sectional view along the line AA in Figure 1;
  • Fig. 6 is a distribution diagram of another light-transmitting anode of each first OLED sub-pixel in the display panel
  • FIG. 7 is a top view of the display panel in the second embodiment of the present application.
  • Fig. 8 is an enlarged view of a partial area in Fig. 7;
  • Figure 9 is a cross-sectional view along the line BB in Figure 8.
  • FIG. 10 is a top view of the display panel in the third embodiment of the present application.
  • Figure 11 is an enlarged view of a part of the area in Figure 10;
  • FIG. 12 is a schematic structural diagram of the metal interconnection structure of the third transistor and the first electrode in an embodiment of the present application.
  • the display panel 1 includes an array type pixel unit 11.
  • Each pixel unit 11 includes a number of sub-pixels 11a, 11b, and 11c.
  • the pixel driving circuit of each sub-pixel (11a, 11b, 11c) includes a sampling transistor X1, a driving transistor X2, and a storage capacitor C.
  • the sampling transistor X1 is used to collect the data signal voltage Vdata and keep the collected data signal voltage Vdata in the storage capacitor C.
  • the driving transistor X2 is used to receive the current supplied by the power line, and supply the driving current Ids to the sub-pixels 11a, 11b, and 11c according to the data signal voltage Vdata held by the storage capacitor C.
  • the width-to-length ratio W/L of the driving transistor X2 of each sub-pixel 11a/11b/11c of the same color is proportional to the driving current Ids.
  • the pixel driving circuit has a 2T1C structure, and the sampling transistor X1 and the driving transistor X2 are not short-circuited as diodes in any working phase.
  • the voltage of the data signal collected by the sampling transistor X1 is Vdata.
  • W is the channel width of the drive transistor
  • L is the channel length of the drive transistor
  • Cox is the capacitance constant, that is, the channel capacitance per unit area of the drive transistor
  • ⁇ is the carrier mobility, that is, the carrier in the semiconductor The average drift rate under a unit electric field
  • VDD is the power supply voltage
  • Vsg is the source gate voltage
  • is the threshold voltage of the driving transistor X2, which is a negative value.
  • the aspect ratio W/L of the driving transistor X2 of the sub-pixels 11a/11b/11c of the same color is proportional to the driving current Ids, that is, VDD-Vdata-
  • FIG. 2 is a circuit diagram of another pixel driving circuit of the display panel in an embodiment of the present application. It can be seen that the pixel driving circuit in FIG. 2 has a 3T1C structure. 2 and 1, the 3T1C structure adds a light-emitting transistor X3 to the 2T1C structure, wherein the light-emitting transistor X3 is located between the driving transistor X2 and the sub-pixels 11a/11b/11c. The light emitting transistor X3 is controlled by the light emitting signal line EM.
  • the aspect ratio W/L of the driving transistor X2 of the sub-pixels 11a/11b/11c of the same color is proportional to the driving current Ids.
  • FIG. 3 is a circuit diagram and a corresponding working timing diagram of still another pixel driving circuit of the display panel in an embodiment of the present application.
  • the pixel driving circuit includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a storage capacitor C;
  • the gate of the first transistor M1 is connected to the scan signal line Sn of the pixel row where the OLED sub-pixel D is located and the gate of the second transistor M2, and the first electrode of the first transistor M1 is connected to the first electrode of the sixth transistor M6.
  • the second electrode of the seventh transistor M7 is connected, and the second electrode of the first transistor M1 is connected to the gate of the seventh transistor M7 and the second electrode of the storage capacitor C;
  • the first electrode of the second transistor M2 is connected to the data signal line VData, and the second electrode of the second transistor M2 is connected to the first electrode of the seventh transistor M7 and the first electrode of the third transistor M3;
  • the gate of the third transistor M3 is connected to the gate of the sixth transistor M6, the first electrode of the third transistor M3 is connected to the first electrode of the seventh transistor M7, and the second electrode of the third transistor M3 is connected to the first electrode of the storage capacitor C.
  • One-pole connection is
  • the gate of the fourth transistor M4 is connected to the scan signal line Sn-1 of the previous pixel row, the first electrode of the fourth transistor M4 is connected to the anode of the OLED sub-pixel D, and the second electrode of the fourth transistor M4 is connected to the initial voltage signal
  • the Vinit line is connected to the second electrode of the fifth transistor M5;
  • the gate of the fifth transistor M5 is connected to the scan signal line Sn-1 of the previous pixel row, the first electrode of the fifth transistor M5 is connected to the gate of the seventh transistor M7 and the second electrode of the storage capacitor C, the fifth transistor The second pole of M5 is connected to the initial voltage signal Vinit line;
  • the gate of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the second electrode of the seventh transistor M7, and the second electrode of the sixth transistor M6 is connected to the first electrode of the fourth transistor M4. connection;
  • the first pole of the storage capacitor C is connected to the power signal line VDD.
  • the working sequence of the pixel driving circuit of the 7T1C structure includes: an initialization phase, a charging phase, and a reading and writing light emitting phase.
  • the scan signal line Sn-1 of the upper row of the OLED sub-pixel D provides a low voltage signal
  • the fourth transistor M4 and the fifth transistor M5 are turned on, and the reference voltage is charged into the anode of the OLED sub-pixel D and the storage capacitor C, providing a negative voltage for the anode of the OLED sub-pixel D, clearing the internal pre-stored voltage, and completing initialization.
  • the scan signal line Sn-1 and the light-emitting signal line EM of the upper row of the OLED sub-pixel D provide high-voltage signals
  • the scan signal line Sn and the data signal line VData of the row where the OLED sub-pixel D is located provide low-voltage signals.
  • the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are turned on, and the difference between the voltage of the data signal line VData and the threshold voltage of the seventh transistor M7 is charged into the storage capacitor In C, the charging process of the storage capacitor C is completed.
  • the scan signal line Sn-1 of the upper row of the OLED sub-pixel D, the scan signal line Sn-1 of the upper row of the OLED sub-pixel D, and the data signal line VData provide high-voltage signals, and the light-emitting signal line EM provides low-voltage signals. Voltage signal.
  • the third transistor M3, the sixth transistor M6, and the seventh transistor M7 are turned on, and the power signal line VDD is directed to the OLED through the third transistor M3, the sixth transistor M6, and the seventh transistor M7.
  • the anode of the sub-pixel D provides a driving voltage to make it emit light normally.
  • the 7T1C pixel circuit has a threshold voltage compensation process of the OLED sub-pixel D during the light-emitting process, so the uniformity of the OLED sub-pixel D's light emission can be guaranteed.
  • the sampling transistor and the driving transistor are the same transistor, and both are the seventh transistor M7.
  • the voltage of the data signal line VData collected by the sampling transistor M7 is Vdata-
  • the drain and gate of the seventh transistor M7 are short-circuited during the charging phase, and the transistor M7 turns into a diode.
  • the charging saturation ⁇ U of the storage capacitor C of the sub-pixels 11a/11b/11c of the same color is the same, and the width-to-length ratio W/L of the driving transistor M7 of the sub-pixels 11a/11b/11c of the same color and the storage capacitor C
  • the size is proportional to the driving current Ids; among them, the charging saturation ⁇ U is the difference between the actual charged voltage and the theoretical shock voltage of the storage capacitor C at the end of the charging phase.
  • ⁇ U Vdata-
  • Vgate is the actual charged voltage of the storage capacitor at the end of the charging phase, Vdata-
  • Cox is the capacitance constant, That is the channel capacitance per unit area of the drive transistor
  • ⁇ is the carrier mobility, that is, the average drift rate of carriers in the semiconductor under a unit electric field
  • VDD is the power supply voltage
  • ⁇ U is the charging saturation of the storage capacitor C
  • W is The channel width of the drive transistor
  • L is the channel length of the drive transistor.
  • the aspect ratio W/L of the driving transistor M7 of each sub-pixel 11a/11b/11c of the same color is proportional to the driving current Ids, that is, VDD-Vdata+ ⁇ U is a fixed value. Due to the same power supply voltage VDD, to make the data voltage Vdata of the same color sub-pixels 11a/11b/11c the same, that is, to achieve the same gray-scale brightness under the same data voltage Vdata, you can control the same color sub-pixels 11a/11b/11c.
  • the charging saturation ⁇ U of the storage capacitor C is the same.
  • the charging saturation ⁇ U of the storage capacitor C is the same, which can be controlled by the storage of the sub-pixels 11a/11b/11c of the same color.
  • the voltage ⁇ V charged by the capacitor C during the charging phase is the same.
  • Q is the charge amount of the storage capacitor C during the charging phase
  • t 0 is the duration of the charging phase
  • Cst is the size of the storage capacitor C.
  • FIG. 4 is a circuit diagram and a corresponding working timing diagram of another pixel driving circuit of the display panel in an embodiment of the present application.
  • the pixel driving circuit includes: a zero-first transistor M01, a zero-second transistor M02, a zero-third transistor M03, a zero-fourth transistor M04, a zero-fifth transistor M05, and a storage capacitor C;
  • the zero-first transistor M01 is connected between the first node N1 and the second node N2, and its gate is connected to the scanning signal line Sn;
  • the zero-second transistor M02 is connected between the power supply voltage VDD and the sub-pixel D, and its gate The pole is connected to the first node N1;
  • the storage capacitor C is connected between the power supply voltage VDD and the first node N1;
  • the zeroth and third transistor M03 is connected between the data signal line and the drain of the zeroth and fourth transistor M04, and its gate is connected to the second control line Sa2; the zeroth and fourth transistor M04 is connected between the second node N2 and the zeroth and third transistor M03 Between the drains of, its gate is connected to the second node N2; the fifty-fifth transistor M05 is connected between the reference voltage Vref and the second node N2, and its gate is connected to the first control line Sa1.
  • the working sequence of the pixel drive circuit of the 5T1C structure includes an initialization phase, a charging phase, and a reading and writing light emitting phase.
  • the scan signal provided by the scan signal line Sn is low level
  • the control signal provided by the first control line Sa1 changes from high level to low level
  • the control signal provided by the second control line Sa2 is high level
  • the data The data signal Vdata provided by the line remains high. Since the scan signal provided by the scan signal line Sn is at a low level, the zero-first transistor M01 controlled by the scan signal line Sn is in a conductive state, and at the same time, the control signal provided by the first control line Sa1 changes from a high level to a low level.
  • the fifth transistor M05 controlled by the first control line Sa1 turns off to on, so the initialization voltage Vref is provided to the first node N1 through the fifth transistor M05 and the zero first transistor M01, thereby using the reference voltage Vref
  • the storage capacitor C is initialized. After initialization, the voltage of the first node N1 is Vref, that is, the lower substrate voltage of the storage capacitor C becomes Vref.
  • the scan signal provided by the scan signal line Sn remains low
  • the control signal provided by the second control line Sa2 changes from high to low
  • the control signal provided by the first control line Sa1 remains high
  • the data The data signal Vdata provided by the line remains low. Since the control signal provided by the first control line Sa1 remains at a high level, the fifth transistor M05 is turned off, and the initialization voltage Vref cannot be provided to the first node N1 via the fifth transistor M05 and the zero-first transistor M01.
  • the zero-first transistor M01 controlled by the scan signal line Sn is still in a conductive state, and the control signal provided by the second control line Sa2 changes from a high level.
  • the zeroth and third transistor M03 controlled by the second control line Sa2 turns off to on, and the data signal Vdata provided by the data line starts to be written into the sub-pixel D via the zeroth and third transistor M03.
  • the zero-one transistor M01, the zero-third transistor M03, and the zero-fourth transistor M04 are all turned on, and the data signal Vdata provided by the data line is provided to the first through the zero-third transistor M03, the zero-fourth transistor M04, and the zero-first transistor M01 in turn.
  • the voltage of the first node N1 starts to rise from Vref.
  • the fourth transistor M04 changes from on to off.
  • Vth is the threshold voltage of the fourth transistor M04.
  • the voltage of the first node N1 that is, the lower substrate voltage of the storage capacitor C, is equal to Vdata-
  • Read and write light-emitting stage the scan signal provided by the scan signal line Sn changes from low level to high level, the control signals provided by the first control line Sa1 and the second control line Sa2 maintain high level, and the data signal provided by the data line Vdata remains high. Since the scan signal provided by the scan signal line Sn changes from low level to high level, the zero-first transistor M01 controlled by the scan signal line Sn changes from on to off, due to the first control line Sa1 and the second control line Sa2 The provided control signals all maintain a high level, and the fifth transistor M05 controlled by the first control line Sa1 and the third transistor M03 controlled by the second control line Sa2 are both in an off state. At this time, the voltage of the first node N1 remains Vdata-
  • the second transistor M02 since the second transistor M02 is turned on, the second transistor M02 outputs the driving current Ids to the sub-pixel D.
  • the fourth transistor M04 is a sampling transistor
  • the second transistor M02 is a driving transistor.
  • the voltage of the data signal line VData collected by the sampling transistor M04 is Vdata-
  • the source and gate of the fourth transistor M04 are short-circuited, and the transistor becomes a diode.
  • W is the channel width of the drive transistor
  • L is the channel length of the drive transistor
  • Cox is the capacitance constant, that is, the channel capacitance per unit area of the drive transistor
  • ⁇ is the carrier mobility, that is, the carrier in the semiconductor The average drift rate under a unit electric field
  • VDD is the power supply voltage
  • Vsg is the source gate voltage
  • is the threshold voltage of the driving transistor M02, which is a negative value.
  • the aspect ratio W/L of the driving transistor M02 of the sub-pixels 11a/11b/11c of the same color is proportional to the driving current Ids, that is, VDD-Vdata is a fixed value. Since the power supply voltage VDD of the sub-pixels 11a/11b/11c of the same color is the same, the data voltage Vdata of the sub-pixels 11a/11b/11c of the same color is also the same. In other words, for each sub-pixel 11a/11b/11c of the same color, under the same data voltage Vdata, the same gray-scale brightness can be achieved, and the brightness display can be uniform.
  • the pixel drive circuit can also adopt a 4T1C, 4T2C, 5T1C, or 6T1C structure.
  • this solution changes the pixel driving circuit of each first OLED sub-pixel.
  • the width-to-length ratio of the driving transistor is such that under the same gray scale, the width-to-length ratio W/L of the driving transistors of the first OLED sub-pixels of the same color is proportional to the driving current Ids.
  • the sampling transistor and/or the driving transistor when the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, they can also be in the same gray scale, and the same color sub-pixels 11a/11b/11c
  • the charging saturation ⁇ U of the storage capacitor C is the same, first determine according to the corresponding formula of the data voltage Vdata of the driving transistor and the driving current Ids: the aspect ratio W/L of the driving transistor of each sub-pixel 11a/11b/11c of the same color and the driving The current Ids is proportional; then according to the relationship between the charging saturation ⁇ U of the sub-pixels 11a/11b/11c of the same color and the voltage ⁇ V charged by the storage capacitor C during the charging phase, by controlling all the sub-pixels 11a/11b/11c of the same color
  • the charging voltage ⁇ V is consistent to achieve the same charging saturation ⁇ U; then according to the same color sub-pixels 11a/11b/11c when
  • Fig. 5 is a cross-sectional view taken along line AA in Fig. 1. 1 and 5, the display panel 1 includes a transparent display area.
  • the transparent display area includes an array of first OLED pixel units 11.
  • Each first OLED pixel unit 11 includes a plurality of first OLED sub-pixels 11a, 11b, 11c, and each first OLED sub-pixel 11a, 11b, 11c includes at least: a light-transmitting anode 111a, and an OLED located on the light-transmitting anode 111a emits light
  • the OLED pixel unit 11 performs a display function; when no driving voltage is applied between the light-trans
  • each light-transmitting anode 111a may be provided with a pixel defining layer 111d, the pixel defining layer 111d has an opening, and the OLED light-emitting material layer 111b is located in the opening.
  • the substrate 10 of the display panel 1 may be a flexible substrate, such as polyimide, or a rigid substrate, such as glass.
  • the transparent anodes 111a in the first OLED pixel units 11 arranged in an array are arranged in one row and several columns.
  • the light-transmitting anodes 111a may also be distributed in one column, several rows, or distributed in rows or columns.
  • the column-distributed light-transmitting anode 111a is relative to the determinant-distributed block light-transmitting anode. Because the pattern between rows is omitted, the pattern in the plane direction is simplified, and the problem of light diffraction in the up and down directions can be alleviated, so it is transparent
  • the light sensor under the display area 10a has a good imaging effect.
  • the row-distributed light-transmitting anode 111a is opposite to the determinant-distributed block light-transmitting anode, and the pattern between the columns is omitted.
  • each of the first OLED sub-pixels 11a, 11b, and 11c is driven by PM or AM.
  • FIG. 6 is a distribution diagram of another light-transmitting anode of each first OLED sub-pixel in the display panel.
  • the transparent display area may be shown in FIG. 1, with one row and several columns of light-transmitting anodes 111a, and the light-transmitting cathode 111c is a surface electrode; or as shown in FIG.
  • the cathode 111c is a surface electrode.
  • Active matrix OLED Active Matrix OLED
  • AMOLED also known as active drive
  • TFT thin film transistor
  • each thin film transistor unit includes a storage capacitor.
  • AMOLED uses independent thin film electrical transistors to control the light emission of each pixel, and each pixel can emit light continuously. In other words, the addressing of each OLED sub-pixel is directly controlled by the thin film transistor array.
  • the row selection signal of the thin film transistor array can be derived from the GIP circuit, and the column selection signal can be derived from the display driver integrated chip (DDIC).
  • DDIC display driver integrated chip
  • Passive-driven OLED Passive Matrix OLED, PMOLED
  • Passive Matrix OLED PMOLED
  • PMOLED Passive Matrix OLED
  • passive-driven simply forms a matrix with cathodes and anodes, and illuminates the pixels at the intersection of rows and columns in the array by scanning, and each pixel is operated at In short pulse mode, it emits high brightness instantaneously.
  • the addressing of each OLED sub-pixel is directly controlled by an external circuit.
  • the display panel shown in FIG. 6 may correspond to a transparent display area in the shape of a drop or a bang.
  • the length of the light-transmitting anode 111a of the first OLED sub-pixel 11a/11b/11c of each row gradually becomes shorter.
  • a pixel driving circuit where the sampling transistor and the driving transistor are not short-circuited as diodes at any working stage, such as the 2T1C structure shown in Figure 1 or the 3T1C structure shown in Figure 2, set a certain row first, such as the first row and the first OLED sub-pixel
  • the width-to-length ratio W/L of the driving transistor X2 of the first OLED sub-pixel 11a/11b/11c in each row is proportional to the driving current Ids under the same gray scale; therefore, it can be in a gray scale, such as 255 gray scale, according to each row
  • the driving current Ids of the first OLED sub-pixel 11a/11b/11c determines the aspect ratio W/L of the driving transistor X2 of each row of the first OLED sub-pixel 11a/11b/11c.
  • sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, such as the 7T1C structure shown in FIG. 3, set a certain row first, such as the first row and the first row.
  • the width-to-length ratio W/L of the driving transistor M7 of the first OLED sub-pixels 11a/11b/11c in each row is proportional to the driving current Ids under the same gray scale; therefore, it can be in a gray scale, such as 255 gray scale, according to each row
  • the driving current Ids of the first OLED sub-pixel 11a/11b/11c determines the aspect ratio W/L of the driving transistor M7 of each row of the first OLED sub-pixel 11a/11b/11c;
  • First set a certain row for example, the size Cst of the storage capacitor C of the transparent anode 111a of the first OLED sub-pixel 11a/11b/11c in the first row;
  • the size Cst of the storage capacitor C of the first OLED sub-pixel 11a/11b/11c of each row is proportional to the driving current Ids; therefore, it can be a gray scale, for example, 255 gray scale, according to the first OLED sub-pixel in each row
  • the driving current Ids of the pixels 11a/11b/11c determines the size Cst of the storage capacitor C of the first OLED sub-pixel 11a/11b/11c in each row.
  • sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are not the same transistor, such as the 5T1C structure shown in Figure 4, first set a certain row, such as the first row The width-to-length ratio W/L of the driving transistor M02 of the light-transmitting anode 111a of the first OLED sub-pixel 11a/11b/11c;
  • the width-to-length ratio W/L of the driving transistor M02 of the first OLED sub-pixel 11a/11b/11c in each row is proportional to the driving current Ids under the same gray scale; therefore, it can be in a gray scale, such as 255 gray scale, according to each row
  • the driving current Ids of the first OLED sub-pixel 11a/11b/11c determines the aspect ratio W/L of the driving transistor M02 of each row of the first OLED sub-pixel 11a/11b/11c.
  • the length of the transparent anode 111a of the first OLED sub-pixel 11a/11b/11c in each row becomes shorter from top to bottom. It can be understood that, in order to achieve the same gray scale brightness, the driving current Ids required for the transparent anode 111a in each row from top to bottom gradually decreases, so the aspect ratio W/L of the driving transistor X2 in the corresponding pixel driving circuit gradually changes small.
  • the longer the length the larger the width-to-length ratio W/L of the driving transistor X2 in the pixel driving circuit.
  • each of the first OLED sub-pixels 11a, 11b, and 11c is driven by PM.
  • the transparent display area has multiple rows of light-transmitting anodes 111a and multiple columns of light-transmitting cathodes 111c, or multiple rows of light-transmitting anodes 111a and multiple rows of light-transmitting cathodes 111c.
  • the longer the length of each row/column light-transmitting anode 111a the larger the width-to-length ratio W/L of the driving transistor X2 in the corresponding pixel driving circuit.
  • FIG. 7 is a top view of the display panel in the second embodiment of the present application.
  • Fig. 8 is an enlarged view of a partial area in Fig. 7.
  • the display panel 2 includes a transparent display area 10a and a non-transparent display area 10b.
  • Each of the first OLED sub-pixels 11a, 11b, and 11c in the transparent display area 10a is the same as the previous embodiment.
  • Fig. 9 is a cross-sectional view taken along line BB in Fig. 8. 8 and 9, the non-transparent display area 10b includes an array of second OLED pixel units 12, each second OLED pixel unit 12 includes a plurality of second OLED sub-pixels 12a, 12b, 12c, each second OLED
  • the sub-pixels 12a, 12b, and 12c at least sequentially include, from bottom to top, a reflective anode 121a formed on the substrate 10, a pixel defining layer 121d having an opening, an OLED light-emitting material layer 121b located in the opening, and an OLED light-emitting material layer 121b On the transparent cathode 121c.
  • the sampling transistor and the driving transistor are not short-circuited as diodes at any working stage, for example, in the 2T1C structure shown in FIG. 1 or the 3T1C structure shown in FIG. 2, under the same gray scale, the first OLED sub-pixels of the same color
  • the ratio of the aspect ratio W/L of the driving transistor X2 of 11a/11b/11c to the driving current Ids is equal to the aspect ratio W/L of the driving transistor X2 of each second OLED sub-pixel 12a/12b/12c and the driving current Ids. Ratio.
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, for example, in the 7T1C structure shown in FIG. 3, the first OLED sub-pixels 11a/11b/11c of the same color
  • the charging saturation ⁇ U of the storage capacitor is the same as the charging saturation ⁇ U of the storage capacitor of each second OLED same-color sub-pixel 12a/12b/12c, and the width-to-length ratio W of the driving transistor of each first OLED same-color sub-pixel 11a/11b/11c
  • the ratio of /L to the driving current Ids is equal to the ratio of the width-to-length ratio W/L of the driving transistor of each second OLED same-color sub-pixel 12a/12b/12c to the driving current Ids, and each first OLED same-color sub-pixel 11a/11b/11c
  • the ratio of the size Cst of the storage capacitor C to the driving current Ids is equal to the ratio of the size
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are not the same transistor, for example, in the 5T1C structure shown in FIG. 4, under the same gray scale, the first OLED sub-pixels of the same color
  • the ratio of the aspect ratio W/L of the driving transistor of 11a/11b/11c to the driving current Ids is equal to the ratio of the aspect ratio W/L of the driving transistor of each second OLED same-color sub-pixel 12a/12b/12c to the driving current Ids .
  • This solution realizes that the same data voltage Vdata is applied to the sub-pixels of the same color in the transparent display area 10a and the non-transparent display area 10b, and the driving current Ids flowing through the sub-pixels of the same color can achieve the display effect of consistent brightness and improve the uniformity of the entire screen display. .
  • the former scheme has low requirements on the driving capability of the driving chip, and the latter scheme
  • the width-length ratio of the driving transistor X2 is more flexible than W/L and the capacitance size Cst of the storage capacitor C.
  • the pixel density of the transparent display area 10a is less than the pixel density of the non-transparent display area 10b. Reducing the pixel density of the transparent display area 10a can simplify the film structure of the pixels and the driving circuit, and reduce the diffraction problem under the light transmission function.
  • FIG. 10 is a top view of the display panel in the third embodiment of the present application.
  • Fig. 11 is an enlarged view of a partial area in Fig. 10.
  • the display panel 3 includes a transparent display area 10a, a non-transparent display area 10b, and a transition area 10c between the transparent display area 10a and the non-transparent display area 10b.
  • Each of the first OLED sub-pixels 11a, 11b, 11c in the transparent display area 10a, and each of the second OLED sub-pixels 12a, 12b, 12c in the non-transparent display area 10b is the same as the previous embodiment.
  • Each third OLED sub-pixel in the transition area 10c is the same as the second OLED sub-pixel 12a, 12b, 12c in the foregoing embodiment.
  • the sampling transistor and the driving transistor are not short-circuited as diodes at any working stage, for example, in the 2T1C structure shown in FIG. 1 or the 3T1C structure shown in FIG. 2, under the same gray scale, the first OLED sub-pixels 11a/11b/11c of the same color
  • the ratio of the width-to-length ratio of the driving transistor W/L to the driving current Ids is equal to the ratio of the width-to-length ratio W/L of the driving transistors of the third OLED sub-pixels of the same color to the driving current Ids, and is not equal to the ratio of the second OLEDs of the same color.
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, for example, in the 7T1C structure shown in FIG. 3, under the same gray scale, the first OLED sub-pixels 11a of the same color
  • the charging saturation ⁇ U of the storage capacitor of /11b/11c is the same as the charging saturation ⁇ U of the storage capacitor of each third OLED sub-pixel of the same color, and is different from the charging saturation ⁇ U of the storage capacitor of each second OLED sub-pixel of the same color.
  • the ratio of the width-to-length ratio W/L of the driving transistors of the first OLED same-color sub-pixels 11a/11b/11c to the driving current Ids is equal to the ratio of the width-to-length ratio W/L of the driving transistors of the third OLED same-color sub-pixels and the driving current Ids.
  • the ratio is not equal to the ratio of the width-to-length ratio W/L of the driving transistors of the second OLED sub-pixels of the same color to the driving current Ids, and the size of the storage capacitor Cst and the driving current of each first OLED same-color sub-pixel 11a/11b/11c
  • the ratio of Ids is equal to the ratio of the storage capacitor size Cst of each third OLED sub-pixel of the same color to the driving current Ids, and is not equal to the ratio of the storage capacitor size Cst of each second OLED sub-pixel of the same color to the driving current Ids.
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are not the same transistor, for example, in the 5T1C structure shown in FIG. 4, under the same gray scale, the first OLED sub-pixels of the same color
  • the ratio of the aspect ratio W/L of the driving transistor of 11a/11b/11c to the driving current Ids is equal to the ratio of the aspect ratio W/L of the driving transistor of each third OLED sub-pixel of the same color to the driving current Ids, and is not equal to each The ratio of the width-to-length ratio W/L of the driving transistors of the second OLED same-color sub-pixels 12a/12b/12c to the driving current Ids.
  • the sampling transistor and the driving transistor are not short-circuited as diodes at any working stage, for example, in the 2T1C structure shown in Figure 1 or the 3T1C structure shown in Figure 2, under the same gray scale, the first OLEDs have the same color
  • the aspect ratio W/L of the driving transistor of the sub-pixel 11a/11b/11c and the driving current Ids are equal to the ratio of the aspect ratio W/L of the driving transistor of each second OLED same-color sub-pixel 12a/12b/12c to the driving current Ids , And equal to the ratio of the width-to-length ratio W/L of the driving transistor of each third OLED sub-pixel of the same color to the driving current Ids.
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are the same transistor, for example, in the 7T1C structure shown in FIG. 3, under the same gray scale, the first OLED sub-pixels 11a of the same color
  • the charging saturation ⁇ U of the storage capacitor of /11b/11c, the charging saturation ⁇ U of the storage capacitor of each second OLED same-color sub-pixel 12a/12b/12c, and the charging saturation ⁇ U of the storage capacitor of each third OLED same-color sub-pixel are the same ,
  • the ratio of the aspect ratio W/L of the driving transistor of each first OLED same-color sub-pixel 11a/11b/11c to the driving current Ids is equal to the aspect ratio W of the driving transistor of each second OLED same-color sub-pixel 12a/12b/12c
  • the sampling transistor and/or the driving transistor are short-circuited as a diode during a working phase, and the sampling transistor and the driving transistor are not the same transistor, for example, in the 5T1C structure shown in FIG. 4, under the same gray scale, the first OLED sub-pixels of the same color
  • the ratio of the aspect ratio W/L of the driving transistor of 11a/11b/11c to the driving current Ids is equal to the ratio of the aspect ratio W/L of the driving transistor of each second OLED same-color sub-pixel 12a/12b/12c to the driving current Ids , And equal to the ratio of the width-to-length ratio W/L of the driving transistor of each third OLED sub-pixel of the same color to the driving current Ids.
  • the pixel density of the transparent display area 10a may be less than the pixel density of the non-transparent display area 10b; the pixel density of the transition area 10c may be between the pixel density of the transparent display area 10a and the pixel density of the non-transparent display area 10b, To further improve the display effect.
  • FIG. 12 is a schematic structural diagram of the metal interconnection structure of the third transistor and the first electrode in an embodiment of the present application.
  • each transistor is electrically connected through a metal interconnection structure 4, and the metal interconnection structure 4 includes: a metal interconnection pattern 41 and a conductive plug 42.
  • the driving current flows through the first electrode of the third transistor M3 and the metal interconnection pattern 41 (see FIG. 12). And/or between the first electrode of the seventh transistor M7 and the metal interconnection pattern 41, and/or the second electrode of the seventh transistor M7 and the metal interconnection pattern 41, and/or between the sixth transistor M6 There may be a plurality of conductive plugs 42 between the first pole and the metal interconnection pattern 41. Multiple refers to two or more.
  • the plurality of conductive plugs 42 can reduce the resistance between the source and drain electrodes and the metal interconnection pattern 41, thereby reducing the power consumption of the conductive plug 42.
  • it may also be a conventional pixel driving circuit such as 2T1C, 3T1C, 4T1C, 4T2C, 5T1C, 6T1C, etc.
  • the driving current flows through the path, that is, there may be multiple conductive plugs between the source and drain of each transistor between the power supply voltage VDD and the ground voltage VSS and the metal interconnection pattern. To reduce the resistance between the source and drain and the metal interconnection pattern, thereby reducing the power consumption of the conductive plug.
  • the driving current flows through the third transistor M3, and/or the sixth transistor M6, and/or the seventh transistor M7 in the range of the aspect ratio: 1:1 ⁇ 10:1.
  • the larger the aspect ratio is set the more the resistance of the transistor itself can be reduced, and the power consumption of the transistor can also be reduced.
  • the driving current flows through the path, that is, the range of the transistor width-to-length ratio between the power supply voltage VDD and the ground voltage VSS can be 1:1-10:1 to reduce the The resistance of the transistor itself can also reduce the power consumption of the transistor.
  • the present application also provides a display panel including the above pixel driving circuit.
  • the above-mentioned pixel driving circuit can also be incorporated into the display panel in the embodiments of FIGS. 1 to 11, and the OLED sub-pixel D may be the first OLED sub-pixel 11a, 11b, 11c.
  • the present application also provides a display device.
  • the display device can be a display device such as a mobile phone, a tablet computer, a car display, etc.
  • the display device includes:
  • the device body has a device area
  • the device area is located under the transparent display area 10a of the display panel, and a photosensitive device that emits or collects light through the transparent display area 10a is arranged in the device area.
  • the photosensitive device includes a camera and/or a light sensor.
  • the light sensor includes one or a combination of an iris recognition sensor and a fingerprint recognition sensor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示装置及其显示面板（1）、显示面板（1）的像素驱动电路，通过改变每一子像素的像素驱动电路中的驱动晶体管（X2）宽长比、或同时改变存储电容（C）大小，使得：同一灰阶下，各同色子像素（11a、11b、11c）的驱动晶体管（X2）的宽长比与驱动电流成正比；或同时各同色子像素（11a、11b、11c）的存储电容（C）的充电饱和度相同，各同色子像素（11a、11b、11c）的存储电容（C）的大小与驱动电流成正比，充电饱和度为存储电容（C）在充电阶段结束时的实际所充电压与理论应冲电压的差值。通过产品结构设置，实现对各个同色子像素（11a、11b、11c）施加同一数据电压，各同色子像素（11a、11b、11c）流经的驱动电流可达到亮度一致的显示效果；避免Gamma调节中，不同时刻、不同像素为获得能使亮度一致的数据电压而进行大量运算，降低对驱动芯片的驱动能力要求。

Description

显示装置及其显示面板、显示面板的像素驱动电路
相关申请的交叉引用
本申请要求2019年03月29日申请的，申请号为201910250976.7，名称为“显示装置及其显示面板、显示面板的像素驱动电路”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示设备技术领域，尤其涉及一种显示装置及其显示面板、显示面板的像素驱动电路。
背景技术
随着显示装置的快速发展，用户对显示屏幕占比的要求越来越高。由于移动终端的显示屏幕上方通常需要安装摄像头、传感器、听筒等元件，因此先前技术中采用异形屏(notch)设计方案，显示屏幕上部通常会预留一部分区域用于安装上述元件，影响了显示屏幕的整体一致性，从而使全面屏显示受到业界越来越多的关注。
发明内容
本申请的目的是提供一种用于全面屏的显示装置及其显示面板、显示面板的像素驱动电路。
本发明的有益效果在于：
1)对于采样晶体管与驱动晶体管在任一工作阶段都未短接为二极管的像素驱动电路，通过改变每一子像素的像素驱动电路中的驱动晶体管宽长比，使得：同一灰阶下，各同色子像素的驱动晶体管的宽长比与驱动电流成正比；
对于采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管不为同一晶体管的像素驱动电路，通过改变每一子像素的像素驱动电路中的驱动晶体管宽长比，使得：同一灰阶下，各同色子像素的驱动晶体管的宽长比与驱动电流成正比；
对于采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管为同一晶体管的像素驱动电路，通过改变每一子像素的像素驱动电路中的驱动晶体管宽长比以及存储电容大小，使得：同一灰阶下，各同色子像素的存储电容的充电饱和度相同，各同色子像素的驱动晶体管的宽长比、存储电容的大小都与驱动电流成正比，其中，所述充电饱和度为所述存储电容在充电阶段结束时的实际所充电压与理论应冲电压的差值。
好处在于：通过产品结构设置，可实现对各个同色子像素施加同一数据电压，各同色子像素流经的驱动电流可达到亮度一致的显示效果；避免Gamma调节过程中，不同时刻、不同像素为获得能使亮度一致的数据电压而进行的大量运算，降低对驱动芯片的驱动能力要求。
2)可选方案中，对于采样晶体管与驱动晶体管在任一工作阶段都未短接为二极管的像素驱动电路，可以为2T1C或3T1C结构。其中3T1C相对于2T1C，在驱动晶体管与子像素之间增加一发光晶体管。
3)可选方案中，对于采样晶体管与驱动晶体管在一工作阶段短接为二极管的像素驱动电路，所述像素驱动电路为4T1C、4T2C、5T1C、6T1C、或7T1C结构。
优选地，所述像素驱动电路为6T1C或7T1C结构，所述存储电容在充电阶段结束时的理论应冲电压为所述数据信号电压与所述驱动晶体管的阈值电压的差值。
4)可选方案中，所述显示面板包括透明显示区，所述像素驱动电路为所述透明显示区中各第一OLED子像素的像素驱动电路。
对于采样晶体管与驱动晶体管在任一工作阶段都未短接为二极管的像素驱动电路，本方案通过改变每一第一OLED子像素的像素驱动电路中的驱动晶体管宽长比，使得：同一灰阶下，各同色第一OLED子像素的驱动晶体管的宽长比与驱动电流成正比；可达到透明显示区的亮度一致，同时又避免了Gamma调节过程中的大量运算。
对于采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管不为同一晶体管的像素驱动电路，本方案通过改变每一第一OLED子像素的像素驱动电路中的驱动晶体管宽长比，使得：同一灰阶下，各同色第一OLED子像素的驱动晶体管的宽长比与驱动电流成正比；可达到透明显示区的亮度一致，同时又避免了Gamma调节过程中的大量运算。
对于采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管为同一晶体管的像素驱动电路，本方案通过改变每一第一OLED子像素的像素驱动电路中的驱动晶体管宽长比以及存储电容大小，使得：同一灰阶下，各同色第一OLED子像素的存储电容的充电饱和度相同，各同色第一OLED子像素的驱动晶体管的宽长比、存储电容的大小都与驱动电流成正比，可达到透明显示区的亮度一致，同时又避免了Gamma调节过程中的大量运算。
5)可选方案中，所述显示面板包括透明显示区与非透明显示区，所述像素驱动电路为所述透明显示区中各第一OLED子像素与非透明显示区各第二OLED子像素的像素驱动电路。
当所述采样晶体管与所述驱动晶体管在任一工作阶段都未短接为二极管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管不为同一晶体管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管为同一晶体管时，各第一OLED同色子像素的存储电容的充电饱和度与各第二OLED同色子像素的存储电容的充电饱和度相同，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，各第一OLED同色子像素的存储电容的大小与驱动电流之比等于各第二OLED同色子像素的存储电容的大小与驱动电流之比。
本方案实现了对透明显示区与非透明显示区的各个同色子像素施加同一数据电压，各同色子像素流经的驱动电流可达到亮度一致的显示效果，提高整屏显示均一性。相对于透明显示区的各个同色子像素施加一数据电压，非透明显示区的各个同色子像素施加另一数据电压的方案，前者方案对驱动芯片的驱动能力要求低，后者方案的驱动晶体管的宽长比、电容大小设置更灵活。
6)可选方案中，对于5)可选方案，透明显示区的像素密度小于所述非透明显示区的像素密度。减小透明显示区的像素密度，可以简化像素、驱动电路的膜层结构，降低透光功能下的衍射问题。
7)可选方案中，所述显示面板包括透明显示区、非透明显示区以及位于所述透明显示区与所述非透明显示区之间的过渡区，所述像素驱动电路为所述透明显示区中各第一OLED子像素、非透明显示区各第二OLED子像素以及过渡区中各第三OLED子像素的像素驱动电路；
当所述采样晶体管与所述驱动晶体管在任一工作阶段都未短接为二极管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且不等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；或同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管不为同一晶体管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且不等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；或同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管为同一晶体管时，各第一OLED同色子像素的存储电容的充电饱和度与各第三OLED同色子像素的存储电容的充电饱和度相同，且与各第二OLED同色子像素的存储电容的充电饱和度不同，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且不等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，各第一OLED同色子像素的存储电容的大小与驱动电流之比等于各第三OLED同色子像素的存储电容的大小与驱动电流之比，且不等于各第二OLED同色子像素的存储电容的大小与驱动电流之比；或同一灰阶下，各第一OLED同色子像素的存储电容的充电饱和度、各第二OLED同色子像素的存储电容的充电饱和度以及各第三OLED同色子像素的存储电容的充电饱和度相同，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，各第一OLED同色子像素的存储电容的大小与驱动电流之比等于各第三OLED同色子像素的存储电容的大小与驱动电流之比，且等于各第二OLED同色子像素的存储电容的大小与驱动电流之比。
本方案实现了对透明显示区与过渡区的各个同色子像素施加同一数据电压，各同色子像素流经的驱动电流可达到亮度一致的显示效果，提高透明显示区与过渡区显示均一性。此外，透明显示区与过渡区的驱动晶体管的宽长比、电容大小设置不必考虑非透明显示区的驱动晶体管的宽长比、电容大小设置，因而各自设置更灵活。
或当所述采样晶体管与所述驱动晶体管在任一工作阶段都未短接为二极管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管不为同一晶体管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管为同一晶体管时，同一灰阶下，各第一OLED同色子像素的存储电容的充电饱和度、各第二OLED同色子像素的存储电容的充电饱和度以及各第三OLED同色子像素的存储电容的充电饱和度相同，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，各第一OLED同色子像素的存储电容的大小与驱动电流之比等于各第三OLED同色子像素的存储电容的大小与驱动电流之比，且等于各第二OLED同色子像素的存储电容的大小与驱动电流之比。
本方案实现了对透明显示区、过渡区、与非透明显示区的各个同色子像素施加同一数据电压，各同色子像素流经的驱动电流可达到亮度一致的显示效果，提高整屏显示均一性。
8)可选方案中，每一第一OLED子像素至少包括：透光阳极、位于所述透光阳极上的OLED发光材料层、以及位于所述OLED发光材料层上的透光阴极；每一第一OLED子像素的透光阳极与透光阴极之间施加驱动电压时，所述第一OLED子像素执行显示功能；每一第一OLED子 像素的透光阳极与透光阴极之间未施加驱动电压时，所述第一OLED子像素执行透光功能；
各第一OLED子像素为PM驱动方式；所述透明显示区具有多行透光阳极和多列透光阴极，或具有多列透光阳极和多行透光阴极；每行/列透光阳极的长度越长，对应的像素驱动电路中的驱动晶体管的宽长比越大。
按列分布的透光阳极相对于阵列式的块状透光阳极可以省略行与行之间的图形，按行分布的透光阳极相对于阵列式的块状透光阳极可以省略列与列之间的图形，上述两种结构都简化了平面方向的图形，可以缓解上下方向上的光线衍射问题，因而透明显示区下的光传感器成像效果佳。
每行/列透光阳极的长度越长，所需的驱动电流大；而长度越长的透光阳极对应的像素驱动电路中的驱动晶体管的宽长比越大，提供的驱动电流越大。
或各第一OLED子像素为PM驱动方式或AM驱动方式；所述透明显示区具有一行若干列透光阳极、或一列若干行透光阳极，所述透光阴极为面电极；每行/列透光阳极的长度越长，对应的像素驱动电路中的驱动晶体管的宽长比越大。
9)可选方案中，所述透明显示区呈水滴状，矩形、圆形、椭圆形或刘海状。对于透光阳极按行分布的情况，水滴状、圆形、椭圆形或刘海状的部分行阳极长度短于其余部分行阳极长度。因而，长度较短的阳极对应的驱动电路中的驱动晶体管的宽长比较短；长度较长的阳极对应的驱动电路中的驱动晶体管的宽长比较长。
10)可选方案中，所述像素驱动电路中，驱动电流流经路径上的各晶体管源漏极与金属互连线图案之间通过多个导电插塞电连接。多个导电插塞相对于一个导电插塞，可以降低源漏极与金属互连图案之间的电阻，从而降低该导电插塞的功耗。
11)可选方案中，所述像素驱动电路中，驱动电流流经路径上的各晶体管的宽长比的范围为：1∶1～10∶1。上述宽长比设置得越大，越能降低该晶体管自身的电阻，也能降低该晶体管上的功耗。
附图说明
图1是本申请一实施例中的显示面板的俯视图；
图2是本申请一实施例中的显示面板的另一种像素驱动电路的电路图；
图3是本申请一实施例中的显示面板的再一种像素驱动电路的电路图及对应工作时序图；
图4是本申请一实施例中的显示面板的又一种像素驱动电路的电路图及对应工作时序图；
图5是沿着图1中的AA直线的剖视图；
图6是显示面板中各第一OLED子像素的另一种透光阳极的分布图；
图7是本申请第二实施例中的显示面板的俯视图；
图8是图7中部分区域的放大图；
图9是沿着图8中的BB直线的剖视图；
图10是本申请第三实施例中的显示面板的俯视图；
图11是图10中部分区域的放大图；
图12是本申请一实施例中的第三晶体管及第一极的金属互连结构的结构示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更为明显易懂，下面结合附图对本申请的具体实施例做详细的说明。
参照图1所示，该显示面板1包括阵列式像素单元11。每一像素单元11包括若干子像素11a、11b、11c。每一子像素(11a、11b、11c)的像素驱动电路包括采样晶体管X1、驱动晶体管X2与存储电容C。采样晶体管X1用于采集数据信号电压Vdata并将所采集到的数据信号电 压Vdata保持在存储电容C。驱动晶体管X2用于接收电源线供给的电流，并根据存储电容C保持的数据信号电压Vdata向子像素11a、11b、11c提供驱动电流Ids。
同一灰阶下，各同色子像素11a/11b/11c的驱动晶体管X2的宽长比W/L与驱动电流Ids成正比。
参照图1所示，像素驱动电路为2T1C结构，采样晶体管X1与驱动晶体管X2在任一工作阶段都未短接为二极管。
采样晶体管X1采集到的数据信号电压为Vdata。
在发光阶段，对于PMOS驱动晶体管X2，数据电压Vdata与驱动电流Ids对应公式为：
Figure PCTCN2019107913-appb-000001
其中，W为驱动晶体管的沟道宽度；L为驱动晶体管的沟道长度；Cox为电容常数，即驱动晶体管单位面积的沟道电容；μ为载流子迁移率，即半导体中载流子在单位电场下的平均漂移速率；VDD为电源电压；Vsg为源栅电压；|Vth|为驱动晶体管X2的阈值电压，为负值。
根据上述公式，同一灰阶下，各同色子像素11a/11b/11c的驱动晶体管X2的宽长比W/L与驱动电流Ids成正比，即VDD-Vdata-|Vth|为一固定值。而由于各同色子像素11a/11b/11c的驱动晶体管X2的阈值电压|Vth|相同、电源电压VDD相同，因而，各同色子像素11a/11b/11c的数据电压Vdata也相同。换言之，对于各个同色子像素11a/11b/11c，在施加同一数据电压Vdata下，可实现同一灰阶亮度，可实现亮度显示均一。
图2是本申请一实施例中的显示面板的另一种像素驱动电路的电路图。可以看出，图2中的像素驱动电路为一种3T1C结构。参照图2与图1所示，3T1C结构相对于2T1C结构增加了一个发光晶体管X3，其中，发光晶体管X3位于驱动晶体管X2与子像素11a/11b/11c之间。发光晶体管X3受控于发光信号线EM。
3T1C结构中，同一灰阶下，各同色子像素11a/11b/11c的驱动晶体管X2的宽长比W/L与驱动电流Ids成正比。
图3是本申请一实施例中的显示面板的再一种像素驱动电路的电路图及对应工作时序图。
可以看出，图3所示为7T1C结构。像素驱动电路包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和存储电容C；
其中，第一晶体管M1的栅极与OLED子像素D所在像素行的扫描信号线Sn和第二晶体管M2的栅极连接，第一晶体管M1的第一极与第六晶体管M6的第一极和第七晶体管M7的第二极连接，第一晶体管M1的第二极与第七晶体管M7的栅极和存储电容C的第二极连接；
第二晶体管M2的第一极与数据信号线VData连接，第二晶体管M2的第二极与第七晶体管M7的第一极和第三晶体管M3的第一极连接；
第三晶体管M3的栅极与第六晶体管M6的栅极连接，第三晶体管M3的第一极与第七晶体管M7的第一极连接，第三晶体管M3的第二极与存储电容C的第一极连接；
第四晶体管M4的栅极与上一像素行的扫描信号线Sn-1连接，第四晶体管M4的第一极与OLED子像素D的阳极连接，第四晶体管M4的第二极与初始电压信号Vinit线和第五晶体管M5的第二极连接；
第五晶体管M5的栅极与上一像素行的扫描信号线Sn-1连接，第五晶体管M5的第一极与第七晶体管M7的栅极和存储电容C的第二极连接，第五晶体管M5的第二极与初始电压信号Vinit线连接；
第六晶体管M6的栅极与发光信号线EM连接，第六晶体管M6的第一极与第七晶体管M7的第二极连接，第六晶体管M6的第二极与第四晶体管M4的第一极连接；
存储电容C的第一极与电源信号线VDD连接。
第一极为源极或漏极中的一个，第二极为另一个。
7T1C结构的像素驱动电路工作时序包括：初始化阶段、充电阶段和读写发光阶段。
其中，在初始化阶段中，OLED子像素D上一行的扫描信号线Sn-1提供低电压信号，OLED子像素所在行的扫描信号线Sn、发光信号线EM以及数据信号线VData提供高电压信号。此时第四晶体管M4和第五晶体管M5导通，参考电压充入OLED子像素D的阳极和存储电容C，为OLED子像素D的阳极提供负电压，清空其内部的预存电压，完成初始化。
在充电阶段，OLED子像素D上一行的扫描信号线Sn-1和发光信号线EM提供高电压信号，OLED子像素D所在行的扫描信号线Sn和数据信号线VData提供低电压信号。此时如3图中黑色实线箭头所示，第二晶体管M2、第五晶体管M5和第七晶体管M7导通，数据信号线VData的电压与第七晶体管M7的阈值电压之差充入存储电容C中，完成存储电容C的充电过程。
在读写发光阶段，OLED子像素D上一行的扫描信号线Sn-1、OLED子像素D上一行的扫描信号线Sn-1以及数据信号线VData提供高电压信号，发光信号线EM提供的低电压信号。此时如3图中黑色虚线箭头所示，第三晶体管M3、第六晶体管M6和第七晶体管M7导通，电源信号线VDD通过第三晶体管M3、第六晶体管M6和第七晶体管M7向OLED子像素D的阳极提供驱动电压，使其正常发光。
相对于2T1C，该7T1C的像素电路在发光过程中具有OLED子像素D的阈值电压补偿过程，因此能够保证OLED子像素D发光的均匀性。
上述7T1C结构中，采样晶体管与驱动晶体管为同一晶体管，都为第七晶体管M7。采样晶体管M7采集到的数据信号线VData的电压为Vdata-|Vth|，Vth为PMOS第七晶体管M7的阈值电压。
参照图3所示，第七晶体管M7的漏极与栅极在充电阶段短接，由三极管变为二极管。
同一灰阶下，各同色子像素11a/11b/11c的存储电容C的充电饱和度ΔU相同，各同色子像素11a/11b/11c的驱动晶体管M7的宽长比W/L、存储电容C的大小都与驱动电流Ids成正比；其中，充电饱和度ΔU为存储电容C在充电阶段结束时的实际所充电压与理论应冲电压的差值。
上述方案的原理在于：
在发光阶段，对于PMOS驱动晶体管M7，数据电压Vdata与驱动电流Ids对应公式为：
Figure PCTCN2019107913-appb-000002
其中，ΔU＝Vdata-|Vth|-Vgate；Vgate为存储电容在充电阶段结束时的实际所充电压，Vdata-|Vth|存储电容在充电阶段结束时的理论应冲电压；Cox为电容常数，即驱动晶体管单位面积的沟道电容；μ为载流子迁移率，即半导体中载流子在单位电场下的平均漂移速率；VDD为电源电压；ΔU为存储电容C的充电饱和度；W为驱动晶体管的沟道宽度；L为驱动晶体管的沟道长度。
根据上述公式，同一灰阶下，各同色子像素11a/11b/11c的驱动晶体管M7的宽长比W/L与驱动电流Ids成正比，即VDD-Vdata+ΔU为一固定值。由于电源电压VDD相同，要使得各同色子像素11a/11b/11c的数据电压Vdata相同，即在施加同一数据电压Vdata下实现同一灰阶亮度，可以通过控制各同色子像素11a/11b/11c的存储电容C的充电饱和度ΔU相同来实现。
由于ΔV＝Vgate-Vinit；其中，ΔV为存储电容C在充电阶段所充电电压，Vinit为初始化 阶段充入存储电容C的初始电压。
与ΔU＝Vdata-|Vth|-Vgate联立，消去Vgate，得到：ΔV+ΔU＝Vdata-|Vth|-Vinit。
可以看出，由于各同色子像素11a/11b/11c的阈值电压|Vth|相同，Vinit相同，因而，存储电容C的充电饱和度ΔU相同可以通过控制各同色子像素11a/11b/11c的存储电容C在充电阶段所充电电压ΔV相同。
而
Figure PCTCN2019107913-appb-000003
Q为充电阶段存储电容C所充电量，t 0为充电阶段持续时间，Cst为存储电容C的大小。
可以看出，各同色子像素11a/11b/11c的存储电容C在充电阶段所充电电压ΔV相同时，存储电容C的大小与驱动电流Ids成正比。
图4是本申请一实施例中的显示面板的又一种像素驱动电路的电路图及对应工作时序图。
可以看出，图4所示为5T1C结构。像素驱动电路包括：第零一晶体管M01、第零二晶体管M02、第零三晶体管M03、第零四晶体管M04、第零五晶体管M05和存储电容C；
其中，第零一晶体管M01连接在第一节点N1与第二节点N2之间，其栅极连接到扫描信号线Sn；第零二晶体管M02连接在电源电压VDD与子像素D之间，其栅极连接到第一节点N1；存储电容器C连接在电源电压VDD与第一节点N1之间；
第零三晶体管M03连接在数据信号线与第零四晶体管M04的漏极之间，其栅极接到第二控制线Sa2；第零四晶体管M04连接在第二节点N2与第零三晶体管M03的漏极之间，其栅极连接到第二节点N2；第零五晶体管M05连接在参考电压Vref与第二节点N2之间，其栅极连接到第一控制线Sa1。
5T1C结构的像素驱动电路工作时序包括：初始化阶段、充电阶段和读写发光阶段。
初始化阶段：扫描信号线Sn提供的扫描信号为低电平，第一控制线Sa1提供的控制信号由高电平变为低电平，第二控制线Sa2提供的控制信号为高电平，数据线提供的数据信号Vdata保持高电平。由于扫描信号线Sn提供的扫描信号为低电平，受扫描信号线Sn控制的第零一晶体管M01处于导通状态，同时由于第一控制线Sa1提供的控制信号由高电平变为低电平，受第一控制线Sa1控制的第零五晶体管M05由截止变为导通，因此初始化电压Vref经由第零五晶体管M05和第零一晶体管M01提供至第一节点N1，从而利用参考电压Vref对存储电容器C进行初始化。初始化之后，第一节点N1的电压为Vref，即存储电容器C的下基板电压变为Vref。
充电阶段：扫描信号线Sn提供的扫描信号保持低电平，第二控制线Sa2提供的控制信号由高电平变为低电平，第一控制线Sa1提供的控制信号保持高电平，数据线提供的数据信号Vdata保持低电平。由于第一控制线Sa1提供的控制信号保持高电平，第零五晶体管M05处于截止状态，初始化电压Vref无法经由第五晶体管M05和第零一晶体管M01提供至第一节点N1。
此时，由于扫描信号线Sn提供的扫描信号保持低电平，受扫描信号线Sn控制的第零一晶体管M01仍处于导通状态，由于第二控制线Sa2提供的控制信号由高电平变为低电平，受第二控制线Sa2控制的第零三晶体管M03由截止变为导通，数据线提供的数据信号Vdata经由第零三晶体管M03开始写入子像素D中，由于此时第零一晶体管M01、第零三晶体管M03和第零四晶体管M04均导通，数据线提供的数据信号Vdata依次经由第零三晶体管M03、第零四晶体管M04和第零一晶体管M01提供至第一节点N1，第一节点N1的电压由Vref开始上升，当第一节点N1的电压上升至Vdata-|Vth|时第零四晶体管M04由导通变为截止。Vth为第零四晶体管M04的阈值电压。
充电完成后，第一节点N1的电压即存储电容器C的下基板电压等于Vdata-|Vth|。
读写发光阶段：扫描信号线Sn提供的扫描信号由低电平变为高电平，第一控制线Sa1和第二控制线Sa2提供的控制信号均保持高电平，数据线提供的数据信号Vdata保持高电平。由于扫描信号线Sn提供的扫描信号由低电平变为高电平，受扫描信号线Sn控制的第零一晶体管M01由导通变为截止，由于第一控制线Sa1和第二控制线Sa2提供的控制信号均保持高电平，受第一控制线Sa1控制的第零五晶体管M05和受第二控制线Sa2控制的第零三晶体管M03均处于截止状态。此时，第一节点N1的电压保持为Vdata-|Vth|。
本阶段由于第零二晶体管M02导通，第零二晶体管M02向子像素D输出驱动电流Ids。
上述5T1C结构中，第零四晶体管M04为采样晶体管，第零二晶体管M02为驱动晶体管。采样晶体管M04采集到的数据信号线VData的电压为Vdata-|Vth|，Vth为采样晶体管M04的阈值电压。
在充电阶段，第零四晶体管M04源极与栅极短接，三极管变为二极管。
在发光阶段，对于PMOS驱动晶体管M02，数据电压Vdata与驱动电流Ids对应公式为：
Figure PCTCN2019107913-appb-000004
其中，W为驱动晶体管的沟道宽度；L为驱动晶体管的沟道长度；Cox为电容常数，即驱动晶体管单位面积的沟道电容；μ为载流子迁移率，即半导体中载流子在单位电场下的平均漂移速率；VDD为电源电压；Vsg为源栅电压；|Vth|为驱动晶体管M02的阈值电压，为负值。
根据上述公式，同一灰阶下，各同色子像素11a/11b/11c的驱动晶体管M02的宽长比W/L与驱动电流Ids成正比，即VDD-Vdata为一固定值。而由于各同色子像素11a/11b/11c的电源电压VDD相同，因而，各同色子像素11a/11b/11c的数据电压Vdata也相同。换言之，对于各个同色子像素11a/11b/11c，在施加同一数据电压Vdata下，可实现同一灰阶亮度，可实现亮度显示均一。
其它可选方案种，像素驱动电路也可以采用4T1C、4T2C、5T1C、或6T1C结构。上述结构中，当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管不为同一晶体管时，本方案通过改变每一第一OLED子像素的像素驱动电路中的驱动晶体管宽长比，使得：同一灰阶下，各同色第一OLED子像素的驱动晶体管的宽长比W/L与驱动电流Ids成正比。
上述结构中，当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管为同一晶体管时，也可以在同一灰阶下，各同色子像素11a/11b/11c的存储电容C的充电饱和度ΔU相同前提下，先根据驱动晶体管的数据电压Vdata与驱动电流Ids对应公式先确定：各同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids成正比；之后再根据各同色子像素11a/11b/11c的充电饱和度ΔU与存储电容C在充电阶段所充电电压ΔV之间关系，通过控制各同色子像素11a/11b/11c的所充电电压ΔV一致来实现充电饱和度ΔU一致；再接着根据各同色子像素11a/11b/11c的所充电电压ΔV一致时，存储电容C的大小Cst与驱动电流Ids成正比，来确定各同色子像素11a/11b/11c的存储电容C的大小Cst。
图5是沿着图1中的AA直线的剖视图。参照图1与图5所示，显示面板1包括透明显示区。透明显示区包括阵列式第一OLED像素单元11。每一第一OLED像素单元11包括若干第一OLED子像素11a、11b、11c，每一第一OLED子像素11a、11b、11c至少包括：透光阳极111a、位于透光阳极111a上的OLED发光材料层111b、以及位于OLED发光材料层111b上的透光阴极111c；每一第一OLED子像素111的透光阳极111a与透光阴极111c之间施加驱动电压时，阵列式排布的第一OLED像素单元11执行显示功能；每一第一OLED子像素111的透光阳极111a与透光阴极111c之间未施加驱动电压时，阵列式排布的第一OLED像素单元11 执行透光功能。
参照图5所示，每个透光阳极111a上可以设有像素定义层111d，像素定义层111d具有开口，OLED发光材料层111b位于该开口内。显示面板1的基底10可以为柔性基底，例如聚酰亚胺，也可以为硬质基底，例如玻璃。
图1中，阵列式排布的第一OLED像素单元11中的透光阳极111a呈一行、若干列分布。其它可选方案中，各透光阳极111a也可以呈一列、若干行分布、或按行、列式分布。按列分布的透光阳极111a相对于行列式分布的块状透光阳极，由于省略了行与行之间的图形，简化了平面方向的图形，可以缓解上下方向上的光线衍射问题，因而透明显示区10a下的光传感器成像效果佳。同理，按行分布的透光阳极111a相对于行列式分布的块状透光阳极，省略了列与列之间的图形。
一个可选方案中，各第一OLED子像素11a、11b、11c为PM驱动方式或AM驱动方式。图6是显示面板中各第一OLED子像素的另一种透光阳极的分布图。本方案中，透明显示区可以如图1所示，具有一行若干列透光阳极111a，透光阴极111c为面电极；也可以如图6所示，具有一列若干行透光阳极111a，透光阴极111c为面电极。
主动驱动式OLED(Active Matrix OLED，AMOLED)，也称有源驱动式中，包括薄膜晶体管(TFT)阵列，每一薄膜晶体管单元包含存储电容。AMOLED是采用独立的薄膜电晶体管控制每个像素发光，且每个像素可以连续发光。换言之，每个OLED子像素的寻址直接受控于薄膜晶体管阵列。薄膜电晶体管阵列的行选择信号可以来源于GIP电路、列选择信号可以来源于显示驱动集成芯片(DDIC)。
被动驱动式OLED(Passive Matrix OLED，PMOLED)，也称无源驱动式中，单纯地以阴极、阳极构成矩阵状，以扫描方式点亮阵列中行列交叉点的像素，每个像素都是操作在短脉冲模式下，为瞬间高亮度发光。换言之，每个OLED子像素的寻址直接受控于外部电路。
图6所示显示面板可以对应水滴状或刘海状的透明显示区。
以下以图6所示透光阳极分布为例，介绍每一第一OLED子像素的透光阳极对应的像素驱动电路中，驱动晶体管W/L与存储电容C的大小Cst的具体确定方法。
参照图6所示，自上而下，各行第一OLED子像素11a/11b/11c的透光阳极111a的长度逐渐变短。
对于采样晶体管与驱动晶体管在任一工作阶段都未短接为二极管的像素驱动电路，例如图1所示2T1C或图2所示3T1C结构，先设定某一行，例如第一行第一OLED子像素11a/11b/11c的透光阳极111a的驱动晶体管X2的宽长比W/L；
由于同一灰阶下，各行第一OLED子像素11a/11b/11c的驱动晶体管X2的宽长比W/L与驱动电流Ids成正比；因而可以在一灰阶，例如255灰阶下，根据各行第一OLED子像素11a/11b/11c的驱动电流Ids，确定各行第一OLED子像素11a/11b/11c的驱动晶体管X2的宽长比W/L。
对于采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管为同一晶体管的像素驱动电路，例如图3所示7T1C结构，先设定某一行，例如第一行第一OLED子像素11a/11b/11c的透光阳极111a的驱动晶体管M7的宽长比W/L；
由于同一灰阶下，各行第一OLED子像素11a/11b/11c的驱动晶体管M7的宽长比W/L与驱动电流Ids成正比；因而可以在一灰阶，例如255灰阶下，根据各行第一OLED子像素11a/11b/11c的驱动电流Ids，确定各行第一OLED子像素11a/11b/11c的驱动晶体管M7的宽长比W/L；
先设定某一行，例如第一行第一OLED子像素11a/11b/11c的透光阳极111a的存储电容C的大小Cst；
由于同一灰阶下，各行第一OLED子像素11a/11b/11c的存储电容C的大小Cst与驱动电流Ids成正比；因而可以在一灰阶，例如255灰阶下，根据各行第一OLED子像素11a/11b/11c的驱动电流Ids，确定各行第一OLED子像素11a/11b/11c的存储电容C的大小Cst。
对于采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管不为同一晶体管的像素驱动电路，例如图4所示5T1C结构，先设定某一行，例如第一行第一OLED子像素11a/11b/11c的透光阳极111a的驱动晶体管M02的宽长比W/L；
由于同一灰阶下，各行第一OLED子像素11a/11b/11c的驱动晶体管M02的宽长比W/L与驱动电流Ids成正比；因而可以在一灰阶，例如255灰阶下，根据各行第一OLED子像素11a/11b/11c的驱动电流Ids，确定各行第一OLED子像素11a/11b/11c的驱动晶体管M02的宽长比W/L。
图6中的弧形区，各行第一OLED子像素11a/11b/11c的透光阳极111a自上而下长度变短。可以理解的是，为实现同一灰阶亮度，自上而下各行透光阳极111a所需驱动电流Ids逐渐变小，因而对应的像素驱动电路中的驱动晶体管X2的宽长比W/L逐渐变小。
同理，对于各列透光阳极111a中，长度越长对应的像素驱动电路中的驱动晶体管X2的宽长比W/L越大。
再一个可选方案中，各第一OLED子像素11a、11b、11c为PM驱动方式。透明显示区具有多行透光阳极111a和多列透光阴极111c，或具有多列透光阳极111a和多行透光阴极111c。每行/列透光阳极111a的长度越长，对应的像素驱动电路中的驱动驱动晶体管X2的宽长比W/L越大。
图7是本申请第二实施例中的显示面板的俯视图。图8是图7中部分区域的放大图。参照图7与图8所示，显示面板2包括透明显示区10a与非透明显示区10b。透明显示区10a中的各第一OLED子像素11a、11b、11c与前述实施例相同。
图9是沿着图8中的BB直线的剖视图。参照图8与图9所示，非透明显示区10b包括阵列式第二OLED像素单元12，每一第二OLED像素单元12包括若干第二OLED子像素12a、12b、12c，每一第二OLED子像素12a、12b、12c自下而上至少依次包括：形成于基底10上的反射阳极121a、具有开口的像素定义层121d、位于开口内的OLED发光材料层121b、以及位于OLED发光材料层121b上的透光阴极121c。
本实施例中，当采样晶体管与驱动晶体管在任一工作阶段都未短接为二极管时，例如图1所示2T1C或图2所示3T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的驱动晶体管X2的宽长比W/L与驱动电流Ids之比等于各第二OLED同色子像素12a/12b/12c的驱动晶体管X2的宽长比W/L与驱动电流Ids之比。
当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管为同一晶体管时，例如图3所示7T1C结构中，各第一OLED同色子像素11a/11b/11c的存储电容的充电饱和度ΔU与各第二OLED同色子像素12a/12b/12c的存储电容的充电饱和度ΔU相同，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids之比等于各第二OLED同色子像素12a/12b/12c的驱动晶体管的宽长比W/L与驱动电流Ids之比，各第一OLED同色子像素11a/11b/11c的存储电容C的大小Cst与驱动电流Ids之比等于各第二OLED同色子像素12a/12b/12c的存储电容的大小Cst与驱动电流Ids之比；
当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管不为同一晶体管时，例如图4所示5T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids之比等于各第二OLED同色子像素12a/12b/12c的驱动晶体管的宽长比W/L与驱动电流Ids之比。
本方案实现了对透明显示区10a与非透明显示区10b的各个同色子像素施加同一数据电压Vdata，各同色子像素流经的驱动电流Ids可达到亮度一致的显示效果，提高整屏显示均一性。相对于透明显示区10a的各个同色子像素施加一数据电压Vdata，非透明显示区10b的各个同色子像素施加另一数据电压Vdata的方案，前者方案对驱动芯片的驱动能力要求低，后者方案的驱动晶体管X2的宽长比W/L、存储电容C的电容大小Cst设置更灵活。
参照图8所示，透明显示区10a的像素密度小于所述非透明显示区10b的像素密度。减小透明显示区10a的像素密度，可以简化像素、驱动电路的膜层结构，降低透光功能下的衍射问 题。
图10是本申请第三实施例中的显示面板的俯视图。图11是图10中部分区域的放大图。参照图10与图11所示，显示面板3包括透明显示区10a、非透明显示区10b、以及位于透明显示区10a与非透明显示区10b之间的过渡区10c。透明显示区10a中的各第一OLED子像素11a、11b、11c、非透明显示区10b中的各第二OLED子像素12a、12b、12c与前述实施例相同。过渡区10c中的各第三OLED子像素与前述实施例中的第二OLED子像素12a、12b、12c相同。
当采样晶体管与驱动晶体管在任一工作阶段都未短接为二极管时，例如图1所示2T1C或图2所示3T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids之比等于各第三OLED同色子像素的驱动晶体管的宽长比W/L与驱动电流Ids之比，且不等于各第二OLED同色子像素的驱动晶体管12a/12b/12c的宽长比W/L与驱动电流Ids之比。
当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管为同一晶体管时，例如图3所示7T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的存储电容的充电饱和度ΔU与各第三OLED同色子像素的存储电容的充电饱和度ΔU相同，且与各第二OLED同色子像素的存储电容的充电饱和度ΔU不同，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids之比等于各第三OLED同色子像素的驱动晶体管的宽长比W/L与驱动电流Ids之比，且不等于各第二OLED同色子像素的驱动晶体管的宽长比W/L与驱动电流Ids之比，各第一OLED同色子像素11a/11b/11c的存储电容的大小Cst与驱动电流Ids之比等于各第三OLED同色子像素的存储电容的大小Cst与驱动电流Ids之比，且不等于各第二OLED同色子像素的存储电容的大小Cst与驱动电流Ids之比。
当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管不为同一晶体管时，例如图4所示5T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids之比等于各第三OLED同色子像素的驱动晶体管的宽长比W/L与驱动电流Ids之比，且不等于各第二OLED同色子像素12a/12b/12c的驱动晶体管的宽长比W/L与驱动电流Ids之比。
本方案实现了对透明显示区10a与过渡区10c的各个同色子像素施加同一数据电压Vdata，各同色子像素流经的驱动电流Ids可达到亮度一致的显示效果，提高透明显示区10a与过渡区10c显示均一性。此外，透明显示区10a与过渡区10c的驱动晶体管X2的宽长比W/L、存储电容C的电容大小Cst设置不必考虑非透明显示区10b的驱动晶体管的宽长比W/L、存储电容C的电容大小Cst设置，因而各自设置更灵活。
另一个可选方案中，当采样晶体管与驱动晶体管在任一工作阶段都未短接为二极管时，例如图1所示2T1C或图2所示3T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids等于各第二OLED同色子像素12a/12b/12c的驱动晶体管的宽长比W/L与驱动电流Ids之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比W/L与驱动电流Ids之比。
当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管为同一晶体管时，例如图3所示7T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的存储电容的充电饱和度ΔU、各第二OLED同色子像素12a/12b/12c的存储电容的充电饱和度ΔU以及各第三OLED同色子像素的存储电容的充电饱和度ΔU相同，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids之比等于各第二OLED同色子像素12a/12b/12c的驱动晶体管的宽长比W/L与驱动电流Ids之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比W/L与驱动电流Ids之比，各第一OLED同色子像素11a/11b/11c的存储电容的大小Cst与驱动电流Ids之比等于各第三OLED同色子像素的存储电容的大小Cst与驱动电流Ids之比，且等于各第二OLED同色子像素12a/12b/12c的存储电容的大小Cst与驱动电流Ids之比。
当采样晶体管和/或驱动晶体管在一工作阶段短接为二极管，且采样晶体管与驱动晶体管不 为同一晶体管时，例如图4所示5T1C结构中，同一灰阶下，各第一OLED同色子像素11a/11b/11c的驱动晶体管的宽长比W/L与驱动电流Ids之比等于各第二OLED同色子像素12a/12b/12c的驱动晶体管的宽长比W/L与驱动电流Ids之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比W/L与驱动电流Ids之比。
本方案实现了对透明显示区10a、过渡区10c、与非透明显示区10b的各个同色子像素施加同一数据电压Vdata，各同色子像素流经的驱动电流Ids可达到亮度一致的显示效果，提高整屏显示均一性。
本方案中，透明显示区10a的像素密度可以小于非透明显示区10b的像素密度；过渡区10c的像素密度可以介于透明显示区10a的像素密度与非透明显示区10b的像素密度之间，以进一步提高显示效果。
以图3中7T1C结构中第三晶体管第一极的电连接为例。图12是本申请一实施例中的第三晶体管及第一极的金属互连结构的结构示意图。参照图12所示，图3所示像素驱动电路中，各晶体管之间通过金属互连结构4电连接，金属互连结构4包括：金属互连线图案41以及导电插塞42。
参照图3所示，如虚线所示，像素驱动电路中，在发光阶段，驱动电流流经路径上的第三晶体管M3的第一极与金属互连线图案41(参照图12所示)之间、和/或第七晶体管M7的第一极与金属互连线图案41之间、和/或第七晶体管M7的第二极与金属互连线图案41、和/或第六晶体管M6的第一极与金属互连线图案41之间之间可以具有多个导电插塞42。多个是指两个及其以上数目。
多个导电插塞42相对于一个导电插塞42，可以降低源漏极与金属互连图案41之间的电阻，从而降低该导电插塞42的功耗。
其它实施例中，也可以为2T1C、3T1C、4T1C、4T2C、5T1C、6T1C等传统像素驱动电路。其它像素驱动电路中，在发光阶段，驱动电流流经路径上，也即电源电压VDD与接地电压VSS之间的各晶体管源漏极与金属互连线图案之间可以具有多个导电插塞，以降低源漏极与金属互连图案之间的电阻，从而降低该导电插塞的功耗。
一个可选方案中，上述像素驱动电路中，驱动电流流经路径上的第三晶体管M3、和/或第六晶体管M6、和/或第七晶体管M7的宽长比的范围为：1∶1～10∶1。上述宽长比设置得越大，越能降低该晶体管自身的电阻，也能降低该晶体管上的功耗。其它像素驱动电路中，在发光阶段，驱动电流流经路径上，也即电源电压VDD与接地电压VSS之间的晶体管的宽长比的范围可以为：1∶1～10∶1，以降低该晶体管自身的电阻，也能降低该晶体管上的功耗。
基于上述像素驱动电路，本申请还提供一种包括上述像素驱动电路的显示面板。
上述像素驱动电路也可以结合入图1至图11实施例中的显示面板，OLED子像素D可以为第一OLED子像素11a、11b、11c。
基于上述显示面板1、2、3，本申请还提供一种显示装置。
该显示装置可以为手机、平板电脑、车载显示屏等的显示装置。
显示装置包括：
设备本体，具有器件区；
以及上述的显示面板1、2、3，覆盖在所述设备本体上；
其中，器件区位于显示面板的透明显示区10a下方，且器件区中设置有透过透明显示区10a发射或者采集光线的感光器件。
感光器件包括：摄像头和/或光线感应器。光线感应器包括：虹膜识别传感器以及指纹识别传感器中的一种或组合。
虽然本申请披露如上，但本申请并非限定于此。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各种更动与修改，因此本申请的保护范围应当以权利要求所限定的范围为准。

Claims (19)

  1. 一种显示面板，包括阵列式像素单元，每一像素单元包括若干子像素，每一子像素的像素驱动电路至少包括：采样晶体管、驱动晶体管与存储电容；所述采样晶体管用于采集数据信号电压并将所采集到的数据信号电压保持在所述存储电容，所述驱动晶体管用于接收电源线供给的电流，并根据所述存储电容保持的数据信号电压向所述子像素提供驱动电流；
    当所述采样晶体管与所述驱动晶体管在任一工作阶段都未短接为二极管时，同一灰阶下，所述驱动晶体管的宽长比与驱动电流成正比；
    当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管不为同一晶体管时，同一灰阶下，所述驱动晶体管的宽长比与驱动电流成正比；
    当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管为同一晶体管时，同一灰阶下，所述存储电容的充电饱和度相同，所述驱动晶体管的宽长比、存储电容的大小都与驱动电流成正比；其中，所述充电饱和度为所述存储电容在充电阶段结束时的实际所充电压与理论应冲电压的差值。
  2. 根据权利要求1所述的显示面板，其中，所述像素驱动电路为2T1C或3T1C结构，所述采样晶体管与所述驱动晶体管在任一工作阶段都未短接为二极管。
  3. 根据权利要求1所述的显示面板，其中，所述像素驱动电路为4T1C、4T2C、5T1C、6T1C、或7T1C结构，所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管。
  4. 根据权利要求3所述的显示面板，其中，所述像素驱动电路为6T1C或7T1C结构，所述存储电容在充电阶段结束时的理论应冲电压为所述数据信号电压与所述驱动晶体管的阈值电压的差值。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板包括透明显示区，所述透明显示区中包括第一OLED子像素，所述像素驱动电路为所述透明显示区中各第一OLED子像素的像素驱动电路。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板包括透明显示区与非透明显示区，所述透明显示区包括第一OLED子像素，所述非透明显示区包括第二OLED子像素，所述像素驱动电路为所述透明显示区中各第一OLED子像素与非透明显示区各第二OLED子像素的像素驱动电路；
    当所述采样晶体管与所述驱动晶体管在任一工作阶段都未短接为二极管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
    当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管不为同一晶体管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
    当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管为同一晶体管时，各第一OLED同色子像素的存储电容的充电饱和度与各第二OLED同色子像素的存储电容的充电饱和度相同，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，各第一OLED同色子像素的存储电容的大小与驱动电流之比等于各第二OLED同色子像素的存储电容的大小与驱动电流之比。
  7. 根据权利要求5所述的显示面板，其中，所述透明显示区的像素密度小于所述非透明显示区的像素密度。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板包括透明显示区、非透明显示区以及位于所述透明显示区与所述非透明显示区之间的过渡区，所述透明显示区包括第一OLED子像素，所述非透明显示区包括第二OLED子像素，所述过渡区包括第三OLED子像素，所述 像素驱动电路为所述透明显示区中各第一OLED子像素、非透明显示区各第二OLED子像素以及过渡区中各第三OLED子像素的像素驱动电路；
    当所述采样晶体管与所述驱动晶体管在任一工作阶段都未短接为二极管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且不等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；或同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
    当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管不为同一晶体管时，同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且不等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；或同一灰阶下，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比；
    当所述采样晶体管和/或所述驱动晶体管在一工作阶段短接为二极管，且所述采样晶体管与所述驱动晶体管为同一晶体管时，各第一OLED同色子像素的存储电容的充电饱和度与各第三OLED同色子像素的存储电容的充电饱和度相同，且与各第二OLED同色子像素的存储电容的充电饱和度不同，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且不等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，各第一OLED同色子像素的存储电容的大小与驱动电流之比等于各第三OLED同色子像素的存储电容的大小与驱动电流之比，且不等于各第二OLED同色子像素的存储电容的大小与驱动电流之比；或同一灰阶下，各第一OLED同色子像素的存储电容的充电饱和度、各第二OLED同色子像素的存储电容的充电饱和度以及各第三OLED同色子像素的存储电容的充电饱和度相同，各第一OLED同色子像素的驱动晶体管的宽长比与驱动电流之比等于各第二OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，且等于各第三OLED同色子像素的驱动晶体管的宽长比与驱动电流之比，各第一OLED同色子像素的存储电容的大小与驱动电流之比等于各第三OLED同色子像素的存储电容的大小与驱动电流之比，且等于各第二OLED同色子像素的存储电容的大小与驱动电流之比。
  9. 根据权利要求8所述的显示面板，其中，
    所述透明显示区的像素密度小于所述非透明显示区的像素密度；所述过渡区的像素密度介于所述透明显示区的像素密度与非透明显示区的像素密度之间。
  10. 根据权利要求5至9中任一项所述的显示面板，其中，每一第一OLED子像素至少包括：透光阳极、位于所述透光阳极上的OLED发光材料层、以及位于所述OLED发光材料层上的透光阴极；每一第一OLED子像素的透光阳极与透光阴极之间施加驱动电压时，所述第一OLED子像素执行显示功能；每一第一OLED子像素的透光阳极与透光阴极之间未施加驱动电压时，所述第一OLED子像素执行透光功能；
    各第一OLED子像素为PM驱动方式，所述透明显示区具有多行透光阳极和多列透光阴极，或具有多列透光阳极和多行透光阴极，每行/列透光阳极的长度越长，对应的像素驱动电路中的驱动晶体管的宽长比越大；
    或各第一OLED子像素为AM驱动方式，所述透明显示区具有一行若干列透光阳极、或一列若干行透光阳极，所述透光阴极为面电极，每行/列透光阳极的长度越长，对应的像素驱动电路中的驱动晶体管的宽长比越大。
  11. 根据权利要求5至9中任一项所述的显示面板，其特征在于，所述透明显示区呈水滴状、矩形、圆形、椭圆形或刘海状。
  12. 根据权利要求1所述的显示面板，其中，所述像素驱动电路中，驱动电流流经路径上 的各晶体管源漏极与金属互连线图案之间通过多个导电插塞电连接，和/或驱动电流流经路径上的各晶体管的宽长比的范围为：1∶1～10∶1；和/或所述像素驱动电路包括2T1C、3T1C、4T1C、4T2C、5T1C、6T1C、或7T1C。
  13. 根据权利要求11所述的显示面板，其中，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管和存储电容；
    其中，所述第一晶体管的栅极与OLED子像素所在像素行的扫描信号线和所述第二晶体管的栅极连接，所述第一晶体管的第一极与所述第六晶体管的第一极和所述第七晶体管的第二极连接，所述第一晶体管的第二极与所述第七晶体管的栅极和所述存储电容的第二极连接；
    所述第二晶体管的第一极与数据信号线连接，所述第二晶体管的第二极与所述第七晶体管的第一极和第三晶体管的第一极连接；
    所述第三晶体管的栅极与所述第六晶体管的栅极连接，所述第三晶体管的第一极与所述第七晶体管的第一极连接，所述第三晶体管的第二极与所述存储电容的第一极连接；
    所述第四晶体管的栅极与上一像素行的扫描信号线连接，所述第四晶体管的第一极与OLED子像素的阳极连接，所述第四晶体管的第二极与初始电压信号线和所述第五晶体管的第二极连接；
    所述第五晶体管的栅极与上一像素行的扫描信号线连接，所述第五晶体管的第一极与所述第七晶体管的栅极和所述存储电容的第二极连接，所述第五晶体管的第二极与初始电压信号线连接；
    所述第六晶体管的栅极与发光信号线连接，所述第六晶体管的第一极与所述第七晶体管的第二极连接，所述第六晶体管的第二极与所述第四晶体管的第一极连接；
    所述存储电容的第一极与电源信号线连接；
    所述第三晶体管的第一极与金属互连线图案之间、和/或第七晶体管的第一极与金属互连线图案之间、和/或第七晶体管的第二极与金属互连线图案、和/或第六晶体管的第一极与金属互连线图案之间之间可以具有多个导电插塞；和/或所述第三晶体管、和/或所述第六晶体管、和/或所述第七晶体管的宽长比的范围为：1∶1～10∶1。
  14. 一种显示面板的像素驱动电路，包括多个晶体管、金属互连线图案和多个导电插塞，所述多个导电插塞位于驱动电流流经路径上的各所述晶体管的源漏极与所述金属互连线图案之间，和/或驱动电流流经路径上的各所述晶体管的宽长比的范围为：1∶1～10∶1。
  15. 根据权利要14所述的像素驱动电路，其中，所述像素驱动电路包括2T1C、3T1C、4T1C、4T2C、5T1C、6T1C、或7T1C。
  16. 根据权利要求14所述的像素驱动电路，其中，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管和存储电容；
    其中，所述第一晶体管的栅极与OLED子像素所在像素行的扫描信号线和所述第二晶体管的栅极连接，所述第一晶体管的第一极与所述第六晶体管的第一极和所述第七晶体管的第二极连接，所述第一晶体管的第二极与所述第七晶体管的栅极和所述存储电容的第二极连接；
    所述第二晶体管的第一极与数据信号线连接，所述第二晶体管的第二极与所述第七晶体管的第一极和第三晶体管的第一极连接；
    所述第三晶体管的栅极与所述第六晶体管的栅极连接，所述第三晶体管的第一极与所述第七晶体管的第一极连接，所述第三晶体管的第二极与所述存储电容的第一极连接；
    所述第四晶体管的栅极与上一像素行的扫描信号线连接，所述第四晶体管的第一极与OLED子像素的阳极连接，所述第四晶体管的第二极与初始电压信号线和所述第五晶体管的第二极连接；
    所述第五晶体管的栅极与上一像素行的扫描信号线连接，所述第五晶体管的第一极与所述第七晶体管的栅极和所述存储电容的第二极连接，所述第五晶体管的第二极与初始电压信号线连接；
    所述第六晶体管的栅极与发光信号线连接，所述第六晶体管的第一极与所述第七晶体管的 第二极连接，所述第六晶体管的第二极与所述第四晶体管的第一极连接；
    所述存储电容的第一极与电源信号线连接；
    所述第三晶体管的第一极与金属互连线图案之间、和/或第七晶体管的第一极与金属互连线图案之间、和/或第七晶体管的第二极与金属互连线图案、和/或第六晶体管的第一极与金属互连线图案之间之间可以具有多个导电插塞；和/或所述第三晶体管、和/或所述第六晶体管、和/或所述第七晶体管的宽长比的范围为1∶1～10∶1。
  17. 一种显示面板，其特征在于，包括权利要求14-16任一项所述的像素驱动电路。
  18. 一种显示装置，所述显示装置包括：
    设备本体，具有器件区；
    以及根据权利要求1至13任一项所述的显示面板，覆盖在所述设备本体上；
    其中，所述器件区位于所述显示面板的透明显示区下方，且所述器件区中设置有透过所述透明显示区发射或者采集光线的感光器件。
  19. 根据权利要求18所述的显示装置，其中，所述感光器件包括摄像头和/或光线感应器。
PCT/CN2019/107913 2019-03-29 2019-09-25 显示装置及其显示面板、显示面板的像素驱动电路 Ceased WO2020199534A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/320,990 US11355051B2 (en) 2019-03-29 2021-05-14 Display device, display panel, and pixel drive circuit of display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910250976.7 2019-03-29
CN201910250976.7A CN110767158B (zh) 2019-03-29 2019-03-29 显示装置及其显示面板、显示面板的像素驱动电路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/320,990 Continuation US11355051B2 (en) 2019-03-29 2021-05-14 Display device, display panel, and pixel drive circuit of display panel

Publications (1)

Publication Number Publication Date
WO2020199534A1 true WO2020199534A1 (zh) 2020-10-08

Family

ID=69328779

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/107913 Ceased WO2020199534A1 (zh) 2019-03-29 2019-09-25 显示装置及其显示面板、显示面板的像素驱动电路

Country Status (3)

Country Link
US (1) US11355051B2 (zh)
CN (1) CN110767158B (zh)
WO (1) WO2020199534A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504289B (zh) 2019-08-27 2022-08-16 武汉天马微电子有限公司 一种显示面板和显示装置
JP2021076629A (ja) * 2019-11-05 2021-05-20 ソニーセミコンダクタソリューションズ株式会社 表示装置、表示装置の駆動方法、及び、電子機器
CN111369941B (zh) 2020-03-19 2021-04-27 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN111799318B (zh) * 2020-07-28 2022-08-19 武汉天马微电子有限公司 一种显示面板及显示装置
CN112259056B (zh) * 2020-09-15 2022-09-06 昆山国显光电有限公司 显示面板及亮度校正方法
CN112086068A (zh) * 2020-09-16 2020-12-15 合肥维信诺科技有限公司 显示装置及其驱动方法
US11688338B2 (en) 2020-11-13 2023-06-27 Chengdu Boe Optoelectronics Technology Co., Ltd. Display device, luminance compensation circuit thereof and luminance compensation method
CN112542126B (zh) * 2020-12-15 2022-08-05 合肥维信诺科技有限公司 显示面板和显示装置
CN112466254B (zh) * 2020-12-17 2022-06-07 武汉天马微电子有限公司 显示面板及显示控制方法、容量的确定方法及显示装置
CN112489585B (zh) 2020-12-25 2024-04-26 厦门天马微电子有限公司 一种显示面板及显示装置
CN113823210B (zh) * 2021-08-19 2023-06-27 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN113744683B (zh) * 2021-09-03 2023-06-27 北京京东方技术开发有限公司 像素电路、驱动方法和显示装置
CN113763861B (zh) * 2021-09-18 2024-07-12 厦门天马微电子有限公司 一种显示面板及其驱动方法、显示装置
CN114038423B (zh) 2021-12-09 2023-03-21 京东方科技集团股份有限公司 显示面板及显示装置
TWI802386B (zh) * 2022-04-25 2023-05-11 大陸商北京歐錸德微電子技術有限公司 畫素電路、oled顯示裝置及資訊處理裝置
CN114822395B (zh) * 2022-05-07 2023-06-27 武汉华星光电半导体显示技术有限公司 显示面板
CN114999369B (zh) 2022-06-08 2023-08-04 滁州惠科光电科技有限公司 像素驱动电路及显示面板
CN119541387B (zh) * 2023-08-29 2025-08-26 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702210A (zh) * 2016-04-25 2016-06-22 上海天马微电子有限公司 有机发光像素驱动电路及其驱动方法
US20180182286A1 (en) * 2016-12-22 2018-06-28 Intel Corporation Digital driver for displays
US20180348561A1 (en) * 2006-09-29 2018-12-06 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
CN109036283A (zh) * 2018-09-06 2018-12-18 京东方科技集团股份有限公司 有机发光场效应晶体管的驱动电路及驱动方法、显示装置
CN109272932A (zh) * 2018-11-28 2019-01-25 昆山国显光电有限公司 像素电路及其驱动方法、显示面板、显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583252B1 (ko) * 2003-12-29 2006-05-24 엘지.필립스 엘시디 주식회사 유기전계 발광소자와 그 제조방법
US20080090403A1 (en) * 2006-10-02 2008-04-17 Credence Systems Corporation Apparatus and method forming a contact to silicide and a contact to a contact
JP5171807B2 (ja) 2007-03-08 2013-03-27 シャープ株式会社 表示装置およびその駆動方法
CN102290027B (zh) * 2010-06-21 2013-10-30 北京大学深圳研究生院 一种像素电路及显示设备
CN104037173B (zh) * 2013-03-08 2017-05-24 中芯国际集成电路制造(上海)有限公司 多晶硅电阻结构及其形成方法
CN103646629B (zh) * 2013-12-18 2016-06-08 信利半导体有限公司 一种主动矩阵有机发光显示器的像素驱动装置
CN104536179B (zh) * 2014-11-28 2017-05-31 深圳市华星光电技术有限公司 平板显示器
CN104898337B (zh) * 2015-06-30 2018-02-02 上海天马微电子有限公司 一种阵列基板、显示面板、显示装置及制作方法
KR102375192B1 (ko) * 2015-07-03 2022-03-17 삼성디스플레이 주식회사 유기 발광 표시 장치
CN106709866B (zh) 2016-11-18 2019-12-13 智慧眼科技股份有限公司 证件照去除网格水印的方法及装置、人脸验证方法及装置
CN107038997A (zh) 2017-05-26 2017-08-11 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN108269840B (zh) * 2017-09-30 2021-08-13 昆山国显光电有限公司 显示屏及显示装置
KR102518854B1 (ko) * 2018-04-05 2023-04-10 삼성디스플레이 주식회사 표시 장치
CN108538206B (zh) * 2018-05-25 2021-02-09 武汉天马微电子有限公司 显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180348561A1 (en) * 2006-09-29 2018-12-06 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
CN105702210A (zh) * 2016-04-25 2016-06-22 上海天马微电子有限公司 有机发光像素驱动电路及其驱动方法
US20180182286A1 (en) * 2016-12-22 2018-06-28 Intel Corporation Digital driver for displays
CN109036283A (zh) * 2018-09-06 2018-12-18 京东方科技集团股份有限公司 有机发光场效应晶体管的驱动电路及驱动方法、显示装置
CN109272932A (zh) * 2018-11-28 2019-01-25 昆山国显光电有限公司 像素电路及其驱动方法、显示面板、显示装置

Also Published As

Publication number Publication date
CN110767158B (zh) 2020-10-27
US11355051B2 (en) 2022-06-07
CN110767158A (zh) 2020-02-07
US20210272499A1 (en) 2021-09-02

Similar Documents

Publication Publication Date Title
CN110767158B (zh) 显示装置及其显示面板、显示面板的像素驱动电路
US11361713B1 (en) Display panel and display device
CN110246459B (zh) 像素电路及其驱动方法、显示面板及显示装置
US11270630B2 (en) Driving circuit, driving method thereof and display apparatus
CN112309332B (zh) 像素电路及其驱动方法、显示基板和显示面板
CN109979394B (zh) 像素电路及其驱动方法、阵列基板及显示装置
CN113192463B (zh) 发光控制移位寄存器、栅极驱动电路、显示装置及方法
US10679556B2 (en) Pixel circuit having a switching circuit, a shared circuit, a first sub-pixel circuit and a second sub-pixel circuit and driving method thereof, display panel
CN109559679B (zh) 触控显示面板及其驱动方法、像素电路、电子装置
CN106940984B (zh) 有机发光显示面板及其驱动方法、有机发光显示装置
CN112352274B (zh) 像素补偿电路、显示面板、驱动方法及显示装置
KR101046415B1 (ko) 화소회로 및 표시장치
CN115691421A (zh) 像素电路及其驱动方法、阵列基板和显示装置
CN108520716B (zh) 一种像素电路单元及驱动方法、显示面板、显示装置
WO2019062579A1 (zh) 像素电路及其驱动方法、显示装置
CN112435628B (zh) 显示面板及其显示控制方法、占空比调整方法及显示装置
CN112771600A (zh) 像素电路及其驱动方法、阵列基板及显示装置
WO2019174228A1 (zh) 像素电路及其驱动方法、显示面板
CN114730542A (zh) 像素驱动电路、显示设备以及像素驱动方法
CN114333692A (zh) 显示面板及使用其的显示设备
CN114360421A (zh) 显示面板及使用该显示面板的显示装置
CN117337459A (zh) 像素电路及其驱动方法、显示面板、显示装置
KR20250102388A (ko) 표시패널과 이를 포함한 표시장치
CN117373392A (zh) 显示屏、显示驱动器、电子设备及其驱动方法
US11527199B2 (en) Pixel circuit including discharge control circuit and storage control circuit and method for driving pixel circuit, display panel and electronic device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19922765

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19922765

Country of ref document: EP

Kind code of ref document: A1