WO2020199405A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2020199405A1
WO2020199405A1 PCT/CN2019/094524 CN2019094524W WO2020199405A1 WO 2020199405 A1 WO2020199405 A1 WO 2020199405A1 CN 2019094524 W CN2019094524 W CN 2019094524W WO 2020199405 A1 WO2020199405 A1 WO 2020199405A1
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Prior art keywords
transistor
electrically connected
node
control signal
signal
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English (en)
French (fr)
Inventor
蔡玉莹
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020199405A1 publication Critical patent/WO2020199405A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED(Organic Light Emitting Diode (Organic Light Emitting Diode) display panels have the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and have been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit.
  • the transistor has the problem of threshold voltage drift.
  • OLED pixel drive circuit needs corresponding compensation structure.
  • the compensation structure of the OLED pixel driving circuit is relatively complicated, which occupies a large area when designing a layout, which is not conducive to the design of a high PPI (Pixels Per Inch, pixel density) display panel.
  • the purpose of the embodiments of the present application is to provide a pixel driving circuit and a display panel, which can solve the technical problem that the compensation structure of the existing pixel driving circuit is relatively complicated and a large area is occupied when designing the layout.
  • An embodiment of the application provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to a scan signal, the source of the third transistor is electrically connected to the second control signal, and the drain of the third transistor is electrically connected to a third node;
  • a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the third node;
  • the first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the third node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to the ground terminal;
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor; the light emitting device is an organic light emitting diode.
  • the combination of the first control signal, the second control signal, the scan signal, and the data signal sequentially corresponds to an initialization phase, a threshold voltage detection phase, and a threshold voltage compensation phase.
  • Phase and light-emitting phase; the data signal includes a reference low potential and a display high potential.
  • the first control signal is at a low potential
  • the second control signal is changed from a high potential to a low potential
  • the scan signal is at a high potential.
  • the data signal is the reference low potential.
  • the first control signal is at a high potential
  • the second control signal is at a low potential
  • the scan signal is at a low potential
  • the data The signal is the reference low potential.
  • the first control signal is at a high potential
  • the second control signal is at a low potential
  • the scan signal is at a low potential
  • the data The signal is the display high potential
  • the first control signal is at a low potential
  • the second control signal is at a low potential
  • the scan signal is at a low potential
  • the data signal is The reference low potential.
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • An embodiment of the present application also provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to a scan signal, the source of the third transistor is electrically connected to the second control signal, and the drain of the third transistor is electrically connected to a third node;
  • a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the third node;
  • the first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the third node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to the ground terminal.
  • the combination of the first control signal, the second control signal, the scan signal, and the data signal sequentially corresponds to an initialization phase, a threshold voltage detection phase, and a threshold voltage compensation phase.
  • Phase and light-emitting phase; the data signal includes a reference low potential and a display high potential.
  • the first control signal is at a low potential
  • the second control signal is changed from a high potential to a low potential
  • the scan signal is at a high potential.
  • the data signal is the reference low potential.
  • the first control signal is at a high potential
  • the second control signal is at a low potential
  • the scan signal is at a low potential
  • the data The signal is the reference low potential.
  • the first control signal is at a high potential
  • the second control signal is at a low potential
  • the scan signal is at a low potential
  • the data The signal is the display high potential
  • the first control signal is at a low potential
  • the second control signal is at a low potential
  • the scan signal is at a low potential
  • the data signal is The reference low potential.
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the light-emitting device is an organic light-emitting diode.
  • An embodiment of the application also provides a display panel, which includes a pixel drive circuit, and the pixel circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate of the third transistor is electrically connected to a scan signal, the source of the third transistor is electrically connected to the second control signal, and the drain of the third transistor is electrically connected to a third node;
  • a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the third node;
  • the first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the third node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to the ground terminal.
  • the combination of the first control signal, the second control signal, the scan signal, and the data signal sequentially corresponds to an initialization phase, a threshold voltage detection phase, and a threshold voltage compensation phase.
  • the light-emitting stage; the data signal includes a reference low potential and a display high potential.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the light emitting device is an organic light emitting diode.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application use a pixel drive circuit with a 3T2C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the embodiment of the application in the initialization phase under the driving timing shown in FIG. 2;
  • FIG. 4 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage detection phase under the driving timing shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage compensation stage under the driving timing shown in FIG. 2;
  • FIG. 6 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase under the driving timing shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, and a light-emitting device OLED. It can be an organic light emitting diode. That is, the embodiment of the present application adopts the pixel driving circuit of the 3T2C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and uses fewer components, the structure is simple and stable, and the cost is saved.
  • the first transistor T1 in the pixel driving circuit is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first node g
  • the source of the first transistor T1 is electrically connected to the power supply voltage Vdd
  • the drain of the first transistor T1 is electrically connected to the second node s.
  • the gate of the second transistor T2 is electrically connected to the first control signal S1
  • the source of the second transistor T2 is electrically connected to the data signal D
  • the drain of the second transistor T2 is electrically connected to the first node g.
  • the gate of the third transistor T3 is electrically connected to the scan signal G
  • the source of the third transistor T3 is electrically connected to the second control signal S2
  • the drain of the third transistor T3 is electrically connected to the third node a.
  • the first terminal of the first capacitor C1 is electrically connected to the first node g, and the second terminal of the first capacitor C1 is electrically connected to the third node a.
  • the first terminal of the second capacitor C2 is electrically connected to the second node s, and the second terminal of the second capacitor C2 is electrically connected to the third node a.
  • the anode terminal of the light emitting device OLED is electrically connected to the second node s, and the cathode terminal of the light emitting device OLED is electrically connected to the ground terminal.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application.
  • the combination of the first control signal S1, the second control signal S2, the scan signal G, and the data signal D corresponds to the initialization phase t1, the threshold voltage detection phase t2, the threshold voltage compensation phase t3, and the light emitting phase t4.
  • the data signal D includes a reference low potential Vref and a display high potential Vdata.
  • the first control signal S1 is at a low level
  • the second control signal S2 is changed from a high level Vgh to a low level Vgl
  • the scan signal G is at a high level
  • the data signal D is a reference low level Vref .
  • the first control signal S1 is at a high level
  • the second control signal S2 is at a low level
  • the scan signal G is at a low level
  • the data signal D is at a reference low level Vref.
  • the first control signal S1 is at a high level
  • the second control signal S2 is at a low level
  • the scan signal G is at a low level
  • the data signal D is a high level Vdata.
  • the first control signal S1 is at a low potential
  • the second control signal S2 is at a low potential
  • the scan signal G is at a low potential
  • the data signal D is a reference low potential Vref.
  • FIG. 3 is a schematic diagram of a path of the pixel driving circuit provided by the application embodiment in the initialization phase in the driving sequence shown in FIG. 2.
  • the first control signal S1 is at a low potential
  • the second transistor T2 is turned off
  • the reference low potential Vref of the data signal D fails to be output to the first node g.
  • the scan signal G is at a high potential
  • the third transistor T3 is turned on
  • the second control signal S2 is output to the third node a.
  • the second control signal S2 changes from a high potential Vgh to a low potential Vgl
  • the third node a is electrically connected to the second end of the first capacitor C1 and the second end of the second capacitor C2, that is, The potential of the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 is changed from a high potential to a low potential. Therefore, due to the capacitive coupling effect, the potential of the first terminal of the first capacitor C1 is also correspondingly pulled down, and the potential of the first terminal of the second capacitor C2 is also correspondingly pulled down.
  • the first end of the first capacitor C1 is electrically connected to the first node g, and the first end of the second capacitor C2 is electrically connected to the second node s. Therefore, the potential of the first node g is also lowered accordingly, and the second node The potential of s is also pulled down accordingly. At this time, the first transistor T1 is turned off.
  • FIG. 4 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage detection phase in the driving sequence shown in FIG. 2.
  • the scan signal G is at a low level
  • the third transistor T3 is turned off
  • the low level of the second control signal S2 fails to be output to the third node a.
  • the first control signal S1 is at a high potential
  • the second transistor T2 is turned on
  • the reference low potential Vref of the data signal D is output to the first node g.
  • the reference low potential Vref of the data signal D needs to be set to a The potential at which a transistor T1 is turned on. That is, the first transistor T1 is turned on, and the power supply voltage Vdd charges the first transistor T1 until the first transistor T1 is turned off.
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage compensation stage under the driving sequence shown in FIG. 2.
  • the scan signal G is at a low level
  • the third transistor T3 is turned off
  • the low level of the second control signal S2 fails to be output to the third node a.
  • the first control signal S1 is at a high potential
  • the second transistor T2 is turned on
  • the display high potential Vdata of the data signal D is output to the first node g. Due to the capacitive coupling effect, the potential of the second node s also changes accordingly.
  • FIG. 6 is a schematic diagram of the light-emitting phase of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal S1 is at a low potential
  • the scanning signal G is at a high potential
  • the second transistor T2 is turned off
  • the third transistor T3 is turned off. Due to the storage effect of the first capacitor C1 and the second capacitor C2, the voltage difference between the potential of the first node g and the potential of the second node s remains unchanged.
  • I OLED 1/2Cox( ⁇ W/L)(Vgs1-Vth) 2 , where I OLED is the current flowing through the light-emitting device OLED, ⁇ is the carrier mobility of the first transistor T1, W and L are the first The width and length of the channel of the transistor T1, Vgs1 is the voltage difference between the gate and the drain of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.
  • the voltage difference between the gate and the drain of the first transistor T1 is equal to the voltage difference between the potential of the first node g and the potential of the second node s.
  • V gs Vdata-Vref+Vth- ⁇ V, into the above formula, we have:
  • I OLED 1/2Cox( ⁇ W/L)(Vdata-Vref+Vth- ⁇ V-Vth) 2
  • the current of the light-emitting device OLED has nothing to do with the threshold voltage of the first transistor T1, and the compensation function is realized.
  • the light emitting device OLED emits light, and the current flowing through the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1.
  • the embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • the pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application use a pixel drive circuit with a 3T2C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种像素驱动电路及显示面板，采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管（T1）的阈值电压（Vth）进行有效补偿，像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
 背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示器面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此，OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，不利于高PPI(Pixels Per Inch，像素密度)显示面板的设计。
 技术问题
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积的技术问题。
 技术解决方案
本申请实施例提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于电源电压，所述第一晶体管的漏极电性连接于第二节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于扫描信号，所述第三晶体管的源极电性连接于所述第二控制信号，所述第三晶体管的漏极电性连接于第三节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第三节点；
所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端电性连接于所述第三节点；
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于接地端；
流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述扫描信号以及所述数据信号相组合先后对应于初始化阶段、阈值电压检测阶段、阈值电压补偿阶段以及发光阶段；所述数据信号包括参考低电位以及显示高电位。
在本申请所述的像素驱动电路中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号由高电位转为低电位，所述扫描信号为高电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，在所述阈值电压检测阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，在所述阈值电压补偿阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述显示高电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
本申请实施例还提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于电源电压，所述第一晶体管的漏极电性连接于第二节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于扫描信号，所述第三晶体管的源极电性连接于所述第二控制信号，所述第三晶体管的漏极电性连接于第三节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第三节点；
所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端电性连接于所述第三节点；
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于接地端。
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述扫描信号以及所述数据信号相组合先后对应于初始化阶段、阈值电压检测阶段、阈值电压补偿阶段以及发光阶段；所述数据信号包括参考低电位以及显示高电位。
在本申请所述的像素驱动电路中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号由高电位转为低电位，所述扫描信号为高电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，在所述阈值电压检测阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，在所述阈值电压补偿阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述显示高电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的像素驱动电路中，所述发光器件为有机发光二极管。
本申请实施例还提供一种显示面板，其包括像素驱动电路，所述像素电路包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于电源电压，所述第一晶体管的漏极电性连接于第二节点；
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
所述第三晶体管的栅极电性连接于扫描信号，所述第三晶体管的源极电性连接于所述第二控制信号，所述第三晶体管的漏极电性连接于第三节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第三节点；
所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端电性连接于所述第三节点；
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于接地端。
在本申请所述的显示面板中，所述第一控制信号、所述第二控制信号、所述扫描信号以及所述数据信号相组合先后对应于初始化阶段、阈值电压检测阶段、阈值电压补偿阶段以及发光阶段；所述数据信号包括参考低电位以及显示高电位。
在本申请所述的显示面板中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的显示面板中，所述发光器件为有机发光二极管。
 有益效果
本申请实施例提供的像素驱动电路及显示面板，采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的时序图；
图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的初始化阶段的通路示意图；
图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压检测阶段的通路示意图；
图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压补偿阶段的通路示意图；
图6为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第一电容C1、第二电容C2以及发光器件OLED，发光器件OLED可以为有机发光二极管。也即，本申请实施例采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。该像素驱动电路中的第一晶体管T1为驱动晶体管。
其中，第一晶体管T1的栅极电性连接于第一节点g，第一晶体管T1的源极电性连接于电源电压Vdd，第一晶体管T1的漏极电性连接于第二节点s。第二晶体管T2的栅极电性连接于第一控制信号S1，第二晶体管T2的源极电性连接于数据信号D，第二晶体管T2的漏极电性连接于第一节点g。第三晶体管T3的栅极电性连接于扫描信号G，第三晶体管T3的源极电性连接于第二控制信号S2，第三晶体管T3的漏极电性连接于第三节点a。第一电容C1的第一端电性连接于第一节点g，第一电容C1的第二端电性连接于第三节点a。第二电容C2的第一端电性连接于第二节点s，第二电容C2的第二端电性连接于第三节点a。发光器件OLED的阳极端电性连接于第二节点s，发光器件OLED的阴极端电性连接于接地端。
在一些实施例中，第一晶体管T1、第二晶体管T2以及第三晶体管T3均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
请参阅图2，图2为本申请实施例提供的像素驱动电路的时序图。如图2所示，第一控制信号S1、第二控制信号S2、扫描信号G以及数据信号D相组合先后对应于初始化阶段t1、阈值电压检测阶段t2、阈值电压补偿阶段t3以及发光阶段t4。其中，数据信号D包括参考低电位Vref以及显示高电位Vdata。
在一些实施例中，在初始化阶段t1，第一控制信号S1为低电位，第二控制信号S2由高电位Vgh转为低电位Vgl，扫描信号G为高电位，数据信号D为参考低电位Vref。
在一些实施例中，在阈值电压检测阶段t2，第一控制信号S1为高电位，第二控制信号S2为低电位，扫描信号G为低电位，数据信号D为参考低电位Vref。
在一些实施例中，在阈值电压补偿阶段t3，第一控制信号S1为高电位，第二控制信号S2为低电位，扫描信号G为低电位，数据信号D为显示高电位Vdata。
在一些实施例中，在发光阶段t4，第一控制信号S1为低电位，第二控制信号S2为低电位，扫描信号G为低电位，数据信号D为参考低电位Vref。
具体的，请参阅图3，图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的初始化阶段的通路示意图。首先，结合图2、图3所示，在初始化阶段t1，第一控制信号S1为低电位，第二晶体管T2关闭，数据信号D的参考低电位Vref未能输出至第一节点g。扫描信号G为高电位，第三晶体管T3打开，第二控制信号S2输出至第三节点a。与此同时，第二控制信号S2由高电位Vgh转为低电位Vgl，且第三节点a均与第一电容C1的第二端以及第二电容C2的第二端电性连接，也即，第一电容C1的第二端和第二电容C2的第二端的电位由高电位转为低电位。因此，由于电容耦合效应，第一电容C1的第一端的电位也相应拉低，第二电容C2的第一端的电位也相应拉低。第一电容C1的第一端与第一节点g电性连接，第二电容C2的第一端与第二节点s电性连接，因此，第一节点g的电位也相应拉低，第二节点s的电位也相应拉低。此时，第一晶体管T1关闭。
在该初始化阶段t1，第一节点g的电位和第二节点s的电位可以根据以下公式进行设置：V g=（Vgh-Vgl）（C1+Cpara）/C1，V s=（Vgh-Vgl）（C2+Coled）/C2，其中，V g为第一节点g的电位，V s为第二节点s的电位，Vgh为第二控制信号S2的高电位，Vgl为第二控制信号S2的低电位，Cpara为第一晶体管T1的栅极和漏极之间的寄生电容，Coled为发光器件OLED的电容。
接着，请参阅图4，图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压检测阶段的通路示意图。结合图2、图4所示，在阈值电压检测阶段t2，扫描信号G为低电位，第三晶体管T3关闭，第二控制信号S2的低电位未能输出至第三节点a。第一控制信号S1为高电位，第二晶体管T2打开，数据信号D的参考低电位Vref输出至第一节点g，需要说明的是，此时数据信号D的参考低电位Vref需设置成让第一晶体管T1打开的电位。也即，第一晶体管T1打开，电源电压Vdd对第一晶体管T1充电，直至第一晶体管T1关闭。
在该阈值电压检测阶段t2，第一节点g的电位和第二节点s的电位可以根据以下公式进行设置：V g=Vref，V s=Vref-Vth，其中，V g为第一节点g的电位，V s为第二节点s的电位，Vref为数据信号D的参考低电位Vref，Vth为第一晶体管T1的阈值电压。
随后，请参阅图5，图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压补偿阶段的通路示意图。结合图2、图5所示，在阈值电压补偿阶段t3，扫描信号G为低电位，第三晶体管T3关闭，第二控制信号S2的低电位未能输出至第三节点a。第一控制信号S1为高电位，第二晶体管T2打开，数据信号D的显示高电位Vdata输出至第一节点g。由于电容耦合效应，第二节点s的电位也相应发生变化。
在该阈值电压获取阶段，第一节点g的电位和第二节点s的电位可以根据以下公式进行设置：V g=Vdata，V s=Vref-Vth+ΔV，其中，V g为第一节点g的电位，V s为第二节点s的电位，Vdata为数据信号D的显示高电位Vdata，Vth为第一晶体管T1的阈值电压，ΔV为显示高电位Vdata对第二节点s的电位所产生的影响。
最后，请参阅图6，图6为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。结合图2、图6所示，在发光阶段t4，第一控制信号S1为低电位，扫描信号G为高电位，第二晶体管T2关闭，第三晶体管T3关闭。由于第一电容C1和第二电容C2的存储作用，第一节点g的电位与第二节点s的电位之间的压差保持不变。
在该发光阶段t4，第一节点g与第二节点s之间的压差可根据以下公式获得：V gs=Vdata-Vref+Vth-ΔV，其中，V gs为第一节点g的电位与第二节点s的电位之间的压差，Vdata为数据信号D的显示高电位Vdata，Vref为数据信号D的参考低电位Vref，Vth为第一晶体管T1的阈值电压，ΔV为显示高电位Vdata对第二节点s的电位所产生的影响。
进一步地，计算流经发光器件OLED的电流的公式为：
I OLED＝1/2Cox(μW/L)(Vgs1－Vth) 2，其中I OLED为流经发光器件OLED的电流，μ为第一晶体管T1的载流子迁移率，W和L分别为第一晶体管T1的沟道的宽度和长度，Vgs1为第一晶体管T1的栅极与漏极极之间的压差、Vth为第一晶体管T1的阈值电压。在本申请实施例中，第一晶体管T1的栅极与漏极极之间的压差等于第一节点g的电位与第二节点s的电位之间的压差。将第一节点g的电位与第二节点s的电位之间的压差V gs=Vdata-Vref+Vth-ΔV代入上式，即有：
I OLED＝1/2Cox(μW/L)(Vdata-Vref+Vth-ΔV-Vth) 2
＝1/2Cox(μW/L)(Vdata-Vref-ΔV) 2
由此可见，发光器件OLED的电流与第一晶体管T1的阈值电压无关，实现了补偿功能。发光器件OLED发光，且流经发光器件OLED的电流与第一晶体管T1的阈值电压无关。
本身申请实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。
本申请实施例提供的像素驱动电路及显示面板，采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于电源电压，所述第一晶体管的漏极电性连接于第二节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于扫描信号，所述第三晶体管的源极电性连接于所述第二控制信号，所述第三晶体管的漏极电性连接于第三节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第三节点；
    所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端电性连接于所述第三节点；
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于接地端；
    流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述扫描信号以及所述数据信号相组合先后对应于初始化阶段、阈值电压检测阶段、阈值电压补偿阶段以及发光阶段；所述数据信号包括参考低电位以及显示高电位。
  3. 根据权利要求2所述的像素驱动电路，其中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号由高电位转为低电位，所述扫描信号为高电位，所述数据信号为所述参考低电位。
  4. 根据权利要求2所述的像素驱动电路，其中，在所述阈值电压检测阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
  5. 根据权利要求2所述的像素驱动电路，其中，在所述阈值电压补偿阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述显示高电位。
  6. 根据权利要求2所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  8. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于电源电压，所述第一晶体管的漏极电性连接于第二节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于扫描信号，所述第三晶体管的源极电性连接于所述第二控制信号，所述第三晶体管的漏极电性连接于第三节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第三节点；
    所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端电性连接于所述第三节点；
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于接地端。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述扫描信号以及所述数据信号相组合先后对应于初始化阶段、阈值电压检测阶段、阈值电压补偿阶段以及发光阶段；所述数据信号包括参考低电位以及显示高电位。
  10. 根据权利要求9所述的像素驱动电路，其中，在所述初始化阶段，所述第一控制信号为低电位，所述第二控制信号由高电位转为低电位，所述扫描信号为高电位，所述数据信号为所述参考低电位。
  11. 根据权利要求9所述的像素驱动电路，其中，在所述阈值电压检测阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
  12. 根据权利要求9所述的像素驱动电路，其中，在所述阈值电压补偿阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述显示高电位。
  13. 根据权利要求9所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述扫描信号为低电位，所述数据信号为所述参考低电位。
  14. 根据权利要求8所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  15. 根据权利要求8所述的像素驱动电路，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  16. 根据权利要求8所述的像素驱动电路，其中，所述发光器件为有机发光二极管。
  17. 一种显示面板，其包括像素驱动电路，所述像素电路包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于电源电压，所述第一晶体管的漏极电性连接于第二节点；
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；
    所述第三晶体管的栅极电性连接于扫描信号，所述第三晶体管的源极电性连接于所述第二控制信号，所述第三晶体管的漏极电性连接于第三节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第三节点；
    所述第二电容的第一端电性连接于所述第二节点，所述第二电容的第二端电性连接于所述第三节点；
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于接地端。
  18. 根据权利要求17所述的显示面板，其中，所述第一控制信号、所述第二控制信号、所述扫描信号以及所述数据信号相组合先后对应于初始化阶段、阈值电压检测阶段、阈值电压补偿阶段以及发光阶段；所述数据信号包括参考低电位以及显示高电位。
  19. 根据权利要求17所述的显示面板，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  20. 根据权利要求17所述的显示面板，其中，所述发光器件为有机发光二极管。
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