WO2020199300A1 - Panneau d'affichage, procédé de fabrication correspondant et dispositif d'affichage - Google Patents

Panneau d'affichage, procédé de fabrication correspondant et dispositif d'affichage Download PDF

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Publication number
WO2020199300A1
WO2020199300A1 PCT/CN2019/085505 CN2019085505W WO2020199300A1 WO 2020199300 A1 WO2020199300 A1 WO 2020199300A1 CN 2019085505 W CN2019085505 W CN 2019085505W WO 2020199300 A1 WO2020199300 A1 WO 2020199300A1
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WO
WIPO (PCT)
Prior art keywords
line
substrate
layer
wire layer
power connection
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Application number
PCT/CN2019/085505
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English (en)
Chinese (zh)
Inventor
魏锋
李金川
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020199300A1 publication Critical patent/WO2020199300A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • This application relates to the technical field of display panels, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • Narrow bezels can make products more fashionable, which is the most intuitive function.
  • Display products with a narrow frame design have more advantages in the use of size.
  • the same size (including the outer frame) the narrow frame product screen display area is larger, for notebooks and mobile phones, means a smaller body, larger size.
  • the enhancement of product quality is also meaningful for users who pursue fashion.
  • the narrow frame also makes the picture look cleaner, which has a soft effect on enhancing the charm of the display.
  • the connection between the wire layer of the display device and the driving circuit is realized by the binding area located at the edge of the non-display area, and there is a problem that the binding area occupies the side space of the display device, which is not conducive to achieving narrow border display.
  • the present application provides a display panel, a manufacturing method thereof, and a display device to reduce the frame area of the display device, which is beneficial to realize a narrow frame display.
  • the embodiments of the present application provide a display panel, the display panel includes: a wire layer, the wire layer includes a binding area and a non-binding area; a substrate provided on the wire layer, the substrate is provided with conduction Holes; scan lines, data lines, and power connection lines arranged on the substrate, wherein the scan lines, data lines and power connection lines are connected to the binding area through via holes.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area through via holes.
  • the binding areas are arranged in an array on the wire layer.
  • the display panel further includes a pixel electrode layer, the pixel electrode layer is located on the scan line, the data line and the power connection line, the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a via hole.
  • the display panel further includes an encapsulation layer, the encapsulation layer is located on the side of the wire layer away from the substrate, and the encapsulation layer covers the non-binding area of the wire layer.
  • the display panel further includes a thin film transistor and a flat layer sequentially arranged on the side of the substrate away from the wire layer.
  • the thin film transistor includes a gate electrode and a source/drain electrode. One end of the scan line is connected to the gate electrode, and the other end is connected to the via hole. One end of the data line is connected to the source/drain, the other end is connected to the through hole, one end of the power connection line is connected to the driving voltage input end of the thin film transistor, and the other end is connected to the through hole.
  • the embodiments of the present application also provide a method for manufacturing a display panel.
  • the manufacturing method includes: providing a substrate; making a via hole on the substrate; filling a conductive material in the via hole and forming on the substrate.
  • the wire layer, the wire layer includes a binding area and a non-binding area; on the side of the substrate away from the wire layer, a scan line, a data line and a power connection line are formed, wherein the scan line, the data line and the power connection line are conductive
  • the hole is connected to the binding area.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area through via holes.
  • the binding areas are arranged in an array on the wire layer.
  • the method further includes: coating the entire surface of the scan lines, data lines, and power connection lines to form a pixel electrode layer, wherein,
  • the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a through hole.
  • the method further includes: forming an encapsulation layer on the side of the wire layer away from the substrate, and the encapsulation layer covers the non-conductive layer of the wire layer. Binding area.
  • the step of forming scan lines, data lines, and power connection lines on the side of the substrate away from the wire layer specifically includes: forming a thin film transistor layer, a flat layer, and a thin film transistor layer on the side of the substrate away from the wire layer. It includes a thin film transistor, a scan line, a data line, and a power connection line.
  • the thin film transistor includes a gate, a source, and a drain. One end of the scan line is connected to the gate, the other end is connected to the via hole, and one end of the data line is connected to the The source or drain is connected, the other end is connected to the through hole, one end of the power connection line is connected to the driving voltage input end of the thin film transistor, and the other end is connected to the through hole.
  • the embodiment of the present application provides a display device, which includes a driving circuit and a display panel, wherein the display panel includes: a wire layer, the wire layer includes a binding area and a non-binding area; The substrate on the wire layer, the substrate is provided with a through hole; the scan line, the data line and the power connection line are provided on the substrate, wherein the scan line, the data line and the power connection line are connected to the binding area through the through hole; The driving circuit is connected with the scan line, the data line and the power connection line through the binding area.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area through via holes.
  • the binding areas are arranged in an array on the wire layer.
  • the display panel further includes a pixel electrode layer, the pixel electrode layer is located on the scan line, the data line and the power connection line, the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a via hole.
  • the display panel further includes an encapsulation layer, the encapsulation layer is located on the side of the wire layer away from the substrate, and the encapsulation layer covers the non-binding area of the wire layer.
  • the display panel provided by the present application includes a wire layer and a substrate arranged on the wire layer, as well as scan lines, data lines and power connection lines arranged on the substrate.
  • the layer includes a binding area and a non-binding area.
  • the substrate is provided with vias. The scan lines, data lines and power connection lines are connected to the binding area through the vias.
  • the binding area of the display panel is designed to The non-luminous surface of the substrate can reduce the frame area of the display device, which is beneficial to realize a narrow frame display.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the structure of the wire layer in FIG. 1;
  • FIG. 3 is a schematic diagram of another cross-sectional structure of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the structure of the wire layer in FIG. 3;
  • FIG. 5 is another schematic diagram of the structure of the wire layer in FIG. 3;
  • FIG. 6 is a schematic side view of the structure of the display panel in FIG. 3;
  • FIG. 7 is a schematic bottom view of the structure of the display panel in FIG. 3;
  • FIG. 8 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the present application.
  • the present application provides a display panel.
  • the binding area located at the edge of the non-display area in the prior art is designed to the non-luminous surface of the substrate to solve the problem that the binding area occupies the side of the display device.
  • the space issue is conducive to the realization of narrow border display.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the structure of the wire layer 11 in FIG.
  • the display panel 10 includes a wire layer 11 and a substrate 12 arranged on the wire layer 11, and a scan line 13, a data line 14 and a power connection line 15 arranged on the substrate 12.
  • the wire layer 11 includes a binding area 111 and a non-binding area 112
  • the substrate 12 is provided with vias 121
  • the scan line 13, the data line 14 and the power connection line 15 are connected to the wire plate 11 through the via 121 Binding area 111.
  • the frame area of the display device can be reduced, which is beneficial to realize narrow frame display.
  • FIG. 3 is another cross-sectional structure diagram of the display panel provided by the embodiment of the present application
  • FIG. 4 is a structure diagram of the wire layer 201 in FIG. 3.
  • the display panel 200 includes a wire layer 201 and a substrate 202 disposed on the wire layer 201, and a scan line 203, a data line 204 and a power connection line 205 disposed on the substrate 202.
  • the wire layer 201 includes a bonding area 2011 and a non-bonding area 2012
  • the substrate 202 is provided with vias 2021
  • the scan lines 203, data lines 204, and power connection lines 205 are connected to the wire board 201 through the vias 2021. Binding zone 2011.
  • the display panel 200 is a top-emitting display panel.
  • the substrate 202 has a light-emitting surface and a non-light-emitting surface away from the light-emitting surface.
  • the wire layer 201 is disposed on the non-light-emitting surface of the substrate 202.
  • the gate lines 203, The data line 204 and the power connection line 205 are arranged on the light-emitting surface of the substrate 202.
  • the substrate 202 may be a glass substrate or a rigid resin substrate, and may also be a flexible substrate used to prepare a flexible display panel.
  • the via hole 2021 is filled with a material with low resistivity, such as indium tin oxide, aluminum, copper, silver, etc., for realizing the conductive connection between the light-emitting surface and the non-light-emitting surface.
  • the wire layer 201 includes a number of wire lines (not shown in the figure), one end of the wire line is at the position of the via 2021, and the other end is at the position of the binding area 2012. The wire line is used to realize the via 2021 and the binding The connection of the designated area 2012.
  • the gate line 203, the data line 204, and the power connection line 205 are first connected to the wire line via the via 2021, and then connected to the binding area 2012 via the wire line.
  • the bonding area 2012 is used to connect with a driving circuit (not shown in the figure), and transmit driving voltage signals to the scan line 203, the data line 204, and the power connection line 205.
  • a thin film transistor 206, a flat layer 207, a pixel anode 208, a pixel light emitting layer 209, and a pixel cathode 210 are sequentially arranged on the light emitting surface of the substrate 202.
  • the thin film transistor 206 includes a gate 2061, a source/drain 2062. One end of the scan line 203 is connected to the gate 2061, and the other end is connected to the via 2021.
  • the layer structure between the gate 2061 and the substrate 202 A via is provided, and the scan line 203 realizes conduction between the gate 2061 and the via 2021 through the via; one end of the data line 204 is connected to the source/drain 2062, and the other end is connected to the via 2021 If there is another layer structure between the source/drain 2062 and the substrate 202, a via is provided on the layer structure between the source/drain 2062 and the substrate 202, and the data line 204 realizes the source/drain through the via.
  • the layer structure between the driving voltage output terminal 2064 of the thin film transistor 206 and the pixel anode 208 is provided with a via, and the via is filled with conductive material, which can realize the driving voltage output terminal 2064 of the thin film transistor and the pixel anode 208
  • the conduction between 208 is to transmit the driving voltage received at the driving voltage input terminal 2063 to the pixel anode 208 and drive the pixel light-emitting layer 209 to emit light.
  • each scan line 203, data line 204, or power connection line 205 corresponds to a through hole 2021, that is, the number of through holes 2021 is not less than the total of the scan line 203, data line 204, and power connection line 205. Quantity.
  • the connection between the scan line 203, the data line 204, and the power connection line 205 and the via 2021 follows the principle of proximity, that is, the position of the via 2021 on the substrate 202 corresponds to the setting position of the three, so that The scan line 203, the data line 204, and the power connection line 205 can be connected to the via 2021 by a shorter line, which is beneficial to reduce the voltage drop.
  • the scan line 203, the data line 204 and the power connection line 205 are respectively connected to the closest bonding area 2011 through the via 2021.
  • the number of binding areas 2011 is related to the size of the display panel 200.
  • the display panel 200 includes a pixel electrode layer, the pixel electrode layer is located on the scan line 203, the data line 204 and the power connection line 205, the pixel electrode layer is a pixel cathode 210 formed by coating the entire surface.
  • the edge of the cathode 210 is connected to the wire layer 201 through the via 2021.
  • electrode traces 211 are formed on the side edge surface of the layer structure between the pixel cathode 210 and the substrate 202 for connecting the pixel cathode 210 to the through hole 2021 of the substrate 202. It is helpful to further reduce the border area of the display panel.
  • the display panel 200 may further include an encapsulation layer 212, which is disposed on the side of the wire layer 201 away from the substrate 202
  • the encapsulation layer 212 covers the non-bonding area 2012 of the wire layer 201 and exposes the bonding area 2011 of the wire layer 201 for connection with the driving circuit.
  • an encapsulation layer 212 may also be provided on the light-emitting surface of the substrate 202 to prevent water and oxygen from entering from the light-emitting surface to damage the display panel.
  • the encapsulation layer 212 may be a single layer or a stacked layer of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., or may be formed by alternately stacking inorganic layers and organic layers.
  • the display panel provided by the embodiment of the present application can reduce the frame area of the display device by designing the binding area of the display panel to the non-luminous surface of the substrate, which is beneficial to realize narrow frame display.
  • Setting multiple bonding areas can shorten the path length of the scan lines, data lines, and power connection lines connected to the bonding area through the via holes, thereby avoiding voltage drop problems caused by excessively long paths.
  • FIG. 8 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the present application.
  • the manufacturing method of the display panel includes the following steps:
  • the substrate may be a glass substrate or a rigid resin substrate, and may also be a flexible substrate used to prepare a flexible display panel.
  • a via hole is made on the substrate by means of laser etching, wherein the diameter of the via hole is 100-300 um.
  • S83 Fill a conductive material in the via hole, and form a wire layer on the substrate.
  • the wire layer includes a binding area and a non-binding area.
  • the display panel is a top-emitting display panel
  • the substrate has a light-emitting surface and a non-light-emitting surface facing away from the light-emitting surface.
  • the wire layer is made by sputtering, coating, developing, etching and other processes, and at the same time, materials with low resistivity such as indium tin oxide, aluminum, Copper, silver, etc., to realize the conduction connection between the light-emitting surface and the non-light-emitting surface.
  • the bonding area of the wire layer is used to connect with the driving circuit.
  • the wire layer includes a plurality of wire lines, one end of the wire line is at the position of the via hole and the other end is at the position of the binding area, and the wire line is used to realize the connection between the via hole and the binding area.
  • the side of the substrate away from the wire layer is the light-emitting surface, and gate lines, data lines and power connection lines are formed on the light-emitting surface.
  • a via is made in the layer structure between the source, drain and the substrate, and the data line realizes the conduction between the source, drain and the via hole through the via; one end of the power connection line is connected to the film The drive voltage input end of the transistor is connected, and the other end is connected to the through hole.
  • the layer structure between the drive voltage input end of the thin film transistor and the substrate A through hole is formed on the upper surface, and the power connection line realizes the conduction between the driving voltage input end of the thin film transistor and the through hole through the through hole.
  • each scan line, data line or power connection line corresponds to a via hole, that is, the number of via holes is not less than the total number of scan lines, data lines and power connection lines.
  • the connection of the scan lines, data lines, and power connection lines with the vias follows the principle of proximity, that is, the location of the vias on the substrate corresponds to the placement of these three, so that the scan lines, data lines and The three power connection lines can be connected to the vias with shorter lines, which is beneficial to reduce the voltage drop.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area via via holes.
  • the number of binding areas is related to the size of the display panel. The larger the size of the display panel, the greater the number of binding areas.
  • multiple binding areas can be arranged in an array on the wire layer or located on the wire layer. The surrounding edge position. In this way, the path length of the via hole connected to the bonding area through the wire line can be shortened, so as to avoid the voltage drop problem caused by the excessively long path, thereby avoiding obvious uneven light emission of the display panel.
  • S85 Coating the entire surface of the scan line, data line, and power connection line to form a pixel electrode layer, where the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through the via hole.
  • the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a via hole.
  • S85 specifically includes:
  • An electrode trace is formed on the side edge surface of the layer structure between the pixel cathode and the substrate.
  • the electrode trace is used to lap the pixel cathode to the through hole of the substrate, which is beneficial to further reduce the frame area of the display panel .
  • the encapsulation layer may be a single layer or a stack of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., or may be formed by alternately stacking inorganic layers and organic layers.
  • the encapsulation layer covers the non-binding area of the wire layer to prevent water and oxygen from intruding through the via holes to damage the display panel. At the same time, the encapsulation layer does not cover the bonding area, so that the bonding area of the wire layer is exposed and can be connected to the driving circuit.
  • an encapsulation layer can also be formed on the light-emitting surface of the substrate to prevent water and oxygen from entering from the light-emitting surface and damaging the display panel.
  • the manufacturing method of the display panel provided by the embodiments of the present application can reduce the frame area of the display device by designing the binding area of the display panel to the non-luminous surface of the substrate, which is beneficial to realize narrow frame display.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 91 includes a driving circuit and the display panel 92 of any of the above embodiments.
  • the display panel 92 includes a wire layer and a substrate arranged on the wire layer, as well as scan lines, data lines and power connection lines arranged on the substrate.
  • the wire layer includes a binding area and a non-binding area
  • the substrate is provided with via holes
  • the scan lines, data lines and power connection wires are connected to the binding area of the wire board through the via holes.
  • the driving circuit is connected with the scan line, the data line and the power connection line through the binding area.
  • the display device provided in this embodiment can reduce the frame area of the display device by designing the binding area of the display panel to the non-luminous surface of the substrate, which is beneficial to realize narrow frame display.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

L'invention concerne un panneau d'affichage (10, 200, 92) et un procédé de fabrication correspondant, ainsi qu'un dispositif d'affichage (91). Le panneau d'affichage (10, 200, 92) comprend : une couche de fil (11, 201), comprenant une région de liaison (111, 2011) et une région de non-liaison (112, 2012) ; un substrat (12, 202) situé sur la couche de fil (11, 201) et comprenant un trou traversant (121, 2021) ; et une ligne de balayage (13, 203), une ligne de données (14, 204) et une ligne de connexion d'alimentation électrique (15, 205) situées sur le substrat (12, 202), la ligne de balayage (13, 203), la ligne de données (14, 204) et la ligne de connexion d'alimentation électrique (15, 205) étant reliées à la région de liaison (111, 2011) au moyen du trou traversant (121, 2021).
PCT/CN2019/085505 2019-04-02 2019-05-05 Panneau d'affichage, procédé de fabrication correspondant et dispositif d'affichage WO2020199300A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910260187.1 2019-04-02
CN201910260187.1A CN109872637B (zh) 2019-04-02 2019-04-02 一种显示面板及其制作方法、显示装置

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WO2020199300A1 true WO2020199300A1 (fr) 2020-10-08

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CN112599532A (zh) * 2019-10-01 2021-04-02 财团法人工业技术研究院 电子装置
CN111584562A (zh) 2020-05-08 2020-08-25 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN111724742B (zh) * 2020-06-11 2022-02-22 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法、显示装置
CN114049843A (zh) * 2021-11-17 2022-02-15 合肥维信诺科技有限公司 显示模组及显示装置

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