WO2020188678A1 - System for assembling semiconductor device, method for assembling semiconductor device, and program for assembling semiconductor device - Google Patents

System for assembling semiconductor device, method for assembling semiconductor device, and program for assembling semiconductor device Download PDF

Info

Publication number
WO2020188678A1
WO2020188678A1 PCT/JP2019/011097 JP2019011097W WO2020188678A1 WO 2020188678 A1 WO2020188678 A1 WO 2020188678A1 JP 2019011097 W JP2019011097 W JP 2019011097W WO 2020188678 A1 WO2020188678 A1 WO 2020188678A1
Authority
WO
WIPO (PCT)
Prior art keywords
verification
semiconductor device
inspection
assembly
unit
Prior art date
Application number
PCT/JP2019/011097
Other languages
French (fr)
Japanese (ja)
Inventor
悠 田井
Original Assignee
キヤノンマシナリー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by キヤノンマシナリー株式会社 filed Critical キヤノンマシナリー株式会社
Priority to JP2019515547A priority Critical patent/JP6621964B1/en
Priority to PCT/JP2019/011097 priority patent/WO2020188678A1/en
Publication of WO2020188678A1 publication Critical patent/WO2020188678A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations

Definitions

  • the present invention relates to a semiconductor device assembly system, a semiconductor device assembly method, and a semiconductor device assembly program.
  • a semiconductor device may have a process of being assembled by mounting an individual piece on a supplied member. For example, a wafer in which a large number of elements are built together is diced and separated into a semiconductor die (a silicon substrate chip in which an electronic circuit is built), which is a lead frame or a lead frame one by one. There is a dicing process of bonding to a predetermined position of a supplied member such as a substrate. A die bonder (bonding device) as in Patent Document 1 is used for this die bonding.
  • the bonding apparatus includes a bonding arm (not shown) having a collet 103 for adsorbing the semiconductor die 101 of the supply unit 102, and an inspection mechanism (not shown) for inspecting the semiconductor die 101 of the supply unit 102.
  • a confirmation camera (not shown) for observing the island portion 105 of the lead frame 104 at the bonding position is provided.
  • the supply unit 102 includes a semiconductor wafer 106 (see FIG. 5), and the semiconductor wafer 106 is divided into a large number of dies 101.
  • the wafer 106 is attached to an adhesive sheet (dicing sheet), and the dicing sheet is held by an annular frame. Then, the wafer 106 on the dicing sheet is individualized to form the die 101 by using a circular blade (dicing saw) or the like. Further, the bonding arm holding the collet 103 can be moved between the pickup position and the bonding position via the transport mechanism.
  • the die moves to the pickup position (step S101), and the die is inspected by an inspection mechanism (for example, visual inspection or energization inspection) (step S102). ), If the inspection result is good (if the inspection is passed) (step S103), the die is picked up (step S104) and bonded to a predetermined position.
  • an inspection mechanism for example, visual inspection or energization inspection
  • step S105 the device is stopped and the user is called (with an error) (step S105) to prompt the die to be reconfirmed (verify).
  • step S106 The user performs verification (step S106), picks up the die if it is a producible die (step S107), and bonds it to a predetermined position (step S104).
  • step S107 the die is moved to the next die without being picked up (step S101). These operations are repeated (step S108).
  • the equipment is stopped each time and the equipment is put into a standby state until the verification is completed, there is a problem that the production is stopped and the production efficiency is deteriorated. In particular, when a certain number of defective products exist, the frequency of stopping the device increases and the production efficiency deteriorates.
  • Patent Document 2 As a device for shortening the downtime of an electronic component assembly device.
  • Patent Document 2 in an apparatus for inserting an electronic component into a printed circuit board, it is inspected whether the insertion is performed normally, and if an insertion error occurs, the electronic component is skipped without stopping the apparatus, and the following It is described that the insertion operation of the electronic component is continued.
  • the die bonding process there may be a die that is not suitable for production in the wafer, and if a die that is not suitable for production is used for assembling a semiconductor device, the quality of the product will be inferior. For this reason, it is important to properly verify the dies that have not passed the inspection.
  • various information such as wafer information, die bonder information, inspection status information of the inspection mechanism, inspection result information by the inspection mechanism, and die information other than inspection by the inspection mechanism. Is required.
  • Patent Document 2 The one described in Patent Document 2 is for inspecting whether or not an electronic component is inserted into a printed circuit board, and if it is not inserted, the user performs a reinsertion operation. That is, the method described in Patent Document 2 is for determining the quality of the state after inserting the electronic component into the printed circuit board, and there is no information necessary for verification as described above. Therefore, in Patent Document 2, it is not possible to judge the quality of the electronic component itself, and even if electronic components that are not suitable for production are mixed, they may be used for assembly and the quality of the product may deteriorate. There is.
  • the present invention aims to improve productivity and to provide a semiconductor device assembly system, a semiconductor device assembly method, and a semiconductor device assembly program capable of assembling high-quality semiconductor devices. Is what you do.
  • the semiconductor device assembly system of the present invention is a semiconductor device assembly system including an assembly device for assembling a semiconductor device using individual pieces inspected by an inspection mechanism, and is re-inspected by inspection by the inspection mechanism.
  • An additional information storage unit for storing additional information required for verification of the required individual piece is provided, and the assembly device of the semiconductor device has additional information of the individual piece required for verification by inspection by an inspection mechanism. Is notified to the additional information storage unit, and the individual piece for which verification is required is not used for assembly at least until the inspection of the individual piece to be inspected next or the end of assembly.
  • the additional information necessary for verification is stored in the additional information storage unit, and the individual pieces that need to be verified are stored until the next individual piece is inspected.
  • the individual pieces that require verification are not used (skipped) for the assembly until the assembly is completed.
  • the user and the verification mechanism can execute the verification at any timing such as during production. That is, even if the inspection result requires verification, the device continues production using the next piece, so that the device can operate without stopping.
  • the user and the verification mechanism can execute the verification based on the information stored in the additional information storage unit, the verification can be appropriately executed.
  • a result recording unit for recording the verification information of each individual body after the verification is executed may be provided.
  • the other semiconductor device assembly system of the present invention is a semiconductor device assembly system including an assembly device for assembling a semiconductor device using individual pieces inspected by the inspection mechanism, and is re-inspected by inspection by the inspection mechanism. It is equipped with a display unit that displays additional information required for verification of the individual pieces that required verification, and the individual pieces that required verification by inspection by the inspection mechanism are at least the individual pieces to be inspected next. It is not used for assembly until the end of body inspection or assembly.
  • the assembly system of another semiconductor device of the present invention additional information of the individual pieces requiring verification is accumulated, and the individual pieces requiring verification are accumulated until the next individual piece is inspected or the individual pieces requiring verification are obtained.
  • the individual pieces that require verification are not used (skipped) for the assembly until the assembly is completed.
  • the user and the verification mechanism can execute the verification at any timing such as during production. That is, even if the inspection result requires verification, the device continues production using the next piece, so that the device can operate without stopping.
  • the user and the verification mechanism can execute the verification based on the information displayed on the display unit, the verification can be appropriately executed.
  • the display unit may include a result input unit for inputting the result of the verification information of the individual body after the verification is executed.
  • the display unit simultaneously displays the information of the individual piece for which verification is required and the verification result input unit, and the verified result of the displayed individual piece is input to the result input unit. Then, the display may be switched to the information of the individual piece that requires the next verification.
  • a data organizing unit for organizing information on individual pieces requiring verification is provided, and the data organizing unit ranks individual pieces requiring verification so that the operating rate of the assembly device is high.
  • the display order of the individual pieces to be displayed on the display unit may be determined based on the ranked information.
  • the data organizing unit ranks individual pieces that need to be verified based on additional information, and determines the display order of the individual pieces to be displayed on the display unit based on the ranked information. It may be.
  • a verification request setting unit for making settings for requesting verification is provided, and when the conditions set in the verification request setting unit are satisfied, a verification request, a warning, and an error stop of the semiconductor device assembly device are stopped. It may be one that does at least one of the above.
  • a pattern recognition unit that recognizes an individual piece generation pattern for which verification is required is provided, and when the generation pattern set in the verification request setting unit is met, a verification request, warning, and semiconductor device are provided. It may perform at least one of the error stop of the assembly device of.
  • a map management unit having map information of a work which is an aggregate of individual pieces is provided, and the map management unit has a verification data holding unit for storing information of individual pieces requiring verification. You may.
  • the additional information includes information on a work that is an aggregate of individual pieces, information on an assembly device of the semiconductor device, information on an inspection state of the inspection mechanism, information on inspection results by the inspection mechanism, and the inspection. It can be any of the individual piece information other than the inspection by the mechanism.
  • the method for assembling a semiconductor device of the present invention is a method for assembling a semiconductor device in which an individual piece is inspected by the assembling device for assembling the semiconductor device and the semiconductor device is assembled using the inspected individual pieces.
  • the inspection is performed, and the additional information necessary for verification of the individual pieces that need to be verified by the inspection is stored, and the assembly device stores the individual pieces that need to be verified at least as follows. It is not used for assembly until the inspection of the individual piece to be inspected or the end of assembly.
  • the semiconductor device assembly program of the present invention is an assembly program for a semiconductor device in which an individual piece is inspected by the assembly device for assembling the semiconductor device and the semiconductor device is assembled to the assembly device using the inspected individual pieces.
  • the step of executing the inspection of the individual pieces and the additional information necessary for the verification of the individual pieces for which the verification which is the re-inspection was required by the inspection is stored, and the assembly device stores the individual pieces that need to be verified. It includes steps in which the body is not used for assembly at least until the next inspection of the individual piece to be inspected or the end of assembly.
  • the semiconductor device assembly system even if the inspection result requires verification, the device continues to be produced using the following individual pieces. It can operate without stopping, and productivity can be improved. Further, since the verification can be executed at any timing, the workability of the user or the like is improved. In addition, since the user and the verification mechanism can appropriately perform verification, it is possible to assemble a high-quality semiconductor device using only producible individual pieces.
  • FIG. 1 shows an assembly system for a semiconductor device according to the first embodiment.
  • the assembly system of the present embodiment is a system for assembling a semiconductor device with an assembly device, and as shown in FIG. 1, a plurality of (for example, 30) assembly devices 1 (1a, 1b, 1c ...)
  • a verification management unit 2 and a map management unit 3 that are networked or electrically connected to the assembly device 1 are provided.
  • the network is, for example, the Internet, an intranet, an extranet, a LAN, a MAN, a WAN, or a combination thereof, and can transmit information between a plurality of points regardless of whether it is wired or wireless.
  • the assembly device 1 can be various devices used for assembling semiconductor devices such as mounters and die bonders.
  • the assembly device 1 is a die bonder that adheres a die (a silicon substrate chip in which an electronic circuit is built) to a supplied member such as a lead frame or a substrate.
  • a die a silicon substrate chip in which an electronic circuit is built
  • a supplied member such as a lead frame or a substrate.
  • the "individual piece” will be described as a die
  • the "work” will be described as a wafer divided into a large number of dies
  • the "supplied member” will be described as a substrate.
  • the die bonder 1 which is an assembly device is provided with an inspection mechanism 4 for inspecting the die.
  • the inspection mechanism 4 can be various inspection mechanisms capable of inspecting the quality of the die, such as visual inspection and energization inspection.
  • the inspection mechanism 4 includes an imaging means (not shown) capable of acquiring an image of the die and an image processing means (not shown) capable of performing image processing based on the acquired image, and the appearance of the die. (For example, the presence or absence of defects such as scratches, cracks, holes, and foreign matter) is to be inspected.
  • the inspection mechanism 4 performs an image-based visual inspection on each die, and the die that passes the inspection is used for assembling the semiconductor device. That is, the collet (not shown) picks up the die that has passed the inspection and mounts it on the substrate.
  • the verification management unit 2 manages information necessary for executing verification of a die that has not passed the inspection by the inspection mechanism 4.
  • the ROM Read Only Memory
  • RAM RandomAccessMemory
  • the ROM stores programs and data executed by the CPU.
  • "verify” means whether or not the die can be produced by re-inspecting the die when the inspection result of the die by the inspection mechanism 4 is not good (when the inspection is not passed). It is to determine (whether or not it can be used for assembling a semiconductor device), and the verification may be performed by the user or by a verification mechanism such as a computer.
  • the verify management unit 2 includes a position identification unit 5, an additional information recording unit 6, a result recording unit 7, and a pattern recognition unit 12.
  • the position specifying unit 5 specifies the position of the die that requires verification, and the additional information storage unit 6 stores additional information required for verification. That is, as a result of performing the die inspection by the inspection mechanism 4, the inspection mechanism 4 is the position identification unit for the die for which the inspection result is not good and it is determined that verification is necessary (the inspection is not passed). 5 stores the position of the die (for example, the position in the X direction and the Y direction), and the additional information storage unit 6 stores additional information necessary for verification.
  • the "die position" may be any information necessary for identifying a unique die on the wafer, and is, for example, the position of the wafer moving mechanism, a map, or other data for specifying the position. It can be information for identifying the die.
  • the additional information is, for example, any one of wafer information, die bonder 1 information, inspection state information of inspection mechanism 4, inspection result information by inspection mechanism 4, and die information other than inspection by inspection mechanism 4. .
  • Wafer information includes, for example, product name (ID), part name (ID), part lot, map data information (product rank including quality information), position (position on wafer, position on tray, assembly). Target position (mount position), etc.
  • the information of the die bonder 1 is, for example, the production recipe name, the production recipe itself or a part thereof, the operator name (ID), the device name (ID), the state of the device (the number of times the tool is used, the temperature, the process conditions), and the like. is there.
  • the inspection state is, for example, an inspection recipe such as lighting, settings related to imaging of a camera, other settings of inspection equipment, parameters of inspection processing, model data / model image, judgment threshold value, and the like.
  • the inspection results are, for example, inspection images, images not used for inspection (for example, images for positioning and other inspections, images for visual confirmation), images of another camera used for visual confirmation, and output of inspection equipment (for image inspection). (Data corresponding to the image), capture of the inspection result screen of the device, inspection time, defect information (judgment, defect classification, image processing characteristics, shape characteristics, brightness characteristics, dimensions, defect area data, defect candidate area data, etc. Extraction area) and so on.
  • the die information other than the inspection by the inspection mechanism 4 is, for example, data of surrounding objects, images and data of another process of the same die, and the like.
  • the inspection information at the time of pickup becomes additional information
  • Map data for example, product rank based on the inspection result in the previous process
  • the result recording unit 7 records the verification information of the die after executing the verification.
  • the information (whether or not the die can be produced) is recorded in the result recording unit 7 of the verification management unit 2.
  • the die bonder 1 picks up the die and bonds it to a predetermined position on the substrate.
  • the pattern recognition unit 12 recognizes the die generation pattern (regularity and relevance) for which verification is required. That is, the pattern recognition unit 12 recognizes whether a plurality of dies for which verification is required are generated in neighboring workpieces, the frequency of occurrence, whether they are generated in a specific region, and the like.
  • the die bonder 1 includes a verify request setting unit 8 and a request unit 9.
  • the verify request setting unit 8 makes settings for requesting and warning the user and the verification mechanism for verification, and for stopping the error of the die bonder 1.
  • Settings for requesting verification can be made by various methods specified by the user. For example, when the number of dies required for verification reaches the number set by the user, when there is a request from the user or the verify management unit 2, the lot end of the wafer, the device error (error of the die bonder 1), and a certain period of time. Every time, etc.
  • a die generation pattern that requires verification may be set.
  • the user can arbitrarily select any of these settings as a criterion for the die bonder 1 to request verification. If the standard for requesting verification is the number of dies that require verification, the user selects this standard and sets the number of dies for executing verification. Further, when the standard for requesting verification is every fixed time, the user selects this standard and sets the standard for a fixed time (for example, 10 minutes).
  • the verify management unit 2 includes a measurement unit for measuring the number of dies to be verified and a timer for measuring at regular time intervals.
  • the pattern recognition unit 13 recognizes the generation pattern of the die that requires verification.
  • the request unit 9 performs at least one of a verification request and a warning, and an error stop of the die bonder 1 when the conditions set in the verify request setting unit 8 are satisfied. For example, when the user sets the verification request setting unit 8 to execute verification when n dies to be verified (n is an arbitrary number of 1 or more) are accumulated, the request unit 9 sets the verification request setting unit 8. When the number of dies to be verified reaches n set in the verify request setting unit 8, it warns that verification is necessary.
  • the warning method may be any method as long as the user can recognize that it should be verified, and may be the alarm function (buzzer, screen display, warning light, lamp) of the die bonder 1 or the verification method.
  • It may be a screen display of a personal computer, a smartphone, a tablet, etc., a lamp, a buzzer, a vibration, or an e-mail sent to a registered e-mail address, which is a part of the management unit 2. It can be done by any or more of these methods.
  • the map management unit 3 has map information of a wafer, which is an aggregate of dies.
  • a ROM Read Only Memory
  • RAM Random Access Memory
  • the map information stores the positions of dies on the wafer and the product ranks including information on the quality of those dies.
  • the map management unit 3 has a map holding unit 10 and a verify data holding unit 11.
  • the map holding unit 10 holds map information indicating the quality of the die at each position.
  • the verify data holding unit 11 holds the information of the verify management unit 2 for each wafer, and stores the die information (position and additional information) that requires verification.
  • the verify data holding unit 11 may write the information of the verify management unit 2 into the map information held by the map holding unit 10.
  • the semiconductor device assembly system of the present embodiment can be realized by installing the semiconductor device assembly program in each of the die bonders 1a, 1b, 1c ..., the verify management unit 2, and the map management unit 3. .. That is, in the semiconductor device assembly program of the present embodiment, in the semiconductor device assembly program in which the die is inspected by the die bonder 1 for assembling the semiconductor device and the semiconductor device is assembled to the die bonder 1 using the inspected die. The steps to perform the inspection, the position of the die that required verification to be re-inspected by the inspection, and the additional information required for verification are stored, and the die bonder assembles the die that requires verification immediately after inspection. It has steps that are not used in.
  • a method of assembling the semiconductor device using the semiconductor device assembly system of the present embodiment in which the program is installed will be described with reference to FIGS. 2 and 3.
  • the basic operations of the die bonders 1a, 1b, 1c ... Are shown in FIG. 2A.
  • the operation of one die bonder 1 (1a) will be described, but each die bonder 1a, 1b, 1c operates independently, and the other die bonders 1b, 1c ... Are the same as those of the die bonder 1a. It is working.
  • the die bonder 1 first requests the map management unit 3 for the map data of the wafer (step S1), and the map management unit 3 transmits the map data to the die bonder 1.
  • step S5 Bonding is performed at a predetermined position.
  • step S5 Bonding is performed at a predetermined position.
  • step S6 the location specifying unit 5 and the additional information storage unit 6 of the verification management unit 2 store the verification information.
  • the die bonder 1 does not use the die for assembly immediately after the inspection, and the die bonder 1 continues production using the next die, so that the die bonder 1 operates without stopping. be able to. It is a thing.
  • "immediately after inspection” means the period from the inspection of a die to the inspection of the next die, or the period until the device is stopped when the die is finally stopped, and is not necessarily immediately after the time. Does not mean.
  • the request unit 9 makes a verify request when the conditions set in the verify request setting unit 8 are satisfied. For example, if the user sets the verify request setting unit 8 to request the execution of verification when the number of dies required for verification reaches the number set in the verify request setting unit 8, the request of the die bonder 1 is made. Part 9 makes a request for verification.
  • the user has previously selected one of the various settings for requesting verification from the verify request setting unit 8. For example, when there is a request from the user or the verification management unit 2, there are a lot end of the wafer, an device error (an error of the die bonder 1), every fixed time, and the like.
  • the user may set a die generation pattern that requires verification in the verify request setting unit 8
  • the pattern recognition unit 12 may set a die generation pattern that requires verification (verification is required).
  • the request unit 9 may be the one that makes the verification request.
  • the user or the verification mechanism performs the operation as shown in FIG. 2 (b) at any arbitrary timing during the operation of the die bonder 1 in FIG. 2 (a).
  • the user confirms the warning status in the die bonder 1 to see if verification is requested (step S8).
  • the warning is the alarm function (buzzer, screen display, warning light, lamp) of the die bonder 1, the screen display of personal computers, smartphones, tablets, etc. that form a part of the verify management unit 2, the lamp, buzzer, vibration. It can be, or it can send an e-mail to a registered e-mail address, etc., and it can be done by one or more of these methods.
  • step S9 If verification is requested, the user executes verification (step S9), and the result recording unit 7 of the verification management unit 2 records the verification result (step S10). On the other hand, if verification is not requested, the user does not perform verification.
  • the die bonder 1 performs the operation as shown in FIG. 2 (c) at any arbitrary timing during the operation shown in FIG. 2 (a). That is, when the die bonder 1 requests the result recording unit 7 of the verification management unit 2 to have a die that can be produced as a result of executing the verification by the user or the verification mechanism (step S11), the result recording unit 7 produces. Send data on possible die positions. If there is a die that can be produced, the die is moved to the position of the die (step S12), the die is picked up (step S13), and the die is bonded to a predetermined position.
  • step S2 Since the inspection has not been executed for the dies other than the dies that have been verified, the operation shown in FIG. 2A is performed. That is, the die is moved to the next die (step S2), the die is inspected by the inspection mechanism 4 (step S3), and if the inspection is passed (step S4), the die is picked up (step S5) at a predetermined position. Bond to. On the other hand, if the inspection by the inspection mechanism 4 is not passed (step S4), the verification management unit 2 is notified of the die position and additional information without stopping the device without picking up the die, and the verification management unit 2 The position specifying unit 5 and the additional information storage unit 6 store the verification information (step S6). These operations are repeated (step S7).
  • the result recording unit 7 transmits the result to the verify data holding unit 11 of the map management unit 3.
  • the map management unit 3 stores the information of the die that needs to be verified even if the wafer having the die that needs to be verified is ejected from the die bonder 1.
  • the verify data holding unit 11 may write the information of the verify management unit 2 into the map information held by the map holding unit 10. Therefore, even if the wafer is ejected from the die bonder 1, the user can verify the die.
  • each die bonder 1a, 1b, 1c ... is a die that requires verification, until verification is completed. Skip to the next die and continue production without picking up. That is, even if the inspection result requires verification, each die bonder 1a, 1b, 1c ... Continues production using the next die, so that the die bonders 1a, 1b, 1c ... Do not stop. It can operate and improve productivity. Then, since the user and the verification mechanism can execute the verification at an arbitrary timing such as during production, the workability of the user is improved. Moreover, since the user and the verification mechanism can execute the verification based on the information accumulated in the position identification unit 5 and the additional information storage unit 6, the verification can be appropriately executed and only the die that can be produced is used. It is possible to assemble high quality semiconductor devices.
  • FIG. 4 shows the semiconductor device assembly system of the second embodiment.
  • the assembly system of the second embodiment includes a data organizing unit 13 and a display unit 14.
  • the display unit 14 displays the position of the die for which verification, which is a re-inspection, is required by the inspection of the inspection mechanism 4, and additional information necessary for verification.
  • the screen of the die bonder 1 a personal computer, and a smartphone.
  • the data organizing unit 13 organizes die information that needs to be verified, and calculates / rearranges data and generates display contents.
  • the verify management unit (not shown in Fig. 4) has a server, and the software on the server side calculates and sorts the data and generates the display contents, and the client of the personal computer, smartphone, and tablet placed on the client side. It is displayed on the display unit 14 of the software (for example, a Web browser).
  • the data organizing unit 13 ranks the dies that need to be verified so that the operation rate of the die bonder 1 is high.
  • the "ranking that increases the operating rate of the die bonder 1" is a ranking according to the degree of urgency that requires verification, for example, a higher ranking is given to those that are approaching wafer frame replacement. That is, when verification is performed after the wafer frame is replaced (after being discharged from the die bonder 1), the wafer frame is replaced again (in order to use the die enabled by verification for production). The work of setting the wafer on the die bonder 1) occurs, and the productivity decreases. Therefore, by presenting the wafer frame to the user in a high order so that the verification is performed at the timing before the replacement of the wafer frame, efficient production can be performed without reducing the productivity.
  • the data organizing unit 13 may use the additional information to rank the dies that require beliafi. For example, if the ranking is determined for each defect size (additional information) (larger defects are ranked higher), verification can be performed from the largest defects, and for dies with relatively high rankings, users with low verification skills And the verify mechanism can also perform verify, and when the verify ability reaches the limit of the user and the verify mechanism, the subsequent dies (dies with a relatively low rank) are verified by other users with high verification skills and the verify mechanism. It is possible to improve the verification efficiency by taking measures such as executing.
  • the ranking of dies by the data organizing unit 13 may be determined based on the operating rate of the die bonder 1, may be determined based on additional information, or may be determined based on the operating rate of the die bonder 1 and the addition. It may be decided based on both information. Furthermore, it may be decided based on other factors.
  • the data organizing unit 13 determines the display order of the dies to be displayed on the display unit 14 based on the ranked information. That is, when a plurality of varieties are mixed and displayed in order from the die having the highest ranking, various varieties may be displayed randomly, and the workability of verification is lowered. Therefore, the data organizing unit 13 further groups the ranked dies by type, so that the display unit 14 displays the dies with high priority for each group.
  • the display unit 14 displays the result input unit 15 for inputting the result (OK / NG) of the verification information of the die after the verification is executed.
  • information on one die that needs to be verified for example, an image of the die, additional information, both the image and the additional information, etc.
  • the verification result input unit 15 of the die Is displayed at the same time, and when the verification result (OK / NG) of the die on which the information is displayed is input to the result input unit 15, the display is switched to the image of the next die.
  • the display unit 14 displays the dies for which verification is required based on the ranking.
  • the die with the highest priority is displayed at the top and the die with the highest priority is displayed at the bottom.
  • the die having the highest priority is displayed first, and the die with the higher priority is displayed so that the priority is lowered as the die becomes later.
  • the semiconductor device assembly system of the second embodiment also has the same action and effect as the semiconductor device assembly system of the first embodiment.
  • the second embodiment by providing the data organizing unit 13, efficient production can be achieved without reducing the productivity.
  • the same configurations as those of the semiconductor device assembly system of the first embodiment are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted.
  • the position specifying unit 5, the additional information storage unit 6, the result recording unit 7, and the pattern recognition unit 12 of the first embodiment may be provided.
  • the data organizing unit 13 and the display unit 14 may be provided on different terminals, or may be provided on the same terminal.
  • the position identification unit 5, the additional information storage unit 6, the result recording unit 7, the verify request setting unit 8, the request unit 9, the pattern recognition unit 12, the data organization unit 13, and the display unit 14 of the first embodiment and the second embodiment are , In this system, it can be installed at any place.
  • the display unit 14 may be a device connected to the additional information storage unit 6 via a network, may be a screen of an assembly device (die bonder 1), or may verify the verify request setting unit 8 and the request unit 9. It can be provided in the management unit 2.
  • the configurations (for example, the position specifying unit 5, the additional information storage unit 6, and the result recording unit 7 pattern recognition unit 12) shown as the same terminal in the drawings need only be present in the system and are not necessarily provided in the same terminal. You don't have to be.
  • the position specifying unit 5 and the additional information storage unit 6 may be provided in separate terminals.
  • the present invention is not limited to the above embodiment, and various modifications can be made, and the setting for requesting verification is individually performed for each die bonder. be able to.
  • die bonder 1 (1a) the number of dies requiring verification reaches 50
  • die bonder 2 (1b) the number of dies requiring verification reaches 100, and so on. ..
  • die bonder 1 (1a) the number of dies for executing verification is used as a reference
  • die bonder 2 (1b) the standard is set every fixed time, and so on.
  • Each die bonder 1 may have different criteria.
  • the verify management unit may have a cancel unit for canceling the verification required, or a die that has become the verification required may be used at the discretion of the user or the like.
  • the die alone requires verification, it may be desired to use the die for assembly because it is a minor error and verification is not required in a pseudo manner. In such a case, even if the die has been verified once, the die may be used for assembly.
  • the semiconductor device assembly device is not limited to the die bonder, but may be a mounter or the like. Although it is particularly effective when there are a plurality of assembly devices as in the embodiment, the number of assembly devices may be one.
  • the verify management unit 2 may be provided in the assembly device. The inspection by the inspection mechanism 4 may be performed at the time of pickup, at the time of mounting, or at other times.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A system for assembling a semiconductor system comprises an assembly device for assembling a semiconductor device by using an individual piece inspected in an inspection mechanism. The system comprises an additional information storage unit, the additional information storage unit storing additional information necessary for verification of the individual piece that is determined to need verification, which is reinspection, according to an inspection of by the inspection mechanism. The assembly device for assembling the semiconductor device informs the additional information storage unit of the additional information of the individual piece that is determined to need verification by the inspection in the inspection mechanism, and does not use, in the assembly, the individual piece that is determined to need verification until completion of the inspection of at least the next individual piece to be inspected or the completion of the assembly.

Description

半導体装置の組立システム、半導体装置の組立方法、及び半導体装置の組立プログラムSemiconductor device assembly system, semiconductor device assembly method, and semiconductor device assembly program
　本発明は、半導体装置の組立システム、半導体装置の組立方法、及び半導体装置の組立プログラムに関する。 The present invention relates to a semiconductor device assembly system, a semiconductor device assembly method, and a semiconductor device assembly program.
　半導体装置は、個片体を被供給部材にマウントすることにより組立られる工程を有することがある。例えば、多数個の素子を一括して造り込まれたウエハをダイシングして、個片体である半導体ダイ（電子回路を作り込んだシリコン基板のチップ）に分離し、これを一個ずつリードフレームや基板等の被供給部材の所定位置にボンディングするというダイボンディングの工程がある。そして、このダイボンディングには、特許文献１のようなダイボンダ（ボンディング装置）が用いられる。 A semiconductor device may have a process of being assembled by mounting an individual piece on a supplied member. For example, a wafer in which a large number of elements are built together is diced and separated into a semiconductor die (a silicon substrate chip in which an electronic circuit is built), which is a lead frame or a lead frame one by one. There is a dicing process of bonding to a predetermined position of a supplied member such as a substrate. A die bonder (bonding device) as in Patent Document 1 is used for this die bonding.
　ボンディング装置は、図４に示すように、供給部１０２の半導体ダイ１０１を吸着するコレット１０３を有するボンディングアーム（図示省略）と、供給部１０２の半導体ダイ１０１を検査する検査機構（図示省略）と、ボンディング位置でリードフレーム１０４のアイランド部１０５を観察する確認用カメラ（図示省略）とを備える。 As shown in FIG. 4, the bonding apparatus includes a bonding arm (not shown) having a collet 103 for adsorbing the semiconductor die 101 of the supply unit 102, and an inspection mechanism (not shown) for inspecting the semiconductor die 101 of the supply unit 102. A confirmation camera (not shown) for observing the island portion 105 of the lead frame 104 at the bonding position is provided.
　供給部１０２は半導体ウエハ１０６（図５参照）を備え、半導体ウエハ１０６が多数のダイ１０１に分割されている。ウエハ１０６は粘着シート（ダイシングシート）に貼り付けられ、このダイシングシートが環状のフレームに保持される。そして、このダイシングシート上のウエハ１０６に対して、円形刃（ダイシング・ソー）等を用いて、個片化してダイ１０１を形成する。また、コレット１０３を保持しているボンディングアームは搬送機構を介して、ピックアップ位置とボンディング位置との間の移動が可能となっている。 The supply unit 102 includes a semiconductor wafer 106 (see FIG. 5), and the semiconductor wafer 106 is divided into a large number of dies 101. The wafer 106 is attached to an adhesive sheet (dicing sheet), and the dicing sheet is held by an annular frame. Then, the wafer 106 on the dicing sheet is individualized to form the die 101 by using a circular blade (dicing saw) or the like. Further, the bonding arm holding the collet 103 can be moved between the pickup position and the bonding position via the transport mechanism.
　ダイをボンディングする際、図６及び図７に示すように、ダイがピックアップポジションに移動して（ステップＳ１０１）、検査機構（例えば外観検査や通電検査）によりダイの検査を実行して（ステップＳ１０２）、検査結果が良好であれば（検査に合格すれば）（ステップＳ１０３）ダイのピックアップを行い（ステップＳ１０４）所定位置にボンディングする。 When bonding the dies, as shown in FIGS. 6 and 7, the die moves to the pickup position (step S101), and the die is inspected by an inspection mechanism (for example, visual inspection or energization inspection) (step S102). ), If the inspection result is good (if the inspection is passed) (step S103), the die is picked up (step S104) and bonded to a predetermined position.
　一方、検査機構による検査に合格しなかった場合（ステップＳ１０３）、装置を停止させてユーザの呼び出しを行って（エラーを出して）（ステップＳ１０５）、ダイの再確認（ベリファイ）を促す。ユーザがベリファイを実行し（ステップＳ１０６）、生産可能なダイである場合は（ステップＳ１０７）、ダイのピックアップを行い（ステップＳ１０４）所定位置にボンディングする。一方、生産可能でないダイである場合は（ステップＳ１０７）、そのダイをピックアップすることなく、次のダイに移動する（ステップＳ１０１）。これらの動作を繰り返し行う（ステップＳ１０８）。 On the other hand, if the inspection by the inspection mechanism is not passed (step S103), the device is stopped and the user is called (with an error) (step S105) to prompt the die to be reconfirmed (verify). The user performs verification (step S106), picks up the die if it is a producible die (step S107), and bonds it to a predetermined position (step S104). On the other hand, if the die cannot be produced (step S107), the die is moved to the next die without being picked up (step S101). These operations are repeated (step S108).
　検査機構による検査に合格しなかった場合、その都度装置を停止させ、ベリファイが完了するまで装置を待機状態とすると、生産が停止して生産効率が悪くなるという問題がある。特に、不良品が一定数存在するような場合には、装置の停止頻度が高くなって生産効率が悪くなる。 If the inspection by the inspection mechanism is not passed, the equipment is stopped each time and the equipment is put into a standby state until the verification is completed, there is a problem that the production is stopped and the production efficiency is deteriorated. In particular, when a certain number of defective products exist, the frequency of stopping the device increases and the production efficiency deteriorates.
　電子部品の組立装置の停止時間を短縮するものとして、特許文献２のものがある。特許文献２には、電子部品をプリント基板に挿入する装置において、挿入が正常に行われたかを検査し、挿入ミスを起こした場合、装置を停止させずにその電子部品を飛び越して、次の電子部品の挿入動作を継続することが記載されている。 There is Patent Document 2 as a device for shortening the downtime of an electronic component assembly device. In Patent Document 2, in an apparatus for inserting an electronic component into a printed circuit board, it is inspected whether the insertion is performed normally, and if an insertion error occurs, the electronic component is skipped without stopping the apparatus, and the following It is described that the insertion operation of the electronic component is continued.
特開２００８‐１２４３８２号公報Japanese Unexamined Patent Publication No. 2008-124382 特開平５‐２８６９２号公報Japanese Unexamined Patent Publication No. 5-28692
　ダイボンディング工程において、ウエハには生産に適さないダイが存在する場合があり、生産に適さないダイを半導体装置の組立に使用すると、製品の品質が劣る。このため、検査に合格しなかったダイについて、適切にベリファイを実行することが重要となる。ダイのベリファイを行うためには、例えば、ウエハの情報、ダイボンダの情報、検査機構の検査状態の情報、検査機構による検査結果の情報、検査機構による検査以外でのダイの情報等、種々の情報が必要になる。 In the die bonding process, there may be a die that is not suitable for production in the wafer, and if a die that is not suitable for production is used for assembling a semiconductor device, the quality of the product will be inferior. For this reason, it is important to properly verify the dies that have not passed the inspection. In order to verify the die, for example, various information such as wafer information, die bonder information, inspection status information of the inspection mechanism, inspection result information by the inspection mechanism, and die information other than inspection by the inspection mechanism. Is required.
　特許文献２に記載されたものは、電子部品がプリント基板に挿入されているか否かを検査するものであり、挿入されていない場合はユーザが再挿入動作を行うものである。すなわち、特許文献２に記載の方法は、電子部品をプリント基板に挿入した後の状態の良否を判断するものであって、前記したようなベリファイに必要な情報はない。このため、特許文献２のものでは、電子部品そのものの良否の判断までは行うことができず、生産に適さない電子部品が混在していても、組立に使用されて製品の品質が低下するおそれがある。 The one described in Patent Document 2 is for inspecting whether or not an electronic component is inserted into a printed circuit board, and if it is not inserted, the user performs a reinsertion operation. That is, the method described in Patent Document 2 is for determining the quality of the state after inserting the electronic component into the printed circuit board, and there is no information necessary for verification as described above. Therefore, in Patent Document 2, it is not possible to judge the quality of the electronic component itself, and even if electronic components that are not suitable for production are mixed, they may be used for assembly and the quality of the product may deteriorate. There is.
　そこで、本発明は斯かる実情に鑑み、生産性の向上を図り、高品質な半導体装置を組立てることができる半導体装置の組立システム、半導体装置の組立方法、及び半導体装置の組立プログラムを提供しようとするものである。 Therefore, in view of such circumstances, the present invention aims to improve productivity and to provide a semiconductor device assembly system, a semiconductor device assembly method, and a semiconductor device assembly program capable of assembling high-quality semiconductor devices. Is what you do.
　本発明の半導体装置の組立システムは、検査機構により検査を行った個片体を用いて半導体装置を組立てる組立装置を備えた半導体装置の組立システムにおいて、検査機構の検査により再検査であるベリファイが必要とされた個片体の、ベリファイに必要な付加情報を記憶する付加情報記憶部を備え、前記半導体装置の組立装置は、検査機構の検査によりベリファイが必要とされた個片体の付加情報を前記付加情報記憶部に通知して、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は、ベリファイが必要とされた個片体を組立に使用しないものである。 The semiconductor device assembly system of the present invention is a semiconductor device assembly system including an assembly device for assembling a semiconductor device using individual pieces inspected by an inspection mechanism, and is re-inspected by inspection by the inspection mechanism. An additional information storage unit for storing additional information required for verification of the required individual piece is provided, and the assembly device of the semiconductor device has additional information of the individual piece required for verification by inspection by an inspection mechanism. Is notified to the additional information storage unit, and the individual piece for which verification is required is not used for assembly at least until the inspection of the individual piece to be inspected next or the end of assembly.
　本発明の半導体装置の組立システムによれば、付加情報記憶部にベリファイに必要な付加情報を蓄積しておき、次の個片体を検査するまでの間、又はベリファイが必要な個片体を最後に組立が終了する場合、組立終了までの間は、ベリファイが必要な個片体を組立に使用しない（スキップする）。これにより、生産が継続する場合は、装置を停止させることなく継続することができる。そして、ユーザやベリファイ機構は、生産中など任意のタイミングでベリファイを実行することができる。すなわち、検査結果が要ベリファイの場合でも、装置は次の個片体を使用して生産を継続するため、装置は停止することなく動作することができる。しかも、ユーザやベリファイ機構は、付加情報記憶部に蓄積された情報に基づいてベリファイを実行できるため、適切にベリファイを実行することができる。 According to the assembly system of the semiconductor device of the present invention, the additional information necessary for verification is stored in the additional information storage unit, and the individual pieces that need to be verified are stored until the next individual piece is inspected. When the assembly is finally completed, the individual pieces that require verification are not used (skipped) for the assembly until the assembly is completed. As a result, when production is continued, it can be continued without stopping the apparatus. Then, the user and the verification mechanism can execute the verification at any timing such as during production. That is, even if the inspection result requires verification, the device continues production using the next piece, so that the device can operate without stopping. Moreover, since the user and the verification mechanism can execute the verification based on the information stored in the additional information storage unit, the verification can be appropriately executed.
　前記構成において、ベリファイ実行後の個片体のベリファイ情報を記録する結果記録部を備えていてもよい。 In the above configuration, a result recording unit for recording the verification information of each individual body after the verification is executed may be provided.
　本発明の他の半導体装置の組立システムは、検査機構により検査を行った個片体を用いて半導体装置を組立てる組立装置を備えた半導体装置の組立システムにおいて、検査機構の検査により再検査であるベリファイが必要とされた個片体の、ベリファイに必要な付加情報を表示する表示部を備え、検査機構の検査によりベリファイが必要とされた個片体を、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は組立に使用しないものである。 The other semiconductor device assembly system of the present invention is a semiconductor device assembly system including an assembly device for assembling a semiconductor device using individual pieces inspected by the inspection mechanism, and is re-inspected by inspection by the inspection mechanism. It is equipped with a display unit that displays additional information required for verification of the individual pieces that required verification, and the individual pieces that required verification by inspection by the inspection mechanism are at least the individual pieces to be inspected next. It is not used for assembly until the end of body inspection or assembly.
　本発明の他の半導体装置の組立システムによれば、ベリファイが必要な個片体の付加情報を蓄積するとともに、次の個片体を検査するまでの間、又はベリファイが必要な個片体を最後に組立が終了する場合、組立終了までの間は、ベリファイが必要な個片体を組立に使用しない（スキップする）。これにより、生産が継続する場合は、装置を停止させることなく継続することができる。そして、ユーザやベリファイ機構は、生産中など任意のタイミングでベリファイを実行することができる。すなわち、検査結果が要ベリファイの場合でも、装置は次の個片体を使用して生産を継続するため、装置は停止することなく動作することができる。しかも、ユーザやベリファイ機構は、表示部に表示された情報に基づいてベリファイを実行できるため、適切にベリファイを実行することができる。 According to the assembly system of another semiconductor device of the present invention, additional information of the individual pieces requiring verification is accumulated, and the individual pieces requiring verification are accumulated until the next individual piece is inspected or the individual pieces requiring verification are obtained. When the assembly is finally completed, the individual pieces that require verification are not used (skipped) for the assembly until the assembly is completed. As a result, when production is continued, it can be continued without stopping the apparatus. Then, the user and the verification mechanism can execute the verification at any timing such as during production. That is, even if the inspection result requires verification, the device continues production using the next piece, so that the device can operate without stopping. Moreover, since the user and the verification mechanism can execute the verification based on the information displayed on the display unit, the verification can be appropriately executed.
　前記構成において、前記表示部は、ベリファイ実行後の個片体のベリファイ情報の結果を入力する結果入力部を備えていてもよい。 In the above configuration, the display unit may include a result input unit for inputting the result of the verification information of the individual body after the verification is executed.
　前記構成において、前記表示部は、ベリファイが必要とされた個片体の情報と、前記ベリファイ結果入力部とを同時に表示し、表示されている個片体のベリファイ結果が結果入力部に入力されると、次のベリファイが必要な個片体の情報に表示を切り替えるものであってもよい。 In the above configuration, the display unit simultaneously displays the information of the individual piece for which verification is required and the verification result input unit, and the verified result of the displayed individual piece is input to the result input unit. Then, the display may be switched to the information of the individual piece that requires the next verification.
　前記構成において、ベリファイが必要な個片体の情報を整理するデータ整理部を備え、前記データ整理部は、ベリファイが必要な個片体を前記組立装置の稼働率が高くなるよう順位づけし、順位づけされた情報に基づいて前記表示部に表示すべき個片体の表示順序を決定するものであってもよい。また、前記データ整理部は、ベリファイが必要な個片体を付加情報に基づいて順位づけし、順位づけされた情報に基づいて前記表示部に表示すべき個片体の表示順序を決定するものであってもよい。 In the above configuration, a data organizing unit for organizing information on individual pieces requiring verification is provided, and the data organizing unit ranks individual pieces requiring verification so that the operating rate of the assembly device is high. The display order of the individual pieces to be displayed on the display unit may be determined based on the ranked information. In addition, the data organizing unit ranks individual pieces that need to be verified based on additional information, and determines the display order of the individual pieces to be displayed on the display unit based on the ranked information. It may be.
　前記構成において、ベリファイを要求するための設定を行うベリファイ要求設定部を備え、前記ベリファイ要求設定部に設定された条件を満たしたときに、ベリファイの要求、警告、半導体装置の組立装置のエラー停止の少なくともいずれかを行うものであってもよい。 In the above configuration, a verification request setting unit for making settings for requesting verification is provided, and when the conditions set in the verification request setting unit are satisfied, a verification request, a warning, and an error stop of the semiconductor device assembly device are stopped. It may be one that does at least one of the above.
　前記構成において、ベリファイが必要とされた個片体の発生パターンを認識するパターン認識部を備え、前記ベリファイ要求設定部に設定された発生パターンに該当したときに、ベリファイの要求、警告、半導体装置の組立装置のエラー停止の少なくともいずれかを行うものであってもよい。 In the above configuration, a pattern recognition unit that recognizes an individual piece generation pattern for which verification is required is provided, and when the generation pattern set in the verification request setting unit is met, a verification request, warning, and semiconductor device are provided. It may perform at least one of the error stop of the assembly device of.
　前記構成において、個片体の集合体であるワークのマップ情報を有するマップ管理部を備え、マップ管理部は、ベリファイが必要な個片体の情報を記憶するベリファイデータ保持部を有するものであってもよい。 In the above configuration, a map management unit having map information of a work which is an aggregate of individual pieces is provided, and the map management unit has a verification data holding unit for storing information of individual pieces requiring verification. You may.
　前記構成において、前記付加情報は、個片体の集合体であるワークの情報、前記半導体装置の組立装置の情報、前記検査機構の検査状態の情報、前記検査機構による検査結果の情報、前記検査機構による検査以外での個片体の情報のいずれかとすることができる。 In the configuration, the additional information includes information on a work that is an aggregate of individual pieces, information on an assembly device of the semiconductor device, information on an inspection state of the inspection mechanism, information on inspection results by the inspection mechanism, and the inspection. It can be any of the individual piece information other than the inspection by the mechanism.
　前記構成において、複数の半導体装置の組立装置を備えた場合に特に有効なものとなる。また、前記半導体装置の組立装置がダイボンダである場合に特に有効なものとなる。 In the above configuration, it is particularly effective when a plurality of semiconductor device assembly devices are provided. Further, it is particularly effective when the assembling device of the semiconductor device is a die bonder.
　本発明の半導体装置の組立方法は、半導体装置を組立てる組立装置にて個片体の検査を行い、検査された個片体を用いて半導体装置を組立てる半導体装置の組立方法において、個片体の検査を実行し、前記検査により再検査であるベリファイが必要な個片体の、ベリファイに必要な付加情報を記憶し、前記組立装置は、ベリファイが必要とされた個片体を、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は組立に使用しないものである。 The method for assembling a semiconductor device of the present invention is a method for assembling a semiconductor device in which an individual piece is inspected by the assembling device for assembling the semiconductor device and the semiconductor device is assembled using the inspected individual pieces. The inspection is performed, and the additional information necessary for verification of the individual pieces that need to be verified by the inspection is stored, and the assembly device stores the individual pieces that need to be verified at least as follows. It is not used for assembly until the inspection of the individual piece to be inspected or the end of assembly.
　本発明の半導体装置の組立プログラムは、半導体装置を組立てる組立装置にて個片体の検査を行い、検査された個片体を用いて半導体装置を組立装置に組立てさせる半導体装置の組立プログラムにおいて、個片体の検査を実行するステップと、前記検査により再検査であるベリファイが必要とされた個片体の、ベリファイに必要な付加情報を記憶し、前記組立装置は、ベリファイが必要な個片体を、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は組立に使用しないステップとを備えたものである。 The semiconductor device assembly program of the present invention is an assembly program for a semiconductor device in which an individual piece is inspected by the assembly device for assembling the semiconductor device and the semiconductor device is assembled to the assembly device using the inspected individual pieces. The step of executing the inspection of the individual pieces and the additional information necessary for the verification of the individual pieces for which the verification which is the re-inspection was required by the inspection is stored, and the assembly device stores the individual pieces that need to be verified. It includes steps in which the body is not used for assembly at least until the next inspection of the individual piece to be inspected or the end of assembly.
　本発明の半導体装置の組立システム、半導体装置の組立方法、及び半導体装置の組立プログラムは、検査結果が要ベリファイの場合でも、装置は次の個片体を使って生産を継続するため、装置は停止することなく動作することができ、生産性の向上を図ることができる。また、任意のタイミングでベリファイを実行できるため、ユーザ等の作業性が向上する。また、ユーザやベリファイ機構は、適切にベリファイを実行できるため、生産可能な個片体のみを使用して高品質な半導体装置を組立てることができる。 In the semiconductor device assembly system, the semiconductor device assembly method, and the semiconductor device assembly program of the present invention, even if the inspection result requires verification, the device continues to be produced using the following individual pieces. It can operate without stopping, and productivity can be improved. Further, since the verification can be executed at any timing, the workability of the user or the like is improved. In addition, since the user and the verification mechanism can appropriately perform verification, it is possible to assemble a high-quality semiconductor device using only producible individual pieces.
本発明の第１実施形態の半導体装置の組立システムを示すブロック図である。It is a block diagram which shows the assembly system of the semiconductor device of 1st Embodiment of this invention. 本発明の半導体装置の組立方法を示すフローチャート図であり、（ａ）はダイボンダの動作を説明する図、（ｂ）はユーザ及びベリファイ管理部の動作を説明する図、（ｃ）はダイボンダの他の動作を説明する図である。It is a flowchart which shows the assembly method of the semiconductor device of this invention, (a) is a figure explaining the operation of a die bonder, (b) is a figure explaining the operation of a user and a verification management unit, (c) is a diagram explaining the operation of a user and the verification management unit, and (c) is other than the die bonder. It is a figure explaining the operation of. 本発明の半導体装置の組立方法を示すシーケンス図である。It is a sequence diagram which shows the assembly method of the semiconductor device of this invention. 本発明の第２実施形態の半導体装置の組立システムを示すブロック図である。It is a block diagram which shows the assembly system of the semiconductor device of 2nd Embodiment of this invention. 一般的なボンディング装置の動作を示す簡略図である。It is a simplified diagram which shows the operation of a general bonding apparatus. ウエハを示す簡略図である。It is a simplified drawing which shows a wafer. 従来の半導体装置の組立方法を示すフローチャート図である。It is a flowchart which shows the assembly method of the conventional semiconductor device. 従来の半導体装置の組立方法を示すシーケンス図である。It is a sequence diagram which shows the assembly method of the conventional semiconductor device.
　以下、本発明の実行の形態を図１～図４に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.
　図１は第１実施形態の半導体装置の組立システムを示す。本実施形態の組立システムは、組立装置にて半導体装置を組立てるためのシステムであって、図１に示すように、複数（例えば３０台）の組立装置１（１ａ、１ｂ、１ｃ・・・）と、組立装置１とネットワーク又は電気的に接続されたベリファイ管理部２及びマップ管理部３とを備える。ネットワークは、例えば、インターネット、イントラネット、エクストラネット、ＬＡＮ、ＭＡＮ、ＷＡＮ、さらにはこれらの組み合わせ等のものであり、有線か無線かは問わず、複数地点間で情報を伝送できるものである。 FIG. 1 shows an assembly system for a semiconductor device according to the first embodiment. The assembly system of the present embodiment is a system for assembling a semiconductor device with an assembly device, and as shown in FIG. 1, a plurality of (for example, 30) assembly devices 1 (1a, 1b, 1c ...) A verification management unit 2 and a map management unit 3 that are networked or electrically connected to the assembly device 1 are provided. The network is, for example, the Internet, an intranet, an extranet, a LAN, a MAN, a WAN, or a combination thereof, and can transmit information between a plurality of points regardless of whether it is wired or wireless.
　組立装置１は、マウンター、ダイボンダ等、半導体装置の組立に用いられる種々の装置とすることができる。本実施形態では、組立装置１は、ダイ（電子回路を作り込んだシリコン基板のチップ）をリードフレームや基板等の被供給部材に接着するダイボンダとしている。以下、「個片体」をダイ、「ワーク」を多数のダイに分割されてなるウエハ、「被供給部材」を基板として説明する。 The assembly device 1 can be various devices used for assembling semiconductor devices such as mounters and die bonders. In the present embodiment, the assembly device 1 is a die bonder that adheres a die (a silicon substrate chip in which an electronic circuit is built) to a supplied member such as a lead frame or a substrate. Hereinafter, the "individual piece" will be described as a die, the "work" will be described as a wafer divided into a large number of dies, and the "supplied member" will be described as a substrate.
　組立装置であるダイボンダ１は、ダイを検査する検査機構４を備えている。検査機構４は、外観検査、通電検査等、ダイの良否を検査できる種々の検査機構とすることができる。本実施形態では、検査機構４は、ダイの画像を取得できる撮像手段（図示省略）と、取得した画像に基づいて画像処理を行う画像処理手段（図示省略）とを備えており、ダイの外観（例えば、傷、クラック、穴等の欠陥や異物の有無）を検査するものとしている。この検査機構４により夫々のダイについて画像に基づく外観検査を行い、検査に合格したダイは、半導体装置の組立に使用される。すなわち、図示省略のコレットは、検査に合格したダイをピックアップして基板にマウントする。 The die bonder 1 which is an assembly device is provided with an inspection mechanism 4 for inspecting the die. The inspection mechanism 4 can be various inspection mechanisms capable of inspecting the quality of the die, such as visual inspection and energization inspection. In the present embodiment, the inspection mechanism 4 includes an imaging means (not shown) capable of acquiring an image of the die and an image processing means (not shown) capable of performing image processing based on the acquired image, and the appearance of the die. (For example, the presence or absence of defects such as scratches, cracks, holes, and foreign matter) is to be inspected. The inspection mechanism 4 performs an image-based visual inspection on each die, and the die that passes the inspection is used for assembling the semiconductor device. That is, the collet (not shown) picks up the die that has passed the inspection and mounts it on the substrate.
　ベリファイ管理部２は、検査機構４による検査に合格しなかったダイのベリファイを実行するために必要な情報を管理するものであり、例えば、ＣＰＵ（Central Processing Unit）を中心としてＲＯＭ（Read Only Memory）やＲＡＭ（Random Access Memory）等がバスを介して相互に接続されたコンピュータで構成でき、ベリファイ用サーバ、ベリファイを実行するための操作端末、ベリファイを実行するための表示画面を備えている。なお、ＲＯＭには、ＣＰＵが実行するプログラムやデータが格納されている。ここで、ベリファイとは、検査機構４によるダイの検査結果が良好でない場合（検査に合格しなかった場合）に、そのダイの再検査を行って、ダイが生産可能なものであるか否か（半導体装置の組立に使用できるものであるか否か）を判断することであり、ベリファイはユーザが行うものであっても、コンピュータ等のベリファイ機構が行うものであってもよい。 The verification management unit 2 manages information necessary for executing verification of a die that has not passed the inspection by the inspection mechanism 4. For example, the ROM (Read Only Memory) is centered on the CPU (Central Processing Unit). ) And RAM (RandomAccessMemory) can be configured by computers connected to each other via a bus, and it has a verification server, an operation terminal for executing verification, and a display screen for executing verify. The ROM stores programs and data executed by the CPU. Here, "verify" means whether or not the die can be produced by re-inspecting the die when the inspection result of the die by the inspection mechanism 4 is not good (when the inspection is not passed). It is to determine (whether or not it can be used for assembling a semiconductor device), and the verification may be performed by the user or by a verification mechanism such as a computer.
　ベリファイ管理部２は、位置特定部５と、付加情報記録部６と、結果記録部７と、パターン認識部１２とを備える。 The verify management unit 2 includes a position identification unit 5, an additional information recording unit 6, a result recording unit 7, and a pattern recognition unit 12.
　位置特定部５は、ベリファイが必要なダイの位置を特定するものであり、付加情報記憶部６は、ベリファイに必要な付加情報を記憶するものである。すなわち、検査機構４によりダイの検査を実行した結果、検査結果が良好ではなく、ベリファイが必要であると判断された（検査に合格しなかった）ダイについては、検査機構４は、位置特定部５にそのダイの位置（例えばＸ方向及びＹ方向の位置）を記憶させるとともに、付加情報記憶部６にベリファイに必要な付加情報を記憶させる。なお、「ダイの位置」とは、ウエハ上の固有のダイを特定するために必要な情報であればよく、例えば、ウエハの移動機構の位置であったり、マップなど、位置を特定するデータからダイを特定するための情報であったりすることができる。付加情報とは、例えば、ウエハの情報、ダイボンダ１の情報、検査機構４の検査状態の情報、検査機構４による検査結果の情報、検査機構４による検査以外でのダイの情報のいずれかである。 The position specifying unit 5 specifies the position of the die that requires verification, and the additional information storage unit 6 stores additional information required for verification. That is, as a result of performing the die inspection by the inspection mechanism 4, the inspection mechanism 4 is the position identification unit for the die for which the inspection result is not good and it is determined that verification is necessary (the inspection is not passed). 5 stores the position of the die (for example, the position in the X direction and the Y direction), and the additional information storage unit 6 stores additional information necessary for verification. The "die position" may be any information necessary for identifying a unique die on the wafer, and is, for example, the position of the wafer moving mechanism, a map, or other data for specifying the position. It can be information for identifying the die. The additional information is, for example, any one of wafer information, die bonder 1 information, inspection state information of inspection mechanism 4, inspection result information by inspection mechanism 4, and die information other than inspection by inspection mechanism 4. ..
　ウエハの情報とは、例えば、製品名（ＩＤ）、部品名（ＩＤ）、部品ロット、マップデータの情報（良否の情報を含む製品ランク）、ポジション（ウエハ上の位置、トレイ上の位置、組立対象の位置（マウント位置））等である。ダイボンダ１の情報とは、例えば、生産レシピ名、生産レシピそのもの又はその一部、オペレータ名（ＩＤ）、装置名（ＩＤ）、装置の状態（ツールの使用回数、温度、プロセスの条件）等である。 Wafer information includes, for example, product name (ID), part name (ID), part lot, map data information (product rank including quality information), position (position on wafer, position on tray, assembly). Target position (mount position), etc. The information of the die bonder 1 is, for example, the production recipe name, the production recipe itself or a part thereof, the operator name (ID), the device name (ID), the state of the device (the number of times the tool is used, the temperature, the process conditions), and the like. is there.
　検査状態とは、例えば、照明、カメラ等の撮像に関する設定、その他検査機器の設定、検査処理のパラメータ、モデルデータ・モデル画像、判定しきい値等の検査レシピである。検査結果とは、例えば、検査画像、検査に使用しない画像（例えば位置決めや、他検査の画像、目視確認用の画像）、目視確認用に用いる別カメラの画像、検査機器の出力（画像検査の画像に相当するデータ）、装置の検査結果画面のキャプチャ、検査時刻、欠陥情報（判定、欠陥分類、画像処理上の特徴、形状特徴、輝度の特徴、寸法、欠陥領域データ、欠陥候補領域データ等の抽出領域）等である。 The inspection state is, for example, an inspection recipe such as lighting, settings related to imaging of a camera, other settings of inspection equipment, parameters of inspection processing, model data / model image, judgment threshold value, and the like. The inspection results are, for example, inspection images, images not used for inspection (for example, images for positioning and other inspections, images for visual confirmation), images of another camera used for visual confirmation, and output of inspection equipment (for image inspection). (Data corresponding to the image), capture of the inspection result screen of the device, inspection time, defect information (judgment, defect classification, image processing characteristics, shape characteristics, brightness characteristics, dimensions, defect area data, defect candidate area data, etc. Extraction area) and so on.
　検査機構４による検査以外でのダイの情報とは、例えば、周辺の対象のデータ、同じダイの別工程の画像及びデータ等である。例えば、マウント時に検査機構４によるダイの検査を行った場合は、ピックアップ時における検査情報が付加情報となり、ピックアップ時に検査機構４によるダイの検査を行った場合は、前工程の検査機の結果や、マップデータ（例えば、前工程での検査結果に基づく製品ランク）が付加情報となる。 The die information other than the inspection by the inspection mechanism 4 is, for example, data of surrounding objects, images and data of another process of the same die, and the like. For example, when the die is inspected by the inspection mechanism 4 at the time of mounting, the inspection information at the time of pickup becomes additional information, and when the die is inspected by the inspection mechanism 4 at the time of pickup, the result of the inspection machine in the previous process or , Map data (for example, product rank based on the inspection result in the previous process) becomes additional information.
　結果記録部７は、ベリファイを実行した後のダイのベリファイ情報を記録するものである。ユーザ又はベリファイ機構が、ベリファイが必要なダイについてベリファイを実行しベリファイが完了すると、その情報（生産可能なダイであるか否か）がベリファイ管理部２の結果記録部７に記録される。生産可能なダイについては、ダイボンダ１はそのダイのピックアップを行って、基板の所定位置にボンディングする。 The result recording unit 7 records the verification information of the die after executing the verification. When the user or the verification mechanism performs verification on the die that requires verification and the verification is completed, the information (whether or not the die can be produced) is recorded in the result recording unit 7 of the verification management unit 2. For a die that can be produced, the die bonder 1 picks up the die and bonds it to a predetermined position on the substrate.
　パターン認識部１２は、ベリファイが必要とされたダイの発生パターン（規則性や関連性）を認識するものである。すなわち、パターン認識部１２は、ベリファイが必要とされたダイが近隣のワークで複数発生しているか、発生頻度、特定の領域で発生しているか、等を認識するものである。 The pattern recognition unit 12 recognizes the die generation pattern (regularity and relevance) for which verification is required. That is, the pattern recognition unit 12 recognizes whether a plurality of dies for which verification is required are generated in neighboring workpieces, the frequency of occurrence, whether they are generated in a specific region, and the like.
　ダイボンダ１は、ベリファイ要求設定部８と要求部９とを備えている。ベリファイ要求設定部８は、ユーザやベリファイ機構へのベリファイの要求や警告、ダイボンダ１のエラー停止するための設定を行うものである。ベリファイを要求するための設定は、ユーザが指定する種々の方法にて行うことができる。例えば、ベリファイが必要なダイの数がユーザの設定した数に到達したとき、ユーザやベリファイ管理部２からの要求があったとき、ウエハのロットエンド、装置エラー（ダイボンダ１のエラー）、一定時間毎、等がある。また、ベリファイを必要とするダイの発生パターンを設定してもよい。 The die bonder 1 includes a verify request setting unit 8 and a request unit 9. The verify request setting unit 8 makes settings for requesting and warning the user and the verification mechanism for verification, and for stopping the error of the die bonder 1. Settings for requesting verification can be made by various methods specified by the user. For example, when the number of dies required for verification reaches the number set by the user, when there is a request from the user or the verify management unit 2, the lot end of the wafer, the device error (error of the die bonder 1), and a certain period of time. Every time, etc. In addition, a die generation pattern that requires verification may be set.
　ユーザは、ダイボンダ１がベリファイを要求するための基準として、これらのいずれかの設定を任意に選択することができる。なお、ベリファイを要求するための基準として、ベリファイが必要なダイの数とする場合は、ユーザはこの基準を選択するとともに、ベリファイを実行するためのダイの数について設定を行う。また、ベリファイを要求するための基準として、一定時間毎とする場合は、ユーザはこの基準を選択するとともに、一定時間（例えば１０分等）について設定を行う。なお、図示省略するが、ベリファイ管理部２には、ベリファイすべきダイの数を計測する計測部や、一定時間毎を計測するタイマーを備えている。また、ベリファイを必要とするダイの発生パターンを設定する場合は、ユーザはこの基準を選択するとともに、ベリファイを必要とするダイが、どのようなパターン（エリア、頻度等）で発生するかについて設定を行う。この場合、パターン認識部１３にてベリファイを必要とするダイの発生パターンを認識する。 The user can arbitrarily select any of these settings as a criterion for the die bonder 1 to request verification. If the standard for requesting verification is the number of dies that require verification, the user selects this standard and sets the number of dies for executing verification. Further, when the standard for requesting verification is every fixed time, the user selects this standard and sets the standard for a fixed time (for example, 10 minutes). Although not shown, the verify management unit 2 includes a measurement unit for measuring the number of dies to be verified and a timer for measuring at regular time intervals. In addition, when setting the generation pattern of the die that requires verification, the user selects this criterion and sets the pattern (area, frequency, etc.) at which the die that requires verification occurs. I do. In this case, the pattern recognition unit 13 recognizes the generation pattern of the die that requires verification.
　要求部９は、ベリファイ要求設定部８に設定された条件を満たしたときに、ベリファイの要求や警告、ダイボンダ１のエラー停止の少なくともいずれかを行うものである。例えば、ユーザはベリファイ要求設定部８に、ベリファイすべきダイがｎ個（ｎは１以上の任意の数）蓄積されたときに、ベリファイを実行するという設定を行った場合、要求部９は、ベリファイすべきダイが、ベリファイ要求設定部８に設定されたｎ個に到達した場合、ベリファイが必要であることを警告する。警告方法は、ユーザがベリファイすべきであることを認識できる方法であれば、いずれの手段であってもよく、ダイボンダ１のアラーム機能（ブザー、画面表示、警告灯、ランプ）であったり、ベリファイ管理部２の一部を構成するパーソナルコンピュータ、スマートホン、タブレット等の画面表示、ランプ、ブザー、振動であったり、登録されたメールアドレスに電子メールを送信するものであったり等とすることができ、これらのいずれか又は複数の方法にて行うことができる。 The request unit 9 performs at least one of a verification request and a warning, and an error stop of the die bonder 1 when the conditions set in the verify request setting unit 8 are satisfied. For example, when the user sets the verification request setting unit 8 to execute verification when n dies to be verified (n is an arbitrary number of 1 or more) are accumulated, the request unit 9 sets the verification request setting unit 8. When the number of dies to be verified reaches n set in the verify request setting unit 8, it warns that verification is necessary. The warning method may be any method as long as the user can recognize that it should be verified, and may be the alarm function (buzzer, screen display, warning light, lamp) of the die bonder 1 or the verification method. It may be a screen display of a personal computer, a smartphone, a tablet, etc., a lamp, a buzzer, a vibration, or an e-mail sent to a registered e-mail address, which is a part of the management unit 2. It can be done by any or more of these methods.
　マップ管理部３は、ダイの集合体であるウエハのマップ情報を有するものであり、例えば、ＣＰＵ（Central Processing Unit）を中心としてＲＯＭ（Read Only Memory）やＲＡＭ（Random Access Memory）等がバスを介して相互に接続されたマイクロコンピュータで構成できる。なお、ＲＯＭには、ＣＰＵが実行するプログラムやデータが格納されている。マップ情報は、ウエハにおけるダイの位置と、それらのダイの良否の情報を含む製品ランク等が記憶されたものである。 The map management unit 3 has map information of a wafer, which is an aggregate of dies. For example, a ROM (Read Only Memory), a RAM (Random Access Memory), and the like are used as a bus centering on a CPU (Central Processing Unit). It can consist of microcomputers connected to each other via. The ROM stores programs and data executed by the CPU. The map information stores the positions of dies on the wafer and the product ranks including information on the quality of those dies.
　マップ管理部３は、マップ保持部１０と、ベリファイデータ保持部１１とを有する。マップ保持部１０は、各位置でのダイの良否について示しているマップ情報を保持するものである。ベリファイデータ保持部１１は、夫々のウエハ毎に、ベリファイ管理部２の情報を保有し、ベリファイが必要なダイの情報（位置及び付加情報）を記憶するものである。ベリファイデータ保持部１１は、マップ保持部１０が有するマップ情報に、ベリファイ管理部２の情報を書き込むものであってもよい。 The map management unit 3 has a map holding unit 10 and a verify data holding unit 11. The map holding unit 10 holds map information indicating the quality of the die at each position. The verify data holding unit 11 holds the information of the verify management unit 2 for each wafer, and stores the die information (position and additional information) that requires verification. The verify data holding unit 11 may write the information of the verify management unit 2 into the map information held by the map holding unit 10.
　本実施形態の半導体装置の組立システムは、夫々のダイボンダ１ａ、１ｂ、１ｃ・・・、ベリファイ管理部２、及びマップ管理部３に、半導体装置の組立プログラムをインストールすることで実現することができる。すなわち、本実施形態の半導体装置の組立プログラムは、半導体装置を組立てるダイボンダ１にてダイの検査を行い、検査されたダイを用いて半導体装置をダイボンダ１に組立てさせる半導体装置の組立プログラムにおいて、ダイの検査を実行するステップと、前記検査により再検査であるベリファイが必要とされたダイの位置、及びベリファイに必要な付加情報を記憶し、ダイボンダは、ベリファイが必要なダイを検査直後には組立に使用しないステップとを備えている。 The semiconductor device assembly system of the present embodiment can be realized by installing the semiconductor device assembly program in each of the die bonders 1a, 1b, 1c ..., the verify management unit 2, and the map management unit 3. .. That is, in the semiconductor device assembly program of the present embodiment, in the semiconductor device assembly program in which the die is inspected by the die bonder 1 for assembling the semiconductor device and the semiconductor device is assembled to the die bonder 1 using the inspected die. The steps to perform the inspection, the position of the die that required verification to be re-inspected by the inspection, and the additional information required for verification are stored, and the die bonder assembles the die that requires verification immediately after inspection. It has steps that are not used in.
　前記プログラムがインストールされた本実施形態の半導体装置の組立システムを使用して、半導体装置を組立てる方法を図２及び図３を用いて説明する。ダイボンダ１ａ、１ｂ、１ｃ・・・の基本動作を図２（ａ）に示す。以下、１台のダイボンダ１（１ａ）の動作について説明するが、夫々のダイボンダ１ａ、１ｂ、１ｃは独立して動作するものであり、他のダイボンダ１ｂ、１ｃ・・・もダイボンダ１ａと同様の動作を行っている。ダイボンダ１は、まず、マップ管理部３にウエハのマップデータを要求する（ステップＳ１）と、マップ管理部３は、ダイボンダ１にマップデータを送信する。 A method of assembling the semiconductor device using the semiconductor device assembly system of the present embodiment in which the program is installed will be described with reference to FIGS. 2 and 3. The basic operations of the die bonders 1a, 1b, 1c ... Are shown in FIG. 2A. Hereinafter, the operation of one die bonder 1 (1a) will be described, but each die bonder 1a, 1b, 1c operates independently, and the other die bonders 1b, 1c ... Are the same as those of the die bonder 1a. It is working. The die bonder 1 first requests the map management unit 3 for the map data of the wafer (step S1), and the map management unit 3 transmits the map data to the die bonder 1.
　ダイがピックアップポジションに移動して（ステップＳ２）、検査機構４によりダイの検査を実行し（ステップＳ３）、検査結果が良好であれば（検査に合格すれば）（ステップＳ４）ダイのピックアップを行い（ステップＳ５）所定位置にボンディングする。一方、検査機構４による検査結果が良好でない場合（検査に合格しない場合）（ステップＳ４）、そのダイをピックアップすることなく、装置を停止させないまま、そのダイの位置及び付加情報をベリファイ管理部２に通知して、ベリファイ管理部２の位置特定部５及び付加情報記憶部６はベリファイ情報を保存する（ステップＳ６）。これらの動作を繰り返し行う（ステップＳ７）。このように、検査結果が要ベリファイの場合でも、検査直後にはそのダイを組立に使用せず、ダイボンダ１は次のダイを使って生産を継続するため、ダイボンダ１は停止することなく動作することができる。ものである。ここで、「検査直後」とは、ダイを検査してから次のダイを検査するまでの間、又はそのダイを最後に装置停止する場合は装置停止までの間をいい、必ずしも時間的な直後を意味するものではない。 The die moves to the pickup position (step S2), the inspection mechanism 4 executes the die inspection (step S3), and if the inspection result is good (passes the inspection) (step S4), the die is picked up. (Step S5) Bonding is performed at a predetermined position. On the other hand, when the inspection result by the inspection mechanism 4 is not good (when the inspection does not pass) (step S4), the position and additional information of the die are verified by the verify management unit 2 without picking up the die and stopping the apparatus. The location specifying unit 5 and the additional information storage unit 6 of the verification management unit 2 store the verification information (step S6). These operations are repeated (step S7). In this way, even if the inspection result requires verification, the die bonder 1 does not use the die for assembly immediately after the inspection, and the die bonder 1 continues production using the next die, so that the die bonder 1 operates without stopping. be able to. It is a thing. Here, "immediately after inspection" means the period from the inspection of a die to the inspection of the next die, or the period until the device is stopped when the die is finally stopped, and is not necessarily immediately after the time. Does not mean.
　要求部９は、ベリファイ要求設定部８に設定された条件を満たしたときに、ベリファイの要求を行う。例えば、ユーザによりベリファイ要求設定部８に、ベリファイが必要なダイの数が、ベリファイ要求設定部８に設定された数に到達したときにベリファイの実行を要求すると設定した場合は、ダイボンダ１の要求部９がベリファイの要求を行う。ユーザは、予め、ベリファイ要求設定部８に、ベリファイを要求するための種々の設定から、いずれかの設定を選択している。例えば、ユーザやベリファイ管理部２からの要求があったとき、ウエハのロットエンド、装置エラー（ダイボンダ１のエラー）、一定時間毎、等がある。また、ユーザは、ベリファイ要求設定部８に、ベリファイを必要とするダイの発生パターンを設定してもよく、パターン認識部１２により、ベリファイが必要とされたダイの発生パターン（ベリファイが必要とされたダイが近隣のワークで複数発生しているか、発生頻度、特定の領域で発生しているか等）を認識して、ベリファイ要求設定部８に設定された発生パターンに該当したときに、要求部９がベリファイの要求を行うものであってもよい。 The request unit 9 makes a verify request when the conditions set in the verify request setting unit 8 are satisfied. For example, if the user sets the verify request setting unit 8 to request the execution of verification when the number of dies required for verification reaches the number set in the verify request setting unit 8, the request of the die bonder 1 is made. Part 9 makes a request for verification. The user has previously selected one of the various settings for requesting verification from the verify request setting unit 8. For example, when there is a request from the user or the verification management unit 2, there are a lot end of the wafer, an device error (an error of the die bonder 1), every fixed time, and the like. In addition, the user may set a die generation pattern that requires verification in the verify request setting unit 8, and the pattern recognition unit 12 may set a die generation pattern that requires verification (verification is required). When the occurrence pattern set in the verify request setting unit 8 is recognized by recognizing whether multiple dies are generated in neighboring workpieces, the frequency of occurrence, whether they are generated in a specific area, etc.), the request unit 9 may be the one that makes the verification request.
　ユーザ又はベリファイ機構は、図２（ａ）のダイボンダ１の動作の途中のいずれか任意のタイミングで図２（ｂ）のような動作を行う。ユーザは、ダイボンダ１において、ベリファイが要求されているか、警告状況を確認する（ステップＳ８）。警告は、ダイボンダ１のアラーム機能（ブザー、画面表示、警告灯、ランプ）であったり、ベリファイ管理部２の一部を構成するパーソナルコンピュータ、スマートホン、タブレット等の画面表示、ランプ、ブザー、振動であったり、登録されたメールアドレスに電子メールを送信するものであったり、等することができ、これらのいずれか又は複数の方法にて行うことができる。 The user or the verification mechanism performs the operation as shown in FIG. 2 (b) at any arbitrary timing during the operation of the die bonder 1 in FIG. 2 (a). The user confirms the warning status in the die bonder 1 to see if verification is requested (step S8). The warning is the alarm function (buzzer, screen display, warning light, lamp) of the die bonder 1, the screen display of personal computers, smartphones, tablets, etc. that form a part of the verify management unit 2, the lamp, buzzer, vibration. It can be, or it can send an e-mail to a registered e-mail address, etc., and it can be done by one or more of these methods.
　ベリファイが要求されていれば、ユーザはベリファイを実行し（ステップＳ９）、ベリファイ管理部２の結果記録部７は、ベリファイ結果の記録を行う（ステップＳ１０）。一方、ベリファイが要求されていなければ、ユーザはベリファイを実行しない。 If verification is requested, the user executes verification (step S9), and the result recording unit 7 of the verification management unit 2 records the verification result (step S10). On the other hand, if verification is not requested, the user does not perform verification.
　さらに、ダイボンダ１は、図２（ａ）の動作の途中のいずれか任意のタイミングで図２（ｃ）のような動作を行う。すなわち、ダイボンダ１は、ベリファイ管理部２の結果記録部７に、ユーザ又はベリファイ機構によるベリファイを実行した結果、生産可能なダイがあるかを要求すると（ステップＳ１１）、結果記録部７は、生産可能なダイの位置のデータを送信する。生産可能なダイがあれば、そのダイの位置に移動し（ステップＳ１２）、ダイのピックアップを行い（ステップＳ１３）所定位置にボンディングする。 Further, the die bonder 1 performs the operation as shown in FIG. 2 (c) at any arbitrary timing during the operation shown in FIG. 2 (a). That is, when the die bonder 1 requests the result recording unit 7 of the verification management unit 2 to have a die that can be produced as a result of executing the verification by the user or the verification mechanism (step S11), the result recording unit 7 produces. Send data on possible die positions. If there is a die that can be produced, the die is moved to the position of the die (step S12), the die is picked up (step S13), and the die is bonded to a predetermined position.
　ベリファイ実行済のダイ以外のダイは検査が未実行であるため、図２（ａ）の動作を行う。すなわち、次のダイへ移動して（ステップＳ２）、検査機構４によりダイの検査を実行して（ステップＳ３）、検査に合格すれば（ステップＳ４）ダイのピックアップを行い（ステップＳ５）所定位置にボンディングする。一方、検査機構４による検査に合格しない場合（ステップＳ４）、そのダイをピックアップすることなく、装置を停止させないままダイの位置及び付加情報をベリファイ管理部２に通知して、ベリファイ管理部２の位置特定部５及び付加情報記憶部６はベリファイ情報を保存する（ステップＳ６）。これらの動作を繰り返し行う（ステップＳ７）。 Since the inspection has not been executed for the dies other than the dies that have been verified, the operation shown in FIG. 2A is performed. That is, the die is moved to the next die (step S2), the die is inspected by the inspection mechanism 4 (step S3), and if the inspection is passed (step S4), the die is picked up (step S5) at a predetermined position. Bond to. On the other hand, if the inspection by the inspection mechanism 4 is not passed (step S4), the verification management unit 2 is notified of the die position and additional information without stopping the device without picking up the die, and the verification management unit 2 The position specifying unit 5 and the additional information storage unit 6 store the verification information (step S6). These operations are repeated (step S7).
　あるウエハにおいて、ピックアップ可能な全てのダイのボンディングが終了したときに、そのウエハにベリファイが必要なダイが残っている場合がある。その際にユーザのベリファイが実行されない場合は、そのウエハリングをしまい、次のウエハを出す必要がある。結果記録部７は、マップ管理部３のベリファイデータ保持部１１にその結果を送信する。これにより、マップ管理部３は、ベリファイが必要なダイを有するウエハがダイボンダ１から排出されても、ベリファイが必要なダイの情報を記憶している。または、ベリファイデータ保持部１１は、マップ保持部１０が有するマップ情報に、ベリファイ管理部２の情報を書き込むものであってもよい。従って、ウエハがダイボンダ１から排出されても、ユーザは、ダイのベリファイを実行することができる。 In a certain wafer, when the bonding of all the dies that can be picked up is completed, there may be a die that needs to be verified on the wafer. If the user's verification is not executed at that time, it is necessary to close the wafer ring and output the next wafer. The result recording unit 7 transmits the result to the verify data holding unit 11 of the map management unit 3. As a result, the map management unit 3 stores the information of the die that needs to be verified even if the wafer having the die that needs to be verified is ejected from the die bonder 1. Alternatively, the verify data holding unit 11 may write the information of the verify management unit 2 into the map information held by the map holding unit 10. Therefore, even if the wafer is ejected from the die bonder 1, the user can verify the die.
　第１実施形態の半導体装置の組立システム、半導体装置の組立方法、及び半導体装置の組立プログラムは、夫々のダイボンダ１ａ、１ｂ、１ｃ・・・はベリファイが必要なダイを、ベリファイが完了するまではピックアップすることなく次のダイへスキップして生産を継続する。すなわち、検査結果が要ベリファイの場合でも、夫々のダイボンダ１ａ、１ｂ、１ｃ・・・は次のダイを使用して生産を継続するため、ダイボンダ１ａ、１ｂ、１ｃ・・・は停止することなく動作することができ、生産性の向上を図ることができる。そして、ユーザやベリファイ機構は、生産中など任意のタイミングでベリファイを実行できるため、ユーザの作業性が向上する。しかも、ユーザやベリファイ機構は、位置特定部５及び付加情報記憶部６に蓄積された情報に基づいてベリファイを実行できるため、適切にベリファイを実行することができ、生産可能なダイのみを使用して高品質な半導体装置を組立てることができる。 In the semiconductor device assembly system, the semiconductor device assembly method, and the semiconductor device assembly program of the first embodiment, each die bonder 1a, 1b, 1c ... is a die that requires verification, until verification is completed. Skip to the next die and continue production without picking up. That is, even if the inspection result requires verification, each die bonder 1a, 1b, 1c ... Continues production using the next die, so that the die bonders 1a, 1b, 1c ... Do not stop. It can operate and improve productivity. Then, since the user and the verification mechanism can execute the verification at an arbitrary timing such as during production, the workability of the user is improved. Moreover, since the user and the verification mechanism can execute the verification based on the information accumulated in the position identification unit 5 and the additional information storage unit 6, the verification can be appropriately executed and only the die that can be produced is used. It is possible to assemble high quality semiconductor devices.
　図４は、第２実施形態の半導体装置の組立システムを示す。第２実施形態の組立システムは、データ整理部１３と表示部１４とを備える。表示部１４は、検査機構４の検査により再検査であるベリファイが必要とされたダイの位置及びベリファイに必要な付加情報を表示するものであり、例えば、ダイボンダ１の画面、パーソナルコンピュータ、スマートホン、タブレット等の画面である。 FIG. 4 shows the semiconductor device assembly system of the second embodiment. The assembly system of the second embodiment includes a data organizing unit 13 and a display unit 14. The display unit 14 displays the position of the die for which verification, which is a re-inspection, is required by the inspection of the inspection mechanism 4, and additional information necessary for verification. For example, the screen of the die bonder 1, a personal computer, and a smartphone. , The screen of a tablet, etc.
　データ整理部１３は、ベリファイが必要なダイの情報を整理するものであり、データの計算・並び替えや表示内容を生成する。例えばベリファイ管理部（図４では図示省略）にサーバを有し、サーバ側のソフトでデータの計算・並び替えや表示内容を生成し、クライアント側に置かれたパーソナルコンピュータ、スマートホン、タブレットのクライアントソフト（例えばＷｅｂブラウザ）の表示部１４に表示される。 The data organizing unit 13 organizes die information that needs to be verified, and calculates / rearranges data and generates display contents. For example, the verify management unit (not shown in Fig. 4) has a server, and the software on the server side calculates and sorts the data and generates the display contents, and the client of the personal computer, smartphone, and tablet placed on the client side. It is displayed on the display unit 14 of the software (for example, a Web browser).
　本実施形態において、データ整理部１３は、ベリファイが必要なダイをダイボンダ１の稼働率が高くなるよう順位づけする。「ダイボンダ１の稼働率が高くなるような順位づけ」とは、例えば、ウエハーフレームの交換が近づいているものを高い順位にする等、ベリファイを必要とする緊急度合に応じた順位づけである。すなわち、ウエハーフレームの交換後（ダイボンダ１から排出された後）にベリファイが行われた場合に、ベリファイにより使用が可能とされたダイを生産に使用するためには、再度そのウエハーフレームを交換（ダイボンダ１にセット）する作業が発生し、生産性が低下する。このため、ウエハーフレームの交換前のタイミングでベリファイが行われるように、高い順位としてユーザに提示することにより、生産性を落とすことなく効率的な生産が可能となる。 In the present embodiment, the data organizing unit 13 ranks the dies that need to be verified so that the operation rate of the die bonder 1 is high. The "ranking that increases the operating rate of the die bonder 1" is a ranking according to the degree of urgency that requires verification, for example, a higher ranking is given to those that are approaching wafer frame replacement. That is, when verification is performed after the wafer frame is replaced (after being discharged from the die bonder 1), the wafer frame is replaced again (in order to use the die enabled by verification for production). The work of setting the wafer on the die bonder 1) occurs, and the productivity decreases. Therefore, by presenting the wafer frame to the user in a high order so that the verification is performed at the timing before the replacement of the wafer frame, efficient production can be performed without reducing the productivity.
　データ整理部１３は、付加情報を使用して、ベリアフィが必要なダイの順位づけを行ってもよい。例えば、欠陥サイズ（付加情報）ごとに順位を決定すれば（大きい欠陥を高い順位とする）、大きい欠陥からベリファイを実行することができ、比較的順位の高いダイについては、ベリファイスキルが低いユーザやベリファイ機構でもベリファイを実行でき、ベリファイ能力がユーザやベリファイ機構の限度に達すると、それ以降のダイ（比較的順位の低いダイ）については、ベリファイスキルが高い他のユーザやベリファイ機構にてベリファイを実行する等の対応ができ、ベリファイ効率の向上を図ることができる。 The data organizing unit 13 may use the additional information to rank the dies that require beliafi. For example, if the ranking is determined for each defect size (additional information) (larger defects are ranked higher), verification can be performed from the largest defects, and for dies with relatively high rankings, users with low verification skills And the verify mechanism can also perform verify, and when the verify ability reaches the limit of the user and the verify mechanism, the subsequent dies (dies with a relatively low rank) are verified by other users with high verification skills and the verify mechanism. It is possible to improve the verification efficiency by taking measures such as executing.
　前記のように、データ整理部１３によるダイの順位づけは、ダイボンダ１の稼働率に基づいて決定してもよいし、付加情報に基づいて決定してもよいし、ダイボンダ１の稼働率と付加情報との両方に基づいて決定してもよい。さらには、その他の要素に基づいて決定してもよい。 As described above, the ranking of dies by the data organizing unit 13 may be determined based on the operating rate of the die bonder 1, may be determined based on additional information, or may be determined based on the operating rate of the die bonder 1 and the addition. It may be decided based on both information. Furthermore, it may be decided based on other factors.
　さらに、データ整理部１３は、順位づけされた情報に基づいて、表示部１４に表示すべきダイの表示順序を決定する。すなわち、複数の品種が混在している場合に、順位づけが高いダイから順に表示すると、種々の品種がランダムに表示されることがあり、ベリファイの作業性が低下する。このため、データ整理部１３は、順位づけされたダイを、さらに品種ごとにグループ分けすることにより、表示部１４には、優先順位の高いダイをグループ毎に表示することになる。 Further, the data organizing unit 13 determines the display order of the dies to be displayed on the display unit 14 based on the ranked information. That is, when a plurality of varieties are mixed and displayed in order from the die having the highest ranking, various varieties may be displayed randomly, and the workability of verification is lowered. Therefore, the data organizing unit 13 further groups the ranked dies by type, so that the display unit 14 displays the dies with high priority for each group.
　表示部１４は、ベリファイ実行後のダイのベリファイ情報の結果（ＯＫ／ＮＧ）を入力する結果入力部１５を表示する。表示部１４の表示方法の一例として、ベリファイが必要な一のダイの情報（例えば、ダイの画像や、付加情報や、画像と付加情報の両方等）と、そのダイのベリファイ結果入力部１５とを同時に表示し、情報が表示されているダイのベリファイ結果（ＯＫ／ＮＧ）が結果入力部１５に入力されると、次のダイの画像に表示を切り替えるようにする。前記したように、表示部１４には、ベリファイが必要とされたダイについて、順位づけに基づいて表示される。この場合、例えば、１回の画面表示で、複数のダイの情報が上方から下方に向かって並ぶリスト状となっている場合には、最上位に優先順位が最も高いダイが表示され、下のダイになる程、優先順位が下がっていくように表示される。また、１回の画面表示で１つのダイの情報を表示する場合は、最初に優先順位が最も高いダイが表示され、後のダイになる程、優先順位が下がっていくように表示される。 The display unit 14 displays the result input unit 15 for inputting the result (OK / NG) of the verification information of the die after the verification is executed. As an example of the display method of the display unit 14, information on one die that needs to be verified (for example, an image of the die, additional information, both the image and the additional information, etc.) and the verification result input unit 15 of the die. Is displayed at the same time, and when the verification result (OK / NG) of the die on which the information is displayed is input to the result input unit 15, the display is switched to the image of the next die. As described above, the display unit 14 displays the dies for which verification is required based on the ranking. In this case, for example, when the information of a plurality of dies is arranged in a list from top to bottom in one screen display, the die with the highest priority is displayed at the top and the die with the highest priority is displayed at the bottom. The higher the die, the lower the priority is displayed. Further, when displaying the information of one die on one screen display, the die having the highest priority is displayed first, and the die with the higher priority is displayed so that the priority is lowered as the die becomes later.
　第２実施形態の半導体装置の組立システムでも、前記第１実施形態の半導体装置の組立システムと同様の作用効果を奏する。特に、第２実施形態では、データ整理部１３を設けたことにより、生産性を落とすことなく効率的な生産が可能となる。なお、図４に示す半導体装置の組立システムにおいて、前記第１実施形態の半導体装置の組立システムと同一の構成については、図１と同一符号を付して説明を省略する。第２実施形態において、第１実施形態の位置特定部５、付加情報記憶部６、結果記録部７、パターン認識部１２を有していてもよい。データ整理部１３と表示部１４とは別端末に夫々設けられても、同一端末に設けられてもよい。 The semiconductor device assembly system of the second embodiment also has the same action and effect as the semiconductor device assembly system of the first embodiment. In particular, in the second embodiment, by providing the data organizing unit 13, efficient production can be achieved without reducing the productivity. In the semiconductor device assembly system shown in FIG. 4, the same configurations as those of the semiconductor device assembly system of the first embodiment are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted. In the second embodiment, the position specifying unit 5, the additional information storage unit 6, the result recording unit 7, and the pattern recognition unit 12 of the first embodiment may be provided. The data organizing unit 13 and the display unit 14 may be provided on different terminals, or may be provided on the same terminal.
　第１実施形態及び第２実施形態の位置特定部５、付加情報記憶部６、結果記録部７、ベリファイ要求設定部８、要求部９、パターン認識部１２、データ整理部１３、表示部１４は、本システムにおいて、任意の場所に設けることができる。例えば、表示部１４は、付加情報記憶部６とネットワークで接続されたデバイスであればよく、組立装置（ダイボンダ１）の画面であってもよいし、ベリファイ要求設定部８や要求部９をベリファイ管理部２に設けたりすることができる。図面上、同一端末として図示されている構成（例えば、位置特定部５、付加情報記憶部６、結果記録部７パターン認識部１２）は、これらがシステム上存在すればよく、必ずしも同一端末に設けられる必要はない。例えば、位置特定部５と付加情報記憶部６とが夫々別端末に設けられていてもよい。 The position identification unit 5, the additional information storage unit 6, the result recording unit 7, the verify request setting unit 8, the request unit 9, the pattern recognition unit 12, the data organization unit 13, and the display unit 14 of the first embodiment and the second embodiment are , In this system, it can be installed at any place. For example, the display unit 14 may be a device connected to the additional information storage unit 6 via a network, may be a screen of an assembly device (die bonder 1), or may verify the verify request setting unit 8 and the request unit 9. It can be provided in the management unit 2. The configurations (for example, the position specifying unit 5, the additional information storage unit 6, and the result recording unit 7 pattern recognition unit 12) shown as the same terminal in the drawings need only be present in the system and are not necessarily provided in the same terminal. You don't have to be. For example, the position specifying unit 5 and the additional information storage unit 6 may be provided in separate terminals.
　以上、本発明の実施形態につき説明したが、本発明は前記実施形態に限定されることなく種々の変形が可能であって、ベリファイを要求するための設定は、夫々のダイボンダ毎に個別に行うことができる。例えば、ダイボンダ１（１ａ）ではベリファイが必要なダイの数が５０個に到達した場合、ダイボンダ２（１ｂ）ではベリファイが必要なダイの数が１００個に到達した場合、等とすることができる。また、全てのダイボンダ１において基準を同一にする必要はなく、例えば、ダイボンダ１（１ａ）ではベリファイを実行するためのダイの数を基準とし、ダイボンダ２（１ｂ）では一定時間毎、等として、夫々のダイボンダ１で異なる基準としてもよい。 Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made, and the setting for requesting verification is individually performed for each die bonder. be able to. For example, in die bonder 1 (1a), the number of dies requiring verification reaches 50, in die bonder 2 (1b), the number of dies requiring verification reaches 100, and so on. .. Further, it is not necessary for all die bonders 1 to have the same standard. For example, in die bonder 1 (1a), the number of dies for executing verification is used as a reference, and in die bonder 2 (1b), the standard is set every fixed time, and so on. Each die bonder 1 may have different criteria.
　要ベリファイになったダイ（ベリファイが必要とされたダイ）について、必ずしもベリファイを実行する必要はなく、要ベリファイのダイをベリファイせずに生産に使用してもよい。この場合、ベリファイ管理部に、要ベリファイを取り消す取り消し部があってもよいし、ユーザ等の判断で、要ベリファイになったダイを使用してもよい。例えば、ダイが単独で要ベリファイとなるような場合は、軽度のエラーであるとして擬似的にベリファイ不要としてダイを組立に使用したい場合がある。このような場合は、一度要ベリファイになったダイであっても、そのダイを組立に使用してもよい。 It is not always necessary to perform verification on the die that requires verification (the die that requires verification), and the die that requires verification may be used for production without verification. In this case, the verify management unit may have a cancel unit for canceling the verification required, or a die that has become the verification required may be used at the discretion of the user or the like. For example, when the die alone requires verification, it may be desired to use the die for assembly because it is a minor error and verification is not required in a pseudo manner. In such a case, even if the die has been verified once, the die may be used for assembly.
　半導体装置の組立装置はダイボンダに限らず、マウンター等であってもよい。実施形態のように、組立装置が複数ある場合に特に有効ではあるが、組立装置は１台であってもよい。ベリファイ管理部２は組立装置の中に設けてもよい。検査機構４よる検査はピックアップ時に行うものであっても、マウント時に行うものであっても、それ以外に行うものであってもよい。 The semiconductor device assembly device is not limited to the die bonder, but may be a mounter or the like. Although it is particularly effective when there are a plurality of assembly devices as in the embodiment, the number of assembly devices may be one. The verify management unit 2 may be provided in the assembly device. The inspection by the inspection mechanism 4 may be performed at the time of pickup, at the time of mounting, or at other times.
１　　 ダイボンダ
２     ベリファイ管理部
３　   マップ管理部
４　   検査機構
５     位置特定部
６　   付加情報記憶部
７　   結果記録部
８     設定部
９　   要求部
１１　   ベリファイデータ保持部
１２　   パターン認識部
１３　   データ整理部
１４　   表示部
１５　　 結果入力部 1 Die bonder 2 Verify management unit 3 Map management unit 4 Inspection mechanism 5 Position identification unit 6 Additional information storage unit 7 Result recording unit 8 Setting unit 9 Request unit 11 Verify data holding unit 12 Pattern recognition unit 13 Data organization unit 14 Display unit 15 Result Input section

Claims (15)

  1. 　検査機構により検査を行った個片体を用いて半導体装置を組立てる組立装置を備えた半導体装置の組立システムにおいて、
    　検査機構の検査により再検査であるベリファイが必要とされた個片体の、ベリファイに必要な付加情報を記憶する付加情報記憶部を備え、
    　前記半導体装置の組立装置は、検査機構の検査によりベリファイが必要とされた個片体の付加情報を前記付加情報記憶部に通知して、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は、ベリファイが必要とされた個片体を組立に使用しないことを特徴とする半導体装置の組立システム。     In a semiconductor device assembly system equipped with an assembly device for assembling a semiconductor device using individual pieces inspected by an inspection mechanism.
    Equipped with an additional information storage unit that stores additional information required for verification of individual pieces that required verification, which is a re-inspection by inspection by the inspection mechanism.
    The assembling device of the semiconductor device notifies the additional information storage unit of additional information of the individual piece whose verification is required by the inspection of the inspection mechanism, and at least inspects or assembles the individual piece to be inspected next. An assembly system for semiconductor devices, characterized in that individual pieces that require verification are not used for assembly until the end.
  2. 　ベリファイ実行後の個片体のベリファイ情報を記録する結果記録部を備えたことを特徴とする請求項１に記載の半導体装置の組立システム。 The semiconductor device assembly system according to claim 1, further comprising a result recording unit that records verification information of individual pieces after verification is executed.
  3. 　検査機構により検査を行った個片体を用いて半導体装置を組立てる組立装置を備えた半導体装置の組立システムにおいて、
      検査機構の検査により再検査であるベリファイが必要とされた個片体の、ベリファイに必要な付加情報を表示する表示部を備え、
      検査機構の検査によりベリファイが必要とされた個片体を、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は組立に使用しないことを特徴とする半導体装置の組立システム。     In a semiconductor device assembly system equipped with an assembly device for assembling a semiconductor device using individual pieces inspected by an inspection mechanism.
    Equipped with a display unit that displays additional information required for verification of individual pieces that required verification, which is a re-inspection by inspection by the inspection mechanism.
    An assembly system for a semiconductor device, characterized in that the individual pieces required to be verified by the inspection of the inspection mechanism are not used for assembly until at least the inspection of the next individual piece to be inspected or the end of assembly. ..
  4. 　前記表示部は、ベリファイ実行後の個片体のベリファイ情報の結果を入力する結果入力部を表示することを特徴とする請求項３に記載の半導体装置の組立システム。 The semiconductor device assembly system according to claim 3, wherein the display unit displays a result input unit for inputting the result of the verification information of the individual piece after the verification is executed.
  5.   前記表示部は、ベリファイが必要とされた個片体の情報と、前記ベリファイ結果入力部とを同時に表示し、表示されている個片体のベリファイ結果が結果入力部に入力されると、次のベリファイが必要な個片体の情報に表示を切り替えることを特徴とする請求項４に記載の半導体装置の組立システム。 The display unit simultaneously displays the information of the individual piece for which verification is required and the verification result input unit, and when the verified result of the displayed individual piece is input to the result input unit, the following The semiconductor device assembly system according to claim 4, wherein the display is switched to individual piece information that requires verification.
  6.   ベリファイが必要な個片体の情報を整理するデータ整理部を備え、前記データ整理部は、ベリファイが必要な個片体を前記組立装置の稼働率が高くなるよう順位づけし、順位づけされた情報に基づいて前記表示部に表示すべき個片体の表示順序を決定することを特徴とする請求項２から請求項５のいずれか１項に記載の半導体装置の組立システム。 It is provided with a data organizing unit that organizes information on individual pieces that require verification, and the data organizing unit ranks and ranks the individual pieces that require verification so that the operating rate of the assembly device is high. The assembly system for a semiconductor device according to any one of claims 2 to 5, wherein the display order of the individual pieces to be displayed on the display unit is determined based on the information.
  7.   ベリファイが必要な個片体の情報を整理するデータ整理部を備え、前記データ整理部は、ベリファイが必要な個片体を付加情報に基づいて順位づけし、順位づけされた情報に基づいて前記表示部に表示すべき個片体の表示順序を決定することを特徴とする請求項２から請求項５のいずれか１項に記載の半導体装置の組立システム。 It is provided with a data organizing unit that organizes information on individual pieces that require verification, and the data organizing unit ranks individual pieces that require verification based on additional information, and the data organizing unit is based on the ranked information. The semiconductor device assembly system according to any one of claims 2 to 5, wherein the display order of the individual pieces to be displayed on the display unit is determined.
  8. 　ベリファイを要求するための設定を行うベリファイ要求設定部を備え、前記ベリファイ要求設定部に設定された条件を満たしたときに、ベリファイの要求、警告、半導体装置の組立装置のエラー停止の少なくともいずれかを行うことを特徴とする請求項１から請求項７のいずれか１項に記載の半導体装置の組立システム。 It is provided with a verify request setting unit for making settings for requesting verification, and when the conditions set in the verify request setting unit are satisfied, at least one of a verification request, a warning, and an error stop of the semiconductor device assembly device. The semiconductor device assembly system according to any one of claims 1 to 7, wherein the method is performed.
  9. 　ベリファイが必要とされた個片体の発生パターンを認識するパターン認識部を備え、前記ベリファイ要求設定部に設定された発生パターンに該当したときに、ベリファイの要求、警告、半導体装置の組立装置のエラー停止の少なくともいずれかを行うことを特徴とする請求項８に記載の半導体装置の組立システム。 It is equipped with a pattern recognition unit that recognizes the generation pattern of individual pieces for which verification is required, and when the generation pattern set in the verification request setting unit is met, a verification request, warning, and semiconductor device assembly device The semiconductor device assembly system according to claim 8, wherein at least one of the error stops is performed.
  10. 　個片体の集合体であるワークのマップ情報を有するマップ管理部を備え、マップ管理部は、ベリファイが必要な個片体の情報を記憶するベリファイデータ保持部を有することを特徴とする請求項１から請求項９のいずれか１項に記載の半導体装置の組立システム。 A claim comprising a map management unit having map information of a work that is an aggregate of individual pieces, and the map management unit having a verification data holding unit for storing information of individual pieces that require verification. The semiconductor device assembly system according to any one of claims 1 to 9.
  11. 　前記付加情報は、個片体の集合体であるワークの情報、前記半導体装置の組立装置の情報、前記検査機構の検査状態の情報、前記検査機構による検査結果の情報、前記検査機構による検査以外での個片体の情報のいずれかであることを特徴とする請求項１から請求項１０のいずれか１項に記載の半導体装置の組立システム。 The additional information includes information on a work that is an aggregate of individual pieces, information on an assembly device of the semiconductor device, information on an inspection state of the inspection mechanism, information on inspection results by the inspection mechanism, and inspection by the inspection mechanism. The semiconductor device assembly system according to any one of claims 1 to 10, wherein the information is one of the pieces of information in the above.
  12. 　複数の半導体装置の組立装置を備えたことを特徴とする請求項１から請求項１１のいずれか１項に記載の半導体装置の組立システム。 The semiconductor device assembly system according to any one of claims 1 to 11, wherein a plurality of semiconductor device assembly devices are provided.
  13. 　前記半導体装置の組立装置は、ダイボンダであることを特徴とする請求項１から請求項１２のいずれか１項に記載の半導体装置の組立システム。 The semiconductor device assembly system according to any one of claims 1 to 12, wherein the semiconductor device assembly device is a die bonder.
  14. 　半導体装置を組立てる組立装置にて個片体の検査を行い、検査された個片体を用いて半導体装置を組立てる半導体装置の組立方法において、
    　個片体の検査を実行し、
    前記検査により再検査であるベリファイが必要な個片体の、ベリファイに必要な付加情報を記憶し、前記組立装置は、ベリファイが必要とされた個片体を、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は組立に使用しないことを特徴とする半導体装置の組立方法。     In the method of assembling a semiconductor device, which inspects individual pieces with an assembly device for assembling a semiconductor device and assembles a semiconductor device using the inspected individual pieces.
    Perform individual body inspection and
    The assembly device stores the additional information required for verification of the individual pieces that require verification, which is a re-inspection by the inspection, and the assembling device sets the individual pieces that require verification to at least the next inspection target. A method for assembling a semiconductor device, which is not used for assembly until the inspection of one body or the end of assembly.
  15. 　半導体装置を組立てる組立装置にて個片体の検査を行い、検査された個片体を用いて半導体装置を組立装置に組立てさせる半導体装置の組立プログラムにおいて、
    　個片体の検査を実行するステップと、
    前記検査により再検査であるベリファイが必要とされた個片体の、ベリファイに必要な付加情報を記憶し、前記組立装置は、ベリファイが必要な個片体を、少なくとも次の検査対象となる個片体の検査又は組立終了時までの間は組立に使用しないステップとを備えたことを特徴とする半導体装置の組立プログラム。     In the semiconductor device assembly program, in which individual pieces are inspected by the assembly device that assembles the semiconductor device, and the semiconductor device is assembled into the assembly device using the inspected individual pieces.
    Steps to perform individual body inspection and
    The assembly device stores the additional information required for verification of the individual pieces that need to be re-inspected by the inspection, and the assembling device sets the individual pieces that need to be verified to at least the next inspection target. An assembly program for a semiconductor device, characterized in that it includes steps that are not used for assembly until the end of inspection or assembly of one body.
PCT/JP2019/011097 2019-03-18 2019-03-18 System for assembling semiconductor device, method for assembling semiconductor device, and program for assembling semiconductor device WO2020188678A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019515547A JP6621964B1 (en) 2019-03-18 2019-03-18 Semiconductor device assembly system, semiconductor device manufacturing method using semiconductor device assembly method, and semiconductor device assembly program
PCT/JP2019/011097 WO2020188678A1 (en) 2019-03-18 2019-03-18 System for assembling semiconductor device, method for assembling semiconductor device, and program for assembling semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/011097 WO2020188678A1 (en) 2019-03-18 2019-03-18 System for assembling semiconductor device, method for assembling semiconductor device, and program for assembling semiconductor device

Publications (1)

Publication Number Publication Date
WO2020188678A1 true WO2020188678A1 (en) 2020-09-24

Family

ID=68917213

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/011097 WO2020188678A1 (en) 2019-03-18 2019-03-18 System for assembling semiconductor device, method for assembling semiconductor device, and program for assembling semiconductor device

Country Status (2)

Country Link
JP (1) JP6621964B1 (en)
WO (1) WO2020188678A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194632A (en) * 1986-02-21 1987-08-27 Hitachi Ltd Manufacturing equipment
JPH01125839A (en) * 1987-11-10 1989-05-18 Tokyo Electron Ltd Inspection
JP2007235031A (en) * 2006-03-03 2007-09-13 Advantest Corp Semiconductor testing device
WO2013161061A1 (en) * 2012-04-27 2013-10-31 富士機械製造株式会社 Wafer map management device and die mounting method of die mounting system
JP2019029611A (en) * 2017-08-03 2019-02-21 ファスフォードテクノロジ株式会社 Die bonding device and semiconductor device manufacturing method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2627929B2 (en) * 1988-07-01 1997-07-09 東京エレクトロン株式会社 Inspection device
US5360747A (en) * 1993-06-10 1994-11-01 Xilinx, Inc. Method of reducing dice testing with on-chip identification
JPH0997820A (en) * 1995-09-28 1997-04-08 Nec Kyushu Ltd Semiconductor wafer
JP3960872B2 (en) * 2002-07-19 2007-08-15 Ｎｅｃエレクトロニクス株式会社 Prober apparatus and semiconductor device inspection method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194632A (en) * 1986-02-21 1987-08-27 Hitachi Ltd Manufacturing equipment
JPH01125839A (en) * 1987-11-10 1989-05-18 Tokyo Electron Ltd Inspection
JP2007235031A (en) * 2006-03-03 2007-09-13 Advantest Corp Semiconductor testing device
WO2013161061A1 (en) * 2012-04-27 2013-10-31 富士機械製造株式会社 Wafer map management device and die mounting method of die mounting system
JP2019029611A (en) * 2017-08-03 2019-02-21 ファスフォードテクノロジ株式会社 Die bonding device and semiconductor device manufacturing method

Also Published As

Publication number Publication date
JPWO2020188678A1 (en) 2021-04-01
JP6621964B1 (en) 2019-12-18

Similar Documents

Publication Publication Date Title
JP5968705B2 (en) Manufacturing method of semiconductor device
KR101700904B1 (en) A semiconductor device and electronic device with discrete component backward traceability and forward traceability
JP4767995B2 (en) Component mounting method, component mounting machine, mounting condition determining method, mounting condition determining apparatus, and program
CN109561651B (en) SMT patch element position control method and system
JP2020013841A (en) Semiconductor manufacturing device and method for manufacturing semiconductor device
TWI621191B (en) Method and system for remotely monitoring wafer testing equipment
JP2016217861A (en) Inspection device, inspection method, and program used in inspection device
JP4788678B2 (en) Component mounting state inspection method
TWI601224B (en) Wafer classification device and wafer classification method, control program product, readable storage medium
WO2020188678A1 (en) System for assembling semiconductor device, method for assembling semiconductor device, and program for assembling semiconductor device
JP7082862B2 (en) Die bonding equipment, semiconductor equipment manufacturing method and semiconductor manufacturing system
US6177287B1 (en) Simplified inter database communication system
JP6880158B1 (en) Work transfer device, work transfer method, transfer body manufacturing method, semiconductor device manufacturing method, and die bonder
JP2018054464A (en) Electronic component conveyance device and electronic component inspection device
JP2008186879A (en) Substrate inspection method
JP6185492B2 (en) Individual component backward traceability and semiconductor device forward traceability
JP4992934B2 (en) Chip inspection apparatus and chip inspection method
JP3356569B2 (en) Semiconductor production management system
KR20150104766A (en) Tracking method for badness history in inspection process
JP2008147443A (en) Process control system, and process control method
EP3553813B1 (en) Die component supply device
TWI389245B (en) Chip sorter with prompt chip pre-position and optical examining process thereof
JPH09148387A (en) Apparatus for processing semiconductor product
JP2003037121A (en) Method for manufacturing semiconductor device
KR101572927B1 (en) Inspection method for remotely monitoring in inspection process

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2019515547

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19920388

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19920388

Country of ref document: EP

Kind code of ref document: A1