JPH09148387A - Apparatus for processing semiconductor product - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively perform wafer test, appearance check, and die bonding of a wafer on which a chip having different functions is formed. SOLUTION: Product type information 15 and quality determination result 16 for each chip are stored as chip map data 41 in association with a wafer identifier 14. Chip map data 42 corresponding to a wafer identifier 26 is taken from the data 41, and the quality information of the chips is displayed so that appearance check is performed only for good products. The chip map data of the chips which have been determined as defective products are changed from good products to defective products, and only good products of chip map data 43 are selected so that die bonding is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor product processing apparatus.

[0002]

2. Description of the Related Art A conventional semiconductor processing apparatus optically reads a wafer identifier 82 attached to a wafer 83 in a contactless manner as shown in FIG. I am trying to process it. (For example, JP-A-59-11618). Further, the conventional semiconductor processing apparatus recognizes the wafer identifier 82 of the wafer for which the wafer test is completed, as shown in FIG. 3, and acquires characteristic data and position data for each chip corresponding to the wafer identifier 82 from the wafer test apparatus. It is read into the control unit at high speed by compression, and is decoded to die-bond only "good products" belonging to the supported rank. (For example, JP-A-4-2625
No. 43).

[0003]

In this conventional semiconductor processing apparatus, in a wafer test in which chips having different functions are formed on the same wafer, wafers having different functions can be processed by a single inspection program at a time. It cannot be inspected. Then, there is a problem that the chip and the tester cannot be connected with a single probe card (a jig for electrically connecting the chip and the wafer test device), and thus the inspection cannot be performed.

Further, in Japanese Patent Laid-Open No. 4-262543,
Since there is no marking on the chip that indicates "defective product" in the wafer test, it is not possible to distinguish between "good product" and "defective product" in the visual inspection after the wafer test, so select "good product" only. However, there is a problem that the appearance inspection cannot be performed. Furthermore, in die bonding, the individual chips are completely separated from the wafer, the type information of the chips recognized on the wafer cannot be used at all, and the pads with different functions have different pad positions. You must use frames. Therefore, in the conventional device that performs die bonding with a single lead frame, there is a problem that chips having different functions are mounted on the same lead frame.

[0005]

The semiconductor processing apparatus of the present invention takes in chip map data consisting of product types of all chips on the wafer and quality judgment results by the wafer identifier, and marks the wafer surface with defects. It is an apparatus for processing a wafer without performing the above, and is composed of a wafer appearance inspection apparatus for inspecting the appearance of the wafer and a die bonding apparatus for die-bonding chips on the wafer onto a lead frame. That is, a wafer identification unit that takes in a wafer identifier, an XY stage that moves the wafer, an image recognition unit that corrects the position of the chip, a display unit that displays the pass / fail information of the chip, and change or change the pass / fail information of the chip map data. An operation unit for setting the feeder unit, a pickup unit for picking up chips, a multi-feeder unit that can simultaneously supply multiple types of lead frames according to the number of product types of chips on the wafer, and for communication It has a control unit for exchanging chip map data via a bus and controlling these peripheral function blocks.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION In a semiconductor product processing apparatus according to the present invention, product type information of each of several types of chips having different functions prefabricated on a wafer and pass / fail information of each chip obtained by a wafer test, Is stored as chip map data, and when these wafers are set in the wafer visual inspection apparatus, the chip map data corresponding to the wafer identifier is taken into the control unit, and the pass / fail information for the wafer visual inspection chip is displayed. Only select "good" and inspect. If the inspected chip is determined to be "defective", enter "defective" from the operation unit, and the control unit sets the corresponding chip map data from "good" to "good". Defective product "
Change to and save. The wafer that has undergone the wafer visual inspection is set in the die bonding device, the chip map data corresponding to the wafer identifier is imported to the control unit, and X is determined based on the “good” coordinates obtained from the chip map data.
-The wafer is moved using the Y stage, the image recognition unit recognizes the chip, measures the amount of deviation from the collet suction position, further moves the XY stage to correct the chip position, and then the pickup unit moves the chip. It is picked up and die-bonded on the lead frame of the multi-feeder part corresponding to the product type of the picked-up chip. Therefore, it is possible to select only "non-defective products" on the wafer for wafer appearance inspection without making defective markings on the wafer and to accurately die-bond a plurality of types of products collectively for each product type.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the electrical configuration of an embodiment of the present invention. In the wafer test apparatus 1, the chip map data 41 corresponding to the wafer identifier 14 fetched from the wafer identification unit 12 is transferred from the communication bus 4 to the control unit 1.
1, the test program is switched by the test section 13 for each chip based on the product type information 15 contained in the chip map data 41, and the non-defective product judgment result 16 for each chip is added to the chip map data 41. Is. The wafer visual inspection device 2 includes a wafer identification unit 22.
The chip map data 42 corresponding to the wafer identifier 26 taken in from the communication bus 4 is taken into the control unit 21, and the pass / fail information 27 corresponding to the position information 28 of the wafer visual inspection chip selected in the XY table 24. Is extracted from the chip map data 42 and displayed on the display unit 23, only the “non-defective product” is selected and the wafer appearance inspection is performed, and the pass / fail judgment result 29 as the inspection result is displayed on the operation unit 25.
It is input from the and added to the chip map data 42. The die bonding apparatus 3 has the feeder setting information 3
D is input to the control unit 31 from the operation unit 34, is set in each lead frame feeder in the multi-feeder unit 37, sets the product type corresponding to the degree frame, and receives the wafer identifier 38 from the wafer identification unit 32. The chip map data 43 corresponding to the above is fetched from the communication bus 4 into the control unit 31, the control unit 31 generates the XY table coordinate data 3C of "good" from the chip map data 43, and the XY table 35 is used to generate the die The bonding chip is moved to a position where image recognition can be performed, and the image recognition unit 33
While recognizing the die-bonded chip, the amount of deviation between the collet suction position and the current die-bonded chip is sent to the control unit 31 as position correction information XY.
Move the die-bonding chip on the table 35,
After the correction is completed, the pickup signal 3B is picked up by the pickup unit 36.
, The die-bonding chip is sucked and transported by the collet, the product type of the die-bonding chip is read from the chip map data 43, and die-bonded to the lead frame on the multi-feeder unit 37 corresponding to the preset product type. To do.

Next, a wafer manufacturing flow in each apparatus of FIG. 1 will be described with reference to the flowchart of FIG. A wafer in which several types of chips having completely different functions are formed on the same wafer (step 51) is tested by the wafer test apparatus 1 and the pass / fail result determined for each chip is added to the chip map data 41 (step 52). ), The wafer is attached to a sheet so that the chips do not scatter after dicing (step 53), the chips on the wafer are completely cut into individual chips with a dicing saw (step 54), and the wafer appearance inspection apparatus 2 performs a wafer test. The wafer appearance inspection is performed on the chips that are “non-defective” in the above, and the pass / fail judgment result 29 is added to the chip map data 42 (step 55), and the wafer test (step 52) and the wafer appearance inspection (step 55) "Good product"
The chip determined to be die-bonded is die-bonded to the lead frame in a predetermined manner by the die-bonding device 3 for each product type (step 56), and the process proceeds to the next step.

Next, the file structure of the chip map data of FIG. 1 will be described based on Table 1 below.

Table 1 Code Chip Map Data Code Chip Map Data ──────────────────────────── 61 Wafer Identifier 70 Second Line Chip Number 62 Wafer size: 63 Number of product types: 64 Chip size X 71 Number of chips in the R row 65 Chip size Y 72 Information on chip 1 66 Chip interval 73 Information on chip 2 67 Starting coordinate X: 68 Starting coordinate Y: 69 1 Number of chips in row 74 Chip N information Chip map data includes a wafer identifier 61 that is an identifier for each wafer, a wafer size 62 that indicates the size of the wafer, and a product type number 63 that is created on the same wafer. And a chip size X64 and a chip size Y65 for generating the coordinates of the chip, and a chip interval 66 which is a distance between adjacent chips. , The starting coordinates X67 and the starting coordinates Y68 which are the reference coordinates on the wafer, and the number of chips in the first row 69 and the number of chips in the second row 70 that indicate the total number of chips in each row of R rows formed on the wafer. .. and the number of chips in the R row is 71 and N formed on the wafer
It is composed of information 72 of the chip 1, information 73 of the chip 2 ... And information 74 of the chip N, which are configured by product type information and quality information for each chip of each chip.
The chip information is represented by a combination of product type and quality information, and an example in which two types of products are formed on the same wafer will be described with reference to Table 2 below.

[0011] The chip information is recorded in 2 bits, and the upper 1 digit indicates the type of product. [0] represents "product A", [1] represents "product B", and the lower 1 digit is the quality of the chip. Information is shown, [0] represents "defective product", and [1] represents "good product". When handling two or more types of products at the same time, the number of bits (b) expressing the product type is determined within the range of the number of product types ≦ 2 ^b .

Next, a method of selecting chips on the wafer will be described with reference to FIG. Chips are formed on the wafer 83 with the orientation flat 81 as a reference, and by optically reading the wafer identifier 82 marked with a laser beam, the head coordinates 87 and the chip size X88 from the chip map data corresponding to the wafer 83 are read. , After the chip size Y89 and the chip information of each chip are fetched, the wafer 83 is scanned along the scanning order 8A with the orientation flat 81 as a reference, the defective product 86 is ignored, and the product A good product 84 or the product B good product 85 is obtained. On the other hand, the coordinates of the chip are calculated by integrating the chip size and the chip is selected. That is, when the X coordinate is obtained, if the position of the chip on the X coordinate is, for example, the fourth chip, the target chip coordinate is obtained by the head coordinate 87+ (chip size X88 + chip interval 66) × (4-1). Further, the Y coordinate can be similarly obtained.
This operation is repeated until there are no more chips to select, and the wafer 83 is processed.

FIG. 4 is an operation flowchart of an embodiment of the present invention. For ICs such as single-chip microcomputers,
There are products that differ only in the contents written in the built-in ROM. Although the functions of the IC are completely different due to the different contents of the ROM, the positions of the pads are the same, and it is very easy to create them on the same wafer. In such an example, it is necessary to inspect the chip while switching the inspection program of the wafer test. As shown in FIGS. 4 and 1, the wafer test apparatus 1 recognizes a wafer by incorporating the wafer identifier 14 assigned to each wafer into the control unit 11 by using the wafer identification unit 12 (step 92), and the wafer identifier The chip map data 41 corresponding to No. 14 is also taken into the control unit 11 via the communication bus 4 (step 93). After moving to the chip to be tested first, the product type information 15 of the chip at that position is fetched from the chip map data 41 into the test section 13 (step 94). The test unit 13 loads the inspection program corresponding to the product type information 15 (step 95) and performs a test (step 96). The pass / fail judgment result 16 which is the result of the test is returned to the control unit 11, and the pass / fail judgment result 16 is added to the chip map data 41 based on the result (step 9).
7). This completes the testing of the first chip and moves to the next chip to be tested (step 98). Of the above operation, steps 94 to 98 are repeated until the test of the Nth chip is completed (step 99).

Next, as a second embodiment, a case will be described in which products having different bonding pad positions on the chip due to different functions are formed on the same wafer. FIG.
FIG. 4 is a schematic view of the operation of a wafer test device having two different types of probe cards (jigs that contact the bonding pads of the chip and electrically connect the chip and the wafer test device). On the wafer 103, the product A to be tested by the probe card A101 and the probe card B1
The product B to be tested at 02 is created. Product A
When testing, the wafer 103 moves the product A, which is the chip under test, to the position of the probe card A 101. The probe card A moves vertically to contact the pads of product A and tests product A. Similarly, when testing the product B, the wafer 103 is moved and the product B is moved to the position of the probe card 102. The probe card B102 descends vertically to test the chip. At this time, the probe card A101 rises vertically and does not contact the wafer at all. The probe cards A and B are switched according to the product type information and each chip is continuously tested.

FIG. 6 is an operation outline of a die bonding apparatus capable of supplying two different types of lead frames. Products A and B having different pad positions are formed on the wafer 111 and die-bonded to different lead frames. The lead frame 112 of product A is
Lead frame supply cassette 113 to feeder 114
The product A that has moved upward and is adsorbed by the pickup unit 115 is mounted on the lead frame. The product A-mounted lead frame 116 is housed in the product A housing cassette 117 and completely separated from the product B. Similarly, the lead frame 118 of the product B moves from the lead frame supply cassette 119 on the feeder 11A, and the product B sucked by the pickup unit 115 is mounted on the lead frame. The product B mounted lead frame 11B is housed in the product B housing / housing cassette 11C and completely separated from the product A. Pickup section 115
These two products A are controlled by the control unit 11D that controls
And B are identified from the chip map data, and the chips are mounted on proper lead frames.

[0016]

As described above, according to the present invention, a wafer in which products having different functions are manufactured on the same wafer is recognized by recognizing the product type of each chip and the quality judgment result based on the chip map data. The wafer test, the visual inspection, and the die bonding can be effectively performed.

Since different products can be produced on the same wafer, it is possible to produce two different products together even if the order quantity of the products is small, and it is effective that the surplus products are less likely to occur. In this case, there is a risk that when a product is divided for each wafer, the product cannot be shipped at all due to an accident that the wafer is broken during production. Therefore, by creating two products on one sheet, such a risk can be avoided. In addition, TEG (Test Element Group) for monitoring the reliability and quality of wafers.
If p) is formed on the same wafer, there is an effect that the performance and quality of each wafer can be systematically monitored.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a manufacturing flowchart of a wafer processed by the apparatus of FIG.

3 is an explanatory view of a wafer processed by the apparatus of FIG. 1. FIG.

FIG. 4 is an operation flowchart of one embodiment of the present invention.

FIG. 5 is an operation schematic diagram of a wafer test apparatus having two types of different probe cards.

FIG. 6 is an operation outline of a die bonding apparatus capable of supplying two different types of lead frames.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer test device 2 Wafer visual inspection device 3 Die bonding device 4 Communication bus 11 Control part 12 Wafer identification part 13 Test part 15 Product type information 16 Good or bad judgment result 23 Display part 24 XY table 25 Operation part 33 Image recognition part 36 Pickup Part 37 Multi-Feeder Part 39 Position Correction Information 3B Pickup Signal 3D Feeder Setting Signal 41 Chip Map Data 82 Wafer Oribeshi 83 Wafer 84 “Good” Chips on Wafer 86 “Bad” Chips on Wafer 87 Start coordinates 88 Chip size X 8A Scanning order

Claims (5)

[Claims] 1. A wafer test apparatus for selecting a chip inspection program based on chip product type information. 2. A first test process for determining the quality of the semiconductor product based on the product type information of the semiconductor product and storing the product type information and the result of the quality determination of the semiconductor product.
A semiconductor product test including a second test step in which only the semiconductor product stored as a non-defective product in the first test step is tested, and the information stored in the first test step is changed according to the pass / fail judgment result. Method. 3. The method for testing a semiconductor product according to claim 2, wherein the second test step is a visual inspection. 4. A semiconductor product processing apparatus having means for switching a probe card according to product type information of a chip, and testing the chip using the probe card according to the product type information. 5. A semiconductor product processing apparatus comprising: switching means for switching a lead frame according to the product type information of the chip; and means for mounting the chip on the lead frame switched by the switching means.