JPH0997820A - Semiconductor wafer - Google Patents

Semiconductor wafer

Info

Publication number
JPH0997820A
JPH0997820A JP25154795A JP25154795A JPH0997820A JP H0997820 A JPH0997820 A JP H0997820A JP 25154795 A JP25154795 A JP 25154795A JP 25154795 A JP25154795 A JP 25154795A JP H0997820 A JPH0997820 A JP H0997820A
Authority
JP
Japan
Prior art keywords
pellet
wafer
mark
pellet regions
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25154795A
Other languages
Japanese (ja)
Inventor
Kazumi Fujito
一三 藤戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP25154795A priority Critical patent/JPH0997820A/en
Publication of JPH0997820A publication Critical patent/JPH0997820A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/54466Located in a dummy or reference die

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of the quality of good pellets caused by markings and to recognize optically good or bad of pellet regions precisely by recording layout information of bag pellets on no-pellet regions where elements cannot be formed at the peripheral region of a wafer. SOLUTION: A wafer 1 made of silicon is provided with pellet regions sectioned by scribing lines; these pellet regions 2 include semiconductor elements formed by the diffusion of impurities and forming wiring. The non-pellet regions 2A outside the pellet regions 2 record the layout information of the result of checking the pellet regions with layer or ink as a mask 3. The non-pellet regions 2A, which record the mark 3, are distributed widely on the peripheral part of the wafer 3 and recording can be repeated easily.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体ウェハーに関
し、特に製品となるペレット領域の検査結果をウェハー
上に記録した半導体ウェハーに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, and more particularly, it relates to a semiconductor wafer in which the inspection result of a pellet region as a product is recorded on the wafer.

【0002】[0002]

【従来の技術】半導体装置の製造工程においては、ウェ
ハーのペレット領域に不純物拡散や配線形成等の工程を
経て素子が形成され、その後スクライブ線より切断され
ペレットに分離されてリードフレームのアイランド等に
搭載されるが、良品のペレットのみを搭載する為にウェ
ハー製造の最終工程でLSIテスタによりペレット領域
の良,不良の判定を行ない、不良の場合は例えば図4に
示したように、ウェハー1上のペレット領域2に針やレ
ーザによるキズあるいはインク等によるマーク8をつけ
る方法が用いられている。
2. Description of the Related Art In a semiconductor device manufacturing process, elements are formed in a pellet region of a wafer through steps such as impurity diffusion and wiring formation, and then cut from scribe lines and separated into pellets to form islands of a lead frame. It is mounted, but in order to mount only good pellets, the LSI tester determines whether the pellet area is good or bad in the final step of wafer manufacturing. In the case of failure, for example, as shown in FIG. There is used a method of making a mark 8 by scratches or ink or the like on the pellet region 2 by a needle or a laser.

【0003】しかしながら、このマーキングによる記録
方法では、マーキング時に発生するごみやインク等の飛
散により、不良ペレット領域周辺の良品ペレット領域の
品質が低下すると共に、ペレットの組立工程において良
品と不良品の光学的認識が困難になるという欠点があっ
た。
However, in the recording method using this marking, the quality of the non-defective pellet region around the defective pellet region is deteriorated due to the scattering of dust, ink, etc. generated at the time of marking, and the optical quality of the non-defective product and the defective product in the pellet assembling process. There was a drawback that it became difficult to recognize the target.

【0004】この対策として図5に示すように、ウェハ
ー1のペレット領域の1つを記録用ペレット領域9と
し、ウェハー上の全ペレット領域の配列と同配列のパタ
ーンを設け、この配列パターンに物理的あるいは電気的
ストレスを加えることにより欠陥を作り込み、ペレット
領域の良,不良の配列情報を記録する方法が、例えば特
開平3−142945号公報に記載されている。
As a countermeasure against this, as shown in FIG. 5, one of the pellet areas of the wafer 1 is used as a recording pellet area 9, and a pattern of the same array as the array of all the pellet areas on the wafer is provided. For example, Japanese Patent Application Laid-Open No. 3-142945 discloses a method of creating a defect by applying electrical or electrical stress and recording good or bad array information of a pellet region.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た従来の記録用ペレット領域を用いる方法では、インク
等によるマーキング法の欠点はなくなるものの、半導体
ウェハーの製造工程において検査結果の記録用ペレット
領域に欠陥が生じた場合、検査結果を誤認識してしまう
という問題が生じ、又記録用ペレット領域を形成するた
めにウェハーの製造工程に特別な工程を付加しなければ
ならないという問題が生じる。更に一度記録した情報の
変更は困難であるという問題もある。
However, although the above-mentioned conventional method of using the recording pellet area eliminates the drawbacks of the marking method using ink or the like, the recording pellet area of the inspection result is defective in the manufacturing process of the semiconductor wafer. Occurs, a problem arises in that the inspection result is erroneously recognized, and a problem arises in that a special process must be added to the wafer manufacturing process to form the recording pellet region. There is also a problem that it is difficult to change the information once recorded.

【0006】本発明の目的は、マーキングによる良品ペ
レットの品質低下を防止し、特別な工程を付加すること
なくペレット領域の良・不良を光学的に精度良く認識で
きるマークを記録した半導体ウェハーを提供することに
ある。
An object of the present invention is to provide a semiconductor wafer having a mark recorded thereon, which prevents deterioration of quality of non-defective pellets due to marking, and allows good or bad recognition of good / defective pellet area without adding a special process. To do.

【0007】[0007]

【課題を解決するための手段】本発明の半導体ウェハー
は、半導体素子が形成された複数のペレット領域を有す
る半導体ウェハーにおいて、ウェハー周辺部の素子形成
ができない非ペレット領域に不良ペレット領域の配列情
報を記録したことを特徴とするものである。
A semiconductor wafer according to the present invention is a semiconductor wafer having a plurality of pellet regions in which semiconductor elements are formed. In a non-pellet area where elements cannot be formed in the peripheral portion of the wafer, array information of defective pellet areas is provided. Is recorded.

【0008】[0008]

【発明の実施の形態】次に本発明について図面を参照し
て説明する。図1は本発明の一実施の形態を説明する為
のウェハーの上面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a top view of a wafer for explaining an embodiment of the present invention.

【0009】図1においてシリコン等のウェハー1上に
はスクライブ線により区画された複数のペレット領域2
が設けられ、このペレット領域2には不純物の拡散や配
線形成等により半導体素子が形成されている。そして、
これらペレット領域2の外側の非ペレット領域2Aに
は、ペレット領域2の検査結果の配列情報が、レーザや
インク等によりマーク3として記録されている。このマ
ーク3を記録する非ペレット領域2Aは、ウェハー1の
周辺部に広く存在する為、再記録は容易である。例え
ば、ペレット領域2の再検査が必要な場合は、マーク3
の上に取り消し用のマークをつけ、他の非ペレット領域
2Aに再検査結果の配列情報のマークを記録すればよ
い。
In FIG. 1, a plurality of pellet regions 2 defined by scribe lines are formed on a wafer 1 made of silicon or the like.
Is provided, and a semiconductor element is formed in the pellet region 2 by diffusion of impurities, wiring formation, and the like. And
In the non-pellet area 2A outside the pellet area 2, array information of the inspection result of the pellet area 2 is recorded as a mark 3 by laser or ink. Since the non-pellet area 2A for recording the mark 3 is widely present in the peripheral portion of the wafer 1, re-recording is easy. For example, if re-inspection of the pellet area 2 is required, the mark 3
A mark for cancellation may be provided on the above, and a mark of sequence information of the re-inspection result may be recorded in another non-pellet area 2A.

【0010】図2(a),(b)は、この配列情報の記
録にバーコードからなるマーク3Aを用いた場合であ
る。図2(a)に示したバーコードからなるマーク3A
を非ペレット領域2Aに記録するため、非ペレット領域
2Aに欠陥4が存在する場合は、他の非ペレット領域2
Aに記録してもよいし、又、図2(b)に示すように、
情報記録の中断マーク5Aと再開マーク5Bを用い欠陥
4をさけてマーキングすることができる。
2A and 2B show the case where the mark 3A made of a bar code is used for recording the array information. Mark 3A composed of the bar code shown in FIG.
Is recorded in the non-pellet area 2A, if the defect 4 exists in the non-pellet area 2A, the other non-pellet area 2A is recorded.
It may be recorded in A, or as shown in FIG.
The defect 4 can be marked by using the information recording interruption mark 5A and the information recording restart mark 5B.

【0011】このように構成された本発明の実施の形態
によれば、不良品の配列情報が非ペレット領域2Aにマ
ーキングされている為、従来のようにマーキング時にご
みやインクによる良品のペレット領域2の品質低下が生
じることはない。従って、ペレット組立工程における情
報の光学的認識は極めて容易である。又記録用ペレット
領域も不要な為、特別の工程は不必要である。
According to the embodiment of the present invention configured as described above, since the array information of the defective product is marked in the non-pellet region 2A, the pellet region of the non-defective product due to dust or ink at the time of marking is conventionally used. No quality degradation of 2 occurs. Therefore, optical recognition of information in the pellet assembly process is extremely easy. Further, since the recording pellet area is not necessary, no special process is required.

【0012】図3(a),(b)は他の情報のマークを
示す図である。図3(a)はウェハー1のペレット領域
2の良・不良の配列を丸印からなる(他の形でもよい)
良品マーク6と不良品マーク7とでマーキングしたもの
であり、又図3(b)は不良品の配列を16進の数字及
び記号で表したものである。例えば、数字の「4」は
「0100」と表わされる為、配列1行目では2番目の
ペレット領域が不良であることを示している。尚、これ
らのマーク3B,3Cは必ずしもペレット領域2の配列
と同等の配列でマーキングしておく必要はなく、マーク
の配列順をあらかじめ決めておけば自由な順にマーキン
グできる。
FIGS. 3A and 3B are views showing marks of other information. In FIG. 3A, the good / bad array of the pellet region 2 of the wafer 1 is formed by circles (other shapes may be used).
The markings are made by the non-defective mark 6 and the defective mark 7, and FIG. 3B shows the arrangement of defective products by hexadecimal numbers and symbols. For example, since the number "4" is represented as "0100", it indicates that the second pellet region is defective in the first row of the array. Note that these marks 3B and 3C do not necessarily have to be marked in the same arrangement as the arrangement of the pellet regions 2, but if the arrangement order of the marks is predetermined, marking can be done in any order.

【0013】[0013]

【発明の効果】以上説明したように本発明は、半導体素
子を作り込むウェハー上に、製品となるペレット領域と
は別のウェハーの周辺部の非ペレット領域に、そのウェ
ハーの検査結果によるペレット領域の良・不良の配列情
報を記録することにより、検査時のマーキングによる良
品ペレットの品質低下を防止し、半導体ウェハーの製造
工程に特別な工程を付加せずに、下地パターン、工程中
の欠陥の影響を受けることなくペレット組立時のマーク
の自動認識の精度を向上させることができるという効果
がある。更に、ウェハー検査工程での再検査による再記
録も容易にできるという効果もある。
As described above, according to the present invention, on a wafer in which a semiconductor element is formed, a pellet region according to the inspection result of the wafer is formed in a non-pellet region around the wafer different from the product pellet region. By recording the array information of good and bad of the, it is possible to prevent the quality deterioration of the good pellet due to the marking at the time of inspection, without adding a special process to the manufacturing process of the semiconductor wafer, the base pattern, the defect in the process There is an effect that the accuracy of automatic mark recognition at the time of pellet assembly can be improved without being affected. Further, there is an effect that re-recording can be easily performed by re-inspection in the wafer inspection process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施の形態の半導体ウェハーの上面
図。
FIG. 1 is a top view of a semiconductor wafer according to an embodiment of the present invention.

【図2】実施の形態に用いるマークを示す図。FIG. 2 is a diagram showing marks used in the embodiment.

【図3】実施の形態に用いる他のマークを示す図。FIG. 3 is a diagram showing another mark used in the embodiment.

【図4】従来の半導体ウェハーの上面図。FIG. 4 is a top view of a conventional semiconductor wafer.

【図5】従来の他の半導体ウェハーの上面図。FIG. 5 is a top view of another conventional semiconductor wafer.

【符号の説明】[Explanation of symbols]

1 ウェハー 2 ペレット領域 2A 非ペレット領域 3,3A〜3C マーク 4 欠陥 5A 中断用マーク 5B 再開用マーク 6 良品用マーク 7 不良品用マーク 8 マーク 9 記録用ペレット領域 1 Wafer 2 Pellet area 2A Non-pellet area 3, 3A to 3C Mark 4 Defect 5A Interruption mark 5B Restart mark 6 Good mark 7 Bad mark 8 Mark 9 Recording pellet area

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子が形成された複数のペレット
領域を有する半導体ウェハーにおいて、ウェハー周辺部
の素子形成ができない非ペレット領域に不良ペレット領
域の配列情報を記録したことを特徴とする半導体ウェハ
ー。
1. A semiconductor wafer having a plurality of pellet regions in which semiconductor elements are formed, wherein the array information of defective pellet regions is recorded in a non-pellet region where the elements cannot be formed in the peripheral portion of the wafer.
【請求項2】 不良ペレット領域の配列情報は光学的に
読取可能なマークにより記録されている請求項1記載の
半導体ウェハー。
2. The semiconductor wafer according to claim 1, wherein the array information of the defective pellet region is recorded by an optically readable mark.
【請求項3】 光学的に読取り可能なマークはバーコー
ドから構成されている請求項2記載の半導体ウェハー。
3. The semiconductor wafer according to claim 2, wherein the optically readable mark comprises a bar code.
【請求項4】 光学的に読取り可能なマークは文字及び
記号から構成されている請求項2記載の半導体ウェハ
ー。
4. The semiconductor wafer according to claim 2, wherein the optically readable mark is composed of characters and symbols.
JP25154795A 1995-09-28 1995-09-28 Semiconductor wafer Pending JPH0997820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25154795A JPH0997820A (en) 1995-09-28 1995-09-28 Semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25154795A JPH0997820A (en) 1995-09-28 1995-09-28 Semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH0997820A true JPH0997820A (en) 1997-04-08

Family

ID=17224460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25154795A Pending JPH0997820A (en) 1995-09-28 1995-09-28 Semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH0997820A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010186806A (en) * 2009-02-10 2010-08-26 Seiko Epson Corp Semiconductor apparatus and method of manufacturing the same
JP6621964B1 (en) * 2019-03-18 2019-12-18 キヤノンマシナリー株式会社 Semiconductor device assembly system, semiconductor device manufacturing method using semiconductor device assembly method, and semiconductor device assembly program

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644041A (en) * 1987-06-25 1989-01-09 Nec Corp Discrimination of quality of semiconductor device
JPH02260440A (en) * 1989-03-30 1990-10-23 Matsushita Electric Ind Co Ltd Ic wafer and discrimination of quality of ic
JPH0499045A (en) * 1990-08-07 1992-03-31 Nec Kyushu Ltd Semiconductor wafer
JPH06163649A (en) * 1992-11-27 1994-06-10 Nec Kansai Ltd Semiconductor wafer and semiconductor element discriminating method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644041A (en) * 1987-06-25 1989-01-09 Nec Corp Discrimination of quality of semiconductor device
JPH02260440A (en) * 1989-03-30 1990-10-23 Matsushita Electric Ind Co Ltd Ic wafer and discrimination of quality of ic
JPH0499045A (en) * 1990-08-07 1992-03-31 Nec Kyushu Ltd Semiconductor wafer
JPH06163649A (en) * 1992-11-27 1994-06-10 Nec Kansai Ltd Semiconductor wafer and semiconductor element discriminating method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010186806A (en) * 2009-02-10 2010-08-26 Seiko Epson Corp Semiconductor apparatus and method of manufacturing the same
JP6621964B1 (en) * 2019-03-18 2019-12-18 キヤノンマシナリー株式会社 Semiconductor device assembly system, semiconductor device manufacturing method using semiconductor device assembly method, and semiconductor device assembly program

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