JP2003124365A - Method of imparting semiconductor integrated circuit chip management information, method of managing semiconductor integrated circuit chip management information, apparatus for imparting semiconductor integrated circuit chip management information, and semiconductor integrated circuit chip having management information - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus for individually managing semiconductor integrated circuit chips even after the plurality of semiconductor integrated circuit chips are cut out from a semiconductor chip by dicing or the like into individual chips, and also to provide semiconductor integrated circuit chips imparted with information for managing them. SOLUTION: The method of semiconductor integrated circuit chip management information comprises a process of recording management information associated with a manufacturing process of each semiconductor integrated circuit chip for each of a plurality of semiconductor integrated circuit chips formed in a semiconductor wafer, and a process wherein when the semiconductor integrated circuit chips are cut out from the semiconductor wafer and then are mounted on a lead frame 10, the management information is imparted near a place of the lead frame 10 where each of the semiconductor integrated circuit chips is mounted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit chip management information giving method, a semiconductor integrated circuit chip management information managing method, and a semiconductor integrated circuit chip management information for leaving a wafer processing history in a finished product of a semiconductor integrated circuit. The present invention relates to a semiconductor integrated circuit chip having an application device and management information.

[0002]

2. Description of the Related Art From a semiconductor wafer to a semiconductor integrated circuit (IC)
The process of manufacturing a chip is roughly divided into a pre-process and a post-process. In the previous step, the semiconductor wafer is subjected to various processes to form a pattern of a plurality of semiconductor integrated circuit chips. In the last step of this previous step, a part of the plurality of semiconductor integrated circuit chips or a test portion of the semiconductor wafer is inspected. Then, in a post process, a plurality of semiconductor integrated circuit chips are individually separated by dicing, mounted on a lead frame, and assembled into semiconductor integrated circuit chips. The manufactured semiconductor integrated circuit chip is subjected to, for example, a product inspection and a reliability test as a final step before shipping.

Generally, semiconductor integrated circuit chips are often quality controlled in units of manufacturing lots under the same process conditions for a plurality of semiconductor wafers. Therefore, for example, reliability, yield management, etc. are often managed in lot units. Alternatively, since the identification numbers are attached to the semiconductor wafers, the yield is increased for each semiconductor wafer,
You can also manage the reliability. However, for a very large amount of semiconductor integrated circuit chips separated from a semiconductor wafer by dicing, an effective method for identifying has not been conventionally taken, and therefore an individual management method has not been taken. Therefore, management of the reliability of each semiconductor integrated circuit chip is not performed. The details will be described with reference to FIG.

FIG. 3 is a diagram for explaining a conventional semiconductor integrated circuit chip assembling process. In this assembly process, a lead frame is used as a semiconductor integrated circuit chip forming member. After the quality inspection is performed on the semiconductor wafer in the last step of the previous steps, the semiconductor wafer is cut into a plurality of semiconductor integrated circuit chips. The cut semiconductor integrated circuit chips are mounted on the lead frame in a preset order. The mounted semiconductor integrated circuit chip is fixed to the lead frame by being connected to each other by a fine wire such as gold.

Next, the semiconductor integrated circuit chip, the bonding portion, and the like are all molded with a resin, except for the portion which will be the lead portion of the semiconductor integrated circuit chip. After the extra lead frame is cut off and subjected to deburring and forming processing, each semiconductor integrated circuit chip is inspected as the final step of the semiconductor integrated circuit chip assembly process. If it passes the inspection, the product name, product number, etc. are marked on the package surface of the semiconductor integrated circuit chip,
A semiconductor integrated circuit chip is completed. In this way, after the semiconductor wafer is cut into individual pieces, a process of assembling the semiconductor integrated circuit chips is performed for each semiconductor integrated circuit chip, but a large number of semiconductor integrated circuit chips cannot be individually identified. It was not possible to carry out individual management.

However, since reliability data may vary depending on the position of the semiconductor integrated circuit chip even within the same semiconductor wafer, there is a demand to manage the reliability data for each semiconductor integrated circuit chip. In addition, at the stage of manufacturing a semiconductor integrated circuit chip by mounting the semiconductor integrated circuit chip on a lead frame, there are cases where it is desired to individually identify the semiconductor integrated circuit chips.

Furthermore, after shipping the semiconductor integrated circuit chip,
For example, there may be a large amount of secular change or deterioration over time in the characteristics of a plurality of semiconductor integrated circuit chips manufactured on a lot-by-lot basis or from a specific semiconductor wafer, but management is performed for each semiconductor integrated circuit chip. Since there is no such information, a follow-up survey cannot be performed for each semiconductor integrated circuit chip, and quick and appropriate response may not be possible.

Therefore, there has been a demand for a method of individually identifying the semiconductor integrated circuit chips even after the plurality of semiconductor integrated circuit chips are separated from the semiconductor wafer by dicing or the like.

There has also been a demand for a semiconductor integrated circuit chip having a code for identifying the semiconductor integrated circuit chip.

At present, as a method of leaving a wafer processing history in a completed IC, (1) when processing a certain layer in the wafer processing step, the position information of the dice on the wafer, that is, each chip is a wafer. Information on which position on the wafer the wafer is in when it is in the state, and (2) the redundant fuse is cut during the redundant relief after probing (electrical test in the wafer state), and the position information There is a way to record.

[0011] Further, conventionally, the technologies provided to meet the above-mentioned requirements are (3) Japanese Patent Application Laid-Open No. 11-238657, (4) Japanese Patent Application Laid-Open No. 10-223657, and (5).
There is the following technique disclosed in JP-A-11-008327.

[0012]

The above (1) to (1)
Consider technology (5). Technique (1 ′): In the method (1), only the wafer position information can be recorded in the finished product, and this information cannot be confirmed unless the finished product is opened. Further, this method causes dust generation due to pattern peeling in the etching process, leading to a reduction in product yield. Since the wafer is used for other than the device, there is a drawback that the number of chips that can be cut out from the wafer is reduced. Technology of (2 '): The method of (2) cannot record position information for a product having no redundant fuse. The wafer processing history information is mainly necessary for failure analysis and the like, and is important information for failure analysis when there is a shot dependence of photolithography or a wafer distribution dependence of a failure distribution. There is a drawback that an extra number of steps is required. (3 ') Technology disclosed in Japanese Patent Laid-Open No. 11-238657: A device forming area for forming a semiconductor device on a chip, and a recording area for recording predetermined defect information and foreign matter information. Area, and an example in which the recording area is configured by a nonvolatile semiconductor memory device, that is, the position information of a chip in a wafer and defect information of a pattern are provided in the semiconductor memory device.
An example of electrically writing to the recording area using the / O pin (a related technique is disclosed in Japanese Patent Laid-Open No. 2001-238657), a magnetic material coating film is applied onto a protective film on a semiconductor device of a chip. However, an example of recording defect information and the like on the magnetic coating film is shown. However, this technology is (a)
Since a storage area other than devices is also provided on the wafer, the number of chips that can be taken from one wafer is reduced, (b) an extra step of forming the storage area is required, and (c) the storage area is used for defect information. There are drawbacks such as being used, and (d) requiring a coating device for a magnetic coating film and a recording / reproducing device. (4 ') Technology disclosed in Japanese Patent Laid-Open No. 10-223657: At the time of die bonding, an identification number corresponding to a characteristic division of each chip is added as characteristic information around the lead frame. Next, when separating a series of resin-sealed lead frames into individual pieces, an example of recognizing the identification number added to the lead frames and dividing into a processed storage case prepared for each of the characteristic divisions and reorganizing It is shown. However, this technique has a drawback that (a) the chip itself is not attached with an identification number after the chip is separated from the lead frame. (5 ') Technology disclosed in JP-A-11-008327 (similar technology is disclosed in JP-A-5-121573): semiconductor wafer number, position of semiconductor integrated circuit chip in semiconductor wafer Is determined as the identification code of the semiconductor integrated circuit chip, and when the semiconductor integrated circuit chip for which the identification code is determined is separated from the semiconductor wafer by dicing and mounted on a semiconductor integrated circuit chip forming member, A step of attaching a code corresponding to the identification code as a first identification code to a position near the semiconductor integrated circuit chip mounted on the circuit chip forming member; and a step of assembling the semiconductor integrated circuit chip, the semiconductor integrated circuit A step of reading the first identification code from the circuit chip forming member, and the read first identification code Attaching a second identification code corresponding to another code to the assembled semiconductor integrated circuit chip.

The first identification code is attached to the discarded frame portion of the lead frame as shown in FIG.

FIG. 4 shows a conventional example (Japanese Patent Laid-Open No. 11-008327).
FIG. 3 is a plan view showing a state in which an identification code is attached to a lead frame on which a semiconductor integrated circuit chip (Japanese Unexamined Patent Publication) is mounted.

After the individual semiconductor integrated circuit chips 5 for which the identification code has been determined are mounted on the lead frame 60,
A code corresponding to the identification code of the semiconductor integrated circuit chip 5 is attached to the position near the semiconductor integrated circuit chip 5 in the form of the barcode 70. It should be noted that it is also possible to create a sticker in which the identification code is written, attach the sticker on the lead frame 60, and use it as the identification code of the semiconductor integrated circuit chip 5.

Unlike the lead frame to which the first identification code is attached, the second identification code to be attached in the subsequent step is different from the lead frame 9 shown in FIG.
Appended to 0.

FIG. 5 shows a conventional example (JP-A-11-008327).
FIG. 3 is a plan view showing a state in which the identification code attached to the lead frame is transferred to the back surface of the package after the mold formation (Japanese Patent Laid-Open Publication No. JP-A-2003-24035).

Package backside 9 of semiconductor integrated circuit chip
A code corresponding to the barcode 70 read by the identification code reading means is added to 0 in the form of the barcode 80 using the second barcode writer. Similar to the barcode 70, the barcode 80 may be used as an identification code of the semiconductor integrated circuit chip 5 by creating a sticker in which an identification code corresponding to the barcode 80 is written and attached to the back surface 90 of the package. It's good.

However, in the conventional example described above (Japanese Patent Laid-Open No. 11-008327), the identification code is first
Attached to the frame part of the lead frame on which the semiconductor integrated circuit chip is mounted, which is also discarded, in the subsequent process,
Since it requires a procedure to re-transcribe on the back side of the package in which the IC, etc. are molded, (a) the number of steps is more than necessary to attach the identification code, and (b) it is possible to make an error when attaching the identification code to the package. However, there are drawbacks such as (c) requiring a device for reading and writing the identification code.

In view of the above-mentioned drawbacks, an object of the present invention is to provide a method and an apparatus therefor capable of individually managing semiconductor integrated circuit chips even after the plurality of semiconductor integrated circuit chips are separated from the semiconductor wafer by dicing or the like. To provide.

Another object of the present invention is to provide a semiconductor integrated circuit chip provided with information capable of managing the semiconductor integrated circuit chip.

[0022]

The present invention adopts the following means for achieving the above object. (1) In the semiconductor integrated circuit chip management information giving method, a step of recording management information regarding a manufacturing process of the semiconductor integrated circuit chip for each of the plurality of semiconductor integrated circuit chips formed on the semiconductor wafer; When the semiconductor integrated circuit chip is separated from the semiconductor wafer and mounted on the lead frame, the management information is attached to a position near the semiconductor integrated circuit chip mounted on the lead frame. (2) In the semiconductor integrated circuit chip management information providing method described in (1) above, the position in the vicinity is an area excluding the wiring area of the inner lead. (3) In the semiconductor integrated circuit chip management information providing method described in (1) above, the position in the vicinity is an area excluding the semiconductor integrated circuit chip placement area of the die pad. (4) In the semiconductor integrated circuit chip management information providing method described in (1) above, the position in the vicinity is a back surface region of the die pad on which the semiconductor integrated circuit chip is not arranged. (5) In the method for assigning semiconductor integrated circuit chip management information according to any one of (1) to (4) above, the management lot information includes a semiconductor wafer manufacturing lot number, a semiconductor wafer number, and a semiconductor integrated circuit in the semiconductor wafer. Select and use from the information on the chip position. (6) In the semiconductor integrated circuit chip management information giving method according to any one of (1) to (4), the management information is a bar code or alphanumeric characters. (7) In the semiconductor integrated circuit chip management information giving device, management information regarding a manufacturing process of the semiconductor integrated circuit chip is recorded for each of the plurality of semiconductor integrated circuit chips formed on the semiconductor wafer, and the semiconductor integrated circuit chip is a semiconductor. Management information managing means for controlling the printing device so as to attach the management information to a position near the semiconductor integrated circuit chip of the lead frame when the semiconductor device is separated from the wafer and mounted on the lead frame; A print means for printing information on the lead frame under the control of the management information management means. (8) In the semiconductor integrated circuit chip management method, when the semiconductor integrated circuit chip mounted on the lead frame is inspected, management information attached to the lead frame at a position near the semiconductor integrated circuit chip mounted. Is read using X-rays, and the inspection result data of the semiconductor integrated circuit chip is managed as management information for each corresponding semiconductor integrated circuit chip. (9) In the semiconductor integrated circuit chip management method, the management information managing means collectively manages management information in the process of forming the semiconductor integrated circuit chips on the wafer.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments for understanding the present invention will be described in detail with reference to the drawings.

According to the present invention, basically, information such as a wafer processing history is recorded on a lead frame in a step before a sealing step in a series of assembling steps.

(Embodiment) Management information is created for each chip, and the management information is recorded and managed in another medium. The management information includes information for individually recognizing each chip after the wafer is cut into individual chips in the assembly process, and information about matters that may cause a reduction in reliability of a semiconductor device product. Will be recorded. The former information includes, for example, the date and time the chip was produced, the lot number, the wafer number, and the position information of each chip within the wafer. The latter information includes information about pattern defects and foreign substances on the wafer surface, abnormal processing history, and the like, which are obtained by inspections performed after the completion of each wafer process step.

If necessary, information such as operating speed, power consumption, operating voltage, etc. can be added as management information for each characteristic category.

This management information is created for each wafer processing step, for example, a wafer step (step of forming chips on a wafer), an inspection step after the wafer step, a chip allocation step, a mounting step, and an inspection step as a finished product. To be done. Therefore, the wafer is processed in the state in which the management information is created and the management information is held according to the progress of the processing process.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram for explaining the operation of the management information management device 31 and the laser printing device 32 in the embodiment of the present invention according to the steps of wafer processing.

The semiconductor integrated circuit chip management information giving device records management information on the manufacturing process of the semiconductor integrated circuit chip for each of the plurality of semiconductor integrated circuit chips formed on the semiconductor wafer, and the semiconductor integrated circuit chip is a semiconductor. A management information management device 31 for controlling the printing device so as to attach the management information to a position near the semiconductor integrated circuit chip mounted on the lead frame when the management information management device 31 is separated from the wafer and mounted on the lead frame; It is composed of a printing device for printing management information on a lead frame under the control of the management information management device 31, for example, a laser printing device 32.

The management information management means 31 stores the management information of the chips from the wafer process S11 ("S" is abbreviated step description) shown in FIG. 2 to the chip separation process S13 in the storage means, and the mounting process. After the individual semiconductor integrated circuit chips for which the management information is determined in S14 are mounted on the lead frame 10, the management information of the semiconductor integrated circuit chips is displayed at the position on the lead frame 10 near the position where the semiconductor integrated circuit chips are mounted. It is a means for controlling the laser printing device 32 so as to print a corresponding code or the like.

The process of the semiconductor integrated circuit chip assembling process related to the management information managing means 31 will be described with reference to FIG.

In the wafer process S11, semiconductor integrated circuit chips are formed on the wafer. The management information about each chip in this step is stored in the management information management means 31.

In the final step of the previous step, the quality inspection S12 on the semiconductor wafer is performed. The management information about each chip in this step is also stored in the management information management means 31.

Next, in a chip dividing step S13, the semiconductor wafer is divided into a plurality of semiconductor integrated circuit chips.

The semiconductor integrated circuit chips thus cut are
By the mounting work step S21 in the mounting step S14, the mounting is performed on the lead frame in a preset order. In the management information adding step S22, the management information that has been managed up to this step is printed on a predetermined portion of the lead frame by the laser printer 32 in the step S22.

The semiconductor integrated circuit chip mounted on the lead frame 10 in the wire bonding step S15 is fixed to the lead frame by connecting them to each other with a fine wire such as gold.

Next, in a molding step S16, the semiconductor integrated circuit chip and the bonding portion are all molded with resin, leaving a portion to be the lead portion of the semiconductor integrated circuit chip.

In the lead cut forming step S17,
After the excess lead frame is cut off and subjected to deburring and forming processing, in the inspection step S18, each semiconductor integrated circuit chip is inspected as the final step of the semiconductor integrated circuit chip assembly step.

If the inspection is passed, the product name, product number, etc. are marked (recorded) on the package surface of the semiconductor integrated circuit chip, and the semiconductor integrated circuit chip is completed.

Now, the step of adding management information to the lead frame will be described in detail.

As shown in FIG. 1A, the unit lead frame 10 including the inner lead portion 11 and the outer lead portion 14 is continuously punched into a single strip.

Under the control of the management information management means 31, in the manufacturing line, a chip (not shown) is mounted on the die pad 12 of the lead frame 10 at the position of the die 13 while successively feeding out the strip.

At the same time, the management information of the chip is confirmed, and information such as a wafer processing history included in the management information is
The surface of the processing history recording areas 21, 22, 23, and 24 of the lead frame 10 shown in FIG. 1B, which is a partially enlarged view of FIG. 1A, is cut and recorded by the laser printing device 32. The "machining history recording area" means an area in which history information at the time of processing is recorded.

The management information can be a bar code or a symbol such as a number or a character.

The processing history recording areas 21, 22, 23 and 24 are located in the vicinity of the semiconductor integrated circuit chip of the lead frame, and in the lead frame shown in FIG.
(1) The die mounting surface of the die pad 12, the die 1
Processing history recording area 21 excluding the area 3 and (2) marking areas 22 and 23 on the front side or the back side of the inner lead 11 excluding the wiring area of the wires, and the processing history recording areas 22 and 23 are the first embodiment of FIG. For example,
All eight inner leads are targeted, and the processing history recording areas 22 and 23 are the inner leads 11.
It is provided inside or outside the region to be resin-molded.
(3) Formed in the processing history recording area 24 on the back surface opposite to the chip mounting surface of the die pad 12 on which the semiconductor element is mounted.

(Inspection Processing) When a defect is found in the semiconductor integrated circuit chip and inspection is required, (a) In the case where the processing history recording areas 21, 22, 23 and 24 are resin-molded, Since the processing history recording areas 21, 22, 23, and 24 cannot be seen with the naked eye, an apparatus using X-rays, for example, a microscope using X-rays, an X-ray transmission apparatus, an ultrasonic flaw detection imaging apparatus, or the like is used. . In particular, an ultrasonic flaw detection imaging device (Scanning)
Acoustic Tomography: SAT,
Or Scanning Acoustic Mic
Rography: SAM) is preferred. (B) When the processing history recording areas 22 and 23 are not resin-molded, the above (a) is also possible,
It can be visually inspected.

According to the semiconductor integrated circuit chip management method, when the semiconductor integrated circuit chip mounted on the lead frame is inspected, the management attached to the IC lead frame at a position near the semiconductor integrated circuit chip is mounted. Information is read using X-rays, and inspection result data of the semiconductor integrated circuit chip is managed as management information for each corresponding semiconductor integrated circuit chip.

The "proximity position" means a portion other than the area occupied by the semiconductor integrated circuit chip mounted on the lead frame, which portion remains when the product is manufactured. For example, in addition to the above-mentioned conditions, a portion included in the molded body of the inner lead and a portion excluding the wiring region where the wire is wired are preferable.

(Effects of the embodiment) By recording the management information on the die pad 12 or the inner lead 11, even if another lot or a different kind is mixed in the lot of the specific standard kind in the test process, the wafer It becomes easy to investigate the history of the machining process.

Since the management information is added to the chip in the mounting process, it is less likely that wrong management information will be added.

Since the management information management device manages the management information about the chips from the wafer process, the information management can be unified.

As a method for recording wafer information on the die pad 12 and the inner leads 11, laser marking is used instead of ink to prevent diffusion of impurities from the ink. With laser marking, it is possible to prevent ink from being erased by the chemicals used during opening during failure analysis, and it is possible to check wafer history information without opening using X-rays. Becomes

[0054]

According to the present invention, chip management information can be appropriately and accurately added to the chip itself. The present invention is
The management information given to the chip can be easily confirmed. According to the present invention, chip management information can be centrally managed.

According to the present invention, not only the position information of the dice on the wafer but also the wafer processing history such as the wafer lot and the processing history is recorded in the assembling process, so that the recording can be performed without using the transfer mask, and dust is generated. Product yield reduction can be prevented. In addition, the wafer position information can be confirmed without opening by analysis using X-rays or the like.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a management information management device 31 in the embodiment of the present invention.
FIG. 6 is a diagram for explaining the operation of the laser printer 32 according to the steps of wafer processing.

FIG. 3 is a diagram for explaining a process of a conventional semiconductor integrated circuit chip assembling process.

FIG. 4 is a plan view showing a state in which an identification code is attached to a lead frame on which a semiconductor integrated circuit chip of a conventional example (Japanese Patent Laid-Open No. 11-008327) is mounted.

FIG. 5 is a plan view showing a state in which an identification code attached to a lead frame is transcribed on the back surface of a package after forming a mold in a conventional example (JP-A-11-008327).

[Explanation of symbols]

10 lead frame 11 Inner lead 12 die pad 13 dice 14 Outer leads 21, 22, 23, 24 marking areas 31 Management information management device 32 Laser printing device

Claims (9)

[Claims] 1. A step of recording management information regarding a manufacturing process of a semiconductor integrated circuit chip for each of a plurality of semiconductor integrated circuit chips formed on a semiconductor wafer, and a step of separating the semiconductor integrated circuit chip from the semiconductor wafer and reading the leads. And a step of attaching the management information to a position near the semiconductor integrated circuit chip of the lead frame when the semiconductor integrated circuit chip is attached to the frame. 2. The semiconductor integrated circuit chip management information providing method according to claim 1, wherein the position in the vicinity is an area excluding the wiring area of the inner lead. 3. The method for providing semiconductor integrated circuit chip management information according to claim 1, wherein the position in the vicinity is an area excluding the semiconductor integrated circuit chip placement area of the die pad. 4. The method for providing semiconductor integrated circuit chip management information according to claim 1, wherein the position in the vicinity is a back surface region of the die pad on which the semiconductor integrated circuit chip is not arranged. 5. The management information is selected from a manufacturing lot number of a semiconductor wafer, a semiconductor wafer number, and information on a position of a semiconductor integrated circuit chip in the semiconductor wafer, and is used. 13. The method for providing semiconductor integrated circuit chip management information according to any one of 1. 6. The semiconductor integrated circuit chip management information providing method according to claim 1, wherein the management information is a bar code or an alphanumeric character. 7. A management information on a manufacturing process of a semiconductor integrated circuit chip is recorded for each of a plurality of semiconductor integrated circuit chips formed on a semiconductor wafer, and the semiconductor integrated circuit chip is separated from the semiconductor wafer to be a lead frame. Management information managing means for controlling the printing device so as to attach the management information to a position near the semiconductor integrated circuit chip of the lead frame when the management information managing means is installed. A semiconductor integrated circuit chip management information providing device comprising: a printing unit that prints on a lead frame under control. 8. When inspecting a semiconductor integrated circuit chip mounted on a lead frame, the management information attached to the lead frame at a position near the semiconductor integrated circuit chip is attached using X-rays. A method for managing a semiconductor integrated circuit chip, comprising reading and managing the inspection result data of the semiconductor integrated circuit chip as management information for each corresponding semiconductor integrated circuit chip. 9. A semiconductor integrated circuit chip management method, wherein management information in a process of forming a semiconductor integrated circuit chip on a wafer is collectively managed by a management information management means.