JP2006032932A - Semiconductor bare chip, method of recording identification information, and method of identifying semiconductor bare chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for improving the identification of a semiconductor bare chip. <P>SOLUTION: The semiconductor bare chip comprises a plurality of fuse elements f11 to f19 disposed on the surface of a semiconductor substrate 1. Identification information on the bare chip represents the presence or absence of the blowout of the fuse elements and the alignment of the fuse elements. The user acquires the identification information by visually identifying states and the alignment of the fuse elements. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor bare chip, and more particularly to a technique for identifying a semiconductor bare chip.

FIG. 1 is a schematic view showing a method of manufacturing a general semiconductor integrated circuit (hereinafter referred to as “IC”).
FIG. 2 is a flowchart showing a method of manufacturing the IC illustrated in FIG.
The IC manufacturing process is roughly divided into a wafer process and an assembly process.
Step S51: A bare wafer that has not been processed is prepared for each lot. Usually, the bare wafer 51 is a batch of about 25 to 50 wafers. In the IC manufacturing process, the wafer processing order within one lot and the IC processing order within one wafer are maintained.

Step S52: Various processes are performed on the bare wafer 51 to manufacture a wafer 52 on which a plurality of ICs are formed. The processing includes, for example, creation of a thin film for a transistor, implantation of impurities, etching, patterning, wiring, and the like.
Step S53: The IC formed on the wafer 52 is inspected.
Step S54: The chip 53 is cut out from the wafer 52 so that one IC is mounted on one chip.

Step S55: Package processing of the chip 53 is performed. Thereby, the IC package 54 is completed. The package processing includes, for example, bonding and packaging into a case.
Step S56: The final inspection of the IC package 54 is performed. If the final inspection is passed, the IC package 54 is shipped.

In the IC manufacturing process, identification information for identifying a chip, for example, a lot number, a wafer number, and a chip number are attached to the package.
In recent years, with the miniaturization of equipment main bodies, cases where bare chip mounting is adopted are increasing. In the bare chip mounting, there is no package to which identification information is attached. Therefore, Patent Document 1 discloses a technique of separately forming a nonvolatile memory on a bare chip. The identification information is recorded in a non-volatile memory and is read out as necessary.
Japanese Patent Laid-Open No. 11-87198

  However, the above-described technique has a problem that if a problem occurs in the bare chip, the nonvolatile memory also malfunctions accordingly, and the identification information may not be read. If the identification information cannot be read, the lot number or the like of the bare chip in which the defect has occurred cannot be specified. For this reason, it is not possible to quickly take effective measures such as replacement and re-inspection of bare chips belonging to the same lot.

Further, the addition of the nonvolatile memory causes a significant increase in the number of manufacturing steps and the chip area.
A first object of the present invention is to provide a technique for improving the identification of a semiconductor bare chip.
A second object of the present invention is to provide a technique for suppressing an increase in manufacturing man-hours required for identifying a semiconductor bare chip.

  A third object of the present invention is to provide a technique for suppressing an increase in chip area required for identifying a semiconductor bare chip.

The semiconductor bare chip according to the present invention includes a semiconductor substrate and a plurality of small pieces that are disposed on the semiconductor substrate so as to be visually recognized from the outside, and whose visibility is changed by processing. And an identification information recording member that represents the identification information of the bare chip.
The semiconductor bare chip according to the present invention is composed of a semiconductor substrate and a plurality of small pieces which are arranged on the semiconductor substrate so as to be visible from the outside and whose visibility is changed by processing. The visibility of each small piece and the arrangement of the small pieces And an identification information recording member representing identification information of the bare chip.

According to the above configuration, the identification information recording member is visible from the outside. Identification information can be acquired by visually recognizing the visually recognized state of each piece and the arrangement of each piece. Therefore, the identification of the semiconductor bare chip can be improved as compared with the conventional case.
The surface of the semiconductor substrate is provided with pads corresponding to the respective small pieces, each of the small pieces being melted by an electric current, a first portion of which is connected to the pad, The two portions may be connected to a ground electrode present on the substrate.

According to the above configuration, fusing by current can be easily performed via the pad. Therefore, an increase in the number of manufacturing steps required for identifying the semiconductor bare chip can be suppressed as compared with laser processing and etching processing.
Further, each of the small pieces may have an elongated shape having both the first portion and the second portion as both ends, and the intermediate portion sandwiched between both ends may be constricted.

According to the above configuration, the constricted portion is selectively fused. Therefore, it is possible to prevent an unexpected part from being blown out.
In addition, a main circuit may be formed on a main surface of the semiconductor substrate, and each of the small pieces may be made of a material that forms the main circuit.
According to the above configuration, it is not necessary to prepare a special material for forming the small piece, so that the cost of the chip can be reduced. Furthermore, if a small piece is formed after forming a part of the main circuit, an increase in manufacturing man-hours required for identifying the semiconductor bare chip can be suppressed.

Further, a main circuit may be formed on a main surface of the semiconductor substrate, and each of the small pieces may be disposed on the same surface as the main circuit.
According to the above configuration, positioning is easier than in the case where the small piece is formed on a different surface from the main circuit. Furthermore, if a small piece is formed after forming a part of the main circuit, an increase in manufacturing man-hours required for identifying the semiconductor bare chip can be suppressed.

  The identification information recording method according to the present invention is a recording method for recording identification information of a bare chip on a semiconductor bare chip in which a plurality of small pieces are disposed on the surface of a semiconductor substrate so as to be visible from the outside. An acquisition step of acquiring identification information, and a processing step of associating each piece with each digit of the binary display of the acquired identification information and performing processing based on bit information of each digit for each piece.

According to the above configuration, one bit can be represented by the presence or absence of small piece processing. Therefore, the identification information can be easily recorded as compared with the case where the processing of the small piece is continuous or stepwise.
Further, a main circuit is formed on the semiconductor substrate, and each of the small pieces is melted by an electric current, and processing in the processing step is performed by using a recording probe added to the main circuit inspection probe card. It may be done by supplying a current to the small piece.

Further, a main circuit is formed on the semiconductor substrate, each of the small pieces is made of a plastic material, and the processing in the processing step is performed by using the recording probe added to the main circuit inspection probe card. It may be done by pressing.
According to the above configuration, the identification information can be recorded in the inspection process of the main circuit. Therefore, identification information can be recorded without providing a special process.

  A method for identifying a semiconductor bare chip according to the present invention is an identification method for identifying a semiconductor bare chip, which images a unique shape of each of a plurality of chips and associates the identification information with the identification information for identifying the chip on a recording medium. A recording step for recording, and a collation step for capturing identification information of the chip by imaging a unique shape of the chip to be identified and collating the captured shape with a plurality of shapes recorded on the recording medium The chip has a fuse element melted on the surface thereof, and a sawtooth pattern appearing on the melt section of the fuse element is used as the unique shape.

According to the above configuration, the sawtooth pattern can be imaged from the outside. Therefore, even if a defect occurs in the semiconductor bare chip, identification information can be acquired by imaging a sawtooth pattern. As a result, the discriminability of the semiconductor bare chip can be improved as compared with the prior art.
Further, an image sensor circuit may be formed on the semiconductor bare chip, and the fuse element may be a fuse element included in the image sensor circuit.

According to the above configuration, it is not necessary to form a special fuse for identifying the chip. Therefore, an increase in manufacturing man-hours required for identifying the semiconductor bare chip can be suppressed, and an increase in the chip area required for identifying the semiconductor bare chip can be suppressed.
A method for identifying a semiconductor bare chip according to the present invention is an identification method for identifying a semiconductor bare chip, in which a unique shape of each of a plurality of chips is imaged and associated with identification information for identifying the chip on a recording medium. A recording step for recording, and a collation step for capturing identification information of the chip by imaging a unique shape of the chip to be identified and collating the captured shape with a plurality of shapes recorded by the recording medium The chip is cut from the wafer, and the sawtooth pattern appearing on the cut surface of the chip is used as the unique shape.

  According to the above configuration, the sawtooth pattern can be imaged from the outside. Therefore, even if a defect occurs in the semiconductor bare chip, identification information can be acquired by imaging a sawtooth pattern. As a result, the discriminability of the semiconductor bare chip can be improved as compared with the prior art. Furthermore, the sawtooth pattern is not specially formed to identify the chip. Therefore, an increase in manufacturing man-hours required for identifying the semiconductor bare chip can be suppressed, and an increase in the chip area required for identifying the semiconductor bare chip can be suppressed.

Embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 3 is a schematic plan view of the semiconductor bare chip according to the first embodiment.
A semiconductor bare chip has an IC formed on a semiconductor substrate 1. A main circuit is formed in the region 2 of the main surface of the substrate. Fuse elements f11 to f19 and pads p11 to p19 are disposed in the region 3 of the main surface of the substrate.

In the first embodiment, nine fuse elements constitute the identification information recording member. The identification information recording member represents chip identification information based on whether or not each fuse element is blown and its arrangement.
One fuse element expresses 1-bit information depending on whether or not it is blown. If there are nine fuse elements, 9-bit identification information can be recorded. The user can read the identification information by visually confirming whether or not the fuse elements are blown and their arrangement.

  The correspondence relationship between each digit of the identification information and each fuse element, and the correspondence relationship between the presence / absence of fusing and the bit information may be any as long as they are determined in common for all chips. For example, if the digits descend in order from the fuse element f11 toward the fuse element f19 and the fuse element “melting” expresses “0”, the identification information “101101111” is recorded in the example shown in FIG. It will be.

The fuse element has an elongated shape, one end is connected to the pad, and the other end is connected to the ground electrode 4. In addition, the structure has a narrowed middle portion sandwiched between both ends. With this structure, the constricted portion is more easily melted than other portions, and an unexpected portion can be prevented from being melted.
The material of the fuse element is preferably the same material as that of the main circuit. By doing so, the manufacturing cost of a chip can be reduced. From such a viewpoint, for example, polysilicon, aluminum, copper, or tungsten can be used.

The fuse element is disposed on the same main surface as the main circuit. Therefore, it can be formed in the same process as the main circuit, and the manufacturing cost of the chip can be reduced.
Thus, in the semiconductor bare chip of the first embodiment, the fuse element for recording the identification information is disposed on the main surface of the substrate 1. Therefore, it can be visually recognized from the outside, and the user can acquire the identification information even if a defect occurs in the chip. As a result, the discriminability of the semiconductor bare chip can be improved as compared with the prior art.

In addition, the number of manufacturing steps of the fuse element is much smaller than that of the nonvolatile memory. Therefore, the manufacturing cost of the chip can be greatly reduced.
Next, a method for recording the identification information on the semiconductor bare chip will be described.
FIG. 4 is a diagram showing a connection relationship between the semiconductor bare chip and the probe card.
The probe card 5 has a configuration for inspecting the main circuit and a configuration for recording identification information. FIG. 4 shows only a configuration for recording identification information. The configuration includes a probe 6 and a switch 7.

Each probe 6 contacts the corresponding pad. The switch 7 is inserted in a wiring connecting the probe 6 and the power source 8 and is turned on / off according to a control signal. The control signal is supplied from a tester described later.
With such a configuration, when the switch 7 is turned on, a current is supplied to the fuse element. The fuse element is blown by supplying current. In the example of FIG. 4, the fuse elements f12 and f15 are fused.

FIG. 5 is a block diagram showing a schematic configuration of the wafer inspection apparatus.
The wafer inspection apparatus includes a probe card 5, a prober 9, and a tester 10.
The prober 9 has a base on which the wafer 11 is placed, and the pads formed on the wafer 11 are brought into contact with the probes of the probe card 5 by moving the base. The tester 10 supplies a control signal to the probe card 5.

FIG. 6 is a flowchart showing a recording method for recording the identification information on the semiconductor bare chip according to the first embodiment.
The identification information is recorded in the wafer inspection process (see FIG. 2: step S53). It is assumed that the wafer 11 has already been placed on the base of the prober 9.
Step S11: The prober 9 carries the wafer 11 and brings the probe and the pad into contact with each other.

Step S12: The tester 10 acquires identification information “101101111” to be recorded.
Step S13: The tester 10 determines whether or not it is necessary to blow each fuse element based on the bit information of each digit of the acquired identification information. The necessity of fusing depends on the correspondence between each digit of the identification information and each fuse element, and the correspondence between the presence / absence of fusing and bit information. Here, the fuse elements f12 and f15 are “necessary”, and the other fuse elements are “unnecessary”.

Step S14: The tester 10 generates a control signal according to the determined necessity of fusing. The control signal turns on a switch corresponding to a fuse element that requires fusing and turns off a switch corresponding to a fuse element that does not require fusing. The tester 10 supplies the generated control signal to the probe card 5. Each switch is ON / OFF controlled according to a control signal. As a result, the fuse elements f12 and f15 are melted.
(Embodiment 2)
The second embodiment is different from the first embodiment in that the identification information is recorded by pressing the identification information recording member. The description of the same points as in the first embodiment will be omitted.

FIG. 7 is a diagram illustrating a connection relationship between the semiconductor bare chip and the probe card according to the second embodiment.
Pads p21 to p29 are disposed in region 3 of the main surface of the substrate of the semiconductor bare chip.
In the second embodiment, nine pads constitute the identification information recording member. The identification information recording member represents the identification information of the chip by the presence / absence of the mark of each pad and its arrangement.

The probe card 13 includes a probe 14, an actuator 15, and a switch 16 as a configuration for recording identification information.
The probe 14 is supported by the actuator 15. When power is supplied, the actuator 15 moves the probe 14 and presses the pad. The switch 16 is inserted in a wiring connecting the actuator 15 and the power source 8 and is turned on / off according to a control signal. The control signal is supplied from the tester.

One pad represents 1-bit information depending on the presence or absence of a mark. The user can read the identification information by visually confirming the presence / absence of the marks on the pad and the arrangement thereof.
The pad material may be any plastic material. However, the same material as the main circuit is preferable. By doing so, the manufacturing cost of a chip can be reduced. From such a viewpoint, for example, a metal wiring material can be used.

The identification information is recorded in the wafer inspection process as in the first embodiment. The difference from the first embodiment is that the actuator 15 presses the pads p22 and p25 via the probe 14. As a result, marks are formed on the pads p22 and p25.
According to the pressing, the damage to the processing object is small compared to the case by fusing. Therefore, the pad pitch can be designed to be narrow, and the chip can be miniaturized.
(Embodiment 3)
FIG. 8 is a schematic diagram showing a method for identifying a semiconductor bare chip according to the third embodiment.

The semiconductor bare chip is formed by forming an image sensor circuit 24 on a semiconductor substrate 21. The imaging circuit 22 and the voltage adjustment circuit 23 are formed on the main surface of the semiconductor substrate 21. The voltage adjustment circuit 23 includes fuse elements f31 to f33, pads p31 to p33, and resistance elements r31 to r33 as its constituent elements.
The third embodiment is characterized in that a sawtooth pattern appearing on the melting section of the fuse element is used for chip identification. Since the sawtooth pattern is microscopically unique to the chip, it can be used for chip identification. The camera 27 images a sawtooth pattern and records the image data on the recording medium 28.

The image sensor circuit 24 includes a voltage adjustment circuit 23 as a standard component. The voltage adjustment circuit 23 is a circuit that adjusts the voltage supplied to the imaging circuit 22, and includes a fuse element for adjusting the resistance value. By using the fuse element for chip identification, it is not necessary to provide an identification information recording member.
FIG. 9 is a flowchart showing a method for identifying a semiconductor bare chip according to the third embodiment.

Here, the case where the lot number of the semiconductor bare chip returned after shipment is specified is taken as an example.
It is assumed that the fuse element disposed on the chip is already blown out as necessary.
Step S21: Search for a blown fuse element on the chip and take an image of a sawtooth pattern appearing on the fuse section of the fuse element. The handling when a plurality of fuse elements are blown is not particularly limited as long as it is defined in common for all chips. For example, all of the plurality of patterns may be imaged, or a part may be selected and imaged according to a predetermined rule.

Step S22: The captured sawtooth pattern is recorded on the recording medium in association with the identification information.
The above steps S21 and S22 are performed for all chips before shipment.
Step S23: Ship the chip.
Step S24: The chip is returned.

Step S25: The blown fuse element on the returned chip is searched for, and a sawtooth pattern appearing on the fused section of the fuse element is imaged.
Step S26: The captured pattern is collated with a plurality of patterns recorded on the recording medium. The collation is performed by a general pattern matching method.
Step S27: If the captured pattern matches any of the recorded patterns, the identification information recorded in association with the pattern is read. Thereby, a lot number can be specified.

As described above, the semiconductor bare chip identification method according to the third embodiment uses the fuse element disposed on the main surface of the substrate 21. Since the fuse element is visible from the outside, the user can acquire identification information even if a defect occurs in the chip. As a result, the discriminability of the semiconductor bare chip can be improved as compared with the prior art.
The image sensor circuit 24 includes a fuse element as standard. Therefore, it is not necessary to provide a specific identification information recording member for identifying the chip, and an increase in the manufacturing process of the chip can be suppressed.
(Embodiment 4)
FIG. 10 is a schematic diagram showing a method for identifying a semiconductor bare chip according to the fourth embodiment.

The fourth embodiment is different from the third embodiment in that the cut surface of the chip is used as a shape unique to the chip. The description of the same points as in Embodiment 3 is omitted.
The semiconductor bare chip is cut out from the wafer. The wafer is cut using a dicing saw.
The fourth embodiment is characterized in that the sawtooth pattern appearing on the cut surface of the chip is used for chip identification. Since the sawtooth pattern is microscopically unique to the chip, it can be used for chip identification. The camera 27 images a sawtooth pattern and records the image data on the recording medium 28. The area imaged by the camera 27 may be anywhere as long as it is determined in common for all chips. For example, an image may be captured over the entire circumference of the chip, or a predetermined part may be imaged.

Thus, the semiconductor bare chip identification method of the fourth embodiment uses the cut surface of the chip. Since the cut surface is visible from the outside, the user can acquire the identification information even if a defect occurs in the chip. As a result, the discriminability of the semiconductor bare chip can be improved as compared with the prior art.
Further, since the cut surface is not specially provided for identifying the chip, an increase in the manufacturing process of the chip can be suppressed.
(Modification)
(1) In Embodiments 1 and 2, although fusing and pressing are given as examples, the present invention is not limited to these. For example, laser processing may be used. When fusing the fuse element by laser processing, it is not necessary to pass an electric current, so that no pad or wiring is necessary.
(2) In Embodiments 1 and 2, the constituent elements of the identification information recording member are arranged one-dimensionally, but the present invention is not limited to this. For example, it may be arranged two-dimensionally.
(3) In Embodiments 1 and 2, the identification information recording member is disposed on the surface of the substrate. However, the present invention is not limited to this as long as it is visible from the outside. For example, the identification information recording member may be covered with a translucent member.
(4) In the third embodiment, a circuit having a fuse element as a standard is described, but the present invention is not limited to this. A special fuse element may be provided to identify the chip.
(5) Although the image sensor circuit has been described in Embodiment 3, the present invention is not limited to this. The same effect can be obtained if the circuit is provided with a fuse element as standard.

  Examples of utilization of the present invention include semiconductor bare chips for various applications.

It is the schematic which shows the manufacturing method of a general semiconductor integrated circuit. 2 is a flowchart showing a method of manufacturing the IC illustrated in FIG. 1 is a schematic plan view of a semiconductor bare chip according to a first embodiment. It is a figure which shows the connection relation of a semiconductor bare chip and a probe card. It is a block diagram which shows schematic structure of a wafer inspection apparatus. 4 is a flowchart showing a recording method for recording identification information on the semiconductor bare chip according to the first embodiment. It is a figure which shows the connection relation of the semiconductor bare chip which concerns on Embodiment 2, and a probe card. FIG. 10 is a schematic diagram illustrating a method for identifying a semiconductor bare chip according to a third embodiment. 10 is a flowchart showing a method for identifying a semiconductor bare chip according to a third embodiment. FIG. 6 is a schematic diagram showing a method for identifying a semiconductor bare chip according to a fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate f11-f19, f31-f33 Fuse element p11-p19, p21-p29, p31-p33 Pad r31-r33 Resistance element 4 Ground electrode 21 Semiconductor substrate 22 Imaging circuit 23 Voltage adjustment circuit 24 Image sensor circuit 27 Camera 28 Recording Medium

Claims (12)

A semiconductor substrate;
Identification information that is arranged on the semiconductor substrate so as to be visible from the outside and includes a plurality of small pieces whose visibility is changed by processing. A semiconductor bare chip comprising: a recording member. On the surface of the semiconductor substrate, pads are arranged corresponding to each small piece,
Each of the small pieces is melted by an electric current, a first portion thereof is connected to the pad, and a second portion is connected to a ground electrode existing on the substrate. The semiconductor bare chip as described. 3. The semiconductor bare chip according to claim 2, wherein each of the small pieces has an elongated shape having both a first portion and a second portion as both ends, and an intermediate portion sandwiched between both ends is constricted. A main circuit is formed on the main surface of the semiconductor substrate,
The semiconductor bare chip according to claim 1, wherein each of the small pieces is made of a material that forms the main circuit. A main circuit is formed on the main surface of the semiconductor substrate,
The semiconductor bare chip according to claim 1, wherein each of the small pieces is disposed on the same surface as the main circuit. A recording method for recording identification information of a bare chip on a semiconductor bare chip in which a plurality of small pieces are arranged to be visible from the outside on the surface of a semiconductor substrate,
An acquisition step of acquiring identification information of the bare chip;
A recording method comprising: a processing step of causing each piece to correspond to each digit of the binary display of the acquired identification information and performing processing for each piece based on bit information of each digit. A main circuit is formed on the semiconductor substrate,
Each of the small pieces is melted by an electric current,
The recording method according to claim 6, wherein the processing in the processing step is performed by supplying a current to the small piece via a recording probe added to the main circuit inspection probe card. A main circuit is formed on the semiconductor substrate,
Each of the small pieces is made of a plastic material,
The recording method according to claim 6, wherein the processing in the processing step is performed by pressing a small piece via a recording probe added to a main circuit inspection probe card. An identification method for identifying a semiconductor bare chip, comprising:
A recording step of imaging a unique shape of each of the plurality of chips, and recording the image on a recording medium in association with identification information for identifying the chip;
A step of imaging a unique shape of a chip to be identified, and obtaining identification information of the chip by collating the captured shape with a plurality of shapes recorded on the recording medium,
The chip has a fuse element blown on the surface thereof, and uses a sawtooth pattern appearing on the melt section of the fuse element as the inherent shape. An image sensor circuit is formed on the semiconductor bare chip,
The identification method according to claim 9, wherein the fuse element is a fuse element included in an image sensor circuit. An identification method for identifying a semiconductor bare chip, comprising:
A recording step of imaging a unique shape of each of the plurality of chips, and recording the image on a recording medium in association with identification information for identifying the chip;
A step of imaging a unique shape of a chip to be identified, and obtaining identification information of the chip by collating the captured shape with a plurality of shapes recorded on the recording medium,
The chip is cut from a wafer, and a sawtooth pattern appearing on the cut surface of the chip is used as the unique shape. A semiconductor substrate;
An identification information record comprising a plurality of small pieces arranged on the semiconductor substrate so as to be visible from the outside and whose visibility is changed by processing, and representing the identification information of the bare chip by the visibility of each small piece and the arrangement of the small pieces. A semiconductor bare chip comprising: a member.

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