KR20030023268A - Semiconductor Integrated Circuit Comprising an ID circuit Capable Of Storing Various ID Information - Google Patents

Abstract

PURPOSE: A semiconductor IC(Integrated Circuit) including an ID circuit for storing various ID information is provided to utilize various information without using an additional device by installing a bar code type ID circuit formed with a plurality of fuses. CONSTITUTION: A semiconductor IC includes a core and a peripheral circuit such as a memory cell array, a column/row coding block, a data read block, and a data write block. A plurality of pads are arranged along an upper side and a lower side of the semiconductor IC. The semiconductor IC further includes an ID(IDentification) circuit(140). The ID circuit(140) is used for storing ID information. The ID circuit(140) is formed with a plurality of fuses(F10-F17). The fuses(F10-F17) are electrically insulated to each other.

Description

Semiconductor Integrated Circuit Comprising an ID Circuit Capable Of Storing Various ID Information

The invention relates to semiconductor integrated circuits. More specifically, the present invention relates to a semiconductor integrated circuit including an ID circuit that can more efficiently and accurately manage information related to a manufacturing process of semiconductor manufacturing.

The manufacturing method for manufacturing a semiconductor device usually consists of a very large number of processes. A typical method of manufacturing a semiconductor device will be briefly described below. First, a photolithography step, an etching step, a cleaning step, and the like are repeatedly performed on the surface of the wafer during the wafer processing process so that specific semiconductor chips are formed on the wafer. Next, a test for determining the good / bad of the individual chips formed on the wafer is performed using a probe device to obtain mapping data, which is sent to a wafer assembly process. First, during the wafer assembly process, the wafer is divided into individual dies in a dicing step. Next, a good die is picked up according to the mapping data and mounted on the lead frame in the bonding step. Then, in the wire bonding step, the lead-out terminal for the semiconductor chip and the connection electrode are connected through wire bonding. Then, in a packaging process, mold molding is performed on the semiconductor chip using a thermosetting resin and specific information is displayed on the surface of the package to complete the semiconductor device.

As described above, in order to complete a semiconductor device, a large number of complicated processes must be executed, and it is necessary to execute accurate information management regarding information on semiconductor products in individual processes. In the semiconductor manufacturing process of the prior art, since the main focus of the manufacturing method in the prior art is tailored to manufacturing a large number of semiconductor devices having the same specifications in order to take advantage of mass production, the information management for semiconductor devices distributed through the process is Relatively easy. That is, in the semiconductor manufacturing method of the prior art, semiconductor devices processed through the same manufacturing system are distributed as one lot unit through the process, and each lot is usually processed under the same conditions, so that information management is relatively easy.

Recently, however, as semiconductor devices have become very widely used in general commodity and component fields, there is a market demand for multi-volume, small quantity production semiconductor devices such as application specific integrated circuit (ASIC) and system on silicon (SOS). Is rising. In quantitative terms, one wafer may sometimes ensure an amount sufficient to produce several types of semiconductor devices for a particular application. At the same time, as in the case of a large-capacity memory chip, there is a situation in which a product can be shipped as long as a part of the chip is good, and therefore, it is necessary to perform information management individually on each chip in a given wafer.

For this purpose, in the semiconductor manufacturing method of the prior art, the distribution of the semiconductor device through various processes, marking the ID information such as numbers and alphabet letters on the surface of the semiconductor chip on the semiconductor package or wafer sealed with resin. Is managed. However, the amount of information that can be recorded using alphabetic characters is limited. In addition, it is necessary to perform edge recognition processing when reading alphanumeric characters, which is difficult. This method adds the problem that the character is susceptible to contamination or damage.

One of the techniques for managing ID information is to use transistors and fuses connected to the pad, as shown in FIGS. 1A and 1B. Referring to FIG. 1A, an ID circuit according to the related art is connected to a pad and includes a resistor R1, NMOS transistors T1-T4, and a fuse F1 as shown in the figure. In such an ID circuit, the on / off of the fuse can be determined by looking at the voltage level across the pad. The ID information of the semiconductor integrated circuit can be found according to the determination result. The ID circuit shown in FIG. 1A is a circuit using one fuse, and the ID circuit shown in FIG. 1B is a circuit using three fuses F2, F3, and F4.

According to the ID circuits illustrated in FIGS. 1A and 1B, a method using a fuse connected to a pad has a disadvantage in that it cannot include various information because the number of pads is limited. In addition, constraints are placed on the layout and layout of the transistors used to implement the circuitry that stores the ID information. In addition, in order to obtain ID information of a semiconductor integrated circuit, a test through a pad may be performed and the result may be analyzed to obtain ID information.

In order to solve this problem, a method of implementing a barcode type pattern in a wafer and managing information using the same is illustrated in FIGS. 2A and 2B. The ID circuit shown in FIG. 2A is a circuit using a one-dimensional barcode pattern, and the ID circuit shown in FIG. 2B is a circuit using a two-dimensional barcode pattern.

The method using the barcode pattern has an advantage that there is no restriction in the implementation of the necessary information because more information can be stored in the semiconductor integrated circuit. However, there is a problem not only in the optical recognition of the pattern, but also vulnerable to dust, scratches, and the like. In addition, after implementing such a pattern, there is a disadvantage in that an additional process and equipment for recognizing and reading the pattern are needed and there is a possibility of misreading the pattern.

Therefore, there is an urgent need for an ID circuit of a semiconductor integrated circuit that implements necessary information in a wafer but does not require new processes and equipment to recognize stored ID information.

An object of the present invention is to provide a semiconductor integrated circuit having a barcode type ID circuit using a fuse array to include a variety of information without additional equipment for information management of the semiconductor manufacturing process.

Another object of the present invention is to provide a semiconductor integrated circuit having an ID circuit capable of recording various kinds of information that can be utilized in a semiconductor device to achieve efficient and sophisticated in-process logistics in a semiconductor manufacturing process.

It is yet another object of the present invention to provide a variety of additional information available, such as information on locally filed claims after shipment that may be correlated with the recorded product ID information, and the manufacturing process history information. It is to provide a semiconductor integrated circuit having an ID circuit capable of providing an improved service for maintenance work.

1A and 1B show prior art ID circuits using pads, transistors, and fuses;

2A and 2B show a prior art ID circuit using a barcode format pattern;

3 shows a semiconductor integrated circuit with ID circuit according to the present invention; And

4 is a diagram for explaining storing ID information using an ID circuit according to the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor integrated circuit 120 core and peripheral circuit

140: ID circuit

(Configuration)

According to a feature of the present invention for achieving the above objects, a semiconductor integrated circuit includes an information management ID circuit provided as chip ID information on each chip disposed on a wafer surface, the ID circuit comprising a plurality of fuses. A fuse array configured.

In this embodiment, the chip ID information includes chip information unique to each chip.

In this embodiment, the chip ID information stored in the ID circuit can be directly confirmed on the wafer without any equipment.

In this embodiment, the chip ID information is stored by controlling the electrical connection states of the fuses constituting the ID circuit.

In this embodiment, the chip ID information may be freely stored using electrical connection states of fuses of a fuse array for information management of a semiconductor manufacturing process.

(Action)

According to such an apparatus, chip ID information can be directly checked on a wafer without any additional equipment during chip analysis.

(Example)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 3A is a view showing a semiconductor integrated circuit having an ID circuit according to a preferred embodiment of the present invention, and FIG. 3B is a preferred embodiment of the ID circuit shown in FIG. 3A. 4 is a diagram for explaining storing ID information using an ID circuit according to the present invention. It is apparent to those skilled in the art that the ID circuit according to the present invention is not limited to the semiconductor integrated circuit and is not used.

Referring to FIG. 3, the semiconductor integrated circuit 100 according to the present invention includes a core and a peripheral circuit 120, for example, the core and the peripheral circuit may include a memory cell array, a row / column coding block, and a data reading block. , Data writing blocks, and the like. A plurality of pads are arranged along the upper side and the lower side of the semiconductor integrated circuit 100. The semiconductor integrated circuit 100 according to the present invention further includes an ID circuit 140, and the ID circuit 140 stores information related to a manufacturing process of semiconductor manufacturing, that is, ID information.

A preferred embodiment of the ID circuit shown in FIG. 3A is shown in FIG. 3B. Referring to FIG. 3B, the ID circuit 140 includes a plurality of fuses, and the fuses are electrically insulated from each other. In this embodiment, the ID circuit 140 is composed of eight fuses F10-F17, but it can be apparent to those who have learned the general knowledge in the art that it can be composed of more fuses. Each fuse may be implemented using a laser fuse. Depending on the electrical connection of the fuses, each fuse will store data '1' or '0'. For example, if the electrical connection is broken, the fuse stores data '1'. In contrast, if the electrical connection is maintained, the fuse stores data '0'. An ID circuit that stores ID information " 10110011 " according to this connection state is shown in FIG. As described above, it is obvious that when using more fuses, more information can be stored.

As described above, after the ID circuit composed of the fuse array is embedded in the semiconductor integrated circuit, the electrical connection of the fuse is determined according to the type of information to be stored, and this is directly on the wafer without any equipment when analyzing the chip. This ensures that the amount of information that can be stored is not restricted without the need for additional equipment for analysis.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, various information may be stored without additional equipment for managing information about a semiconductor manufacturing process. In addition, various types of information that can be utilized in the semiconductor device may be recorded to achieve efficient and sophisticated in-process logistics in the semiconductor manufacturing process. In addition, it provides several kinds of additional information available, such as post-shipment claims filed locally and manufacturing process history information that may be correlated with the recorded product ID information, to provide for maintenance of the shipped product. It can provide improved services.

Claims (5)

Each chip disposed on the wafer surface has an information management ID circuit provided as chip ID information, the ID circuit including a fuse array composed of a plurality of fuses F10-F17. . The method of claim 1, And the chip ID information includes chip information unique to each chip. The method of claim 1, The chip ID information stored in the ID circuit can be directly confirmed on the wafer without a separate equipment. The method of claim 1, And chip ID information is stored by controlling electrical connection states of fuses constituting the ID circuit. The method of claim 1, And wherein the chip ID information can be freely stored using electrical connection states of fuses of a fuse array for information management of a semiconductor manufacturing process.