KR20070054011A - Semiconductor memory chip including signature id circuit - Google Patents

Abstract

The present invention relates to a semiconductor memory chip including a signature ID circuit. A semiconductor memory chip according to the present invention includes a plurality of pads connected to internal circuits of the semiconductor memory chip; A reference signature ID circuit electrically connected to at least one pad of the plurality of pads (hereinafter, referred to as first pads) and storing reference signature ID information; And a plurality of signature ID circuits electrically connected to a plurality of pads (hereinafter referred to as second pads) except for the first pads and storing signature ID information corresponding to an integer multiple of the reference signature ID information. Include. According to the present invention, it is possible to obtain accurate signature ID information regardless of the threshold voltage of the NMOS transistor in the signature ID circuit.

Description

Semiconductor memory chip with signature ID circuit {SEMICONDUCTOR MEMORY CHIP INCLUDING SIGNATURE ID CIRCUIT}

1 shows a portion of a semiconductor memory chip having a signature ID circuit according to the prior art.

FIG. 2 is a circuit diagram illustrating the signature ID circuit shown in FIG. 1.

3 is a block diagram illustrating a semiconductor memory chip according to the present invention.

FIG. 4 is a diagram illustrating signature ID information according to fuse cutting in the signature ID circuit shown in FIG. 3.

5 is a flowchart illustrating a method of testing signature ID information of a semiconductor memory chip according to the present invention.

* Explanation of symbols for main parts of drawings *

100 and 200: semiconductor memory chips 110 and 210: internal circuit

120, 220: reference signature identification circuit

121-12n, 221-22n: Signature ID circuit

The present invention relates to a semiconductor memory chip, and more particularly, to a semiconductor memory chip including a signature ID circuit.

A semiconductor memory chip is a memory device that stores data and can be read out when needed. Semiconductor memories can be broadly divided into random access memory (RAM) and read only memory (ROM). ROM is nonvolatile memory that does not lose its stored data even when its power supply is interrupted. The ROM includes PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), Flash Memory, and the like. RAM is a so-called volatile memory that loses its stored data when the power is turned off. RAM includes Dynamic RAM (DRAM) and Static RAM (SRAM).

The manufacturing method of a semiconductor memory chip usually consists of a very large number of processes. A typical method of manufacturing a semiconductor memory chip will be briefly described below. First, the wafer processing process is repeatedly performed on the wafer surface by a photolithography step, an etching step, a cleaning step, and the like, and specific semiconductor memory chips are formed on the wafer. Next, a test for good / bad judgment of the individual chips formed on the wafer is performed using a probe device to obtain mapping data, which is sent to a wafer assembly process.

During the wafer assembly process, the wafer is divided into individual dies in a dicing step. Next, a good die is picked up according to the mapping data and mounted on the lead frame in the bonding step. Then, in the wire bonding step, the lead-out terminal for the semiconductor memory chip and the connection electrode are connected by wire bonding. Then, in a packaging process, mold molding is performed on the semiconductor memory chip using a thermosetting resin and specific information is displayed on the surface of the package to complete the semiconductor memory chip.

As described above, in order to complete a semiconductor memory chip, many complicated processes must be executed, and it is necessary to manage accurate information about the semiconductor memory chip in individual processes. Since the main focus of the semiconductor manufacturing process according to the prior art is tailored to mass production of semiconductor memory chips with the same specifications in order to take advantage of mass production, information management on semiconductor memory chips distributed through the process is relatively easy. That is, in the semiconductor manufacturing method of the prior art, semiconductor memory chips processed through the same manufacturing system are distributed as one lot unit through the process, and each lot is usually processed under the same conditions so that information management is relatively easy.

Recently, however, as semiconductor memory chips have become very widely used in general commodity and component fields, the market for small-volume, low-volume production semiconductor memory chips such as application specific integrated circuit (ASIC) and system on silicon (SOS) The demand is rising. Quantitatively, one wafer may sometimes ensure an amount sufficient to produce several types of semiconductor memory chips for a particular application. At the same time, as in the case of a large-capacity memory chip, there is a situation in which a product can be shipped as long as a part of the chip is good, and therefore, it is necessary to perform information management separately on each chip in a given wafer.

For this purpose, in the semiconductor manufacturing method of the prior art, the distribution of semiconductor devices through various processes, marking the ID information such as numbers and alphabet letters on the surface of the semiconductor memory chip on the semiconductor package or wafer sealed with resin. Is managed. However, the amount of information that can be recorded using alphabetic characters is limited. In addition, it is necessary to perform edge recognition processing when reading alphanumeric characters, which is difficult. This method adds the problem that the character is susceptible to contamination or damage.

1 shows a portion of a semiconductor memory chip having a signature ID circuit according to the prior art. Referring to FIG. 1, diodes D1 and D2 are provided as a protective circuit (ElectorStatic Diode (ESD)) between the pad 10 and the first power supply voltage VDD and between the pad 10 and the ground voltage VSS. Each is connected. The signature ID circuit 20 is connected between the pad 10 and the second power supply voltage VDDQ.

The signature ID circuit 20, as is well known, consists of diodes connected in series between the power supply voltage and the pad and fuses connected across each of the diodes (see FIG. 2). As shown in FIG. 1, a power supply of a semiconductor memory chip is divided into a first power supply voltage VDD and a second power supply voltage VDDQ. As shown in FIG. 1, when the protection circuit ESD is provided, the signature ID circuit 20 may use the second power supply voltage VDDQ instead of the first power supply voltage VDD.

When the chip information is confirmed using the signature ID circuit of the semiconductor memory chip, the chip information can be detected by setting up specific conditions during the test. Since the normal device function should not be affected at all when detecting information, the number of diodes adjusted by fuse cutting by forcing current of the second power supply voltage VDDQ to 0 V and pad 10 is normally controlled. The measurement of the level determined by the package information is confirmed.

FIG. 2 is a circuit diagram illustrating the signature ID circuit shown in FIG. 1. Referring to FIG. 2, the signature ID circuit 20 includes a plurality of diode-connected NMOS transistors N1 to N5 and a plurality of fuses F1 to F4, which are connected as shown in FIG. 2. . The fact that package information is stored with or without a blown fuse is apparent to those of ordinary skill in the art.

In order to measure the signature ID information, the second power supply voltage VDDQ should be 0V, and a proper current should flow through the pad 10. At this time, the voltage of the pad 10 can be distinguished from 1Vt to 5Vt according to the fuse cutting, thereby storing the signature ID information. Where Vt is the threshold voltage of each diode-connected NMOS transistor.

However, the threshold voltage of diode-connected NMOS transistors can vary depending on the manufacturing process. If the threshold voltages of the NMOS transistors are different, the same signature ID information is stored, but there is a possibility that the NMOS transistor is stored differently.

For example, assume that the threshold voltage of the NMOS transistor in the first semiconductor memory chip is 1V and the threshold voltage of the NMOS transistor in the second semiconductor memory chip is 0.8V. When all of the first to fourth fuses F1 to F4 are cut, the pad voltage of the first semiconductor memory chip is 5V and the pad voltage of the second semiconductor memory chip is 4V. If the voltage section in the case where all of the first to fourth fuses F1 to F4 are cut is 4.5 V to 5.5 V, the signature ID information of the second semiconductor memory chip is the first to third fuses. There is a problem that is incorrectly determined to have cut F1 ~ F3). This becomes a factor of reducing the reliability of the signature ID information of the semiconductor memory chip.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a semiconductor memory chip capable of providing accurate signature ID information regardless of the threshold voltage of a diode-connected NMOS transistor, and a method thereof. have.

A semiconductor memory chip according to the present invention includes a plurality of pads connected to internal circuits of the semiconductor memory chip; A reference signature ID circuit electrically connected to at least one pad of the plurality of pads (hereinafter, referred to as first pads) and storing reference signature ID information; And a plurality of signature ID circuits electrically connected to a plurality of pads (hereinafter referred to as second pads) except for the first pads and storing signature ID information corresponding to an integer multiple of the reference signature ID information. Include.

In this embodiment, the reference signature ID circuit and the plurality of signature ID circuits each comprise a plurality of diode-connected NMOS transistors. The reference signature ID information and the signature ID information vary depending on threshold voltages of the plurality of diode-connected NMOS transistors. The reference signature ID circuit and the plurality of signature ID circuits change threshold voltages of the plurality of diode-connected NMOS transistors according to fuse cutting.

A method of reading signature ID information of a semiconductor memory chip according to the present invention, the semiconductor memory chip comprising: a plurality of pads connected to an internal circuit of the semiconductor memory chip; A reference signature ID circuit electrically connected to at least one pad of the plurality of pads (hereinafter, referred to as first pads) and storing reference signature ID information; And a plurality of signature ID circuits electrically connected to a plurality of pads (hereinafter referred to as second pads) except for the first pads and storing signature ID information corresponding to an integer multiple of the reference signature ID information. Include.

The method of reading the signature ID information may include providing a signature ID test enable signal to the semiconductor memory chip; Supplying current to the plurality of pads; Measuring voltage at the plurality of pads; Obtaining voltage values of the second pads based on voltage values of the first pads; And identifying the signature ID information through the voltage values of the second pads. Here, the test enable signal is 0V provided to a power pad among the plurality of pads.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a block diagram illustrating a semiconductor memory chip according to the present invention. Referring to FIG. 3, by way of example, two semiconductor memory chips 100, 200 are shown. Each semiconductor memory chip includes an internal circuit and a signature ID circuit for storing signature ID information.

Here, for the convenience of explanation, it is assumed that each signature ID circuit is the same as the circuit shown in FIG. In addition, it is assumed that the threshold voltage Vta of the diode-connected NMOS transistor in the signature ID circuits 120, 121,..., 12n of the first semiconductor memory chip 100 is 1V. Assume that the threshold voltage (Vtb) of the diode-connected NMOS transistor in the signature ID circuits 220, 221, ..., 22n in Fig. 9) is 0.8V.

Referring to FIG. 3, the first and second semiconductor memory chips 100 and 200 include respective reference signature ID circuits 120 and 220. For example, the respective reference signature ID circuits 120 and 220 do not fuse cut in the signature ID circuit 20 of FIG. 2. That is, in the test operation, the reference pads PAD_0 and 130 of the first reference signature ID circuit 120 have Vta (1V) and the reference pads PAD_0 and 230 of the second reference signature ID circuit 220. ) Has Vtb (0.8V).

 The plurality of signature ID circuits 121 to 12n of the first semiconductor memory chip 100 and the plurality of signature ID circuits 221 to 22n of the second semiconductor memory chip 200 have signature IDs according to whether fuses are cut or not. Save the information. For example, the signature ID circuit 121 of the first semiconductor memory chip 100 stores information corresponding to 2Vta (2V) when the first fuse F1 is cut, and the first to third fuses F1. If ~ F3) is cut, it stores the information corresponding to 4Vta (4V). Similarly, the signature ID circuit 221 of the second semiconductor memory chip 200 stores information corresponding to 2 Vtb (1.6 V) when the first fuse F1 is cut, and stores the first through third fuses F1 ˜. When F3) is cut, information corresponding to 4Vtb (3.2V) is stored.

FIG. 4 is a diagram illustrating signature ID information according to fuse cutting in the signature ID circuit shown in FIG. 3. In FIG. 4, the first voltage section does not include a reference signature ID circuit, and the second voltage section includes a case with a reference signature ID circuit.

According to the first voltage section, when the first to second fuses F1 to F2, the first to third fuses F1 to F3, and the first to fourth fuses F1 to F4 are cut, the second The signature ID information stored in the semiconductor memory chip is failed. This is because voltage sections are determined by measured voltage values without reference signature ID information. For example, when the first to third fuses F1 to F3 in the signature ID circuit of the first semiconductor memory chip 100 are cut, the signature ID circuit stores the signature ID information corresponding to 4V. do. However, in the case of the second semiconductor memory chip 100, the signature ID information corresponding to 3.2V is stored. According to the first voltage section, the second semiconductor memory chip 200 is failed because the first to third fuses have a voltage value of 3.5 V to 4.5 V when the fuses are cut.

However, according to the second voltage section, since the voltage section is determined based on the reference signature ID information, no fail occurs even when the threshold voltage Vt of the NMOS transistor in the signature ID circuit is changed. For example, when the first to third fuses in the signature ID circuit of the first semiconductor memory chip 100 are cut, the signature ID circuit stores the signature ID information corresponding to 4Vta. The signature ID circuit of the second semiconductor memory chip 200 stores signature ID information corresponding to 4 Vtb. According to the second voltage section, since the first to third fuses have a voltage value of 3.5 Vt to 4.5 Vt when the first to third fuses are cut, the second semiconductor memory chip 200 is not failed. Here, Vt is a voltage value obtained by measuring reference signature ID information.

5 is a flowchart illustrating a method of testing signature ID information of a semiconductor memory chip according to the present invention.

In step S100, the signature ID test enable signal is applied to the semiconductor memory chip. Here, the enable signal is to set the power supply terminal VDDQ to 0V. In step S200, current is provided to the signature ID pads. In operation S300, voltage values of signature ID pads of all chips are measured. In step S400, the voltage section is set based on the voltage value of the reference signature ID pad. At step S500, the correct signature ID information is identified.

According to the method of testing a semiconductor memory chip including a reference signature ID circuit and its signature ID information according to the present invention, even if the threshold voltage of an NMOS transistor in a signature ID circuit is changed, accurate signature ID information can be obtained. Can be. In addition, when an extra pad exists in the semiconductor chip, a plurality of reference signature ID circuits may be provided to set the voltage section to the measured value without calculating the threshold voltage value for the fuse cutting. This will give you more accurate signature ID information.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

According to the present invention, it is possible to obtain accurate signature ID information regardless of the threshold voltage of the NMOS transistor in the signature ID circuit.

Claims (6)

In a semiconductor memory chip: A plurality of pads connected to internal circuits of the semiconductor memory chip; A reference signature ID circuit electrically connected to at least one pad of the plurality of pads (hereinafter, referred to as first pads) and storing reference signature ID information; And And a plurality of signature ID circuits electrically connected to a plurality of pads (hereinafter, referred to as second pads) except for the first pads and storing signature ID information corresponding to an integer multiple of the reference signature ID information. Semiconductor memory chip. The method of claim 1, And said reference signature ID circuit and said plurality of signature ID circuits each comprise a plurality of diode-connected NMOS transistors. The method of claim 2, And the reference signature ID information and the signature ID information vary according to threshold voltages of the plurality of diode-connected NMOS transistors. The method of claim 2, And the reference signature ID circuit and the plurality of signature ID circuits change threshold voltages of the plurality of diode-connected NMOS transistors according to fuse cutting. In a method of reading the signature ID information of a semiconductor memory chip: The semiconductor memory chip, A plurality of pads connected to internal circuits of the semiconductor memory chip; A reference signature ID circuit electrically connected to at least one pad of the plurality of pads (hereinafter, referred to as first pads) and storing reference signature ID information; And And a plurality of signature ID circuits electrically connected to a plurality of pads (hereinafter, referred to as second pads) except for the first pads and storing signature ID information corresponding to an integer multiple of the reference signature ID information. and, The method of reading the signature ID information, Providing a signature ID test enable signal to the semiconductor memory chip; Supplying current to the plurality of pads; Measuring voltage at the plurality of pads; Obtaining voltage values of the second pads based on voltage values of the first pads; And And identifying the signature ID information through the voltage values of the second pads. The method of claim 5, The test enable signal is a signature ID information reading method of a semiconductor memory chip, characterized in that 0V provided to the power pad of the plurality of pads.

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