JP2009188301A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2009188301A
JP2009188301A JP2008028705A JP2008028705A JP2009188301A JP 2009188301 A JP2009188301 A JP 2009188301A JP 2008028705 A JP2008028705 A JP 2008028705A JP 2008028705 A JP2008028705 A JP 2008028705A JP 2009188301 A JP2009188301 A JP 2009188301A
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semiconductor
semiconductor chip
wafer
manufacturing
semiconductor device
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JP5341359B2 (en
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Yoko Serizawa
葉子 芹澤
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Seiko Instruments Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which can obtain easily a lot number of a semiconductor chip, a wafer number and a position information in a wafer even after dividing the semiconductor chip into individual pieces. <P>SOLUTION: After probing testing of the semiconductor chip 2, according to an identification rule determined beforehand, an identification mark is provided in a pad opening portion 7, a dummy wiring portion 3 and a fuse portion 4 in the semiconductor chip 2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体チップを個片化した後でも、半導体チップのロット番号、ウェハ番号、ウェハ内の位置情報を容易に得ることができる半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, in which a lot number, a wafer number, and position information in a wafer can be easily obtained even after the semiconductor chips are separated.

従来の半導体ウェハを半導体チップ個々に切断分離後にウェハ内におけるチップ個々の正確な位置を判別する方法として、前工程では複数回パターン形成して識別マークを付する方法がある。(例えば、特許文献１参照)
また、予め取り込んでいた半導体ウェハの裏面研削痕の画像データと、ＬＳＩチップの裏面研削痕の画像データとを重ね合わせて照合し、ＬＳＩチップの半導体ウェハにおける位置を特定する方法などもある。(例えば、特許文献２参照)
特開平７−１２２４７９号公報 特開２００４−５５８８２号公報 As a method for discriminating the accurate position of each chip in the wafer after the semiconductor wafer is cut and separated into individual semiconductor wafers, there is a method of forming an identification mark by patterning a plurality of times in the previous process. (For example, see Patent Document 1)
There is also a method of identifying the position of the LSI chip on the semiconductor wafer by superimposing and collating the image data of the backside grinding trace of the semiconductor wafer and the image data of the backside grinding trace of the LSI chip that have been captured in advance. (For example, see Patent Document 2)
JP-A-7-122479 JP 2004-55882 A

しかしながら、上記の複数回のパターン形成で識別マークを付する方法では、製造工程やマスク等が増えて露光方法や装置の管理方法が複雑化し、またマーク付加によるチップ面積が大きくなるという問題点があった。また、裏面画像データを取り込み照合するという方法では、保存するデータが膨大となることや小さな半導体チップでは隣接する半導体チップとの識別が困難になるという懸念がある。   However, the above-described method of attaching an identification mark by patterning a plurality of times has a problem in that the number of manufacturing processes, masks, etc. increase, the exposure method and the management method of the apparatus become complicated, and the chip area increases due to the addition of the mark. there were. Further, in the method of taking back side image data and collating, there is a concern that the data to be stored becomes enormous and that it is difficult to distinguish between adjacent semiconductor chips with a small semiconductor chip.

本発明では、製造工程が増えてしまう複雑な手法ではなく、簡単な方法によって、ウェハ面付け効率も良好で、識別も容易な識別マークを半導体チップへ付することを目的とする。   An object of the present invention is to attach an identification mark to a semiconductor chip with good wafer imposition efficiency and easy identification by a simple method, not a complicated method that increases the number of manufacturing steps.

上記課題を解決するために、本発明では以下のような手段を用いた。   In order to solve the above problems, the present invention uses the following means.

半導体ウェハ上に複数の半導体チップを形成する工程と、前記半導体チップをプロービング試験する工程と、前記半導体ウェハのロット番号、ウェハ番号、半導体ウェハ内の位置情報と、これに対応した識別マークとの間の識別ルールを決める工程と、前記半導体チップに表面から入射するレーザによって、前記半導体チップの所望の領域に、前記識別ルールに従って、半導体ウェハのロット番号、ウェハ番号および半導体ウェハ内の位置情報を認識できる識別マークを付する工程と、を有することを特徴とする半導体装置の製造方法とする。   A step of forming a plurality of semiconductor chips on a semiconductor wafer, a step of probing the semiconductor chip, a lot number of the semiconductor wafer, a wafer number, position information in the semiconductor wafer, and an identification mark corresponding thereto A step of determining an identification rule between the semiconductor wafer, a laser beam incident on the semiconductor chip from the surface, and a semiconductor wafer lot number, a wafer number, and position information in the semiconductor wafer in a desired region of the semiconductor chip according to the identification rule And a step of attaching a recognizable identification mark.

また、前記所望の領域が、前記半導体チップのパッド開口部の周縁部であることを特徴とする半導体装置の製造方法とする。   Further, the semiconductor device manufacturing method is characterized in that the desired region is a peripheral portion of a pad opening of the semiconductor chip.

また、前記所望の領域が、前記半導体チップのパッド開口部以外の配線パターンが形成されていない領域であることを特徴とする半導体装置の製造方法とする。   Further, the semiconductor device manufacturing method is characterized in that the desired region is a region where a wiring pattern other than the pad opening of the semiconductor chip is not formed.

また、前記所望の領域が、前記半導体チップのダミー配線領域であることを特徴とする半導体装置の製造方法とする。   Further, the semiconductor device manufacturing method is characterized in that the desired region is a dummy wiring region of the semiconductor chip.

また、前記所望の領域が、前記半導体チップのヒューズ領域であることを特徴とする半導体装置の製造方法とする。   Further, the semiconductor device manufacturing method is characterized in that the desired region is a fuse region of the semiconductor chip.

また、前記識別マークが、一つの半導体チップに複数箇所設けられていることを特徴とする半導体装置の製造方法とする。   The semiconductor device manufacturing method is characterized in that a plurality of the identification marks are provided on one semiconductor chip.

また、前記入射するレーザがフェムト秒レーザであることを特徴とする半導体装置の製造方法とする。   The semiconductor device manufacturing method is characterized in that the incident laser is a femtosecond laser.

さらには、半導体ウェハ上に複数の半導体チップを形成する工程と、前記半導体チップをプロービング試験する工程と、前記半導体チップのヒューズをトリミングする工程と、前記ヒューズの破断面の画像データを取り込む工程と、前記半導体チップの位置情報、ウェハ番号、ロット番号などの識別情報を取り込む工程と、前記画像データと前記識別情報を照合する工程と、を有することを特徴とする半導体装置の製造方法とする。   Furthermore, a step of forming a plurality of semiconductor chips on a semiconductor wafer, a step of probing the semiconductor chip, a step of trimming a fuse of the semiconductor chip, and a step of capturing image data of a fracture surface of the fuse A method of manufacturing a semiconductor device, comprising: a step of taking identification information such as position information of the semiconductor chip, a wafer number, and a lot number, and a step of collating the image data with the identification information.

また、前記トリミングは、レーザ法もしくは電流法によって実施されることを特徴とする半導体装置の製造方法とする。   The trimming is performed by a laser method or a current method.

以上の半導体装置の製造方法を行うことで、半導体チップに対し、容易に識別マークを付することができ、その識別マークから半導体チップの位置情報ばかりでなく、ウェハ番号やロット番号までも認識することができる。   By performing the semiconductor device manufacturing method described above, an identification mark can be easily attached to a semiconductor chip, and not only the position information of the semiconductor chip but also the wafer number and lot number are recognized from the identification mark. be able to.

以下、本発明の実施の形態を図１および図２に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2.

図１は、半導体チップが面付けされた半導体ウェハの平面図である。半導体ウェハ１の表面には複数の半導体チップ２が整然と面付けされている。この半導体チップは、微細なパターンはレチクルを使ったステップアンドリピート方式で製造され、パッド開口などの疎なパターンの場合はマスクを使った一括露光方式で製造したものである。   FIG. 1 is a plan view of a semiconductor wafer having semiconductor chips attached thereto. A plurality of semiconductor chips 2 are regularly arranged on the surface of the semiconductor wafer 1. In this semiconductor chip, a fine pattern is manufactured by a step-and-repeat method using a reticle, and a sparse pattern such as a pad opening is manufactured by a batch exposure method using a mask.

図２は、本発明の実施例を示す半導体チップの拡大図である。図２(a)は、半導体チップのパッド開口部付近の拡大図であり、図２(b)は、半導体チップのダミー配線やヒューズ部の拡大図を示している。   FIG. 2 is an enlarged view of a semiconductor chip showing an embodiment of the present invention. 2A is an enlarged view of the vicinity of the pad opening of the semiconductor chip, and FIG. 2B is an enlarged view of the dummy wiring and the fuse portion of the semiconductor chip.

図２(a)に示す半導体チップではパッド開口部７の中に識別マーク６が形成されている。パッド開口部７にはアルミ合金などの金属膜が露出しているため、プロービング試験を終えた後にレーザを照射することにより、容易に識別マーク６を付することができる。識別マーク６は半導体ウェハ内の位置情報だけでなく、ウェハ番号やロット番号も認識できるようにマーキングしておく。識別マーク６とロット番号、ウェハ番号、位置情報、さらには半導体チップの品質情報との間の識別ルールは予め決めておいて、これに従って識別マーク６が付される。   In the semiconductor chip shown in FIG. 2A, an identification mark 6 is formed in the pad opening 7. Since a metal film such as an aluminum alloy is exposed in the pad opening 7, the identification mark 6 can be easily attached by irradiating a laser after the probing test is completed. The identification mark 6 is marked so that not only the position information in the semiconductor wafer but also the wafer number and lot number can be recognized. An identification rule between the identification mark 6 and the lot number, wafer number, position information, and quality information of the semiconductor chip is determined in advance, and the identification mark 6 is attached accordingly.

識別マーク６はパッド開口部７を形成する保護膜の縁端部分の一部に設けることが望ましい。これは後のボンディング工程を経ても識別可能とするためである。小さなチップでは一枚のウェハから数万個から数十万個の収量を得られるが、複数のパッドを活用したり、一つのパッドの中に複数の識別マーク６を付したりすることで全ての半導体チップに位置を認識するための識別マークを設けることが可能である。レーザの照射条件によっては照射部の金属膜を全除去することも表層のみを除去することも可能である。パッド下に半導体素子が形成されているのであれば、ダメージの少ない表層除去が望ましい。   The identification mark 6 is desirably provided on a part of the edge portion of the protective film that forms the pad opening 7. This is because identification is possible even after a subsequent bonding step. With a small chip, a yield of tens of thousands to hundreds of thousands can be obtained from a single wafer, but all of them can be obtained by using multiple pads or attaching multiple identification marks 6 in one pad. An identification mark for recognizing the position can be provided on the semiconductor chip. Depending on the laser irradiation conditions, it is possible to completely remove the metal film of the irradiated portion or to remove only the surface layer. If a semiconductor element is formed under the pad, it is desirable to remove the surface layer with little damage.

上述の実施例では、パッド開口部に識別マークを付する方法を示したが、パッド開口部以外の配線パターンが形成されていない領域８にも識別マーク６を付することも可能である。これは半導体チップの中の半導体素子間の領域のうち、比較的隙間の大きい領域を活用する方法であるが、この場合は焦点制御可能で微小なマーキングが可能なレーザ、例えばフェムト秒レーザなどの方式を用いて、保護膜表面や保護膜内部に識別マークを付することができる。   In the above-described embodiment, the method of attaching the identification mark to the pad opening is shown. However, it is also possible to attach the identification mark 6 to the region 8 where the wiring pattern other than the pad opening is not formed. This is a method of utilizing a region having a relatively large gap among regions between semiconductor elements in a semiconductor chip. In this case, a laser capable of fine marking, such as a femtosecond laser, can be controlled in focus. An identification mark can be attached to the surface of the protective film or inside the protective film by using the method.

図２(ｂ)は、ダミー配線やヒューズを有する半導体チップの拡大図である。半導体チップの領域５にはダミー配線３、４やヒューズ６が配置されており、パッド開口部７にはプローブ針９が接触している。ヒューズ６は半導体チップの抵抗値や検出電圧を決定するためにトリミングという手法で部分的にカットされる。カットの手法にはレーザによるものや電流によるもの等様々である。カットされたヒューズの切断面は一様ではなく、個々で異なる。半導体ウェハ上の全ての半導体チップについて、ヒューズ切断面の画像データを半導体ウェハのロット番号、ウェハ番号および半導体チップの位置情報とともにコンピュータ当を介してハードディスク等の記憶媒体にデータとして取り込む。このようなデータを予め保管しておけば、半導体チップを個片化した後でも半導体チップの照合が可能となる。   FIG. 2B is an enlarged view of a semiconductor chip having dummy wirings and fuses. Dummy wirings 3 and 4 and a fuse 6 are disposed in the region 5 of the semiconductor chip, and a probe needle 9 is in contact with the pad opening 7. The fuse 6 is partially cut by a technique called trimming to determine the resistance value and detection voltage of the semiconductor chip. There are various cutting methods such as laser and current. The cut surfaces of the cut fuses are not uniform and vary from one individual to another. For all the semiconductor chips on the semiconductor wafer, the image data of the fuse cut surface is taken as data into a storage medium such as a hard disk through a computer together with the lot number of the semiconductor wafer, the wafer number and the position information of the semiconductor chip. If such data is stored in advance, the semiconductor chip can be verified even after the semiconductor chip is separated.

また、ヒューズカットして不要となった配線に対して半導体ウェハのロット番号、ウェハ番号および半導体チップの位置情報に応じた識別ルールに従って識別マークを付するという方法もある。   There is also a method in which an identification mark is attached to a wiring that becomes unnecessary after the fuse is cut, according to an identification rule corresponding to the lot number of the semiconductor wafer, the wafer number, and the position information of the semiconductor chip.

照合は、ダイシング工程以降の様々な場面、例えば、パッケージ工程などの後工程、信頼性試験工程、出荷検査工程、そして、ユーザーからの問合せなど様々な工程や場面で必要とされるが、本発明の方法を用いれば、容易にかつ迅速に半導体チップの情報を得ることができる。   The verification is required in various scenes after the dicing process, for example, a post process such as a packaging process, a reliability test process, a shipping inspection process, and various processes and scenes such as an inquiry from the user. If this method is used, information on the semiconductor chip can be obtained easily and quickly.

図２(ｂ)には、ヒューズ４の他、ダミー配線３を示しているが、半導体ウェハのロット番号、ウェハ番号および半導体チップの位置情報に応じて、ダミー配線３の一部をカットする。後の工程で位置情報等が必要になった場合は、ダミー配線のカット位置を観察し、予め決めておいた識別ルールと照合するだけで、半導体チップの位置情報、ウェハ番号、ロット番号を容易に得ることができる。この場合、一つの半導体チップ当りのカット箇所は一つである必要はなく、ロット番号、ウェハ番号、位置情報毎にカットすることであっても良いし、さらに、ロット番号等の個別項目につき複数のカットを行っても良い。   FIG. 2B shows the dummy wiring 3 in addition to the fuse 4, but a part of the dummy wiring 3 is cut according to the lot number of the semiconductor wafer, the wafer number, and the position information of the semiconductor chip. If location information is required in a later process, the position of the semiconductor chip, wafer number, and lot number can be easily obtained by simply observing the cut position of the dummy wiring and comparing it with a predetermined identification rule. Can get to. In this case, it is not necessary to have one cut location per semiconductor chip, and it may be cut for each lot number, wafer number, position information, and more than one for each item such as a lot number. You may make a cut.

以上説明したように、本発明の半導体装置の製造方法を用いれば、半導体チップが個片化された状態でも半導体チップの位置情報等を容易に取得することができる。   As described above, by using the method for manufacturing a semiconductor device of the present invention, it is possible to easily acquire the position information of the semiconductor chip even when the semiconductor chip is singulated.

本発明の実施例を示す半導体チップを面付けした半導体ウェハの平面図The top view of the semiconductor wafer which imposed the semiconductor chip which shows the Example of this invention 本発明の実施例を示す半導体チップの拡大図 （ａ）半導体チップのパッド開口部付近の拡大図 （ｂ）半導体チップのダミー配線やヒューズ部の拡大図(A) Enlarged view of the vicinity of the pad opening of the semiconductor chip (b) Enlarged view of the dummy wiring and fuse portion of the semiconductor chip

符号の説明Explanation of symbols

１ 半導体ウェハ
２ 半導体チップ
３ ダミー配線
４ ヒューズ
５ 半導体チップのダミー配線やヒューズを有する領域
６ 識別マーク
７ パッド開口部
８ 配線パターンが形成されていない領域
９ プローブ針 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor chip 3 Dummy wiring 4 Fuse 5 Area | region which has dummy wiring and fuse of semiconductor chip 6 Identification mark 7 Pad opening 8 Area | region where wiring pattern is not formed 9 Probe needle

Claims (9)

半導体ウェハ上に複数の半導体チップを形成する工程と、
前記半導体チップをプロービング試験する工程と、
前記半導体ウェハのロット番号、ウェハ番号、半導体ウェハ内の位置情報と、これに対応した識別マークとの間の識別ルールを決める工程と、
前記半導体チップに表面から入射するレーザによって、前記半導体チップの所望の領域に、前記識別ルールに従って、前記半導体ウェハのロット番号、ウェハ番号および半導体ウェハ内の位置情報を認識できる前記識別マークを付する工程と、を有することを特徴とする半導体装置の製造方法。 Forming a plurality of semiconductor chips on a semiconductor wafer;
Probing the semiconductor chip; and
A step of determining an identification rule between the lot number of the semiconductor wafer, the wafer number, position information in the semiconductor wafer, and an identification mark corresponding thereto;
The identification mark which can recognize the lot number of the semiconductor wafer, the wafer number, and the position information in the semiconductor wafer is attached to a desired region of the semiconductor chip according to the identification rule by a laser incident on the semiconductor chip from the surface. And a method of manufacturing a semiconductor device. 前記所望の領域が、前記半導体チップのパッド開口部の周縁部であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the desired region is a peripheral portion of a pad opening of the semiconductor chip. 前記所望の領域が、前記半導体チップのパッド開口部以外の配線パターンが形成されていない領域であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the desired region is a region where a wiring pattern other than the pad opening of the semiconductor chip is not formed. 前記所望の領域が、前記半導体チップのダミー配線領域であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the desired region is a dummy wiring region of the semiconductor chip. 前記所望の領域が、前記半導体チップのヒューズ領域であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the desired region is a fuse region of the semiconductor chip. 前記識別マークが、一つの半導体チップに複数箇所設けられていることを特徴とする請求項１乃至請求項５のいずれか一項記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of identification marks are provided on one semiconductor chip. 前記入射するレーザがフェムト秒レーザであることを特徴とする請求項１乃至請求項６のいずれか一項記載の半導体装置の製造方法。   The semiconductor device manufacturing method according to claim 1, wherein the incident laser is a femtosecond laser. 半導体ウェハ上に複数の半導体チップを形成する工程と、
前記半導体チップをプロービング試験する工程と、
前記半導体チップのヒューズをトリミングする工程と、
前記ヒューズの破断面の画像データを取り込む工程と、
前記半導体チップの位置情報、ウェハ番号、ロット番号などの識別情報を取り込む工程と、を有することを特徴とする半導体装置の製造方法。 Forming a plurality of semiconductor chips on a semiconductor wafer;
Probing the semiconductor chip; and
Trimming the fuse of the semiconductor chip;
Capturing image data of the fracture surface of the fuse;
And a step of taking identification information such as position information, wafer number, lot number and the like of the semiconductor chip. 前記トリミングは、レーザ法もしくは電流法によって実施されることを特徴とする請求項８に記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the trimming is performed by a laser method or a current method.
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