CN110690176B - Method for distinguishing target crystal grains and failure analysis method of packaged chip - Google Patents
Method for distinguishing target crystal grains and failure analysis method of packaged chip Download PDFInfo
- Publication number
- CN110690176B CN110690176B CN201910972839.4A CN201910972839A CN110690176B CN 110690176 B CN110690176 B CN 110690176B CN 201910972839 A CN201910972839 A CN 201910972839A CN 110690176 B CN110690176 B CN 110690176B
- Authority
- CN
- China
- Prior art keywords
- target
- crystal grains
- grains
- distinguishing
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The invention relates to a method for distinguishing target crystal grains and a method for analyzing failure of a packaged chip, wherein the method for distinguishing the target crystal grains comprises the following steps: obtaining a sample with a plurality of crystal grains, wherein at least one crystal grain is a target crystal grain, and at least part of a cutting path area at the edge of each crystal grain is exposed; determining the position of the target grain in the sample; forming laser marks in a cutting path area at the edge of a part of the crystal grains so as to distinguish the target crystal grains from the crystal grains except the target crystal grains; separating the plurality of grains; and distinguishing the target crystal grains according to whether the laser marks are formed in the cutting path area of the edge of each crystal grain. The method for distinguishing the target crystal grains can improve the distinguishing efficiency and avoid damaging the target crystal grains.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for distinguishing target crystal grains and a method for analyzing failure of a packaged chip.
Background
In the current mass storage chip, a commonly adopted method for increasing the storage capacity of a single package is to stack a plurality of storage dies (die) into a packaged chip product, for example, up to 16 dies are packaged into a single packaged chip product. However, in such packaged products, if a die fails, it needs to be individually removed from the stacked dies for analysis. Because the chip function and the position in the packaged chip are fixed, the specific position of the failed crystal grain in the sample can be determined according to the test result under the state that the position of each crystal grain is fixed; however, in the process of obtaining the failed die, the dies need to be separated so as to be tested individually. However, each die in the packaged chip generally has the same appearance, and after separation, the position of each die is not determined, and it is difficult to find the target die from the position.
In the prior art, in order to solve the above problem, the target crystal grains are usually removed by grinding in a state where the crystal grains are stacked. In the case of a grain stack, the position of each grain is determined, and thus other grains can be removed by grinding, leaving only the target grain.
In the process of removing the target crystal grains by a grinding method, the crystal grains are easy to be cracked; the grinding uniformity is difficult to control, and target crystal grains are easy to be incomplete; moreover, if the number of stacked grains is large, the whole grinding process is time-consuming and requires a high requirement for operators.
Therefore, how to efficiently distinguish the target grains is a problem to be solved.
Disclosure of Invention
The invention aims to provide a method for distinguishing target crystal grains and a method for analyzing the failure of a packaged chip, and improve the efficiency of distinguishing the target crystal grains.
The invention provides a method for distinguishing target crystal grains, which comprises the following steps: obtaining a sample with a plurality of crystal grains, wherein at least one crystal grain is a target crystal grain, and at least part of a cutting path area at the edge of each crystal grain is exposed; determining the position of the target grain in the sample; forming laser marks in a cutting path area at the edge of a part of the crystal grains so as to distinguish the target crystal grains from the crystal grains except the target crystal grains; separating the plurality of grains; and distinguishing the target crystal grains according to whether the laser marks are formed in the cutting path area of the edge of each crystal grain.
Optionally, the appearance of each of the grains is the same.
Optionally, the laser mark is formed in a scribe line region at the edge of the target grain.
Optionally, the laser mark is formed in a scribe line region of a grain other than the target grain.
Optionally, the depth of the laser mark is 1 μm to 10 μm, and the width of the pattern line of the laser mark is 1 μm to 10 μm.
Optionally, the die includes a functional region and the dicing street region surrounding the functional region; the laser mark is located entirely within the scribe line region.
Optionally, the multiple crystal grains are stacked and fixed by an adhesive layer; the edges of the dies are staggered so that at least a portion of the scribe line area at the edge of each die is exposed.
Optionally, the method for separating the plurality of crystal grains includes: the sample is treated with a chemical reagent that dissolves the adhesive layer, causing the grains to separate from each other.
Optionally, the laser mark is located on the front side or/and the back side of the target crystal grain.
Optionally, the method for obtaining the sample with the plurality of grains comprises: providing a packaged chip; and treating the packaged chip by fuming nitric acid, removing the packaged shell of the packaged chip, and obtaining the sample.
Optionally, the pattern of laser marks comprises at least one of dots, lines, circles, rectangles, or polygons.
The technical scheme of the invention also provides a failure analysis method of the packaged chip, wherein a plurality of crystal grains are packaged in the packaged chip, and the failure analysis method comprises the following steps: determining the positions of failed crystal grains in the packaged chip in the plurality of crystal grains, and taking the failed crystal grains as target crystal grains; adopting any one of the above distinguishing methods for the target crystal grains to distinguish and independently extract failure crystal grains in the plurality of crystal grains; and carrying out failure analysis on the failed crystal grains.
Optionally, the packaged chip is a memory chip.
The method for distinguishing the target crystal grains distinguishes the target crystal grains from the non-target crystal grains by forming the laser marks on the cutting path regions at the edges of the target crystal grains or the non-target crystal grains, is easy to realize, does not damage devices in the crystal grains, and thus avoids influencing the accuracy of the test result of the subsequent test on the target crystal grains.
Drawings
Fig. 1 to 4 are schematic diagrams illustrating a process of differentiating a target crystal grain according to an embodiment of the present invention.
Detailed Description
The following describes in detail specific embodiments of a method for distinguishing a target die and a method for analyzing a failure of a packaged chip according to the present invention with reference to the accompanying drawings.
Referring to fig. 1, a sample 100 having a plurality of dies 101 is obtained, wherein at least one die 101 is a target die 101a and at least a partial scribe line region at the edge of each die 101 is exposed; the position of the target grain 101a in the sample 100 is determined.
The die 101 is a bare chip formed by cutting a wafer. The sample 100 may be obtained from inside a packaged chip, a plurality of grains are packaged in the packaged chip, and the sample 100 may be obtained after removing a package case of the packaged chip. In one embodiment, the sample may be obtained by treating the packaged chip with fuming nitric acid, and removing the package casing of the packaged chip. In fig. 1, sample 100 having four grains 101 is taken as an example only, and in other embodiments, there may be less than four or more than four grains within the sample. For example, a sample taken within a memory chip may include 16 grains.
In the process of cutting the wafer to form the dies, a plurality of dies are usually formed on the wafer, a cutting street with a certain width is formed between adjacent dies, and the dies are cut along the cutting street to be divided. The width of the scribe line can be about tens of microns, and during the cutting process, the scribe line is usually cut along the center line of the scribe line, so that a scribe line with a certain width remains at the edge of the divided crystal grain. Thus, the die 101 includes a functional area and a scribe line area 1011 surrounding the functional area. And each die 101 in the sample 100 exposes at least a portion of the scribe line area 1011.
The position of each die 101 within the sample 100 is relatively fixed. In a process of testing a packaged chip, when a certain die inside the packaged chip is found to be failed, the failed die needs to be taken out for failure analysis. Under the condition that the positions of all crystal grains are fixed, according to the test result, the specific positions of the failure crystal grains, namely the target crystal grains in the sample can be determined. In this particular embodiment, the position of the target grain 101a within the sample 100 is determined.
In this embodiment, the dies 101 are stacked on top of each other and have staggered edges such that a portion of the scribe line area 1011 at the edge is exposed from each die 101. The edges of the crystal grains 101 are stacked in a staggered manner, so that the stability of the stacked structure is easy to maintain, and the problems of collapse and the like are avoided.
A protection layer 102 is formed on the front surface of each die 101 to protect devices or connection structures on the surface of the die 101. Adjacent crystal grains 101 are fixed by an adhesive layer 103. Specifically, in two adjacent dies 101, the back surface of one die 101 is stacked and fixed on the protection layer 102 on the front surface of the other die 101.
Referring to fig. 2, the target crystal grain and the crystal grains other than the target crystal grain are distinguished by forming a laser mark in a scribe line region at a part of the edge of the crystal grain.
The distinction between target grains and non-target grains may be achieved by laser marking the scribe line regions of the target grains or grains other than the target grains within the sample.
In this embodiment, the laser mark 201 is formed in the scribe lane area 1011 at the edge of the die 101 other than the target die 101a, so as to completely avoid the possibility of damaging the target die 100a during the process of forming the laser mark 201, and avoid affecting the accuracy of the subsequent analysis of the target die 100 a.
The scribe line region 1011 is locally irradiated with laser light, and a laser mark 201 is formed at a position corresponding to the scribe line region 1011 due to high energy density of the laser light. In this embodiment, the laser mark 201 is a recess with a certain depth, and a laser mark with a specific pattern can be formed by moving the laser.
In other embodiments, the differentiation may also be made by forming laser marks only on the target crystal grains 101 a. Since the number of the target crystal grains 101a is small, the laser mark is formed on the target crystal grain 101a, and the number of the laser marks to be formed can be reduced, thereby reducing the time taken to form the laser mark and improving the efficiency. Further, possible damage to the target die 101a can be avoided by using a laser of lower energy and controlling the size of the laser mark 201.
The laser mark 201 can be formed by a laser marking machine, the laser has a small beam diameter due to high beam concentration degree of laser, the angle of the beam is easy to control, and the laser mark 201 can be formed at any required position in a cutting track area 1011 exposed at the edge of the crystal grain 101. Since the scribe line region 1011 is located at the edge-most position of the crystal grains 101, the laser beam is not easily blocked between the adjacent crystal grains 101 during the process of forming the laser mark 201 even if the adjacent crystal grains 101 are stacked on each other.
In a specific embodiment of the present invention, the depth of the laser mark 201 is 1 μm to 10 μm, and the pattern width is 1 μm to 10 μm, so as to avoid transmitting damage to the functional region of the die 101 due to the transmission effect in the material. The laser mark 201 is located completely within the scribe line region 1011, and preferably located at the outermost edge of the scribe line region 1011, so as to minimize the influence of the laser mark 201 on the functional area inside the die 101.
The laser mark may be selectively formed on the front or back of each die 101 according to the position of the exposed scribe line region 1011 at the edge of the die 101. For the convenience of subsequent identification, the laser mark 201 may also be formed on both the front and back sides of the die 101. In the case where the laser mark is not easily formed on the front and back surfaces of the die 101, for example, in the case where the size of the exposed scribe line region is too small, the laser mark may be selectively formed on the side surface of the die 101, but in the process of forming the laser mark on the side surface, it is necessary to take care to control the position of the sample, so as to prevent the die in the sample 100 from being vertically placed as much as possible, and thus the inside of the functional region in the die is affected by the stress.
The pattern of the laser mark 201 may include at least one of a dot, a line, a circle, a rectangle, or a polygon. The shape and depth of the laser mark 201 can be set by the skilled person according to the needs. The width of the line or pattern size of the laser mark 201 may be in the range of 1 μm to 10 μm for easy recognition.
Referring to fig. 3, a plurality of grains 101 in the sample 100 are separated.
Since the crystal grains 101 are fixed to each other by the adhesive layer 103 (see fig. 2), the crystal grains 101 may be separated by removing the adhesive layer 103 or modifying the adhesive layer 103 to remove the adhesiveness.
The high-temperature baking can reduce the adhesion of the adhesive layer 103, and thus the crystal grains 101 are easily separated one by one. However, since the high temperature process easily causes the performance degradation of the devices inside the die 101 and increases the risk of the operation process, it is necessary to avoid the high temperature process.
Preferably, the sample is treated with a chemical reagent that dissolves the adhesive layer 103, dissolving the adhesive layer 103, thereby separating the individual grains 101 from each other. Specifically, the sample may be soaked in the chemical reagent, and the grains 101 may be separated from each other by dissolving the adhesive layer 103 for a certain period of time. After the dies 101 are separated from each other, the positions of the dies are uncertain, and the target die 101a cannot be directly and accurately obtained.
Referring to fig. 4, the target die 101a is identified according to whether the laser mark is formed in the scribe line region 1011 at the edge of each die 101.
Since the size of the laser mark 201 is in the micrometer scale, whether the laser mark 201 exists or not can be observed obviously through a microscope. The edge of each of the separated crystal grains 101 is observed by a microscope, and the target chip 101a can be accurately obtained.
In this embodiment, the laser mark 201 is formed on the edge of the crystal grain 101 other than the target crystal grain 101 a. Therefore, when the existence of any laser mark 201 is observed on a certain crystal grain 101, it can be confirmed that the crystal grain 101 is the target crystal grain 101 a.
In other embodiments, laser marks may be formed directly on the target die 101 a. When the laser mark 201 is observed on a certain crystal grain 101 after the crystal grains 101 are separated from each other, it is confirmed that the crystal grain 101 is the target crystal grain 101 a.
According to the method for distinguishing the target crystal grains, the laser marks are formed on the cutting path regions at the edges of the target crystal grains or the non-target crystal grains to distinguish the target crystal grains from the non-target crystal grains, the method is easy to realize, devices in the crystal grains cannot be damaged, and therefore the accuracy of the test result of the follow-up test on the target crystal grains is prevented from being influenced.
The specific implementation manner of the invention also provides a failure analysis method of the packaged chip.
The packaged chip is internally packaged with a plurality of crystal grains, and the failure analysis method specifically comprises the following steps:
step 1: and determining the specific position of the failed crystal grain in the packaged chip in the plurality of crystal grains, and taking the failed crystal grain as a target crystal grain.
Step 2: by adopting the method for distinguishing the target crystal grains in the above embodiment, the failed crystal grains in the plurality of crystal grains are distinguished and extracted individually.
And step 3: and carrying out failure analysis on the failed crystal grains.
The method for distinguishing the target crystal grains in the specific embodiment can efficiently and accurately distinguish the failed crystal grains and avoid damage to the failed crystal grains in the distinguishing process, so that the efficiency and the accuracy of failure analysis on the packaged chip can be improved.
The failure analysis method of the packaged chip is particularly suitable for chips with multiple internally packaged crystal grains having the same appearance, such as memory chips.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (13)
1. A method for distinguishing target dies, comprising:
obtaining a sample with a plurality of crystal grains, wherein the crystal grains are mutually stacked, at least one crystal grain is a target crystal grain, and at least part of cutting path areas at the edges of the mutually stacked crystal grains are exposed;
determining the position of the target grain in the sample;
forming laser marks in a cutting path area at the edge of a part of the crystal grains so as to distinguish the target crystal grains from the crystal grains except the target crystal grains;
separating the plurality of grains;
and distinguishing the target crystal grains according to whether the laser marks are formed in the cutting path area of the edge of each crystal grain.
2. The method of distinguishing a target crystal grain according to claim 1, wherein the appearance of each of the crystal grains is the same.
3. The method of differentiating a target die as claimed in claim 1, wherein the laser mark is formed within a scribe lane area at the target die edge.
4. The method of distinguishing a target crystal grain according to claim 1, wherein the laser mark is formed in a scribe lane region of a crystal grain other than the target crystal grain.
5. The method for distinguishing a target crystal grain according to claim 1, wherein the depth of the laser mark is 1 μm to 10 μm, and the width of the pattern line of the laser mark is 1 μm to 10 μm.
6. A method of distinguishing a target die as claimed in claim 1, wherein the die comprises a functional area and the scribe line area surrounding the functional area; the laser mark is located entirely within the scribe line region.
7. The method for distinguishing a target crystal grain according to claim 6, wherein a plurality of the crystal grains are fixed by an adhesive layer.
8. The method for distinguishing target grains according to claim 7, wherein the method for separating the plurality of grains comprises: the sample is treated with a chemical reagent that dissolves the adhesive layer, causing the grains to separate from each other.
9. A method of distinguishing between target dies according to claim 1 wherein the laser mark is located on the front side or/and the back side of the target die.
10. The method for distinguishing target crystal grains according to claim 1, wherein the method for obtaining the sample having the plurality of crystal grains comprises: providing a packaged chip; and treating the packaged chip by fuming nitric acid, removing the packaged shell of the packaged chip, and obtaining the sample.
11. The method of distinguishing a target grain of claim 1, wherein the pattern of laser marks comprises at least one of dots, lines, circles, rectangles, or polygons.
12. A failure analysis method of a packaged chip, wherein a plurality of crystal grains are packaged in the packaged chip, is characterized by comprising the following steps:
determining the positions of failed crystal grains in the packaged chip in the plurality of crystal grains, and taking the failed crystal grains as target crystal grains;
distinguishing and individually extracting failure grains from the plurality of grains by using the method for distinguishing target grains according to any one of claims 1 to 11;
and carrying out failure analysis on the failed crystal grains.
13. The failure analysis method of claim 12, wherein the packaged chip is a memory chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910972839.4A CN110690176B (en) | 2019-10-14 | 2019-10-14 | Method for distinguishing target crystal grains and failure analysis method of packaged chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910972839.4A CN110690176B (en) | 2019-10-14 | 2019-10-14 | Method for distinguishing target crystal grains and failure analysis method of packaged chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110690176A CN110690176A (en) | 2020-01-14 |
| CN110690176B true CN110690176B (en) | 2022-01-11 |
Family
ID=69112426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910972839.4A Active CN110690176B (en) | 2019-10-14 | 2019-10-14 | Method for distinguishing target crystal grains and failure analysis method of packaged chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110690176B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111812124B (en) * | 2020-06-24 | 2023-06-13 | 上海华力集成电路制造有限公司 | Failure analysis delamination method |
| CN113030706B (en) * | 2021-03-12 | 2021-11-23 | 长江存储科技有限责任公司 | Failure analysis sample manufacturing method and failure analysis sample |
| CN113299573B (en) * | 2021-04-28 | 2022-06-10 | 长鑫存储技术有限公司 | Wafer grinding method and wafer failure analysis method |
| CN117214186B (en) * | 2023-11-08 | 2024-01-26 | 合肥晶合集成电路股份有限公司 | Sample failure analysis method, device and medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120025344A1 (en) * | 2010-07-29 | 2012-02-02 | Stmicroelectronics S.R.L. | Traceable integrated circuits and production method thereof |
| CN103367324A (en) * | 2012-04-01 | 2013-10-23 | 上海华虹Nec电子有限公司 | Cutting channel for semiconductor chip |
| CN106783651A (en) * | 2015-11-19 | 2017-05-31 | 无锡华润上华半导体有限公司 | A kind of method for determining semiconductor device failure position |
| CN107993951A (en) * | 2017-11-21 | 2018-05-04 | 长江存储科技有限责任公司 | Method for the short circuit of fast positioning 3 D memory array area |
-
2019
- 2019-10-14 CN CN201910972839.4A patent/CN110690176B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120025344A1 (en) * | 2010-07-29 | 2012-02-02 | Stmicroelectronics S.R.L. | Traceable integrated circuits and production method thereof |
| CN103367324A (en) * | 2012-04-01 | 2013-10-23 | 上海华虹Nec电子有限公司 | Cutting channel for semiconductor chip |
| CN106783651A (en) * | 2015-11-19 | 2017-05-31 | 无锡华润上华半导体有限公司 | A kind of method for determining semiconductor device failure position |
| CN107993951A (en) * | 2017-11-21 | 2018-05-04 | 长江存储科技有限责任公司 | Method for the short circuit of fast positioning 3 D memory array area |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110690176A (en) | 2020-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110690176B (en) | Method for distinguishing target crystal grains and failure analysis method of packaged chip | |
| US7554211B2 (en) | Semiconductor wafer and manufacturing process for semiconductor device | |
| JP3386126B2 (en) | Method and apparatus for separating circuit dice from wafer | |
| US20080012096A1 (en) | Semiconductor chip and method of forming the same | |
| US7211370B2 (en) | Method for dicing wafer | |
| US8349624B2 (en) | Method for fabricating semiconductor device | |
| CN100576434C (en) | The manufacture method of chip identification and light shield | |
| CN106098577A (en) | IC substrate and manufacture method thereof | |
| CN107634032B (en) | Wafer and wafer manufacturing method | |
| CN105047612A (en) | Wafer processing method | |
| US20060255431A1 (en) | Semiconductor wafer | |
| CN106997866A (en) | The processing method of chip | |
| US20040185580A1 (en) | Method for dicing semiconductor wafer | |
| US7211500B2 (en) | Pre-process before cutting a wafer and method of cutting a wafer | |
| JP4697823B2 (en) | Method for dividing brittle substrate | |
| US10454240B2 (en) | Method of producing an optoelectronic component | |
| CN106783651B (en) | Method for determining failure position of semiconductor device | |
| JPH10288585A (en) | Method and device for analyzing cut part | |
| KR20100010841A (en) | Semiconductor chip layout and semiconductor chip with chip seperation region | |
| US20150279786A1 (en) | Semiconductor wafer | |
| KR100674950B1 (en) | Semiconductor wafer including reference semiconductor chip and method of semiconductor chip assembly using the same | |
| CN112720885A (en) | Crystal bar slotting method and crystal bar slotting device | |
| CN111029331A (en) | Wafer and cutting method thereof | |
| US20090166324A1 (en) | Full-wafer backside marking process | |
| CN108695248A (en) | processing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |