CN103367324A - Cutting channel for semiconductor chip - Google Patents
Cutting channel for semiconductor chip Download PDFInfo
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- CN103367324A CN103367324A CN2012100945755A CN201210094575A CN103367324A CN 103367324 A CN103367324 A CN 103367324A CN 2012100945755 A CN2012100945755 A CN 2012100945755A CN 201210094575 A CN201210094575 A CN 201210094575A CN 103367324 A CN103367324 A CN 103367324A
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- cutting road
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Abstract
The invention discloses a cutting channel for a semiconductor chip. Cutting channels with two kinds of width dimensions are set; the cutting channels with a large width dimension are used at the periphery of an exposure unit, and various marks used for aligning and monitoring are placed in the cutting channels; and the cutting channels with a small width dimension are used in other regions so as to differentiate different chips. The cutting channel disclosed by the invention not only can meet the requirement that all marks are placed in the cutting channels, but also can effectively reduce the proportion of area occupied by a blank cutting channel region in the exposure unit, thereby greatly improving the number of effective chips on a single wafer especially in chip products with a small area.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly relate to the Cutting Road that is used for semiconductor chip in a kind of semiconductor product manufacturing.
Background technology
The Cutting Road of semiconductor product when satisfying the cutting needs, also is used in the mark of putting various photoetching alignment mark and every monitoring usefulness, during for explained hereafter at present.In order to satisfy the demand of putting these marks, Cutting Road must satisfy certain width dimensions requirement.Along with constantly dwindling of device critical size, the required unit are of realization said function is also constantly dwindled, for the better simply device of some function ratio, chip (chip) quantity that can place in an exposing unit significantly increases, and then also causes the ratio of the shared exposing unit area of Cutting Road between the different chips to increase synchronously; Same Cutting Road is after having placed the required mark of technique, and the area of blank Cutting Road also significantly increases, and in fact these blank Cutting Roads have caused the loss to Effective number of chips amount on the wafer, and the space is wasted in a large number.Therefore there is new design to propose Cutting Road is dwindled, namely uses the Cutting Road of narrow dimension, and mark is moved on in the chip.But because the size of chip does not have stationarity because of the difference of product, be not the integral multiple of mark size, can cause unfixed waste to putting of mark equally.A large amount of similar marks of while are placed on the same area and also can the effect of technique and mark itself be exerted an influence, may produce the phase mutual interference erroneous judgement of registration signal such as alignment mark, in addition, also quantitative statistics has brought huge complexity to Effective number of chips in such design.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of Cutting Road for semiconductor chip, can satisfy Cutting Road and place markd demand, can effectively reduce the ratio that blank Cutting Road zone takies the exposing unit area again.
For solving the problems of the technologies described above, the Cutting Road for semiconductor chip of the present invention is to adopt following technical scheme to realize, the Cutting Road of wide, narrow two kinds of width dimensions is set; Use the Cutting Road of wide size in the periphery of exposing unit, and place therein various marks for aiming at and monitor purposes; The Cutting Road of narrow dimension is used in other zones, to distinguish different chips.
The present invention is by the Cutting Road of the two kinds of different width dimensions of arranging simultaneously, both can guarantee under the situation of not doing any change that original Cutting Road placed characteristic and the function of various marks, again can decrease blank Cutting Road zone take the ratio of exposing unit area, significantly promote on the single-wafer the effectively quantity of chip; Do not produce any negative effect, can not bring new complexity to the statistics of effective chip yet.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is Cutting Road embodiment one schematic diagram for semiconductor chip;
Fig. 2 is Cutting Road embodiment two schematic diagrames for semiconductor chip;
Fig. 3 is Cutting Road embodiment three schematic diagrames for semiconductor chip;
Fig. 4 is Cutting Road embodiment four schematic diagrames for semiconductor chip.
Embodiment
After chip area significantly dwindled, number of chips can significantly increase in the exposing unit, and Cutting Road is after placing every mark, and the area of blank Cutting Road will occur vacant in a large number, and the ratio that makes blank Cutting Road zone take the exposing unit area increases.In order to address this problem, the present invention proposes a kind of new design, use simultaneously the Cutting Road of two kinds of width dimensions.
Embodiment one
Referring to shown in Figure 1, use the Cutting Road of wide size in the periphery of exposing unit, be used for placing various for such as photoetching alignment mark and every process-monitor mark; Use the Cutting Road of narrow dimension in other zone of exposing unit, namely between each chip, use the Cutting Road of narrow dimension, be used for the interval and distinguish different chips.On the Cutting Road of narrow dimension, do not place any mark, can significantly reduce so the shared area of Cutting Road of original wide size.After all processing steps of product are all finished, use the method for etching that all Cutting Roads are directly worn quarter, thereby realize the cutting and separating of product.
Stand out between the Cutting Road of wide size and the Cutting Road of narrow dimension more is conducive to the utilization to effective area apart from larger.Wherein, the Cutting Road width of narrow dimension should be as far as possible little, to save to greatest extent its shared area, preferably is controlled at less than or equal to 20 μ m.
Need to be placed on the periphery owing to be used for the mark of measurement alignment precision, therefore, present embodiment moves on to specific zone to all marks, i.e. the outmost turns position of exposing unit as far as possible.Be used for placing the width of Cutting Road of the wide size of various marks, can reach required separately actual effect and be as the criterion to satisfy every mark.Various alignings and monitoring mark are arranged in according to the actual production demand in the Cutting Road of wide size, need be placed on respectively four corners such as overlay mark etc.
Embodiment two
Referring to shown in Figure 2, the difference of present embodiment and embodiment one is, vertically also is provided with a Cutting Road that runs through the wide size of exposing unit along the center of described exposing unit.All the other and embodiment one are identical.
Embodiment three
Referring to shown in Figure 3, the difference of present embodiment and embodiment one is, also is provided with a Cutting Road that runs through the wide size of exposing unit along the central cross of described exposing unit.All the other and embodiment one are identical.
Embodiment four
Referring to shown in Figure 4, the difference of present embodiment and embodiment one is, along the center of described exposing unit, horizontal and vertical also the intersection respectively is provided with a Cutting Road that runs through the wide size of exposing unit.All the other and embodiment one are identical.
Embodiment five
Referring to shown in Figure 2, the difference of present embodiment and embodiment three is that the Cutting Road of the wide size that this laterally runs through can be in the excentral optional position of described exposing unit.
Embodiment six
Referring to shown in Figure 3, the difference of present embodiment and embodiment two is that the Cutting Road of the wide size that this vertically runs through can be in the excentral optional position of described exposing unit.
Embodiment seven
Referring to shown in Figure 4, the difference of present embodiment and embodiment four is that the Cutting Road of this horizontal and vertical wide size that runs through can be in the excentral optional position of described exposing unit.
Embodiment two to embodiment four considers the difference that needs generally speaking to detect exposing unit center and four corners, and therefore the Cutting Road of width dimensions is set near the exposing unit center, is used for placing certification mark.
In addition, the Cutting Road that is arranged on the width dimensions at exposing unit periphery and center in above-described embodiment two to embodiment four should be tried one's best into the symmetry distribution.
The present invention is for having a large amount of chips in the exposing unit, thereby causes the product of large stretch of Cutting Road blank to have obvious reduction Cutting Road occupation proportion, promotes the advantage of the Effective number of chips amount of chip product on the single-wafer.Simultaneously, use the present invention fully without any need for redesign and the change of mark, also do not affect the quantitative statistics of edge Effective number of chips.
Although the present invention utilizes specific embodiment to describe, the explanation of embodiment is not limit the scope of the invention.The one skilled in the art is by with reference to explanation of the present invention, in the situation that does not deviate from the spirit and scope of the present invention, carries out easily various modifications or can make up embodiment, and these belong to protection scope of the present invention equally.
Claims (9)
1. a Cutting Road that is used for semiconductor chip is characterized in that: the Cutting Road that wide, narrow two kinds of width dimensions are set; Use the Cutting Road of wide size in the periphery of exposing unit, and place therein various marks for aiming at and monitor purposes; The Cutting Road of narrow dimension is used in other zones, to distinguish different chips.
2. Cutting Road according to claim 1 is characterized in that: when the product cutting and separating, adopt the method for etching directly to wear all Cutting Roads quarter.
3. Cutting Road according to claim 1, it is characterized in that: the width dimensions of the Cutting Road of described narrow dimension is less than or equal to 20 μ m.
4. Cutting Road according to claim 1 is characterized in that: also be provided with a Cutting Road that runs through the wide size of exposing unit along the central cross of described exposing unit.
5. Cutting Road according to claim 1 is characterized in that: vertically also be provided with a Cutting Road that runs through the wide size of exposing unit along the center of described exposing unit.
6. Cutting Road according to claim 1 is characterized in that: along the center of described exposing unit, horizontal and vertical also the intersection respectively is provided with a Cutting Road that runs through the wide size of exposing unit.
7. Cutting Road according to claim 1 is characterized in that: laterally also be provided with a Cutting Road that runs through the wide size of exposing unit in the excentral optional position of described exposing unit.
8. Cutting Road according to claim 1 is characterized in that: vertically also be provided with a Cutting Road that runs through the wide size of exposing unit in the excentral optional position of described exposing unit.
9. Cutting Road according to claim 1 is characterized in that: horizontal and vertical also the intersection respectively is provided with a Cutting Road that runs through the wide size of exposing unit in the excentral optional position of described exposing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100945755A CN103367324A (en) | 2012-04-01 | 2012-04-01 | Cutting channel for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100945755A CN103367324A (en) | 2012-04-01 | 2012-04-01 | Cutting channel for semiconductor chip |
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| CN103367324A true CN103367324A (en) | 2013-10-23 |
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| CN2012100945755A Pending CN103367324A (en) | 2012-04-01 | 2012-04-01 | Cutting channel for semiconductor chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701252A (en) * | 2013-12-05 | 2015-06-10 | 上海华虹宏力半导体制造有限公司 | Automatic chip layout distributing method |
| CN107065450A (en) * | 2017-05-10 | 2017-08-18 | 株洲中车时代电气股份有限公司 | A kind of power semiconductor chip, the reticle and its exposure method of the chip |
| CN110690176A (en) * | 2019-10-14 | 2020-01-14 | 长江存储科技有限责任公司 | Method for distinguishing target crystal grains and failure analysis method of packaged chip |
| CN112180691A (en) * | 2020-09-30 | 2021-01-05 | 上海华力集成电路制造有限公司 | On-line monitoring method for spliced chips |
| CN117727694A (en) * | 2024-02-07 | 2024-03-19 | 立芯精密智造(昆山)有限公司 | Wafer cutting method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701252A (en) * | 2013-12-05 | 2015-06-10 | 上海华虹宏力半导体制造有限公司 | Automatic chip layout distributing method |
| CN104701252B (en) * | 2013-12-05 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | A kind of method of automatic placement chip layout |
| CN107065450A (en) * | 2017-05-10 | 2017-08-18 | 株洲中车时代电气股份有限公司 | A kind of power semiconductor chip, the reticle and its exposure method of the chip |
| CN107065450B (en) * | 2017-05-10 | 2018-10-02 | 株洲中车时代电气股份有限公司 | A kind of power semiconductor chip, the reticle and its exposure method of the chip |
| CN110690176A (en) * | 2019-10-14 | 2020-01-14 | 长江存储科技有限责任公司 | Method for distinguishing target crystal grains and failure analysis method of packaged chip |
| CN110690176B (en) * | 2019-10-14 | 2022-01-11 | 长江存储科技有限责任公司 | Method for distinguishing target crystal grains and failure analysis method of packaged chip |
| CN112180691A (en) * | 2020-09-30 | 2021-01-05 | 上海华力集成电路制造有限公司 | On-line monitoring method for spliced chips |
| CN112180691B (en) * | 2020-09-30 | 2024-01-09 | 上海华力集成电路制造有限公司 | On-line monitoring method for spliced chip |
| CN117727694A (en) * | 2024-02-07 | 2024-03-19 | 立芯精密智造(昆山)有限公司 | Wafer cutting method |
| CN117727694B (en) * | 2024-02-07 | 2024-04-26 | 立芯精密智造(昆山)有限公司 | Wafer cutting method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140113 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20140113 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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| RJ01 | Rejection of invention patent application after publication | ||
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Application publication date: 20131023 |