CN104009020A - Wafer and acceptance test method thereof - Google Patents
Wafer and acceptance test method thereof Download PDFInfo
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- CN104009020A CN104009020A CN201310062594.4A CN201310062594A CN104009020A CN 104009020 A CN104009020 A CN 104009020A CN 201310062594 A CN201310062594 A CN 201310062594A CN 104009020 A CN104009020 A CN 104009020A
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Abstract
The invention discloses a wafer comprising dies which are formed on the wafer and are arranged in a matrix. The dies are divided into a plurality of test blocks. Each test block includes at least four dies arranged in a matrix. Spacing regions between dies of each test block are formed in subscribe lines disposed in the test block. The subscribe lines of each test block are provided with at least two alignment patterns, and the transverse subscribe line and the longitudinal subscribe line are respectively provided with at least one alignment pattern. A wafer acceptance test method is further disclosed. The test regions are positioned by the alignment patterns arranged in the transverse and longitudinal subscribe lines. By adopting the wafer and the test method, wafer damage caused by alignment pattern misidentification can be effectively avoided.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relating to a kind of wafer can acceptance test method and a kind of wafer.
Background technology
WAT(wafer acceptance test, wafer can acceptance test) be the important step in chip manufacturing proces, whether meet the design object of expection for detection of the chip on wafer, be also whether the electrical parameter of chip meets customer demand.
WAT's is that carry out subregion (block), tests a region at every turn.The multiple wafers of district inclusion (die), multiple wafers are all spaced apart each other, and wherein between wafer, the region at interval is referred to as scribe line or Cutting Road (subscribe line).For the position in accurate assignment test region, some alignment patterns all to be set conventionally on wafer, to assist aligning.Alignment patterns is just arranged in above-mentioned scribe line, and circuitous pattern on its figure and wafer is completely different, is beneficial to differentiate.
But, in traditional WAT method, because the aligning accuracy of probe program is inadequate, when the alignment patterns in scribe line relatively approaches, if there is the situation of misidentification alignment patterns, will cause locating bias.Probe just can not accurately drop on test point like this, and scratches other parts of wafer, causes wafer loss.
Summary of the invention
Based on this, be necessary to provide one can pinpoint wafer can acceptance test method.
In addition, also provide the accurately wafer in assignment test region of a kind of WAT of making method.
A kind of wafer, comprise formed thereon and be matrix arrange wafer, described wafer is divided into multiple test zones, each test zone comprises at least four and is the wafer that matrix is arranged, interval region between the wafer of described each test zone forms the scribe line that is positioned at described test zone, in scribe line in described each test zone, be provided with at least two alignment patterns, and in horizontal scribe line and longitudinal scribe line, an alignment patterns be at least set respectively.
Therein in an embodiment, described alignment patterns is arranged in phase mutual edge distance horizontal and longitudinal scribe line farthest.
A kind of wafer can acceptance test method, comprises the steps: at least two alignment patterns are set in the scribe line of each test zone, and in horizontal scribe line and in longitudinal scribe line, an alignment patterns is at least set respectively; Adopt the contraposition of low power benchmark to adjust the angle of wafer on testboard; Adopt the contraposition of high power benchmark to position test zone, specifically comprise: described in location, be arranged on respectively the alignment patterns in horizontal scribe line and be arranged on the alignment patterns in longitudinal scribe line; Definition test module; Check Wafer alignment information and test.
In an embodiment, before the step of the angle that adopts low power benchmark contraposition adjustment wafer on testboard, also the edge of wafer is carried out to contraposition therein.
In an embodiment, the step that the angle of wafer on testboard adjusted in described employing low power benchmark contraposition comprises the upper, middle and lower that utilize under low power contraposition module, the angle of left and right 5 contraposition modules adjustment wafer therein.
In an embodiment, the step that adopts the contraposition of high power benchmark to position test zone comprises that the upper, middle and lower that utilize under high power contraposition module, left and right 5 contraposition modules position test zone therein.
Above-mentioned wafer and method of testing, carry out on time utilizing alignment patterns, owing to being separately positioned in horizontal and vertical scribe line, the relative coordinate of the two is fixed, in the time that one of them alignment patterns is easily mistaken for, the position of another alignment patterns certainly leads to skew (being generally the position that is displaced to wafer), and alignment patterns is not the same with the circuitous pattern on wafer or is similar.When be easily mistaken for producing skew due to one of them, another alignment patterns cannot be identified in wrong position, thereby can not position test zone, follow-up testing procedure just cannot carry out, and therefore can effectively avoid the wafer causing because of misidentification alignment patterns to damage.
Brief description of the drawings
Fig. 1 is the wafer schematic diagram of an embodiment;
Fig. 2 is the partial enlarged drawing of A part in Fig. 1;
Fig. 3 is the flow chart that the wafer of an embodiment can acceptance test method.
Embodiment
As shown in Figure 1, be the wafer schematic diagram of an embodiment.This wafer 10 comprise formed thereon and be matrix arrange wafer 100, described wafer 100 is divided into multiple test zones 200.The division of test zone 200 can need or divide with functional area according to test.Each test zone 200 comprises at least 4 and is the wafer 100 that matrix is arranged.
As shown in Figure 2, be the partial enlarged drawing of A part in Fig. 1.In wafer 10, wafer 100 is not compact arranged, but has each other the interval of 60 ~ 100 microns, i.e. scribe line or Cutting Road (subscribe line).The wafer 10 of the present embodiment is provided with two alignment patterns 202,204 in the scribe line in each test zone 200, and is separately positioned in horizontal scribe line and in longitudinal scribe line.The position of the alignment patterns in other test zones 200 can arrange with reference to A part.
Above-mentioned wafer 10, carry out on time utilizing alignment patterns 202,204, owing to being separately positioned in horizontal and vertical scribe line, the relative coordinate of the two is fixed, in the time that one of them alignment patterns is easily mistaken for, the position of another alignment patterns certainly leads to skew (being generally the position that is displaced to wafer), and alignment patterns is not the same with the circuitous pattern on wafer or is similar.When be easily mistaken for producing skew due to one of them, another alignment patterns cannot be identified in wrong position, thereby can not position test zone 200, follow-up testing procedure just cannot carry out, and therefore can effectively avoid the wafer causing because of misidentification alignment patterns to damage.
In a preferred embodiment, alignment patterns 202,204 is arranged in phase mutual edge distance horizontal and longitudinal scribe line farthest.Like this, in the time that one of them alignment patterns is easily mistaken for, the position of another alignment patterns can produce maximum skew, is conducive to avoid mistake.
As shown in Figure 3, be the flow chart that the wafer of an embodiment can acceptance test method.The method comprises the steps.
S101: two alignment patterns are set in the scribe line of each test zone, and described two alignment patterns are separately positioned in horizontal scribe line and in longitudinal scribe line.Specifically can alignment patterns be set with reference to the mode in figure 2.
S102: the edge of wafer is carried out to contraposition.Wafer 10 as shown in Figure 1, has two edges that scabble, and utilizes this edge to carry out thick contraposition, and wafer is placed on to the tram on testboard.
S103: adopt the contraposition of low power benchmark to adjust the angle of wafer on testboard.This step comprises the upper, middle and lower that utilize under low power contraposition module, the angle of left and right 5 contraposition modules adjustment wafer.
S104: adopt the contraposition of high power benchmark to position test zone.This step specifically comprises: described in location, be arranged on respectively the alignment patterns in horizontal scribe line and be arranged on the alignment patterns in longitudinal scribe line.Same, the contraposition of high power benchmark utilizes the upper, middle and lower under high power contraposition module, left and right 5 contraposition modules to position test zone.
After having located, can carry out test job, carry out following steps.
S105: definition test module.
S106: check Wafer alignment information and test.
Above-mentioned method of testing, aim at owing to utilizing respectively the alignment patterns 202,204 being arranged in horizontal and vertical scribe line, and the relative coordinate of the two is fixed, in the time that one of them alignment patterns is easily mistaken for, the position of another alignment patterns certainly leads to skew (being generally the position that is displaced to wafer), and alignment patterns is not the same with the circuitous pattern on wafer or is similar.When be easily mistaken for producing skew due to one of them, another alignment patterns cannot be identified in wrong position, thereby can not position test zone 200, follow-up testing procedure just cannot carry out, and therefore can effectively avoid the wafer causing because of misidentification alignment patterns to damage.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (6)
1. a wafer, comprise formed thereon and be matrix arrange wafer, described wafer is divided into multiple test zones, each test zone comprises at least four and is the wafer that matrix is arranged, interval region between the wafer of described each test zone forms the scribe line that is positioned at described test zone, it is characterized in that, in the scribe line in described each test zone, be provided with at least two alignment patterns, and in horizontal scribe line and longitudinal scribe line, an alignment patterns is at least set respectively.
2. wafer according to claim 1, is characterized in that, described alignment patterns is arranged in phase mutual edge distance horizontal and longitudinal scribe line farthest.
3. wafer can an acceptance test method, comprises the steps:
At least two alignment patterns are set in the scribe line of each test zone, and in horizontal scribe line and longitudinal scribe line, an alignment patterns are at least set respectively;
Adopt the contraposition of low power benchmark to adjust the angle of wafer on testboard;
Adopt the contraposition of high power benchmark to position test zone, specifically comprise: described in location, be arranged on respectively the alignment patterns in horizontal scribe line and be arranged on the alignment patterns in longitudinal scribe line;
Definition test module;
Check Wafer alignment information and test.
4. wafer according to claim 3 can acceptance test method, it is characterized in that, adopting before the contraposition of low power benchmark adjusts the step of the angle of wafer on testboard, also the edge of wafer is carried out to contraposition.
5. wafer according to claim 3 can acceptance test method, it is characterized in that, the step that the angle of wafer on testboard adjusted in described employing low power benchmark contraposition comprises the upper, middle and lower that utilize under low power contraposition module, the angle of left and right five contraposition modules adjustment wafer.
6. wafer according to claim 3 can acceptance test method, it is characterized in that, the step that adopts the contraposition of high power benchmark to position test zone comprises that the upper, middle and lower that utilize under high power contraposition module, left and right five contraposition modules position test zone.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310062594.4A CN104009020B (en) | 2013-02-27 | 2013-02-27 | Wafer and its acceptance test method |
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| CN201310062594.4A CN104009020B (en) | 2013-02-27 | 2013-02-27 | Wafer and its acceptance test method |
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| CN104009020A true CN104009020A (en) | 2014-08-27 |
| CN104009020B CN104009020B (en) | 2017-08-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297659A (en) * | 2014-10-28 | 2015-01-21 | 北京思比科微电子技术股份有限公司 | Pattern CP device for CMOS image sensor products |
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| US6905897B1 (en) * | 2003-12-10 | 2005-06-14 | Nanya Technology Corp. | Wafer acceptance testing method and structure of a test key used in the method |
| KR20050064287A (en) * | 2003-12-23 | 2005-06-29 | 삼성전자주식회사 | Wafer with overlay measurement key in the middle area of photolithography field |
| US20080142997A1 (en) * | 2006-12-17 | 2008-06-19 | Chien-Li Kuo | Metal structure |
| CN102722082A (en) * | 2012-07-04 | 2012-10-10 | 上海宏力半导体制造有限公司 | Mask and overlay measuring method |
| CN102931186A (en) * | 2011-12-15 | 2013-02-13 | 无锡中星微电子有限公司 | Wafer with narrower scribing slots |
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2013
- 2013-02-27 CN CN201310062594.4A patent/CN104009020B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6905897B1 (en) * | 2003-12-10 | 2005-06-14 | Nanya Technology Corp. | Wafer acceptance testing method and structure of a test key used in the method |
| KR20050064287A (en) * | 2003-12-23 | 2005-06-29 | 삼성전자주식회사 | Wafer with overlay measurement key in the middle area of photolithography field |
| US20080142997A1 (en) * | 2006-12-17 | 2008-06-19 | Chien-Li Kuo | Metal structure |
| CN102931186A (en) * | 2011-12-15 | 2013-02-13 | 无锡中星微电子有限公司 | Wafer with narrower scribing slots |
| CN102722082A (en) * | 2012-07-04 | 2012-10-10 | 上海宏力半导体制造有限公司 | Mask and overlay measuring method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297659A (en) * | 2014-10-28 | 2015-01-21 | 北京思比科微电子技术股份有限公司 | Pattern CP device for CMOS image sensor products |
| CN104297659B (en) * | 2014-10-28 | 2017-08-08 | 北京思比科微电子技术股份有限公司 | The band pattern CP test devices of CMOS image sensor product |
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| CN104009020B (en) | 2017-08-08 |
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