CN107065450A - A kind of power semiconductor chip, the reticle and its exposure method of the chip - Google Patents
A kind of power semiconductor chip, the reticle and its exposure method of the chip Download PDFInfo
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- CN107065450A CN107065450A CN201710325616.XA CN201710325616A CN107065450A CN 107065450 A CN107065450 A CN 107065450A CN 201710325616 A CN201710325616 A CN 201710325616A CN 107065450 A CN107065450 A CN 107065450A
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- chip
- reticle
- power semiconductor
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- territory element
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The invention discloses a kind of power semiconductor chip, the reticle and its exposure method of the chip, method includes：More than two territory elements into are divided large size chip according to exposure field size, any of corner, edge or central area unit are divided into according to chip type, same type territory element figure is consistent；Territory element is combined into reticle, reticle includes all territory element types divided by chip, and reticle size is less than or equal to chip size；Using respective regions unit in shadow shield selection reticle to silicon wafer exposure；Silicon chip biasing and rotary setting by litho machine, by the territory element pattern transfer of exposure to silicon chip relevant position, expose window, and silicon chip biasing and rotation process by shadow shield by remaining area unit, expose one by one.The present invention can solve the problem that existing chip manufacturing using polylith version splicing, and reticle quantity is more, cost big, error is easily caused during splicing, it is impossible to suitable for the technical problem prepared with labyrinth chip.
Description
Technical field
The present invention relates to manufacture technique of power electronic device field, partly led more particularly, to a kind of spliced large scale power
Body chip, the reticle and its exposure method of the chip.
Background technology
With the development and the continuous extension of application field of technology, power semiconductor is in modern power electronics technology
In in occupation of increasingly consequence.At present, the positive high frequency of power semiconductor, high-power, intellectuality and module
Change direction to develop.Wherein, how the key technology applied as power semiconductor, realize the big work(of power semiconductor modular
Rate capacity turns into the emphasis direction of research and development in the current technical field.In order to realize the high power capacity of power semiconductor modular,
Prior art is generally used to be packaged into a power model to increase it by several several or even small more than ten chip progress parallel connections
Power density.In the Power Electronic Circuit that modern power switching device is dominated, the device such as IGBT, power VDMOSFET, FRD
It is often in parallel using multiple devices, to realize between required power grade, but many devices device used in parallel by strict demand
Performance Match, otherwise will cause to open the problems such as speed is uneven, ultimately result in Module Fail.This requires boost device
Power grade, and the power grade of chip can directly be improved by the lifting of device size, and directly reduce needed for application
Number of chips, and then improve module reliability, reduce packaging cost.
But the problems such as light intensity uniformity, exposure accuracy of many exposure machine equipments in order to keep exposure area, exposure field
It is often smaller, so as to limit the direct lifting of device size.The exposure field size of main flow stepper is at present
22mm*22mm, on the premise of limited exposure field, makes large scale power semiconductor generally direct using multiple reticles
The mode of splicing, i.e.,：Large-sized chip 200 is decomposed into by n territory element 300 according to exposure field size, carried out spliced
Exposure.As shown in Figure 1, it is the outline drawing of a large scale power semiconductor, 300 be the territory element of one of them, 2
For dicing lane area, 3 be the line of demarcation of chip 200, and the domain of whole power semiconductor is divided into n part, every part respectively less than or
, will be per a independent plate-making equal to the maximum exposure of exposure sources.One piece of territory element for carrying dicing lane area 2 is taken in addition
300, remove the graphics chip of centre, only design alignment mark in dicing lane area 2, one piece of mark domain is fabricated separately.Specific system
Make method as follows：
(1) using each plate as independent shot (projection exposure), whole device is n shot splicing；
(2) mark domain is used, alignment mark is formed on wafer by way of photoetching, etching；
(3) using the telltale mark made in step 2, the alignment of reticle and wafer is realized, is positioned by alignment mark,
The reticle of remaining area unit is exposed to the shot positions specified successively；
(4) chip is developed after completing all territory element exposures, large scale power device will be now formed on chip
Complete domain needed for part.
This mode needs to use the reticle of polylith in single-layer lithography, if being divided into n territory element, first layer
Photoetching then needs n+1 reticles, and remainder layer also at least needs n reticles.In addition, simple direct zoning, also can
The figure of each region stitching portion is caused because alignment error, map migration is caused, the phenomenon, the property of final influence device such as discontinuous
Energy.
In the prior art, mainly there are following two documents related to the present patent application：
Document 1 is that CEC ＆ Huatsing Microelectronics Engineering Center Co., Ltd. applied on 01 17th, 2008, and in 2010
11 days 08 month open, Publication No. CN101252101A Chinese invention patent application《Make super using exposure field splicing
The method of high power intelligent device》.The technical scheme of the patent of invention in parallel by N number of identical power device unit,
And the ultra-high power intelligent device that the circuit containing control is constituted, when technique is manufactured, this N number of identical power device unit
Or control circuit, scribe line is not set therebetween, is exposed using step printing mode, exposure field is mutually spliced.It is big at one
Multiple ultra-high power intelligent devices will be produced on the substrate silicon wafer of area simultaneously, will be set between adjacent ultra-high power intelligent device
Scribe line is put, is encapsulated in favor of the scribing in future.Described in the patent of invention is to complete one by N number of complete by connecting method
The ultra-high power intelligent device of exactly the same power device unit spliced, this scheme is only merely by identical list
Member is spliced, therefore is only applicable to the device that can be spliced with identical unit, and stitching portion figure because
For alignment error, map migration is caused, the phenomenon such as discontinuous, finally influence device performance.
Document 2 is that No.44 Inst., China Electronical Science and Technology Group Co. applied on 08 27th, 2013, and in
On November 27th, 2013 is open, Publication No. CN103412468A Chinese invention patent application《Photoetching large scale CCD chip
Splice exposure method》.The technical scheme of the patent of invention is exposed to each CCD splicing chips respectively using connecting method,
On the splicing edge of lastblock lithography mask version figure, it is 0.1 micron to be provided with the width overlapping with next piece of lithography mask version
Overlay region, and the termination of the geometric figure in overlay region is provided with the square compensation that size is 0.1 micron × 0.1 micron
Breach.The method that the inventive technique scheme is provided is improved primarily directed to the graphical quality of splicing regions, while also mentioning
The method that splicing exposure forms large scale figure, but this method is that chip is directly divided into the figure for meeting exposure field size
Shape, then multiexposure, multiple exposure splicing is carried out, it is necessary to which substantial amounts of photolithography plate, complex process degree is very high.
The content of the invention
In view of this, it is an object of the invention to provide a kind of power semiconductor chip, the reticle of the chip and its exposure
Light method, is formed using polylith version direct splicing with solving existing chip manufacturing, causes reticle increasing number, cost increase,
And the critical size of stitching portion figure is not considered during direct splicing, easily cause stitching error, it is impossible to suitable for complexity knot
Technical problem prepared by the chip of structure.
In order to realize foregoing invention purpose, the present invention specifically provides a kind of technology of power semiconductor chip exposure method
A kind of implementation, power semiconductor chip exposure method, comprises the following steps：
S101 large-sized graphics chip) is divided into by two or more by line of demarcation according to the exposure field size of litho machine
Territory element, the territory element is divided into by corner areas unit, fringe region unit or center according to the type of figure
Any of territory element type, and ensure that the inside figure of same type territory element is completely the same；
S102 the territory element) is combined into reticle, the reticle includes all areas divided by the chip
Domain cell type, the size of the reticle is less than or equal to the size of the chip, wherein the corner areas unit or side
Edge territory element includes alignment mark；
S103) choose the respective regions unit in the reticle using shadow shield to be exposed silicon chip, first exposure
Unit on the basis of the territory element of light, and with alignment mark；
S104) by the silicon chip biasing on litho machine and rotary setting, by the territory element pattern transfer of exposure to silicon chip
Relevant position, reference cell is formed by development, and by the alignment mark of reference cell, by remaining territory element
By the exposure window of the shadow shield, and silicon chip biasing and rotation process, it is exposed one by one；
S105 developed after the exposure for) completing all territory elements of chip, obtain the first layer light of the chip
Needle drawing shape, and perform etching, complete the first layer process of the chip；
S106) using the alignment mark of first layer process formation, the exposure, development and etching of the chip succeeding layer are completed
Technique.
It is preferred that, the territory element figure positioned at the line of demarcation both sides is consistent in setting range, the setting model
Enclose the position error more than the shadow shield.
It is preferred that, the figure of the territory element junction is vertical with the line of demarcation.
It is preferred that, the corner areas unit is the territory element of the corner in tape terminal area or figure sideline, the edge
Territory element is the territory element at the edge in tape terminal area or figure sideline, and the central area unit is without termination environment and figure
The territory element at the center in shape sideline.
It is preferred that, the reticle is square structure, and the reticle has continuous figure sideline.
It is preferred that, the exposure window of the shadow shield is unilateral to external expansion 1 on the basis of the line of demarcation of respective regions unit
~10 μm.
It is preferred that, by upper offset (a1-a2)/2 in the horizontal direction of the center to the reticle, in the vertical direction is inclined
(b1-b2)/2 are put, required figure will be formed on the corner areas cell projection to the silicon chip.Wherein, a1 is chip
Length, b1 is the width of chip, and a2 is the length of reticle, and b2 is the width of reticle.
It is preferred that, large-sized graphics chip is divided into by m rows × n by line of demarcation and arranges square territory element, m >=4,
n≥4.The corner areas unit, fringe region unit and central area unit are combined into and meet exposure field size, and relatively
In the less reticle of the size of the chip.
It is preferred that, the graphics chip is divided into 4 rows × 4 and arranged, totally 16 square territory elements.
It is preferred that, the reticle is arranged by 3 rows × 3, totally 9 square territory elements compositions.
The present invention also specifically provides a kind of technic relization scheme of above-mentioned power semiconductor chip reticle in addition, a kind of
Power semiconductor chip reticle, the reticle is combined by the square territory element of two or more, and including：Effective district
Figure, and the dicing lane figure positioned at the effective district figure neighboring, the territory element is by large-sized graphics chip
Divided and formed by line of demarcation.The territory element is corner areas unit, fringe region unit according to the Type division of figure
Or any of central area unit type, the inside figure of same type territory element is completely the same.The reticle bag
All territory element types divided by the chip are included, the size of the reticle is less than or equal to the size of the chip.
Territory element figure positioned at the line of demarcation both sides is consistent in setting range, and the setting range is more than the screening of litho machine
The position error of tabula rasa.
It is preferred that, the figure of the territory element junction is vertical with the line of demarcation.
It is preferred that, the corner areas unit is the territory element of the corner in tape terminal area or figure sideline, the edge
Territory element is the territory element at the edge in tape terminal area or figure sideline, and the central area unit is without termination environment and figure
The territory element at the center in shape sideline.
It is preferred that, the reticle is square structure, and the reticle has continuous figure sideline.
It is preferred that, the graphics chip is divided into m rows × n and arranges square territory element, m >=4, n >=4.By the corner
Territory element, fringe region unit and central area unit, which are combined into, meets exposure field size, and relative to the chi of the chip
Very little less reticle.
It is preferred that, the graphics chip is divided into 4 rows × 4 and arranged, totally 16 square territory elements.
It is preferred that, the reticle is arranged by 3 rows × 3, totally 9 square territory elements compositions.
It is preferred that, the corner areas unit or fringe region unit with dicing lane figure include alignment mark.
The present invention also specifically provides a kind of technic relization scheme of above-mentioned power semiconductor chip, a kind of power half in addition
Conductor chip, is made using method as described above, and the chip is large-sized FRD chips.
The present invention also specifically provides the technic relization scheme of another above-mentioned power semiconductor chip, and a kind of power is partly led
Body chip, is made using method as described above, and the chip is large-sized igbt chip or MOSFET chips.
It is preferred that, igbt chip or the MOSFET chip is using any of center grid, edge grid or corner grid knot
Structure.
By implementing the power semiconductor chip that the invention described above is provided, the reticle of the chip and its skill of exposure method
Art scheme, has the advantages that：
(1) it is of the invention by the way that large scale power semiconductor chip figure is divided into different types of territory element, and will
Different zones unit is combined into the domain for meeting the requirement of exposure machine exposure field size, and big chi is realized by the way of splicing exposure
Very little component graphics, realize the purpose that large scale power semiconductor chip is made using small size lithography layout shape, and traditional
Implementation is compared, and is reduced the quantity of reticle, is reduced manufacturing cost；
(2) present invention forms the reference cell with alignment mark first on chip, and remaining area unit then passes through base
Quasi- unit alignment mark carries out positioning exposure, completes the splicing of all territory elements, and then forms complete domain, ultimately forms work(
Rate semiconductor devices, preparation method is simple, improve using polylith reticle carry out splicing tape come error, improve alignment with
The precision of splicing；
(3) the invention provides one kind in the case of limited exposure field, spliced large scale power semiconductor device is manufactured
The method of part, so as to improve the power grade of individual devices, reduces the number of chips needed for encapsulation, it is possible to achieve complexity figure
Prepared by the chip of shape, replace the chip of multiple small sizes is used in parallel can obtain bigger work(by using large-sized chip
Rate density.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described.It should be evident that drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other embodiments are obtained according to these accompanying drawings.
Fig. 1 is to realize the signal that large scale power semiconductor chip makes using exposure field splicing in the prior art
Figure；
Fig. 2 is the structural representation of power semiconductor chip region division example 1 of the present invention；
Fig. 3 is the structural representation of power semiconductor chip region division example 2 of the present invention；
Fig. 4 is the structural representation of power semiconductor chip region division example 3 of the present invention；
Fig. 5 is the structural representation of power semiconductor chip region division example 4 of the present invention；
Fig. 6 is a kind of contour structures schematic diagram of specific embodiment of power semiconductor chip of the present invention；
Fig. 7 is that the structure in a kind of specific embodiment of power semiconductor chip reticle of the present invention divides schematic diagram；
Fig. 8 is the signal of the first exposure area in a kind of specific embodiment of power semiconductor chip exposure method of the present invention
Figure；
Fig. 9 is the signal of the second exposure area in a kind of specific embodiment of power semiconductor chip exposure method of the present invention
Figure；
Figure 10 is the signal of the 3rd exposure area in a kind of specific embodiment of power semiconductor chip exposure method of the present invention
Figure；
Figure 11 is the schematic diagram of exposure process in a kind of specific embodiment of power semiconductor chip exposure method of the present invention；
Figure 12 is the large scale FRD device architecture top views that power semiconductor chip exposure method of the present invention is applied；
Figure 13 is the partial enlargement structural representation of I parts in Figure 12；
Figure 14 is a kind of longitudinal profile for large scale FRD devices that power semiconductor chip exposure method of the present invention is applied
Structure chart；
Figure 15 is that the longitudinal direction for another large scale FRD devices that power semiconductor chip exposure method of the present invention is applied is cutd open
Face structure chart；
Figure 16 is that the longitudinal direction for the third large scale FRD devices that power semiconductor chip exposure method of the present invention is applied is cutd open
Face structure chart；
Figure 17 is that the longitudinal direction for the 4th kind of large scale FRD device that power semiconductor chip exposure method of the present invention is applied is cutd open
Face structure chart；
Figure 18 is the large scale IGBT device structure top view that power semiconductor chip exposure method of the present invention is applied；
Figure 19 is the large scale IGBT device and cellular plot structure that power semiconductor chip exposure method of the present invention is applied
Top view；
Figure 20 is the A-A ' of a certain territory element in Figure 19 to part section structural representation；
In figure：In 1- effective districts, 2- dicing lane area, 3- lines of demarcation, 4- corner areas units, 5- fringe region units, 6-
Heart territory element, 7- shadow shields, 8- corners exposure area, 9- termination environments outer edge, 10- termination environments inner edge, 11- exposal windows
Mouthful, 12- edge exposures region, 13- center exposures region, 14- termination environments, 15- figures sideline, 20- anode aluminium laminations, 21- anodes
Aluminium lamination edge, 31-P+ anode regions, 32-N- areas, 33-N+ cathodic regions, 34- anode p-types island, 35- anode P- areas, 36- negative electrode P types
Island, 40- cellulars, 41- grid interconnection lines, 42- corners grid, 43- emitter stages, 50-N- substrates, 51-P- bases, 52-N+ source electrodes
Area, 53-P+ buses area, 100- reticles, 101- effective district figures, 102- dicing lane figures, 200- chips, 300- regions are single
Member.
Embodiment
For the sake of quoting and understanding, by the technical term hereinafter used, write a Chinese character in simplified form or abridge and be described below：
MOSFET：Metal-Oxide-Semiconductor Field-Effect Transistar, metal-oxide
The abbreviation of semiconductor field effect transistor；
FRD：Fast Recovery Diode, the abbreviation of fast recovery diode；
IGBT：Insulated Gate Bipolar Transistor, the abbreviation of insulated gate bipolar transistor；
VDMOS：Vertical Dauble-Diffused MOSFET, vertical double diffused metal-oxide semiconductor field effect
Answer the abbreviation of transistor.
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, clear, complete description is carried out to the technical scheme in the embodiment of the present invention.Obviously, described embodiment is only
Only it is a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the common skill in this area
All other embodiment that art personnel are obtained under the premise of creative work is not made, belongs to the model that the present invention is protected
Enclose.
As shown in accompanying drawing 1 to accompanying drawing 20, power semiconductor chip of the present invention, the reticle of the chip and its exposure are given
The specific embodiment of method, the invention will be further described with specific embodiment below in conjunction with the accompanying drawings.
Embodiment 1
The embodiment carries out the introduction of technical scheme by taking the exposure of large scale FRD devices as an example, and with three types
Illustrated exemplified by the FRD devices in region.The large size chip mentioned in the present embodiment and following embodiments refers to photoetching figure
Shape size is more than the chip 200 of the photo-etching machine exposal size (generally 22mm*22mm) of current main flow.A kind of power semiconductor
The specific embodiment of chip exposure method, comprises the following steps：
S101) as shown in Figure 6, according to the exposure field size of litho machine by line of demarcation 3 by large-sized figure of chip 200
Shape is divided into several territory elements 300, according to the type of chip 200 that 300 points of territory element is (such as attached for corner areas unit
In Fig. 6 shown in A) 4,6 three kinds of fringe region unit (as shown in B in accompanying drawing 6) 5 and central area unit (as shown in C in accompanying drawing 6)
Type, and ensure that the inside figure of same type territory element 300 is completely the same；Corner areas unit 4 is tape terminal area or figure
The territory element 300 of the corner in shape sideline, fringe region unit 5 is the territory element at the edge in tape terminal area or figure sideline
300, central area unit 6 be without termination environment and the center in figure sideline territory element 300 by line of demarcation 3 by big chi
The very little figure of chip 200 is divided into m rows × n and arranges square territory element 300, m >=4, n >=4；Embodiment 1 can also be applied to
Include the graph exposure of chip 200 of m rows × n column regions unit 300, wherein, m >=1, n >=2 or m >=2, n >=1；Now, chip
200 figure may be divided into one or two kinds of area types；
S102) as shown in Figure 7, corner areas unit 4, fringe region unit 5 and central area unit 6 are combined into symbol
The reticle 100 of the relative small size of exposure field size is closed, reticle 100 includes all territory elements divided by chip 200
300 type, wherein the corner areas unit 4 with dicing lane figure 102 or the fringe region list with dicing lane figure 102
Member 5 includes alignment mark；
S103) as shown in Figure 8, using the respective regions unit in the selection reticle 100 of shadow shield 7 (as shown in Figure 4
The territory element 300 exposed first is corner areas unit 4) 300 pairs of silicon chips are exposed, the territory element of first exposure
Unit on the basis of 300, and with alignment mark；Shadow shield 7 is that a kind of other parts in addition to central, clear region are opaque
Baffle plate, and the size in central, clear region can be adjusted；
S104) by the silicon chip biasing on litho machine and rotary setting, by the pattern transfer of territory element 300 of exposure to silicon
The relevant position of piece, reference cell, and alignment mark (the FRD device succeeding layers for passing through reference cell are formed by development
Photoetching then with the alignment mark of reference cell), by exposure window 11 of the remaining territory element 300 by shadow shield 7,
And silicon chip biasing and rotation process, it is exposed one by one, as shown in accompanying drawing 9 and accompanying drawing 10, with 300 points of the territory element of post-exposure
Wei not fringe region unit 5 and central area unit 6；
S105 developed after the exposure for) completing all territory elements 300 of chip 200, obtain the first layer light of chip 200
Needle drawing shape, and perform etching, complete the first layer process of chip 200；The processing procedure of FRD devices includes multiple photoetching, in first layer
During photoetching, first choose the territory element 300 with alignment mark and expose, make to be formed with alignment mark on chip 200 by development
Reference cell；
S106) using the alignment mark of first layer process formation, complete to expose the succeeding layer of chip 200 one by one successively
Light, development and etching technics, the photoetching of succeeding layer is with the alignment mark of reference cell, you can institute is obtained on chip 200
The large scale FRD device first layer litho patterns needed.
As shown in accompanying drawing 12 and accompanying drawing 13, the figure of the junction of regional unit 300 is vertical with line of demarcation 3, positioned at point
The figure of the territory element 300 of the both sides of boundary line 3 is consistent in setting range, and the setting range is determined slightly larger than shadow shield 7
Position error.The figure of the junction of regional unit 300 is consistent, can efficiently reduce the alignment of the junction of territory element 300
Error.9 be termination environment outer edge as shown in Fig. 13, and 10 be termination environment inner edge, and 20 be FRD anode aluminium lamination, and 21 be sun
Pole aluminium lamination edge.
As shown in Figure 8, the exposure window 11 of shadow shield 7 on the basis of the line of demarcation 3 of respective regions unit 300 it is unilateral to
1~10 μm of external expansion, as shown in H in accompanying drawing.
As shown in Figure 11, by upper offset (a1-a2)/2 in the horizontal direction of the center to reticle 100, in vertical side
(b1-b2)/2 are upwardly biased, corner areas unit 4 is projected required figure is formed to silicon chip.Wherein, a1 is chip 200
Length, b1 be chip 200 width, a2 be reticle 100 length, b2 be reticle 100 width.
As a kind of typical specific embodiment of the present invention, as shown in accompanying drawing 6 to accompanying drawing 11, the figure of chip 200 is further
It is divided into 4 rows × 4 to arrange, totally 16 square territory elements 300.And reticle 100 uses square structure, and by 3 row × 3
Row, totally 9 square territory elements 300 are constituted, while having continuous figure sideline 15, now, the area of reticle 100 is only
For the 56.25% of the area of chip 200.When reticle 100 includes 3 row area above unit 300, being formed after exposure can be with 3 row
The chip 200 of the figure of any of the above multirow territory element 300；When reticle 100 includes 3 row area above unit 300, exposure
Being formed afterwards can be with the chip 200 of the figure of 3 row any of the above multiple row territory element 300.With the fringe region unit in chip 200
5 and central area unit 6 increase, and the area of reticle 100 is constant, and the reticle 100 of same area can make bigger
The chip 200 of area.
Although it should be noted that above-described embodiment 1 describe technical scheme with three kinds of region division types to the present invention
Power semiconductor chip exposure method is described, but the technical scheme that embodiment 1 is described may be equally applicable to arbitrarily
The quantity of territory element 300 in one direction is more than or equal to 2, i.e., the situation of only one or two kinds of region division types is such as attached
Shown in Fig. 2 to accompanying drawing 5, the example of several different zones partition structures of power semiconductor chip is given.As shown in Figure 2, core
It is corner areas unit 4 that the figure of piece 200, which is divided into 1 row × 2 and arranges 300,2 territory elements 300 of totally 2 territory elements,
The chip 200 formed after then exposing also includes the figure that 1 row × 2 arrange totally 2 territory elements 300.As shown in Figure 3, chip 200
Figure to be divided into 2 in 300,3 territory elements 300 of totally 3 territory elements of the row of 1 row × 3 be corner areas unit 4,
It is fringe region unit 5 between two corner areas units 4, then the chip 200 that is formed includes the row above area of 1 row × 3 after exposing
The figure of domain unit 300.As shown in Figure 4, the figure of chip 200 is divided into 2 rows × 2 and arranges totally 4 territory elements 300,4
Individual territory element 300 is corner areas unit 4, then the chip 200 formed after exposing also includes 2 rows × 2 and arranges totally 2 region lists
The figure of member 300.As shown in Figure 5, the figure of chip 200 is divided into 2 rows × 3 and arranges 300,6 areas of totally 6 territory elements
Domain unit 300 includes 4 corner areas units 4 and 2 fringe region units 5 altogether, then the chip 200 formed after exposing is also wrapped
Include the figure of the row area above unit 300 of 2 rows × 3.
The power semiconductor chip exposure method technical scheme that embodiment 1 is described gives one kind in limited exposure field condition
Under, the method for manufacturing spliced large scale power semiconductor chip, so as to be improved on the premise of the limited area of reticle 100
The power grade of individual devices, the quantity of chip needed for reducing power module package.The technical scheme that embodiment 1 is described is completed
The photoetching of chip individual layer domain only needs one piece of reticle 100 to can be achieved with the making of large scale power semiconductor chip, reduces
Cost of manufacture.And the figure of territory element 300 stitching portion both sides within the specific limits one is required in zoning unit 300
Cause, alignment precision is also improved to a certain extent, it is ensured that the performance of chip.Except FRD devices, the method for embodiment description
It is also applied for other types of big line width element manufacturing.
Embodiment 2
A kind of specific embodiment of power semiconductor chip reticle, reticle 100 is single by the square region of two or more
Member 300 is combined, and including：Effective district figure 101, and the dicing lane figure positioned at the neighboring of effective district figure 101
102, territory element 300 is divided by line of demarcation 3 by large-sized figure of chip 200 and formed.Territory element 300 is according to figure
Type division is any of corner areas unit 4, fringe region unit 5 or central area unit 6 type, same type area
The inside figure of domain unit 300 is completely the same.Reticle 100 includes the class of all territory elements 300 divided by chip 200
Type, the size of reticle 100 is less than or equal to the size of chip 200.In embodiment as shown in accompanying drawing 6 to accompanying drawing 11, region
Unit 300 includes corner areas unit 4, fringe region unit 5 and the three types of central area unit 6, by corner areas unit
4th, fringe region unit 5 and central area unit 6 are combined into square reticle 100 smaller size of relative to chip 200.
Wherein, the figure of chip 200 needs the figure for meeting the junction of regional unit 300 vertical with line of demarcation 3, position
It is consistent in the figure of the territory element 300 of the both sides of line of demarcation 3 in setting range, the setting range is more than the screening of litho machine
The position error of tabula rasa 7.
Large-sized chip 200 is normally divided into m rows × n and arranges square territory element 300, m >=4, n >=4.It is used as this
A kind of typical specific embodiment is invented, the figure of chip 200 is further divided into 4 rows × 4 and arranged, totally 16 square territory elements
300.The reticle 100 of relative small size is then further arranged by 3 rows × 3, and totally 9 square territory elements 300 are constituted.Carry
The corner areas unit 4 or fringe region unit 5 of dicing lane figure 102 include alignment mark.
Embodiment 3
A kind of specific embodiment of power semiconductor chip, is made, chip 200 is big using the method described in embodiment 1
The FRD chips of size, and chip 200 structure meet the junction of regional unit 300 figure it is vertical with line of demarcation 3, position
It is consistent in the figure of the territory element 300 of the both sides of line of demarcation 3 in setting range, the setting range is more than the screening of litho machine
The position error of tabula rasa 7.Specifically, the large scale FRD devices with following vertical structure are applied to, area is mainly required
Line of demarcation 3 between domain unit 300 is located at the centre of figure, and the distance on figure both sides is bigger than the position error of shadow shield 7,
It can thus avoid because the map migration that the position error of shadow shield 7 is caused.
As shown in Figure 14, it is a kind of vertical structure schematic diagram of large scale FRD chips, wherein dotted line is with reference to boundary
Line.20 show anode aluminium lamination in such as accompanying drawing 14, and 31 be P+ anode regions, and 32 be N- areas, and 33 be N+ cathodic regions.
As shown in Figure 15, it is the vertical structure schematic diagram of another large scale FRD chips, wherein dotted line is with reference to boundary
Line, centre of the line of demarcation in positive surface anode P or P+ areas.As 34 show anode p-type island in accompanying drawing 15.
As shown in Figure 16, it is the vertical structure schematic diagram of the third large scale FRD chips, wherein dotted line is with reference to boundary
Line, line of demarcation is in the middle of positive surface anode P or P+ areas.As 35 show anode P- areas in accompanying drawing 16.
As shown in Figure 17, it is the vertical structure schematic diagram of the 4th kind of large scale FRD chip, wherein dotted line is with reference to boundary
Line, line of demarcation is overleaf in the middle of negative electrode P or N+ areas.As 36 show negative electrode p-type island in accompanying drawing 17.
In addition, the structure of large scale FRD chips can also be that the back side of the front anode construction and accompanying drawing 17 of accompanying drawing 15 is cloudy
The combination of pole structure, line of demarcation 3 needs to meet in the middle of positive surface anode P or P+ areas simultaneously, and in the negative electrode P or N+ areas of the back side
Between.The structure of large scale FRD chips can also be the group of the front anode construction of accompanying drawing 16 and the back side cathode construction of accompanying drawing 17
Close, the requirement in line of demarcation 3 is identical.
Embodiment 4
The specific embodiment of another power semiconductor chip, is made using the method described in embodiment 1, and chip 200 is
The large scale igbt chip or MOSFET chips or other chips of the division of territory element 300 can be carried out.Such as accompanying drawing 18 and accompanying drawing 19
Shown, the grid of igbt chip interconnects area by the grid of igbt chip and emitter stage area of isolation split into grid form, each to spell
Line of demarcation between order member is located at grid interconnection region, and this is the chip 200 using corner grid structure.In accompanying drawing 18
In, 41 be grid interconnection line, and 42 be corner grid, and 43 be emitter stage, in accompanying drawing 19, and 14 be termination environment.In addition, igbt chip
Or to may be alternatively located at center (center grid structure) or edge (the edge grid structure) of chip 200 etc. other for the gate regions of MOSFET chips
Position.As shown in Figure 20, be cellular 40 in accompanying drawing 15 A-A ' to sectional structure chart, wherein 50 be N- substrates, 51 be P-
Base, 52 be N+ source areas, and 53 be P+ buses area.
By implementing the power semiconductor chip that the specific embodiment of the invention is described, the reticle of the chip and its exposure side
The technical scheme of method, can produce following technique effect：
(1) power semiconductor chip of specific embodiment of the invention description, the reticle and its exposure method of the chip are led to
Cross and large scale power semiconductor chip figure is divided into different types of territory element, and different zones unit is combined into completely
The domain of sufficient exposure machine exposure field size requirement, realizes large-size device figure by the way of splicing exposure, realizes profit
The purpose of large scale power semiconductor chip is made with small size lithography layout shape, compared with traditional implementation, is reduced
The quantity of reticle, reduce manufacturing cost；
(2) power semiconductor chip of specific embodiment of the invention description, the reticle and its exposure method of the chip is first
The reference cell with alignment mark is first formed on chip, remaining area unit is then determined by reference cell alignment mark
Position exposure, completes the splicing of all territory elements, and then forms complete domain, ultimately forms power semiconductor, making side
Method is simple, improve using polylith reticle carry out splicing tape come error, improve alignment and the precision spliced；
(3) power semiconductor chip of specific embodiment of the invention description, the reticle and its exposure method of the chip are carried
One kind is supplied in the case of limited exposure field, the method for manufacturing spliced large scale power semiconductor, so as to improve
The power grade of individual devices, reduces the number of chips needed for encapsulation, it is possible to achieve prepared by the chip of complex figure, by adopting
Replace the chip of multiple small sizes is used in parallel can obtain bigger power density with large-sized chip.
The embodiment of each in this specification is described by the way of progressive, and what each embodiment was stressed is and other
Between the difference of embodiment, each embodiment identical similar portion mutually referring to.
The above described is only a preferred embodiment of the present invention, not making any formal limitation to the present invention.Though
So the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with those skilled in the art
Member, in the case where not departing from the Spirit Essence and technical scheme of the present invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible variations and modification to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, the technical spirit according to the present invention is to made for any of the above embodiments any simple
Modification, equivalent substitution, equivalence changes and modification, still fall within the scope of technical solution of the present invention protection.
Claims (21)
1. a kind of power semiconductor chip exposure method, it is characterised in that comprise the following steps：
S101 large-sized chip (200) figure) is divided into two by line of demarcation (3) according to the exposure field size of litho machine
Territory element (300) above, corner areas unit (4), side are divided into according to the type of figure by the territory element (300)
Any of edge territory element (5) or central area unit (6) type, and ensure the interior of same type territory element (300)
Portion's figure is completely the same；
S102 the territory element (300)) is combined into reticle (100), the reticle (100) is included by the chip
(200) all territory elements (300) type divided, the size of the reticle (100) is less than or equal to the chip (200)
Size, wherein the corner areas unit (4) or fringe region unit (5) include alignment mark；
S103) the respective regions unit (300) on the reticle (100) is chosen using shadow shield (7) to be exposed silicon chip,
Unit on the basis of the territory element (300) of first exposure, and with alignment mark；
S104) by the silicon chip biasing on litho machine and rotary setting, by territory element (300) pattern transfer of exposure to silicon chip
Relevant position, reference cell is formed by development, and by the alignment mark of reference cell, by remaining territory element
(300) by the exposure window (11) of the shadow shield (7), and silicon chip biasing and rotation process, it is exposed one by one；
S105 developed after the exposure for) completing all territory elements of the chip (200) (300), obtain the chip (200)
First layer litho pattern, and perform etching, complete the first layer process of the chip (200)；
S106) using the alignment mark of first layer process formation, the exposure, development and quarter of chip (200) succeeding layer are completed
Etching technique.
2. power semiconductor chip exposure method according to claim 1, it is characterised in that：Positioned at the line of demarcation (3)
Territory element (300) figure of both sides is consistent in setting range, and the setting range is more than the positioning of the shadow shield (7)
Error.
3. power semiconductor chip exposure method according to claim 2, it is characterised in that：The territory element (300)
The figure of junction is vertical with the line of demarcation (3).
4. power semiconductor chip exposure method according to claim 3, it is characterised in that：The corner areas unit
(4) for tape terminal area (14) or figure sideline (15) corner territory element (300), the fringe region unit (5) be band
The territory element (300) at the edge of termination environment (14) or figure sideline (15), the central area unit (6) is without termination environment
(14) and figure sideline (15) center territory element (300).
5. power semiconductor chip exposure method according to claim 4, it is characterised in that：The reticle (100) is
Square structure, the reticle (100) has continuous figure sideline (15).
6. the power semiconductor chip exposure method according to claim 1,2,3,4 or 5 any one, it is characterised in that：Institute
State the exposure window (11) of shadow shield (7) on the basis of the line of demarcation (3) of respective regions unit (300) it is unilateral to external expansion 1~
10μm。
7. power semiconductor chip exposure method according to claim 6, it is characterised in that：By to the reticle
(100) center upper offset (a1-a2)/2 in the horizontal direction, in the vertical direction biasing (b1-b2)/2, by the corner areas
Required figure is formed on unit (4) projection to the silicon chip；Wherein, a1 is the length of chip (200), and b1 is chip (200)
Width, a2 be reticle (100) length, b1 be reticle (100) width.
8. the power semiconductor chip exposure method according to claim 1,2,3,4,5 or 7 any one, it is characterised in that：
Large-sized chip (200) figure is divided into m rows × n by line of demarcation (3) and arranges square territory element (300), m >=4, n
≥4；The corner areas unit (4), fringe region unit (5) and central area unit (6) be combined into to meet exposure field big
It is small, and relative to the less reticle of size (100) of the chip (200).
9. power semiconductor chip exposure method according to claim 8, it is characterised in that：Chip (200) figure
It is divided into 4 rows × 4 to arrange, totally 16 square territory elements (300).
10. power semiconductor chip exposure method according to claim 8, it is characterised in that：The reticle (100) by
3 rows × 3 are arranged, totally 9 square territory elements (300) compositions.
11. a kind of power semiconductor chip reticle, it is characterised in that the reticle (100) is by the square area of two or more
Domain unit (300) is combined, and including：Effective district figure (101), and positioned at effective district figure (101) neighboring
Dicing lane figure (102), the territory element (300) by large-sized chip (200) figure by line of demarcation (3) divide and
Into；The territory element (300) is corner areas unit (4), fringe region unit (5) or center according to the Type division of figure
Any of territory element (6) type, the inside figure of same type territory element (300) is completely the same；The reticle
(100) all territory elements (300) type divided by the chip (200) is included, the size of the reticle (100) is less than
Or equal to the size of the chip (200)；Territory element (300) figure positioned at the line of demarcation (3) both sides is in setting range
Inside it is consistent, the setting range is more than the position error of the shadow shield (7) of litho machine.
12. power semiconductor chip reticle according to claim 11, it is characterised in that：The territory element (300)
The figure of junction is vertical with the line of demarcation (3).
13. power semiconductor chip reticle according to claim 12, it is characterised in that：The corner areas unit
(4) for tape terminal area (14) or figure sideline (15) corner territory element (300), the fringe region unit (5) be band
The territory element (300) at the edge of termination environment (14) or figure sideline (15), the central area unit (6) is without termination environment
(14) and figure sideline (15) center territory element (300).
14. power semiconductor chip reticle according to claim 13, it is characterised in that：The reticle (100) is
Square structure, the reticle (100) has continuous figure sideline (15).
15. the power semiconductor chip reticle according to claim 11,12,13 or 14 any one, it is characterised in that：Institute
State chip (200) figure and be divided into m rows × square territory element (300) of n row, m >=4, n >=4, by the corner areas unit
(4), fringe region unit (5) and central area unit (6), which are combined into, meets exposure field size, and relative to the chip
(200) the less reticle of size (100).
16. power semiconductor chip reticle according to claim 15, it is characterised in that：Chip (200) figure
It is divided into 4 rows × 4 to arrange, totally 16 square territory elements (300).
17. power semiconductor chip reticle according to claim 15, it is characterised in that：The reticle (100) is by 3
Row × 3 is arranged, totally 9 square territory element (300) compositions.
18. the power semiconductor chip reticle according to claim 11,12,13,14,16 or 17 any one, its feature
It is：The corner areas unit (4) or fringe region unit (5) with dicing lane figure (102) include alignment mark.
19. a kind of power semiconductor chip, it is characterised in that the chip (200) is using described in any one of claim 1 to 10
Method makes, and the chip (200) is large-sized FRD chips.
20. a kind of power semiconductor chip, it is characterised in that the chip (200) is using described in any one of claim 1 to 10
Method makes, and the chip (200) is large-sized igbt chip or MOSFET chips.
21. power semiconductor chip according to claim 20, it is characterised in that：Igbt chip or the MOSFET chip
Using any of center grid, edge grid or corner grid structure.
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| CN113433799A (en) * | 2020-03-23 | 2021-09-24 | 长鑫存储技术有限公司 | Wafer edge exposure method, wafer edge exposure device and mask plate |
| CN114279571A (en) * | 2021-12-03 | 2022-04-05 | 中国电子科技集团公司第十一研究所 | Infrared focal plane outgoing circuit chip and preparation method thereof |
| CN114326336A (en) * | 2021-11-19 | 2022-04-12 | 无锡中微晶园电子有限公司 | Large-size chip exposure method |
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| CN114326336B (en) * | 2021-11-19 | 2024-03-22 | 无锡中微晶园电子有限公司 | Large-size chip exposure method |
| CN114279571A (en) * | 2021-12-03 | 2022-04-05 | 中国电子科技集团公司第十一研究所 | Infrared focal plane outgoing circuit chip and preparation method thereof |
| CN114279571B (en) * | 2021-12-03 | 2024-03-22 | 中国电子科技集团公司第十一研究所 | Infrared focal plane readout circuit chip and preparation method thereof |
| CN115236955A (en) * | 2022-09-23 | 2022-10-25 | 武汉光谷量子技术有限公司 | Photoetching method for obtaining symmetrical pattern |
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