CN114326336A

CN114326336A - Large-size chip exposure method

Info

Publication number: CN114326336A
Application number: CN202111398197.5A
Authority: CN
Inventors: 季骏; 高晓君; 廖聪湘; 顾霞; 孙建洁
Original assignee: Wuxi Zhongwei Microchips Co ltd
Current assignee: Wuxi Zhongwei Microchips Co ltd
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2022-04-12
Anticipated expiration: 2041-11-19
Also published as: CN114326336B

Abstract

The invention discloses a large-size chip exposure method, and belongs to the field of integrated circuit manufacturing. Dividing a chip to be manufactured into a structure formed by splicing a plurality of chips; manufacturing a photoetching plate corresponding to each layer of circuit structure of each spliced chip; placing the photoetching pattern of the first spliced chip on the position of the first spliced chip of the wafer and exposing the photoetching pattern, and leaving a mark of an alignment mark on the wafer; placing the photoetching pattern of the second spliced chip at the position of the second spliced chip of the wafer, selecting an alignment mark left after the exposure of the first spliced chip during alignment, and carrying out alignment exposure; and repeating the steps until the exposure of all the spliced chips of the current level is completed. The mark of the shallow alignment mark left after the initial exposure of the current level is only needed to be found without manufacturing an additional mark, and the mark is aligned to be exposed during the subsequent exposure of the current level, so that the splicing precision among the graphs of the current level is met, the one-time exposure and corrosion process flow is saved, and the cost is reduced.

Description

Large-size chip exposure method

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a large-size chip exposure method.

Background

The exposure process is an important process in the chip manufacturing process, and aims to transfer the geometric figures on the photoetching plate onto a wafer and then form a circuit structure on the wafer through processes such as corrosion and the like.

Obviously, the geometric figure on the photoetching plate is essentially the circuit structure of the chip and is transferred to the wafer by means of exposure. When an integrated circuit produces a large chip, sometimes the size exceeds the view field limit of a photoetching machine due to oversize, the whole pattern cannot be transferred onto a wafer through one-time exposure, at this time, the chip needs to be divided into a plurality of chips with the size smaller than or equal to the maximum exposure view field of the photoetching machine, multiple exposures are carried out through a plurality of photomasks, and the patterns exposed by different photomasks are spliced to obtain a complete chip pattern, namely splicing exposure.

At the moment, the alignment precision of the same layer of multi-exposure different patterns has great influence on the electrical parameters and yield of the product, and the alignment method plays an important role in the pattern splicing precision. In actual process, alignment is generally performed by aligning with a mark left by a previous layer of pattern when exposure alignment is performed by a lithography machine, and then developing and reading an alignment value to confirm alignment accuracy. When the same layer is exposed for multiple times, the alignment is required to be performed with not only the previous layer but also the previous exposure patterns of the same layer, so that the accurate splicing effect is achieved. At this time, if the good splicing effect between different exposure patterns on the same layer is to be maintained, the alignment mark needs to be made on the wafer in advance, which increases the process steps.

Disclosure of Invention

The invention aims to provide an exposure method for a large-size chip, so as to save one-time exposure and corrosion process flow and reduce the cost.

In order to solve the above technical problem, the present invention provides a large-size chip exposure method, comprising:

dividing a chip to be manufactured into a structure formed by splicing a plurality of chips;

manufacturing a photoetching plate corresponding to each layer of circuit structure of each spliced chip;

placing the photoetching graph of the first spliced chip at the position of the first spliced chip of the wafer, exposing the photoetching graph, and leaving a mark of an alignment mark on the wafer after exposure;

placing the photoetching pattern of the second spliced chip at the position of the second spliced chip of the wafer, selecting an alignment mark left after the exposure of the first spliced chip during alignment, and carrying out alignment exposure;

and repeating the steps until the exposure of all the spliced chips of the current level is completed.

Optionally, the chip to be manufactured is divided into a structure formed by splicing a plurality of chips according to the size of the maximum exposure field area of the photoetching machine.

Optionally, the size of each split spliced chip is smaller than or equal to the maximum exposure field of the lithography machine.

Optionally, after the exposure of all the spliced chips in the current level is completed, the large-size chip exposure method further includes:

developing and displaying the wafer, adjusting an alignment correction value if an alignment difference exists, and entering the next procedure after the wafer is qualified;

the subsequent level exposure can be carried out by utilizing the alignment mark left after the previous level photoetching and corrosion until the process flow of the whole chip is completed.

In the large-size chip exposure method provided by the invention, no extra mark is needed to be made, only the mark of the shallow contraposition mark left after the initial exposure of the current layer is needed to be found, and the mark is aligned to be exposed during the subsequent exposure of the layer, so that the splicing precision among the patterns of the layer can be met, the one-time exposure and corrosion process flow is saved, and the cost is reduced.

Drawings

FIG. 1 is a schematic flow chart of a large-scale chip exposure method provided by the present invention;

FIG. 2 is a schematic view of a first tiled die after exposure to form a latent image;

FIG. 3 is a schematic view of the completed chip splice after exposure of a second splice chip to the alignment latent image;

FIG. 4 is a schematic diagram of a first layer of a wafer after development to form a complete wafer.

Detailed Description

The following describes a large-sized chip exposure method according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The invention provides a large-size chip exposure method, the flow of which is shown in figure 1, and the method comprises the following steps:

step S11, dividing the chip to be manufactured into a structure formed by splicing a plurality of chips;

s12, manufacturing a photoetching plate corresponding to each layer of circuit structure of each spliced chip;

s13, placing the photoetching layout of the first spliced chip at the position of the first spliced chip of the wafer, exposing the photoetching layout, and leaving an alignment mark on the wafer after exposure;

s14, placing the photoetching layout of the second spliced chip at the position of the second spliced chip of the wafer, selecting an alignment mark left after the exposure of the first spliced chip during alignment, and carrying out alignment exposure;

and step S15, repeating the steps until the exposure of all the spliced chips of the current level is completed.

The chip is divided into two parts for illustration: dividing a chip to be manufactured into a structure formed by splicing two chips according to the size of the maximum exposure field area of the photoetching machine, wherein the size of each spliced chip is smaller than or equal to the maximum field of view of the photoetching machine;

manufacturing a photoetching plate corresponding to the circuit structure of each layer of the two spliced chips according to the dividing result;

through the accurate operation of the photoetching machine, the photoetching pattern of the first spliced chip is placed at the position of the first spliced chip of the wafer, the first spliced chip is exposed, and a shallow mark (latent image) of an alignment mark is left on the wafer after exposure, as shown in fig. 2;

placing the photoetching pattern of the second spliced chip at the position of the second spliced chip of the wafer by the accurate operation of the photoetching machine, selecting an alignment mark (latent image) left after the exposure of the first spliced chip during alignment, and performing alignment exposure, wherein the alignment mark is shown in fig. 3;

developing the wafer to form a first layer of pattern of the complete chip as shown in FIG. 4; performing display inspection, adjusting an alignment correction value if an alignment difference exists, and entering the next procedure after the alignment correction value is qualified;

The invention can save one-time exposure and corrosion process flow and reduce the cost by carrying out alignment exposure by using the latent image left on the wafer after the first exposure.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A large-size chip exposure method is characterized by comprising the following steps:

2. The exposure method for large-size chips as defined in claim 1, wherein the chips to be fabricated are divided into a plurality of chips to be joined together according to the maximum exposure field area size of the lithography machine.

3. The large-sized chip exposure method according to claim 2, wherein the size of each of the divided spliced chips is smaller than or equal to the maximum exposure field of view of the lithography machine.

4. The large-size chip exposure method according to claim 1, wherein after the exposure of all the tiles of the current level is completed, the large-size chip exposure method further comprises: