JP2979682B2 - Method of assembling semiconductor device using map - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of assembling a semiconductor device using a map, and more particularly to a map obtained by superposing a shot layout obtained at the time of exposure and test data obtained at the time of a primary test. The origin of the chip code is determined by combining the map consisting of the position information of the chip obtained by the primary test in the wafer inspection process and the outer dimension information of the wafer, and the map made coincident with the origin of the map is used for the chip in the assembly process. The present invention relates to a method for assembling a semiconductor device used as layout information.

2. Description of the Related Art In recent years, in semiconductor devices, while elements formed on one chip have been miniaturized and highly integrated, the size of a wafer has also increased, and the number of chips cut out from one wafer has also increased. ing. Therefore, it is important to accurately grasp the position of the chip on the wafer and the characteristics of the chip.

[0003] The devices provided on the wafer are subjected to wafer inspection at the final stage of the wafer process before being scribed as chips. This wafer inspection is a primary test, also called a probing test, and when a defective chip is found by this primary test, it was once performed to make a distinction by, for example, attaching an ink mark. However, recently, information on which position of a chip on a wafer is defective is, for example, temporarily stored in a floppy medium or the like via a CPU, or directly connected online between CPUs, for example. A so-called map (map) method that is useful for rationalizing the assembly process has been adopted.

According to this mapping method, for example, chips can be easily classified into several grades. Also, for example, in an assembling process for die bonding a chip,
Since the address of the non-defective chip to be bonded next is known in advance, the working efficiency can be improved. Further, this map method is an effective method that can analyze a wafer process based on test data of a primary test and manage history after the primary test.

[0005]

2. Description of the Related Art The first map created in the map method is created based on data obtained by a primary test, that is, an electrical test. However, in general, since square chips are arranged on a circular wafer, chips arranged near the end face of the wafer often fall on the end face of the wafer and a part of the chips is often missing. The occurrence of such chipped chips is caused by alignment at the time of exposure for patterning chip-shaped elements on a wafer.

FIGS. 5A and 5B are views for explaining an example of alignment at the time of exposure, wherein FIG. 5A is a plan view and FIG. 5B is a sectional view. In the figure, 1 is a wafer, 2 is a chip, 3 is a chip,
5 is a facet and 6 is a chamfered surface.

In FIG. 5 (A), a circular wafer 1 is provided with a facet (abbreviation for orientation flat, orientation flat) whose peripheral edge is cut linearly to give directionality. In the exposure for patterning the elements on the wafer 1, facets 5
Is set as the X axis, the right end face of the wafer 1 is set as the Y axis, and alignment is performed based on an XY coordinate system in which the origin virtually exists outside the wafer 1.

After this alignment, a shot layout is performed, for example, while interacting with the CPU. One shot indicates a range in which the exposure operation can be performed at one time. In some cases, one chip 2 may be exposed, or a plurality of chips 2 may be exposed collectively.

In the example shown here, two chips 2 are exposed in one shot. Then, while the exposure device, also called a stepper, moves intermittently in the XY directions,
Exposure is performed sequentially. Therefore, the shot layout information obtained at the time of this exposure most accurately represents the position of the chip on the wafer.

Incidentally, the end face of the wafer 1 is chamfered for the purpose of preventing deburring or chipping of the end face generated during dicing, and as shown in FIG. Has become. Therefore, when the chips 2 aligned near the end face of the wafer 1 hang on the chamfered surface 6 of the wafer 1, even if the chips 2 are apparently exposed,
There is a case where the chip 3 does not function properly as an element.

Further, even in a wafer process for producing the same kind, if the lot of the wafer 1 is different from that of FIG.
In some cases, the dimensions of the wafer 1 are different as indicated by the dashed line. For this reason, there is an inconvenience that the chip 2 existing in the wafer 1 of a certain lot does not exist in the wafer 1 of another lot.

On the other hand, recently, an identification method called a chip code has been adopted for chips arranged on a wafer. FIG. 6 is an explanatory view of the coordinate origin of the chip code, where 1 is a wafer, 2 is a chip, and 4 is an origin chip.

In the chip code, among a plurality of chips 2 formed on the wafer 1, the wafer 1
The tip 2 closest to the geometrical center O of FIG.

FIGS. 6A, 6B and 6C show various examples of the origin chip 4. FIG. And, for example, (-4,3)
The chip 2 is identified by taking the addresses ± X in the horizontal direction and ± Y in the vertical direction.

[0015]

As described above, the chips laid out on the wafer are determined by the shot layout in the exposure process. However, since the dimensions of the wafer differ from lot to lot, the maps created by the primary test also differ from lot to lot.

Therefore, in order to prevent confusion in the assembly process of inspecting and die bonding individual chips after scribing, for example, a complicated operation of marking each wafer so that it can be visually confirmed is necessary. Met.

The origin of the coordinates set in the primary test can be arbitrarily shifted by an operator who performs the test on software. for that reason,
In some cases, chips located at the same position on each wafer may exist at different addresses, and there is a problem that data cannot be used in subsequent analysis or the like.

Furthermore, the origin of the coordinates set in the primary test is different from the origin of the coordinates in the chip code, which is inconvenient when performing analysis or the like. Therefore, the present invention provides a chip code by superimposing a map obtained by combining shot layout information at the time of exposure and test data obtained at the time of the primary test, and a map obtained by the primary test with the external dimension information of the wafer. It is an object of the present invention to provide a method of assembling a semiconductor device using a map obtained by determining an origin of the map and matching the origin of the map as chip layout information in an assembling process.

[0019]

SUMMARY OF THE INVENTION The above-mentioned problem is that a map used in an assembling process after a primary test in a wafer inspection process includes shot layout information obtained at the time of exposing a wafer in an exposure process. A method of assembling a semiconductor device using a map formed by superimposing test data obtained at the next test, and a chip layout information obtained at a first test in a wafer inspection process using an origin of the map. And a method of assembling a semiconductor device using a map configured to match the origin of the chip code by combining the dimensions of the wafer.

[0020]

According to the first aspect of the present invention, the chip layout information obtained from the shot layout at the time of exposure most accurately indicates the chip layout.
Since information such as the number and arrangement of chips in the shot and the origin of the chip code is also included, the information is taken out to a storage medium or the like. The map is superimposed on the test data obtained in the primary test.

According to a second aspect of the present invention, the origin of the chip code is determined by combining the chip layout information obtained at the time of the primary test in the wafer inspection process and the external dimension information of the wafer. To match. And the origin of the chip code is X-
Missing chips generated in the first to third quadrants of the wafer, which are the origin of the Y coordinate system, are corrected with reference to the fourth quadrant to be used as chip layout information. Further, correction is performed once for one product type, and the chip layout information obtained therefrom is temporarily stored so as to be adapted to wafers of the same product type to be handled thereafter.

Thus, the chip layout of the primary test is corrected based on the most accurate chip layout information obtained from the shot layout at the time of exposure, or
If the origin of the map obtained after the primary test matches the origin of the chip code, an accurate map can be obtained. Further, such map information can be written into the CPU to form a map system.

The information of the missing chips in this map is obtained by using the defect data and the defect category (details of the defect) in the CP without manual intervention.
U can be written. Further, the present invention can be uniformly used for an assembling process and subsequent processes such as, for example, a history analysis of chips.

[0024]

FIG. 1 is an explanatory view of a first embodiment of the present invention, and FIG.
FIG. 3 is an explanatory view of superposition of shot layout information and primary test data, and FIG. 3 is an explanatory view of a second embodiment of the present invention.
(A) Determination of the X-axis, (B) Determination of the Y-axis, FIG. In the figure, 1 is a wafer, 2 is a chip, 3 is a chip, 4 is an origin chip,
5 is a facet.

Embodiment 1 In FIG. 1, the exposure apparatus is also called a stepper, and the shot layout information obtained here is read out online or once in a storage medium such as a floppy disk, and is then called a primary prober. It is sent to the test equipment. Then, the wafer 1 is aligned based on the shot layout information.

The primary test apparatus used in the wafer test is also called a prober, and generally performs a rough alignment within several mm, and then performs a precise alignment by the chip 2 in the wafer 1. Has become. So, after the precise alignment,
A primary test is performed based on chip layout information obtained from shot layout information of the exposure apparatus.

On the other hand, since the external dimension information of the wafer 1 can be known at the time of the primary test, the chip 3 may be determined from the result and removed from the chip layout information. Does not exist, defective data may be input. In this way, the chip 3 can be omitted from testing.

In order to determine the chip layout information from the shot layout information, since the size of the chip 2 is known in advance, the chip layout information can be easily determined by inputting data through interaction with a CPU or the like.

In FIG. 2, the test data after the completion of the primary test undergoes a data format rewrite in order to flow to a subsequent process. However, alignment of the wafer 1 performed at the time of exposure is performed with the end face of the facet 5 as the X axis and the right end face as the Y axis as described with reference to FIG. Therefore, even if there is a difference in the size of the wafer 1, the chip layout in the third quadrant is correct. Rows and columns aligned along the vicinity of the X axis and the Y axis have no chip 3 even in the primary test.

Therefore, the chip row closest to the X-axis on the end face of the facet 5 and the chip row closest to the Y-axis on the right end face are defined as a standard row and a standard column, respectively.
Overlay on U. Then, the origin (0, 0) of the chip code can be determined, and the test data of the primary test can be easily corrected.

In this manner, a map system used in an assembling process after the primary test is created by superposing the chip layout information obtained from the shot layout information at the time of exposure and the test data obtained at the time of the primary test. Can be.

Embodiment 2 Since the origin of the chip code is set to the origin (0,0) of the chip code with the chip 2 closest to the center point of the wafer 1 as the origin chip 4, it is necessary to specify the origin chip 4. Determine the X and Y axes.

First, with respect to the X axis, a map obtained from the data of the primary test and the direction of the facet 5 are used as shown in FIG.
As shown in (A), the center is determined from the number of chips in the vertical row of the chips 2 arranged on the right side excluding the facet 5, and this is defined as the X axis. However, if the chip 3 is missing, the center is determined by majority vote.

Next, similarly to the X axis, the center of the Y axis is determined from the number of chips in the horizontal row of the chips 2 arranged near the center of the wafer 1, and this is defined as the Y axis.
However, if the chip 3 is missing, the center is determined by majority vote.

Thus, the determined X axis and Y axis are used as the coordinate system of the map. Then, the origin (0, 0) of the chip code can be determined, for example, as shown in the figure, with the chip 2 located closest to the origin O of the XY coordinate system being the origin chip 4. That is, the origin O of the map coincides with the origin (0, 0) of the chip code.

On the other hand, in FIG. 4, in the fourth quadrant of the XY coordinate system thus determined, the alignment performed at the time of exposure is performed as shown in FIG. The shot layout information has good reproducibility irrespective of the size difference of the wafer 1. Moreover, only the facet 5 is asymmetric in the Y direction. However, if the shot size, that is, the shape of the chip becomes large relative to the size of the wafer 1, the facet 5 becomes symmetric in both the X direction and the Y direction. Become.

Therefore, by inverting the chip layout information in the fourth quadrant about the X axis and the Y axis, it is possible to correct the presence of the chip 3 in the chip layout of the primary test. However, facet 5 symmetrical with respect to the X axis
Since the chip layout of the portions indicated by the dotted lines in the first and second quadrants on the opposite side has not been corrected, the data obtained in the primary test is used, or in some cases, is visually checked and corrected.

Such a correction of the chip layout is performed once immediately after the primary test on a standard wafer of a certain type. If this chip layout information is stored, subsequent chip types can be sequentially corrected using the chip layout information.

[0039]

According to the present invention, a map is constructed by combining shot layout information obtained in the exposure step and test data of the primary test, or the origin of the map is determined by the chip layout information and the wafer dimensions obtained in the primary test. And constructing a map that matches the origin of the chip code, an accurate map system can be established.

The map information is an effective means for the primary test in the wafer inspection process, the assembling process such as dicing after the inspection process, or the analysis of the defect which goes back to the wafer process. Therefore, the present invention largely contributes to the efficiency of the semiconductor device manufacturing process.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of superposition of shot layout information and primary test data.

FIG. 3 is an explanatory view of a second embodiment of the present invention.
(B) is the determination of the Y axis.

FIG. 4 is an explanatory diagram of a method of correcting a missing chip.

FIG. 5 is a diagram illustrating an example of alignment at the time of exposure;
(A) is a plan view and (B) is a sectional view.

FIG. 6 is an explanatory diagram of a coordinate origin of a chip code.

[Explanation of symbols]

 1 wafer 2 chip 3 chipped chip 4 origin chip 5 facet

Claims (5)

(57) [Claims] 1. A map used in an assembling process after a primary test in a wafer inspection process includes: shot layout information obtained when exposing a wafer in an exposure process; and test data obtained in the primary test. A method of assembling a semiconductor device using a map characterized by being superimposed. 2. The method according to claim 1, wherein an origin of the map is set to 1 in a wafer inspection process.
A method of assembling a semiconductor device using a map, characterized by combining chip layout information obtained at the time of the next test and outer dimension information of a wafer to match the origin of a chip code. 3. The chip layout information, wherein chipped chips generated in the first to third quadrants of a wafer having the origin of the chip code as the origin of a coordinate system are corrected with reference to a fourth quadrant to provide chip layout information. A method for assembling a semiconductor device using the described map. 4. A semiconductor device using a map according to claim 3, wherein chip layout information obtained by the correction according to claim 2 performed once for one product type is stored and adapted for subsequent same product types. How to assemble the device. 5. A method of assembling a semiconductor device using a map formed by writing information on an origin of a chip code and a missing chip to a CPU using the map described in claim 1 and the map described in claim 2 to form a map system. .